US20170077940A1 - A/d converter circuit, pipeline a/d converter, and wireless communication device - Google Patents
A/d converter circuit, pipeline a/d converter, and wireless communication device Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
- H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
- H03M1/164—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
- H03M1/181—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values
- H03M1/183—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values the feedback signal controlling the gain of an amplifier or attenuator preceding the analogue/digital converter
- H03M1/185—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values the feedback signal controlling the gain of an amplifier or attenuator preceding the analogue/digital converter the determination of the range being based on more than one digital output value, e.g. on a running average, a power estimation or the rate of change
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Abstract
An A/D converter circuit has an amplifier circuit to amplify an input signal and output a first amplification signal and a second amplification signal, the second amplification signal having an amplification error smaller than that in the first amplification signal, a first sampling circuit to sample the first amplification signal, a first A/D converter to perform A/D conversion on the first amplification signal sampled by the first sampling circuit and output a first digital signal, a second sampling circuit to sample the second amplification signal, a D/A converter to perform D/A conversion on the first digital signal and output a first analog signal, a subtracter to subtract the first analog signal from the second amplification signal sampled by the second sampling circuit and output a second analog signal, and a second A/D converter to perform A/D conversion on the second analog signal and output a second digital signal.
Description
- This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2015-178185, filed on Sep. 10, 2015, the entire contents of which are incorporated herein by reference.
- Embodiments of the present invention relate to an A/D converter circuit, a pipeline A/D converter, and a wireless communication device.
- The speed of a general pipeline A/D converter is controlled by amplification time for an operational amplifier to amplify a residual signal and A/D conversion time for the post-stage to perform A/D conversion on the residual signal amplified by the operational amplifier. As a method to shorten the A/D conversion time, it is proposed to perform A/D conversion on upper bits of the residual signal by a first A/D converter before performing A/D conversion on lower bits of the residual signal by a second A/D converter (e.g. a successive approximation A/D converter) utilizing the result of A/D conversion performed by the first A/D converter. This method makes it possible to shorten the A/D conversion time for the successive approximation A/D converter, by which A/D conversion time as a whole can be consequently shortened.
- However, in the above conventional method, the residual signal inputted into the first A/D converter and that inputted into the second A/D converter are sampled at the same timing, which causes overhead in the sampling period and imposing a limitation on the speed of A/D conversion.
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FIG. 1 is a diagram showing an example of an A/D converter circuit according to a first embodiment. -
FIG. 2 is a diagram explaining the operation of a sub-range A/D converter. -
FIG. 3 is a diagram showing an example of a pipeline A/D converter having the A/D converter circuit according to the first embodiment. -
FIG. 4 is a timing chart showing the operation of the A/D converter circuit according to the first embodiment. -
FIG. 5 is a diagram showing a first example of an amplifier circuit. -
FIG. 6 is a diagram showing the operation of the amplifier circuit ofFIG. 5 . -
FIG. 7 is a diagram showing a second example of the amplifier circuit. -
FIG. 8 is a diagram showing the operation of the amplifier circuit ofFIG. 7 . -
FIG. 9 is a diagram showing a third example of the amplifier circuit. -
FIG. 10 is a diagram showing the operation of the amplifier circuit ofFIG. 9 . -
FIG. 11 is a diagram showing a fourth example of the amplifier circuit. -
FIG. 12 is a diagram showing an example of an A/D converter circuit according to a second embodiment. -
FIG. 13 is a diagram showing a relationship between an output signal of an amplifier circuit and an amplification error. -
FIG. 14 is a diagram showing an example of an A/D converter circuit according to a third embodiment. -
FIG. 15 is a diagram explaining the operation of a sub-range A/D converter having redundancy. -
FIG. 16 is a diagram showing an example of an A/D converter circuit according to a fourth embodiment. -
FIG. 17 is a diagram showing an example of a wireless communication device according to a fifth embodiment. - According to one embodiment, an A/D converter circuit has:
- an amplifier circuit to amplify an input signal and output a first amplification signal and a second amplification signal, the second amplification signal having an amplification error smaller than that in the first amplification signal;
- a first sampling circuit to sample the first amplification signal;
- a first A/D converter to perform A/D conversion on the first amplification signal sampled by the first sampling circuit and output a first digital signal;
- a second sampling circuit to sample the second amplification signal;
- a D/A converter to perform D/A conversion on the first digital signal and output a first analog signal;
- a subtracter to subtract the first analog signal from the second amplification signal sampled by the second sampling circuit and output a second analog signal; and
- a second A/D converter to perform A/D conversion on the second analog signal and output a second digital signal.
- Hereinafter, embodiments of the present invention will be explained referring to the drawings.
- An A/D converter circuit according to a first embodiment will be explained referring to
FIGS. 1 to 4 .FIG. 1 is a diagram showing an example of an A/D converter circuit according to the present embodiment. As shown inFIG. 1 , the A/D converter circuit according to the present embodiment has anamplifier circuit 1, afirst sampling circuit 2, a first A/D converter 3, asecond sampling circuit 4, a D/A converter 5, asubtracter 6, and a second A/D converter 7. The following explanation is based on an example where an input signal of the A/D converter circuit is a voltage signal, but the input signal may be replaced by a current signal. - The
amplifier circuit 1 is inputted with an input signal Vin. Theamplifier circuit 1 amplifies the input signal Vin inputted thereto, and outputs a first amplification signal V1 and a second amplification signal V2. When theamplifier circuit 1 has an amplification factor of Gv, the ideal amplification signal of theamplifier circuit 1 is Vin×Gv. The first amplification signal V1 is a signal obtained by amplifying the input signal Vin coarsely, and its amplification error from the ideal amplification signal Vin×Gv is larger than that in the second amplification signal V2. The second amplification signal V2 is a signal obtained by amplifying the input signal Vin more finely (with higher accuracy), and its amplification error from the ideal amplification signal Vin×Gv is smaller than that in the first amplification signal V1. - The
amplifier circuit 1 is controlled by control signals φ3 and φ4. The control signals φ3 and φ4 are clock signals. Theamplifier circuit 1 amplifies the input signal Vin while the control signals φ3 and φ4 are H (High). Hereinafter, a period during which the control signal φi is H is referred to as Phase i. The first amplification signal V1 is an amplification signal at the end ofPhase 3, and the second amplification signal V2 is an amplification signal at the end ofPhase 4. Note that the configuration of theamplifier circuit 1 will be mentioned in detail later. - The
first sampling circuit 2 is inputted with the first amplification signal V1 outputted by theamplifier circuit 1. Thefirst sampling circuit 2 samples the first amplification signal V1 inputted thereto. Thefirst sampling circuit 2 is formed using e.g. a switched capacitor circuit having a sampling capacitor. - The
first sampling circuit 2 is controlled by the control signal φ3. Thefirst sampling circuit 2 samples the first amplification signal V1 duringPhase 3. Then, thefirst sampling circuit 2 holds the first amplification signal V1 sampled at the end ofPhase 3, and outputs it. - The first A/D converter 3 (ADC 1) is inputted with the output signal of the
first sampling circuit 2, which is i.e. the first amplification signal V1 sampled by thefirst sampling circuit 2 at the end ofPhase 3. The first A/D converter 3 performs A/D conversion on the first amplification signal V1 inputted thereto, and outputs a first digital signal D1. The first digital signal D1 corresponds to a result of A/D conversion on the upper bits of the input signal VIN. - The first A/
D converter 3 is controlled by the control signal φ4. The first A/D converter 3 performs A/D conversion on the first amplification signal V1 duringPhase 4. The following is based on the definition that the first A/D converter 3 has a resolution of M bits, and the first digital signal D1 is an M-bit digital signal. - The
second sampling circuit 4 is inputted with the second amplification signal V2 outputted by theamplifier circuit 1. Thesecond sampling circuit 4 samples the second amplification signal V2 inputted thereto. Thesecond sampling circuit 4 is formed using e.g. a switched capacitor circuit having a sampling capacitor. - The
second sampling circuit 4 is controlled by the control signal φ4. Thesecond sampling circuit 4 samples the second amplification signal V2 duringPhase 4. Then, thesecond sampling circuit 4 holds the second amplification signal V2 sampled at the end ofPhase 4, and outputs it. - The D/A converter 5 (DAC) is inputted with the first digital signal D1 outputted by the first A/
D converter 3. The D/A converter 5 performs D/A conversion on the first digital signal D1 inputted thereto, and outputs a first analog signal A1. The D/A converter 5 may be a capacitor DAC, or may be a resistance DAC. The D/A converter 5 has a resolution of M bits. - The
subtracter 6 is inputted with the output signal of thesecond sampling circuit 4, which is i.e. the second amplification signal V2 sampled by thesecond sampling circuit 4 at the end ofPhase 4, and the first analog signal A1 outputted by the D/A converter 5. Thesubtracter 6 subtracts the first analog signal A1 from the second amplification signal V2, and outputs a second analog signal A2. The second analog signal A2 corresponds to a residual signal obtained by subtracting the result of A/D conversion on the upper bits from the input signal Vin. - The second A/D converter 7 (ADC 2) is inputted with the second analog signal A2 outputted by the
subtracter 6. The second A/D converter 7 performs A/D conversion on the second analog signal A2 inputted thereto, and outputs a second digital signal D2. The second digital signal D2 corresponds to a result of A/D conversion on the lower bits of the input signal Vin. - The second A/
D converter 7 is controlled by control signals φ1 to φ3. The second A/D converter 7 performs A/D conversion on the second analog signal A2 duringPhases 1 to 3. The following is based on the definition that the second A/D converter 7 has a resolution of L bits, and the second digital signal D2 is an L-bit digital signal. - In the A/D converter circuit according to the present embodiment, the sum of the first digital signal D1 and second digital signal D2 is treated as a result of A/D conversion on the input signal Vin. The sum of the first digital signal D1 and second digital signal D2 should be obtained by a digital circuit in the post-stage.
- Note that each of the first A/
D converter 3 and second A/D converter 7 is e.g. a flash A/D converter, a successive approximation A/D converter, a pipeline A/D converter, a delta-sigma A/D converter, etc., but should not be limited thereto. Further, it is desirable that the resolution M of the first A/D converter 3 is smaller than the resolution L of the second A/D converter 7, which is because the first amplification signal V1 has a larger amplification error compared to the second amplification signal V2. - In the A/D converter circuit according to the present embodiment, the first A/
D converter 3, D/Aconverter 5,subtracter 6, and second A/D converter 7 operate similarly to a general sub-range A/D converter.FIG. 2 is a schematic diagram explaining the operation of a sub-range A/D converter. - In the example of
FIG. 2 , the sub-range A/D converter is formed using anADC 1 having a resolution of 2 bits (corresponding to the first A/D converter 3), a DAC (corresponding to the D/A converter 5 and subtracter 6), and anADC 2 having a resolution of 2 bits (corresponding to the second A/D converter 7). TheADC 1 has a full scale of −Vref to Vref, and theADC 2 has a full scale of 0 to Vref/2. - When this sub-range A/D converter is inputted with the input signal Vin, the
ADC 1 performs coarse 2-bit A/D conversion first. In the example ofFIG. 2 , theADC 1 outputs [11] corresponding to a value equal to or greater than Vref/2 and equal to or less than Vref, as a result of A/D conversion. The output of theADC 1 corresponds to a result of A/D conversion on the upper bits of the input signal Vin. - Next, the DAC performs residual calculation of subtracting the result of A/D conversion performed by the
ADC 1 from the input signal Vin. The amount to be subtracted by the DAC is determined by the result of A/D conversion performed by theADC 1. The DAC performs residual calculation so that the residual value falls within the full scale of theADC 2. - In the example of
FIG. 2 , the DAC subtracts Vref/2 from Vin based on [11] as a result of A/D conversion. Accordingly, theADC 2 is inputted with Vin−Vref/2. - Then, the
ADC 2 performs fine 2-bit A/D conversion. In the example ofFIG. 2 , theADC 2 outputs [10] corresponding to a value equal to or greater than Vref/4 and equal to or less than 3Vref/8, as a result of A/D conversion. The output of theADC 2 corresponds to a result of A/D conversion on the lower bits of the input signal Vin. - Consequently, the result of A/D conversion performed by this sub-range A/D converter on the input signal Vin becomes As mentioned above, in the A/D converter circuit according to the present embodiment, the first A/
D converter 3 operates as theADC 1, the combination of the D/A converter 5 andsubtracter 6 operates as the DAC, and the second A/D converter 7 operates as theADC 2. - Next, the operation of the A/D converter circuit according to the present embodiment will be explained referring to
FIGS. 3 and 4 .FIG. 3 is a diagram showing an example of a pipeline A/D converter having the A/D converter circuit according to the present embodiment. In the example ofFIG. 3 , the pipeline A/D converter has two pipeline stages, which are i.e. a first stage and a second stage. - The first stage has a sample-and-hold circuit 8 (S/H 1), a sample-and-hold circuit 9 (S/H 2), an A/D converter 10 (ADC 0), a D/A converter 11 (DAC), a
subtracter 12, and theamplifier circuit 1 of the A/D converter circuit according to the present embodiment. - The sample-and-
hold circuits 8 and 9 are connected in parallel and controlled by the control signal φ to sample an input signal VIN of the pipeline A/D converter duringPhase 1. Then, each of the sample-and-hold circuits 8 and 9 holds the sampled input signal VIN and outputs it. - The A/
D converter 10 is controlled by the control signal φ2, and performs A/D conversion on the input signal VIN sampled by the sample-and-hold circuit 8 to output a digital signal D0 duringPhase 2. It is defined that the A/D converter 10 has a resolution of K bits, and the digital signal D0 is a K-bit digital signal. The A/D converter 10 is e.g. a flash A/D converter, a successive approximation A/D converter, etc., but should not be limited thereto. - The D/
A converter 11 performs D/A conversion on the digital signal D0 outputted by the A/D converter 10, and outputs an analog signal A0. - The
subtracter 12 outputs a residual signal by subtracting the analog signal A0 outputted by the D/A converter 11 from the input signal VIN sampled by the sample-and-hold circuit 9. The residual signal outputted by thesubtracter 12 corresponds to the input signal Vin of theamplifier circuit 1 according to the present embodiment. -
FIG. 4 is a timing chart showing the operation of the pipeline A/D converter ofFIG. 3 . As shown inFIG. 4 , the pipeline A/D converter ofFIG. 3 has fourPhases 1 to 4 corresponding to the control signals φ1 to φ4, respectively. That is, Phases 1 to 4 correspond to one cycle operation. In the following, operation to be performed when the first cycle is started will be explained as an example. - First, in
Phase 1, each of the sample-and-hold circuits 8 and 9 in the first stage samples the input signal VIN. Each of the sample-and-hold circuits 8 and 9 holds the input signal VIN sampled at the end ofPhase 1. - Next, in
Phase 2, the A/D converter 10 (ADC 0) performs A/D conversion on the input signal VIN outputted by the sample-and-hold circuit 8, and outputs the K-bit digital signal D0. Further, the D/A converter 11 performs D/A conversion on the digital signal D0, and outputs the analog signal A0. Further, thesubtracter 12 subtracts the analog signal A0 from the input signal VIN outputted by the sample-and-hold circuit 9, and outputs a residual signal Vin. The sample-and-hold circuit 9 holds the residual signal Vin at the end ofPhase 2. - After that, in
Phase 3, theamplifier circuit 1 amplifies the residual signal Vin coarsely, and outputs the first amplification signal V1. In the example ofFIG. 3 , since the A/D converter 10 in the first stage has a resolution of K bits, theamplifier circuit 1 has an amplification factor of 2K. In this case, the first amplification signal V1 is a signal made coarsely approach to Vin×2K. - In addition, in
Phase 3, thefirst sampling circuit 2 in the second stage samples the first amplification signal V1 outputted by theamplifier circuit 1. Thefirst sampling circuit 2 holds the first amplification signal V1 sampled at the end ofPhase 3. - Then, in
Phase 4, theamplifier circuit 1 amplifies the residual signal Vin finely (with high accuracy), and outputs the second amplification signal V2. Further, thesecond sampling circuit 4 in the second stage samples the second amplification signal V2 outputted by theamplifier circuit 1. Thesecond sampling circuit 4 holds the second amplification signal V2 sampled at the end ofPhase 4. - In addition, in
Phase 4, the first A/D converter 3 (ADC 1) in the second stage performs A/D conversion on the first amplification signal V1 outputted by thefirst sampling circuit 2, and outputs the M-bit first digital signal D1. The first digital signal D1 corresponds to a result of A/D conversion on the upper bits in the second stage. Further, the D/A converter 5 performs D/A conversion on the digital signal D1, and outputs the first analog signal A1. Further, thesubtracter 6 subtracts the first analog signal A1 from the second amplification signal V2 outputted by thesecond sampling circuit 4, and outputs the second analog signal A2. The second analog signal A2 corresponds to a residual signal in the second stage. Thesecond sampling circuit 4 holds the analog signal A2 at the end ofPhase 4. - Operation for the first cycle ends at this point, and operation for the second cycle starts. Operation in the first stage is performed similarly to the first cycle. On the other hand, in the second stage, in the first to third phases of the second cycle, the second A/D converter 7 (ADC 2) performs A/D conversion on the second analog signal A2 outputted by the
second sampling circuit 4, and outputs the L-bit second digital signal D2. The second digital signal D2 corresponds to a result of A/D conversion on the lower bits in the second stage. - At this point, the A/D conversion performed on the input signal VIN by the pipeline A/D converter of
FIG. 3 for the first cycle ends. The input signal VIN is converted into N (=K+M+L) bits through the A/D conversion. - Subsequent operation in the second stage is performed similarly to the first cycle. For example, in
Phase 3, thefirst sampling circuit 2 samples the first amplification signal V1 depending on the input signal VIN in the second cycle. - As explained above, in the A/D converter circuit according to the present embodiment, the first A/
D converter 3 performs A/D conversion on the upper bits inPhase 4, and the second A/D converter 7 performs A/D conversion on the lower bits inPhases 1 to 3. That is, the A/D converter circuit according to the present embodiment can perform A/D conversion continuously duringPhases 1 to 4. - This is because the first amplification signal V1 is sampled by the
first sampling circuit 2 in the operation phase different from the operation phase for thesecond sampling circuit 4 to sample the second amplification signal V2. As shown inFIG. 4 , the first amplification signal V1 is sampled inPhase 3, and the second amplification signal V2 is sampled inPhase 4. - As a result, the A/D converter circuit according to the present embodiment does not suffer from overhead in the sampling period. Therefore, in the A/D converter circuit according to the present embodiment, the time during which A/D conversion can be performed (available conversion time) gets longer compared to a conventional A/D converter circuit which cannot perform A/D conversion during the sampling period.
- In a conventional A/D converter circuit having a short available conversion time, when an A/D converter (e.g. successive approximation A/D converter) requiring long A/D conversion time is used as the second A/
D converter 7, it is necessary, due to the lack of available conversion time, to lengthen the available conversion time in order to secure the A/D conversion time for the second A/D converter 7. As a result, the conventional A/D converter circuit requires long A/D conversion time. - On the other hand, in the A/D converter circuit according to the present embodiment does not cause the lack of available conversion time even when an A/D converter requiring long A/D conversion time is used as the second A/
D converter 7. Consequently, the A/D conversion time required for the A/D converter circuit according to the present embodiment becomes shorter than that for the conventional A/D converter circuit. Therefore, the A/D converter circuit according to the present embodiment can perform A/D conversion at high speed in a short A/D conversion time. - Further, in the conventional A/D converter circuit, an amplification phase and a conversion phase are provided by two clock signals having a duty ratio of 1:1. In such an A/D converter circuit, the conversion phase can be lengthened equivalently by changing the duty ratio of the clock signals. That is, the available conversion time can be lengthened without changing the time for the first cycle.
- However, there is a problem that a duty changing circuit for changing the duty ratio of the clock signals consumes a large amount of power. On the other hand, in the present embodiment, the available conversion time can be lengthened without changing the duty ratio of the clock signals. Therefore, the present embodiment makes it possible to restrain the increase in power consumption while increasing the speed of the A/D converter circuit.
- Note that, in the above explanation, the second A/
D converter 7 performs A/D conversion duringPhases 1 to 3, but the second A/D converter 7 may perform A/D conversion during a partial period inPhases 1 to 3. Further, the A/D converter 10 ofFIG. 3 may perform A/D conversion not inPhase 2 but at the start ofPhase 3. In this case, the sample-and-hold circuits 8 and 9 may sample the input signal VIN inPhases - Hereinafter, examples of the
amplifier circuit 1 will be explained. - A first example of the
amplifier circuit 1 will be explained referring toFIGS. 5 and 6 .FIG. 5 is a diagram showing an example of theamplifier circuit 1 according to the present example. As shown inFIG. 5 , theamplifier circuit 1 is a successive approximation amplifier having an operational amplifier, and has anoperational amplifier 13, a feedback capacitor CF, a switch SW1, acomparator 14, alogic circuit 15, and aDAC 16. Thecomparator 14,logic circuit 15, andDAC 16 are included in a successive approximation circuit. - The
operational amplifier 13 has an inverting input terminal connected to a node N1, a non-inverting input terminal connected to a reference voltage line, and an output terminal connected to one end of the switch SW1. The node N1 corresponds to an input terminal of theamplifier circuit 1 inputted with the input signal Vin. The reference voltage line is e.g. a ground line. The gain of theoperational amplifier 13 is defined as A. - The feedback capacitor CF has one end connected to the node N1 and the other end connected to a node N2.
- The node N2 corresponds to an output terminal of the
amplifier circuit 1 outputting the amplification signals V1 and V2. - The switch SW1 has one end connected to the output terminal of the
operational amplifier 13 and the other end connected to the node N2. The switch SW1 is controlled by the control signal φ3, and turned on duringPhase 3. - The
comparator 14 has one end connected to the node N1 and the other end connected to a reference voltage line. Thecomparator 14 outputs, from its output terminal, a result of comparison between a voltage VX of the node N1 and a reference voltage. - The
logic circuit 15 has an input terminal connected to the output terminal of thecomparator 14 and an output terminal connected to an input terminal of theDAC 16. Thelogic circuit 15 controls theDAC 16 depending on the comparison result inputted from thecomparator 14. Thelogic circuit 15 is controlled by a control signal φ5. The control signal φ5 is a clock signal turning on and off at predetermined time intervals duringPhase 4. - The
DAC 16 has an input terminal connected to the output terminal of thelogic circuit 15 and an output terminal connected to the node N2. TheDAC 16 is controlled by thelogic circuit 15, and outputs an analog signal depending on the comparison result, by which the output signal of the node N2 is controlled. -
FIG. 6 is a diagram showing the operation of theamplifier circuit 1 ofFIG. 5 . First, inPhase 3, the switch SW1 is turned on, and the input signal Vin is amplified by theoperational amplifier 13. As shown inFIG. 6 , an output signal Vout of theamplifier circuit 1 at the end ofPhase 3 is sampled by thefirst sampling circuit 2 as the first amplification signal V1. Due to the nature of the operational amplifier, the first amplification signal V1 has an amplification error of Vout/A from the ideal amplification signal Vin×Gv. - Next, in
Phase 4, the switch SW1 is turned off, thelogic circuit 15 is inputted with the control signal φ5, and the successive approximation circuit performs successive approximation. That is, thecomparator 14 compares the voltage VX with the reference voltage, thelogic circuit 15 controls theDAC 16 to make the voltage VX approach to the reference voltage based on the comparison result, and theDAC 16 outputs an analog signal to control the output signal Vout. - The successive approximation circuit repeats such successive approximation each time the control signal φ5 becomes H. This makes the voltage VX approach asymptotically to the reference voltage, and consequently, the output signal Vout approaches asymptotically to the ideal amplification signal Vin×Gv. Then, the output signal Vout at the end of
Phase 4 is sampled by thesecond sampling circuit 4 as the second amplification signal V2. - The amplification error between the second amplification signal V2 and the ideal amplification signal Vin×Gv is settled within the LSB of the
DAC 16. This amplification error becomes smaller than the amplification error (Vout/A) in the first amplification signal V1. - As explained above, the
amplifier circuit 1 can be formed using theoperational amplifier 13 having a successive approximation circuit. The first amplification signal V1 becomes the output signal Vout before undergoing the successive approximation, and the second amplification signal V2 becomes the output signal Vout after undergoing the successive approximation. - Note that, in the present example, the control signal φ5 may be a clock signal different from the control signal φ4, or may be a clock signal generated from the control signal φ4.
- A second example of the
amplifier circuit 1 will be explained referring toFIGS. 7 and 8 .FIG. 7 is a diagram showing an example of theamplifier circuit 1 according to the present example. As shown inFIG. 7 , theamplifier circuit 1 is a CLS (Correlated Level Shifting) amplifier having an operational amplifier, and has theoperational amplifier 13, the feedback capacitor CF, a level-shifting capacitor CCLS, and switches SW1 to SW3. Theoperational amplifier 13, switch SW1, and feedback capacitor CF function similarly to the first example. - The switch SW2 has one end connected to the output terminal of the
operational amplifier 13 and the other end connected to a node N3. The switch SW2 is controlled by the control signal φ4, and turned on duringPhase 4. - The switch SW3 has one end connected to the node N3 and the other end connected to a reference voltage line. The switch SW3 is controlled by the control signal φ3, and turned on during
Phase 3. - The level-shifting capacitor CCLS has one end connected to the node N3 and the other end connected to the node N2. The level-shifting capacitor CCLS shifts the level of the output signal Vout of the
amplifier circuit 1 inPhase 4. -
FIG. 8 is a diagram showing the operation of theamplifier circuit 1 ofFIG. 7 . First, inPhase 3, the switch SW1 is turned on, and the input signal Vin is amplified by theoperational amplifier 13. As shown inFIG. 8 , the output signal Vout of theamplifier circuit 1 at the end ofPhase 3 is sampled by thefirst sampling circuit 2 as the first amplification signal V1. Due to the nature of theoperational amplifier 13, the first amplification signal V1 has an amplification error of Vout/A from the ideal amplification signal Vin×Gv. - Next, in
Phase 4, the switch SW1 is turned off, and the switches SW2 and SW3 are turned on. As a result, the level of the output signal Vout is shifted as shown inFIG. 8 . After that, based on the output signal Vout after undergoing the level-shifting, theoperational amplifier 13 amplifies the input signal Vin. This makes the output signal Vout approach asymptotically to the ideal amplification signal Vin×Gv. Then, the output signal Vout at the end ofPhase 4 is sampled by thesecond sampling circuit 4 as the second amplification signal V2. - The second amplification signal V2 has an amplification error of Vin/A2 from the ideal amplification signal Vin×Gv. This amplification error becomes smaller than the amplification error (Vout/A) in the first amplification signal V1.
- As explained above, the
amplifier circuit 1 can be formed using a CLS amplifier. The first amplification signal V1 becomes the output signal Vout before undergoing the level-shifting, and the second amplification signal V2 becomes the output signal Vout after undergoing the level-shifting. - A third example of the
amplifier circuit 1 will be explained referring toFIGS. 9 and 10 . In the first and second examples, theamplifier circuit 1 has two amplification phases, and amplifies the input signal Vin in two stages. On the other hand, in the present example, theamplifier circuit 1 is a general inverting amplifier which amplifies the input signal Vin in one stage. -
FIG. 9 is a diagram showing an example of theamplifier circuit 1 according to the present example. As shown inFIG. 9 , theamplifier circuit 1 has theoperational amplifier 13 and feedback capacitor CF. Theoperational amplifier 13 and feedback capacitor CF function similarly to the second example. -
FIG. 10 is a diagram showing the operation of theamplifier circuit 1 ofFIG. 9 . In the present example, as shown inFIG. 10 , the output signal Vout1 at the end ofPhase 3 is sampled by thefirst sampling circuit 2 as the first amplification signal V1. Further, the output signal Vout2 at the end ofPhase 4 is sampled by thesecond sampling circuit 4 as the second amplification signal V2. As will be understood fromFIG. 10 , the amplification error in the second amplification signal V2 becomes smaller than the amplification error in the first amplification signal V1. - As explained above, the
amplifier circuit 1 can be formed using a general amplifier circuit having theoperational amplifier 13. In this case, the first amplification signal V1 has an amplification error of Vout1/A, and the second amplification signal V2 has an amplification error of Vout2/A2. - A fourth example of the
amplifier circuit 1 will be explained referring toFIG. 11 . In the first to third examples, theamplifier circuit 1 has one amplifier (operational amplifier). On the other hand, in the present example, theamplifier circuit 1 has two amplifiers.FIG. 11 is a diagram showing an example of theamplifier circuit 1 according to the present example. As shown inFIG. 11 , theamplifier circuit 1 hasamplifiers - The amplifier 17 (first amplifier) is an amplifier arbitrarily selected, such as an operational amplifier. The
amplifier 17 is inputted with the input signal Vin, amplifies the input signal Vin inputted thereto, and outputs the output signal Vout. The output signal Vout of theamplifier 17 at the end ofPhase 3 is sampled by thefirst sampling circuit 2 as the first amplification signal V1. - The amplifier 18 (second amplifier) is an amplifier arbitrarily selected, such as an operational amplifier. The
amplifier 18 is inputted with the input signal Vin, amplifies the input signal Vin inputted thereto, and outputs the output signal Vout. The output signal Vout of theamplifier 18 at the end ofPhase 4 is sampled by thesecond sampling circuit 4 as the second amplification signal V2. - The
amplifiers amplifiers amplifier 18 is higher than that of theamplifier 17. - As explained above, the
amplifier circuit 1 can be formed using twoamplifiers - An A/D converter circuit according to a second embodiment will be explained referring to
FIGS. 12 and 13 .FIG. 12 is a diagram showing an example of the A/D converter circuit according to the present embodiment. As shown inFIG. 12 , the A/D converter circuit according to the present embodiment has acontrol circuit 19. The other components are similar to those of the first embodiment. - The
control circuit 19 is inputted with a result of A/D conversion (first digital signal D1) from the first A/D converter 3. Thecontrol circuit 19 controls theamplifier circuit 1 based on the first digital signal D1 inputted thereto. - As mentioned above, when the
amplifier circuit 1 is formed using an operational amplifier, the output signal Vout of theamplifier circuit 1 has an amplification error of Vout/A. Therefore, as shown inFIG. 13 , the amplification error in the first amplification signal V1 becomes V1/A. - Since the first digital signal D1 is a result of A/D conversion on the first amplification signal V1, the amplification error V1/A can be estimated based on the first digital signal D1. For example, in the example of
FIG. 13 , when the first digital signal D1 is [11], the amplification error is equal to or greater than Vref/2A and equal to or less than Vref/A. - Accordingly, the
control circuit 19 controls theamplifier circuit 1 based on the first digital signal D1. For example, in the case of theamplifier circuit 1 according to the first example, the frequency of successive approximation may be controlled based on the first digital signal D1. - Concretely, the
control circuit 19 is required to increase the frequency of successive approximation as the amplification error estimated from the first digital signal D1 becomes larger, and reduce the frequency of successive approximation as the amplification error becomes smaller. This makes it possible to appropriately control the frequency of successive approximation of theamplifier circuit 1 and prevent theamplifier circuit 1 from performing unnecessary successive approximation, which leads to the reduction in the power consumption of theamplifier circuit 1. - Further, in the case of the
amplifier circuit 1 according to the second and third examples, driving power of theoperational amplifier 13 may be controlled based on the first digital signal D1. - Concretely, the
control circuit 19 is required to increase the driving power as the amplification error estimated from the first digital signal D1 becomes larger, and reduce the driving power as the amplification error becomes smaller. This makes it possible to make the amplification error in the second amplification signal V2 further smaller, which consequently improves the accuracy of A/D conversion performed by the A/D converter circuit. - Note that the
control circuit 19 may control theamplifier circuit 1 based on the first amplification signal V1 sampled by thefirst sampling circuit 2. The method of this control is as described above. - An A/D converter according to a third embodiment will be explained referring to
FIG. 14 . In the present embodiment, explanation will be given on an A/D converter circuit having the first A/D converter 3 which is used also as the second A/D converter 7.FIG. 14 is a diagram showing an example of the A/D converter circuit according to the present embodiment. As shown inFIG. 14 , this A/D converter circuit has a switch SW and does not have the second A/D converter 7. The other components are similar to those of the first embodiment. Hereinafter, differences from the first embodiment will be mainly explained. - The switch SW has one end connected to an input terminal of the first A/
D converter 3 and the other end connected to an output terminal of thefirst sampling circuit 2 or an output terminal of thesubtracter 6. The switch SW is a switch capable of connecting the input terminal of the first A/D converter 3 to an output terminal of thefirst sampling circuit 2 or an output terminal of thesubtracter 6. The switch SW is controlled by the control signals φ1 to φ4. - The switch SW is connected to the output terminal of the
first sampling circuit 2 duringPhase 4. Accordingly, the output terminal of thefirst sampling circuit 2 is connected to the input terminal of the first A/D converter 3. DuringPhase 4, the first A/D converter 3 is inputted with the first amplification signal V1 from thefirst sampling circuit 2, performs A/D conversion on the first amplification signal V1 inputted thereto, and outputs the first digital signal D1. The outputted first digital signal D1 is inputted into the D/A converter 5. This corresponds to the operation of the first A/D converter 3 in the first embodiment. - The switch SW is connected to the output terminal of the
subtracter 6 duringPhases 1 to 3. Accordingly, the output terminal of thesubtracter 6 is connected to the input terminal of the first A/D converter 3. DuringPhases 1 to 3, the first A/D converter 3 is inputted with the second analog signal A2 from thesubtracter 6, performs A/D conversion on the second analog signal A2 inputted thereto, and outputs the second digital signal D2. This corresponds to the operation of the second A/D converter 7 in the first embodiment. - In this way, in the present embodiment, the first A/
D converter 3 performs the operation of the first A/D converter 3 or second A/D converter 7 in the first embodiment depending on the switching of the switch SW. This enables one A/D converter to perform A/D conversion similarly to the first embodiment. According to the present embodiment, reducing one A/D converter makes it possible to reduce the circuit area of the A/D converter circuit. - An A/D converter circuit according to a fourth embodiment will be explained referring to
FIGS. 15 and 16 . In the present embodiment, explanation will be given on an A/D converter circuit when the second A/D converter 7 has redundancy. - In the A/D converter circuit in each of the above embodiments, there is a likelihood that an A/D conversion error arises in the first digital signal D1 depending on the amplification error in the first amplification signal V1. Such an A/D conversion error can be cancelled by letting the second A/
D converter 7 have redundancy. In the present embodiment, the second A/D converter 7 has a redundancy of 0.5 bits. Here,FIG. 15 is a diagram explaining the operation of a sub-range A/D converter when theADC 2 has redundancy. - In the example of
FIG. 15 , the sub-range A/D converter is formed using anADC 1 having a resolution of 2 bits (corresponding to the first A/D converter 3), a DAC (corresponding to the D/A converter 5 and subtracter 6), and anADC 2 having a resolution of 2.5 bits (corresponding to the second A/D converter 7). TheADC 1 has a full scale of −Vref to Vref, and theADC 2 has a full scale of −Vref/4 to 3Vref/4. That is, the full scale of theADC 2 is broader than that ofFIG. 2 by the LSB of theADC 1. - In this way, when setting the full scale of the
ADC 2 to bring an over range, theADC 2 obtains redundancy. In the example ofFIG. 15 , the A/D converter circuit can normally perform A/D conversion on the input signal Vin as long as an amplification error Verrormax in the first amplification signal V1 satisfies the following formula. -
-
FIG. 16 is a diagram showing an example of the A/D converter circuit according to the present embodiment. In the example ofFIG. 16 , the second A/D converter 7 is a successive approximation A/D converter. Further, the first A/D converter 3 has a resolution of 2 bits, and the second A/D converter 7 has a resolution of 2.5 bits. - The
DAC 5 andsubtracter 6 are formed using a capacitor DAC having capacitors C1 to C6. Each of the capacitors C1 and C2 has a capacitance value of C, the capacitor C3 has a capacitance value of 2C, each of the capacitors C4 and C5 has a capacitance value of 4C, and the capacitor C6 has a capacitance value of 8C. In the example ofFIG. 16 , redundancy is realized by the capacitors C4 and C5 each having a capacitance value of 4C. - The second A/
D converter 7 has acomparator 71 and a logic circuit 72. - The
comparator 71 has one input terminal connected to the output terminal of thesecond sampling circuit 4, the other input terminal connected to an output terminal of the capacitor DAC, and an output terminal connected to the logic circuit 72. Thecomparator 71 outputs a result of comparison between the second amplification signal V2 inputted from one input terminal and the output signal (second analog signal A2) of the capacitor DAC inputted from the other input terminal. - The logic circuit 72 is inputted with the comparison result from the
comparator 71, and outputs the second digital signal D2 depending on the comparison result. The second digital signal D2 outputted by the logic circuit 72 is fed back to the capacitor DAC. - In the A/D converter circuit of
FIG. 16 , the result of A/D conversion performed by the first A/D converter 3 (first digital signal D1) is written in the capacitors C5 and C6 at the end ofPhase 3. After that, inPhase 4, thecomparator 71 compares the second analog signal A2 with the second amplification signal V2, and the logic circuit 72 rewrites the second digital signal D2 depending on the comparison result. The second A/D converter 7 repeatedly rewrites the second digital signal D2 until the second analog signal A2 becomes smaller than the second amplification signal V2, and the second digital signal D2 finally obtained is treated as the result of A/D conversion. In the example ofFIG. 16 , DADC, which is the result of A/D conversion on the input signal Vin, can be expressed by the following formula. -
D ADC=8*D 1[1]+4*D 1[0]+4*D 2[2]+2*D 2[1]+D 2[0] (2) - In Formula (2), D1[i] represents a value of the i-th bit of the first digital signal D1, and D2[j] represents a value of the j-th bit of the second digital signal D2. Such a calculation is performed by a digital circuit provided in the post-stage of the A/D converter circuit. The digital circuit performing the calculation of Formula (2) can be formed using a full adder and a half adder.
- According to the present embodiment, redundancy of the second A/
D converter 7 makes it possible to cancel the A/D conversion error caused by the amplification error in the first amplification signal V1. Further, range mismatch between the D/A converter 5 and second A/D converter 7 can be prevented. - Furthermore, as shown in
FIG. 16 , using a successive approximation A/D converter as the second A/D converter 7 makes it possible to reduce the power consumption of the second A/D converter 7. - A wireless communication device according to a fifth embodiment will be explained referring to
FIG. 17 . The wireless communication device according to the present embodiment has the A/D converter circuit according to the first embodiment.FIG. 17 is a diagram showing an example of a wireless communication device according to the present embodiment. As shown inFIG. 17 , the wireless communication device according to the present embodiment has a BB integratedcircuit 110, an RFintegrated circuit 120, and anantenna 130. - The BB integrated
circuit 110 has acontrol circuit 111, a transmittingprocessing circuit 112, a receivingprocessing circuit 113, a D/A converter (DAC) 114, and an A/D converter (ADC) 115. Thecontrol circuit 111, transmittingprocessing circuit 112, and receivingprocessing circuit 113 in the BB integratedcircuit 110 perform digital signal processing. The digital transmission signal generated by the transmittingprocessing circuit 112 is converted into an analog transmission signal by the D/A converter 114 and inputted into the RFintegrated circuit 120. When the D/A converter 114 is omitted, the analog transmission signal can be generated by inputting the digital transmission signal directly into the RFintegrated circuit 120 and modulating a PLL (phase-locked loop) circuit directly. The A/D converter 115 ofFIG. 17 is the A/D converter circuit according to the first embodiment. - The
control circuit 111 performs processing of e.g. MAC (Media Access Control) layer. Thecontrol circuit 111 may perform processing of a layer higher than the MAC layer in the network hierarchy. Further, thecontrol circuit 111 may perform processing concerning MIMO (Multi-Input Multi-Output). For example, thecontrol circuit 111 may perform processing for estimating a propagation channel, calculating transmission weight, separating a stream, etc. - The transmitting
processing circuit 112 generates a digital transmission signal. The receivingprocessing circuit 113 performs demodulation and decoding, and then analyzes a synchronization word, a preamble, and a physical header. - The RF
integrated circuit 120 has atransmitter circuit 121 and areceiver circuit 122. Although not shown in the drawing, thetransmitter circuit 121 has a transmitting filter for extracting a signal in the transmission band, a mixer for up-converting the signal after passing the transmitting filter into a radio frequency, an amplifier for amplifying the up-converted signal. - In the example of
FIG. 17 , the wireless communication device has oneantenna 130, but it may have a plurality ofantennas 130. - When transmitting/receiving a radio signal by each
antenna 130, the RFintegrated circuit 120 may have a switch for connecting any one of thetransmitter circuit 121 andreceiver circuit 122 to the antenna. Such a switch makes it possible to connect the antenna to thetransmitter circuit 121 at the time of transmission, and connect the antenna to thereceiver circuit 122 at the time of reception. - The RF
integrated circuit 120 and BB integratedcircuit 110 shown inFIG. 17 may be formed on one chip, or may be formed on separate chips respectively. Further, it is also possible to use a discrete part to form a part of the RFintegrated circuit 120 and BB integratedcircuit 110 while using one or more chips to form the rest thereof. - Further, the RF
integrated circuit 120 and BB integratedcircuit 110 may be formed using a wireless device which can be reconfigured based on software. In this case, a digital signal processor should be used to realize the functions of the RFintegrated circuit 120 and BB integratedcircuit 110 by software. In this case, the wireless communication device shown inFIG. 17 includes a bus, a processor, and an external interface. The processor and external interface are connected to each other through the bus, and firmware is executed by the processor. The firmware can be updated by a computer program. Due to the firmware executed by the processor, the RFintegrated circuit 120 and BB integratedcircuit 110 shown inFIG. 17 can perform processing. - The wireless communication device shown in
FIG. 17 can be applied to: a stationary wireless communication device such as an access point, a wireless router, and a computer; a portable wireless terminal such as a smartphone and a cellular phone; a peripheral device such as a mouse and a keyboard for wirelessly communicating with a host device; a card-type member (such as an IC card, a memory card, and a SIM card) having wireless communication functions; and a wearable terminal for wirelessly communicating biological information. - The system of wireless communication between the wireless communication devices as shown in
FIG. 17 should not be particularly limited, and various types of communication systems such as post-third-generation cellular communication, wireless LAN, Bluetooth (registered trademark), and proximity wireless communication can be used. - Further, the A/
D converter 115 ofFIG. 17 may be the A/D converter circuit according to the second embodiment, may be the A/D converter circuit according to the third embodiment, or may be the A/D converter circuit according to the fourth embodiment. - While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Claims (20)
1. An A/D converter circuit comprising:
an amplifier circuit to amplify an input signal and output a first amplification signal and a second amplification signal, the second amplification signal having an amplification error smaller than that in the first amplification signal;
a first sampling circuit to sample the first amplification signal;
a first A/D converter to perform A/D conversion on the first amplification signal sampled by the first sampling circuit and output a first digital signal;
a second sampling circuit to sample the second amplification signal;
a D/A converter to perform D/A conversion on the first digital signal and output a first analog signal;
a subtracter to subtract the first analog signal from the second amplification signal sampled by the second sampling circuit and output a second analog signal; and
a second A/D converter to perform A/D conversion on the second analog signal and output a second digital signal.
2. The A/D converter circuit of claim 1 , wherein the first sampling circuit samples the first amplification signal in an operation phase different from an operation phase for the second sampling circuit to sample the second amplification signal.
3. The A/D converter circuit of claim 1 , wherein the amplifier circuit is a successive approximation amplifier comprising an operational amplifier.
4. The A/D converter circuit of claim 3 ,
wherein the first amplification signal is an output signal obtained before the successive approximation amplifier performs successive approximation, and
the second amplification signal is an output signal obtained after the successive approximation amplifier performs successive approximation.
5. The A/D converter circuit of claim 1 , wherein the amplifier circuit is a CLS amplifier having an operational amplifier.
6. The A/D converter circuit of claim 5 ,
wherein the first amplification signal is an output signal obtained before the CLS amplifier performs level-shifting, and
the second amplification signal is an output signal obtained after the CLS amplifier performs level-shifting.
7. The A/D converter circuit of claim 1 , wherein the amplifier circuit is an inverting amplifier comprising an operational amplifier.
8. The A/D converter circuit of claim 1 ,
wherein the amplifier circuit comprises a first amplifier and a second amplifier,
the first amplification signal is an output signal of the first amplifier, and
the second amplification signal is an output signal of the second amplifier.
9. The A/D converter circuit of claim 1 , wherein at least one of frequency of operation of the amplifier circuit and driving power of the amplifier circuit is controlled by the first digital signal.
10. The A/D converter circuit of claim 1 , wherein the first A/D converter is used also as the second A/D converter.
11. The A/D converter circuit of claim 10 further comprising a switch to be capable of connecting an input terminal of the first A/D converter to an output terminal of the first sampling circuit and an output terminal of the subtracter.
12. The A/D converter circuit of claim 1 , wherein the second A/D converter has redundancy.
13. A pipeline A/D converter comprising an A/D converter circuit,
the A/D converter circuit comprises:
an amplifier circuit to amplify an input signal and output a first amplification signal and a second amplification signal, the second amplification signal having an amplification error smaller than that in the first amplification signal;
a first sampling circuit to sample the first amplification signal;
a first A/D converter to perform A/D conversion on the first amplification signal sampled by the first sampling circuit and output a first digital signal;
a second sampling circuit to sample the second amplification signal;
a D/A converter to perform D/A conversion on the first digital signal and output a first analog signal;
a subtracter to subtract the first analog signal from the second amplification signal sampled by the second sampling circuit and output a second analog signal; and
a second A/D converter to perform A/D conversion on the second analog signal and output a second digital signal.
14. A wireless communication device comprising an A/D converter circuit,
the A/D converter circuit comprising:
an amplifier circuit to amplify an input signal and output a first amplification signal and a second amplification signal, the second amplification signal having an amplification error smaller than that in the first amplification signal;
a first sampling circuit to sample the first amplification signal;
a first A/D converter to perform A/D conversion on the first amplification signal sampled by the first sampling circuit and output a first digital signal;
a second sampling circuit to sample the second amplification signal;
a D/A converter to perform D/A conversion on the first digital signal and output a first analog signal;
a subtracter to subtract the first analog signal from the second amplification signal sampled by the second sampling circuit and output a second analog signal; and
a second A/D converter to perform A/D conversion on the second analog signal and output a second digital signal.
15. The wireless communication device of claim 14 , wherein the first sampling circuit samples the first amplification signal in an operation phase different from an operation phase for the second sampling circuit to sample the second amplification signal.
16. The wireless communication device of claim 14 , wherein the amplifier circuit is a successive approximation amplifier comprising an operational amplifier.
17. The wireless communication device of claim 16 ,
wherein the first amplification signal is an output signal obtained before the successive approximation amplifier performs successive approximation, and
the second amplification signal is an output signal obtained after the successive approximation amplifier performs successive approximation.
18. The wireless communication device of claim 14 , wherein the amplifier circuit is a CLS amplifier comprising an operational amplifier.
19. The wireless communication device of claim 18 ,
wherein the first amplification signal is an output signal obtained before the CLS amplifier performs level-shifting, and
the second amplification signal is an output signal obtained after the CLS amplifier performs level-shifting.
20. The wireless communication device of claim 14 , wherein the amplifier circuit is an inverting amplifier comprising an operational amplifier.
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