US20160254006A1 - Multistage IIR Filter and Parallelized Filtering of Data with Same - Google Patents

Multistage IIR Filter and Parallelized Filtering of Data with Same Download PDF

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US20160254006A1
US20160254006A1 US13/909,723 US201313909723A US2016254006A1 US 20160254006 A1 US20160254006 A1 US 20160254006A1 US 201313909723 A US201313909723 A US 201313909723A US 2016254006 A1 US2016254006 A1 US 2016254006A1
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filter
stages
multistage
values
memory
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Khushbu P. Rathi
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Dolby Laboratories Licensing Corp
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Dolby Laboratories Licensing Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/04—Recursive filters
    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10L—SPEECH ANALYSIS TECHNIQUES OR SPEECH SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING TECHNIQUES; SPEECH OR AUDIO CODING OR DECODING
    • G10L19/00—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis
    • G10L19/04—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis using predictive techniques
    • G10L19/26—Pre-filtering or post-filtering
    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10L—SPEECH ANALYSIS TECHNIQUES OR SPEECH SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING TECHNIQUES; SPEECH OR AUDIO CODING OR DECODING
    • G10L19/00—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis
    • G10L19/0017—Lossless audio signal coding; Perfect reconstruction of coded audio signal by transmission of coding error
    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10L—SPEECH ANALYSIS TECHNIQUES OR SPEECH SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING TECHNIQUES; SPEECH OR AUDIO CODING OR DECODING
    • G10L19/00—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis
    • G10L19/008—Multichannel audio signal coding or decoding using interchannel correlation to reduce redundancy, e.g. joint-stereo, intensity-coding or matrixing
    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10L—SPEECH ANALYSIS TECHNIQUES OR SPEECH SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING TECHNIQUES; SPEECH OR AUDIO CODING OR DECODING
    • G10L19/00—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis
    • G10L19/04—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis using predictive techniques
    • G10L19/16—Vocoder architecture
    • G10L19/167—Audio streaming, i.e. formatting and decoding of an encoded audio signal representation into a data stream for transmission or storage purposes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H2017/0072—Theoretical filter design
    • H03H2017/009—Theoretical filter design of IIR filters

Definitions

  • the invention pertains to multistage filters comprising biquadratic filter stages, and to parallelized filtering of data (e.g., audio data) using such filters.
  • Some embodiments of the invention are methods, systems, and processors for filtering audio data (using a multistage filter comprising biquadratic filter stages) during encoding or decoding of the data in accordance with one of the formats known as Dolby Digital (AC-3), Dolby Digital Plus (E-AC-3), and Dolby E, or in accordance with another encoding format.
  • Dolby, Dolby Digital, Dolby Digital Plus, and Dolby E are trademarks of Dolby Laboratories Licensing Corporation.
  • performing an operation “on” signals or data e.g., filtering or scaling the signals or data
  • performing the operation directly on the signals or data or on processed versions of the signals or data (e.g., on versions of the signals that have undergone preliminary filtering or other processing prior to performance of the operation thereon).
  • a digital biquadratic filter is a second-order recursive linear filter, containing two poles and two zeros.
  • the abbreviation “biquad” (or “bi-quad”) filter will be used herein to denote a digital biquadratic filter.
  • the transfer function of a biquad filter is the ratio of two quadratic functions:
  • H ⁇ ( z ) b 0 + b 1 ⁇ z - 1 + b 2 ⁇ z - 2 1 + a 1 ⁇ z - 1 + a 2 ⁇ z - 2
  • High-order recursive filters can be highly sensitive to quantization of their coefficients, and can easily become unstable.
  • First and second-order recursive filters can also have instability problems of this type but the instability problems are much less severe. Therefore, high-order recursive filters are typically implemented as serially cascaded filters comprising a serial cascade of bi-quad sections (and optionally also a first-order filter).
  • serially cascaded filters are sometimes referred to herein as multistage biquad filters, and comprise a sequence of bi-quad filters (sometimes referred to herein as bi-quad stages or bi-quad sections).
  • a Dolby Digital Plus encoder typically employs a two-stage biquad filter (i.e., a filter including two cascaded biquad filters) to implement high pass filtering in a transient detector subsystem, a four-stage biquad filter (i.e., a filter including four cascaded biquad filters) to implement low pass filtering in a low frequency effects (“LFE”) subsystem, and a three-stage biquad filter to implement bandwidth limiting low pass filtering.
  • a two-stage biquad filter i.e., a filter including two cascaded biquad filters
  • LFE low frequency effects
  • a Dolby E encoder typically employs a two-stage biquad filter (i.e., a filter including two cascaded biquad filters) to implement high pass filtering in a transient detector subsystem, and a four-stage biquad filter (i.e., a filter including four cascaded biquad filters) to implement low pass filtering in a low frequency effects (“LFE”) subsystem.
  • a Dolby E decoder typically employs a three-stage biquad filter (i.e., a filter including three cascaded biquad filters) to implement low pass filtering in a low frequency effects (“LFE”) subsystem.
  • FIG. 1 is a diagram of a biquad filter (of a type sometimes referred to as Direct Form II—Transposed structure), including elements 1 , 2 , 3 , 4 , 5 , b 0 , b 1 , b 2 , ⁇ a 1 , and ⁇ a 2 , connected as shown.
  • Elements 1 , 2 , and 3 are addition elements
  • elements 4 and 5 are delay elements
  • each of gain elements b 0 , b 1 , b 2 , ⁇ a 1 , and ⁇ a 2 applies a corresponding one of gains b 0 , b 1 , b 2 , ⁇ a 1 , and ⁇ a 2 , to the signal asserted to its input.
  • the resulting multistage biquad filter is an example of a two-stage biquad filter that can be employed (e.g., to implement high pass filtering in a transient detector subsystem of an audio encoder as mentioned above).
  • the output signal, x 1 ( n ) of the first stage is the input signal to the second stage.
  • an output sample calculation in each stage at instant “n” i.e., the stage's output signal y(n)
  • a time-domain signal x(n) an input signal or a signal generated in another stage of the multistage filter
  • previous outputs i.e., the outputs y(n ⁇ 1) and y(n ⁇ 2), at instants n ⁇ 1 and n ⁇ 2.
  • the output of each earlier stage is input to the subsequent stage, so that the output of subsequent stage cannot be determined until after the output of the earlier stage has been determined.
  • SIMD single instruction, multiple data
  • ALUs arithmetic logic units
  • AMUs arithmetic manipulation units
  • Dolby Digital Plus encoders which encode audio data in accordance with the Dolby Digital Plus format
  • Dolby Digital Plus encoders have been implemented as programmed ARM neon processors (each of which is an ARM Cortex processor with a Neon SIMD engine allowing parallel processing), and as programmed Texas Instruments C64 digital signal processors.
  • Many audio data encoders e.g., encoders which encode audio data in accordance with the AC-3, Dolby Digital Plus, Dolby E, and/or other encoding formats
  • SIMD single instruction, multiple data
  • ALUs arithmetic logic units
  • AMUs arithmetic manipulation units
  • Typical embodiments of the present invention employ parallel processing to implement a multistage biquad filter.
  • Some embodiments employ parallel processing to implement a multistage biquad filter of a type used in encoding audio data in accordance with the AC-3 (Dolby Digital) format, the Dolby Digital Plus format, or the Dolby E format.
  • some embodiments are audio encoding methods, systems, and processors (e.g., for encoding audio data in accordance with the AC-3, Dolby Digital Plus, or Dolby E format) employing at least one multistage biquad filter implementing (or designed in accordance with) an embodiment of the invention.
  • An AC-3 encoded bitstream comprises one to six channels of audio content, and metadata indicative of at least one characteristic of the audio content.
  • the audio content is audio data that has been compressed using perceptual audio coding.
  • the invention is a multistage filter comprising at least two stages (each of which is a biquad filter), wherein the stages are combined with latency between said stages, such that all the stages are operable independently in response to a single, common stream of instructions, to perform fully parallelized processing of data in said stages.
  • the multistage filter also includes a controller coupled to assert the common stream of instructions to all the stages, and a data memory coupled to all the stages, and all the stages are operable in parallel to filter a block of input data values in response to the common stream of instructions, but with each of the stages operating on different data values, and with at least one of the stages operating on data values which include buffered values, generated by another one of the stages in response to a subset of the input data values and stored with different latencies in the memory before being retrieved for processing in said one of the stages.
  • the multistage filter in these embodiments has a SIMD (single instruction, multiple data) architecture in which the individual biquad filter stages operate independently and in parallel in response to the single stream of instructions.
  • the multistage filter may include N stages (where N is a number greater than one), and one of the stages (the “M+1”th stage in the sequence) may operate on data values generated by a previous one of the stages (the “M”th stage in the sequence) at different times (e.g., in response to a sequence of different input data values of the block), stored in a buffer memory (at different times), and read (by the “(M+1)”th stage) from the buffer memory after residing in the buffer memory with different latency times.
  • the invention is a multistage filter, including:
  • biquad filter stages including a first biquad filter stage and a subsequent biquad filter stage;
  • a controller coupled to the biquad filter stages and configured to assert a single stream of instructions to both the first biquad filter stage and the subsequent biquad filter stage, wherein said first biquad filter stage and said subsequent biquad filter stage operate independently and in parallel in response to the stream of instructions,
  • the first biquad filter stage is coupled to the memory and configured to perform biquadratic filtering on a block of N input samples in response to the stream of instructions to generate intermediate values, and to assert the intermediate values to the memory (for storage in said memory), wherein the intermediate values include a filtered version of each of at least a subset of the input samples, and
  • the subsequent biquad filter stage is coupled to the memory and configured to perform biquadratic filtering on buffered values retrieved from the memory in response to the stream of instructions to generate a block of output values, wherein the output values include an output value corresponding to each of the input samples in the block of N input samples, and the buffered values include at least some of the intermediate values generated in the first biquad filter stage in response to the block of N input samples.
  • the multistage filter is configured to perform multistage filtering of the block of N input samples in a single processing loop with iteration over a sample index but without iteration over a biquadratic filter stage index.
  • the subsequent biquad filter stage is configured to generate an output value corresponding to a “j”th one of the input samples in response to a subset of the buffered values retrieved from the memory, where j is an index in the range from M ⁇ 1 to N ⁇ 1, said subset including the filtered version of the “j”th one of the input samples, the filtered version of a “j ⁇ 1”th one of the input samples, and the filtered version of a “j ⁇ 2”th one of the input samples.
  • the subsequent biquad filter stage is configured to generate an output value corresponding to each of the input samples in response to a different subset of the buffered values retrieved from the memory, each said subset includes at least three of the intermediate values generated in the first biquad filter stage and retrieved from the memory after residing in said memory for different latency times.
  • the subset of the buffered values retrieved to generate the output value corresponding to a “j”th one of the input samples includes at least one value generated in the first biquad filter stage in response to the “j”th one of the input samples, at least one value generated in the first biquad filter stage in response to the “j ⁇ 1”th one of the input samples, and at least one value generated in the first biquad filter stage in response to the “j ⁇ 2”th one of the input samples.
  • the invention is a method for performing multistage filtering on a block of N input samples, said method including the steps of:
  • step (b) performing a second biquadratic filtering operation on buffered values retrieved from the memory, to generate a block of output values, wherein the output values include an output value corresponding to each of the input samples in the block of N input samples, a different subset of the buffered values is retrieved and filtered to generate the output value corresponding to each of the input samples in the block, and each said subset of the buffered values includes at least two (e.g., three) of the intermediate values generated during performance of step (a) which are retrieved from the memory after residing in said memory for different latency times,
  • steps (a) and (b) are performed in response to a single stream of instructions, such that steps (a) and (b) are performed independently and in parallel in response to the single stream of instructions.
  • the multistage filtering of the block of input samples is performed in a single loop with iteration over a sample index but without iteration over a biquadratic filter stage index.
  • the buffered values retrieved in step (b) to generate the output value corresponding to the “j”th one of the input samples, where j is an index in the range from M ⁇ 1 to N ⁇ 1, include the filtered version of the “j”th one of the input samples generated in step (a), the filtered version of a “j ⁇ 1”th one of the input samples generated in step (a), and the filtered version of a “j ⁇ 2”th one of the input samples generated in step (a).
  • the invention is an audio encoder configured to generate encoded audio data in response to input audio data, said encoder including at least one multistage filter (which is any embodiment of the inventive multistage filter) coupled and configured to filter the audio data (e.g., to filter a preliminarily processed version of the audio data).
  • the invention is a method for encoding audio data to generate encoded audio data, including by performing any embodiment of the inventive multistage biquad filtering method on the audio data (e.g., on a preliminarily processed version of the audio data).
  • an embodiment of the invention is an audio encoder including a pre-processing stage (for preliminary processing of input audio data to be encoded by the encoder), wherein the pre-processing stage includes at least one multistage filter (which is any embodiment of the inventive multistage filter) coupled and configured to filter the audio data (e.g., the input data or a preliminarily processed version of the input data).
  • a pre-processor for performing preliminary processing of audio data to be encoded by an encoder
  • the pre-processor includes at least one multistage filter (which is any embodiment of the inventive multistage filter) coupled and configured to filter the audio data (e.g., data that is input to the pre-processor or a preliminarily processed version of such input data).
  • the invention is an audio decoder configured to generate decoded audio data in response to encoded audio data.
  • the decoder includes at least one multistage filter (which is any embodiment of the inventive multistage filter) coupled and configured to filter the encoded audio data (e.g., to filter a preliminarily processed version of the encoded audio data).
  • the invention is a method for decoding encoded audio data to generate decoded audio data.
  • the decoding includes performance of any embodiment of the inventive multistage biquad filtering method on the encoded audio data (e.g., on a preliminarily processed version of the encoded audio data).
  • an embodiment of the invention is an audio decoder including a post-processing stage (for post-processing of decoded audio data that has been decoded by the decoder), wherein the post-processing stage includes at least one multistage filter (which is any embodiment of the inventive multistage filter) coupled and configured to filter audio data (e.g., the decoded data or a processed version of the decoded data).
  • the post-processing stage includes at least one multistage filter (which is any embodiment of the inventive multistage filter) coupled and configured to filter audio data (e.g., the decoded data or a processed version of the decoded data).
  • Another embodiment of the invention is a post-processor (e.g., for performing post-processing of decoded audio data that has been decoded by an decoder), wherein the post-processor includes at least one multistage filter (which is any embodiment of the inventive multistage filter) coupled and configured to filter audio data (e.g., decoded data that is input to the post-processor or a processed version of such input data).
  • the post-processor includes at least one multistage filter (which is any embodiment of the inventive multistage filter) coupled and configured to filter audio data (e.g., decoded data that is input to the post-processor or a processed version of such input data).
  • SIMD instructions are used to program a processor (e.g., a digital signal processor or general purpose processor) to implement a multistage filter.
  • the multistage filter may implement bandwidth filtering, low pass filtering (e.g., in an LFE subsystem of an audio encoder), high pass filtering (e.g., in a transient detector subsystem of an audio encoder), or other filtering.
  • inventive system can be or include a programmable general purpose processor, digital signal processor, or microprocessor, programmed with software or firmware and/or otherwise configured to perform any of a variety of operations on data, including an embodiment of the inventive method or steps thereof.
  • a general purpose processor may be or include a computer system including an input device, a memory, and processing circuitry programmed (and/or otherwise configured) to perform an embodiment of the inventive method (or steps thereof) in response to data asserted thereto.
  • encoders e.g., encoders which encode audio data in accordance with the Dolby Digital Plus, AC-3, or Dolby E format
  • decoders implemented as programmed processors (e.g., ARM neon processors, each of which is an ARM Cortex processor with a Neon SIMD engine allowing parallel processing, or other processors having SIMD (single instruction, multiple data) units and/or multiple ALUs (arithmetic logic units) or AMUs (arithmetic manipulation units)) or programmed (and/or otherwise configured) digital signal processors (e.g., DSPs having SIMD units and/or multiple ALUs or AMUs).
  • programmed processors e.g., ARM neon processors, each of which is an ARM Cortex processor with a Neon SIMD engine allowing parallel processing, or other processors having SIMD (single instruction, multiple data) units and/or multiple ALUs (arithmetic logic units) or AMUs (arithmetic manipulation units)) or
  • FIG. 1 is a block diagram of a conventional biquad filter.
  • FIG. 1A is a block diagram of a conventional multistage biquad filter.
  • FIG. 2 is a flow chart of a conventional method for performing filtering in a filter implemented as serially-cascaded biquad filters (“cascaded biquad sections”).
  • FIG. 3 is a flow chart of an embodiment of the inventive method for performing filtering in a multi-stage biquad filter comprising cascaded biquad filters (“cascaded biquad sections”) which operate in parallel in response to a single stream of instructions.
  • FIG. 4 is a block diagram of a multi-stage filter (e.g., implemented by programming a DSP or other processor in accordance with an embodiment of the invention) which comprises cascaded biquad filters and which can perform a method of the type described with reference to FIG. 3 .
  • memory 10 includes memory locations which store each block of input data x(n), and buffer memory locations which store all required ones of the intermediate values x 1 (n), . . . , x N ⁇ 1 (n) generated by the biquad filters.
  • FIG. 5 is a block diagram of a system including an encoder (including an embodiment of the inventive multistage filter) and a decoder (also including an embodiment of the inventive multistage filter).
  • FIG. 6 is a flow chart of another embodiment of the inventive method for performing filtering in a multi-stage biquad filter comprising cascaded biquad filters (“cascaded biquad sections”) which operate in parallel in response to a single stream of instructions.
  • FIG. 7 is a flow chart of an embodiment of steps 40 , 41 , and 42 of the FIG. 6 embodiment of the inventive method.
  • FIG. 8 is a flow chart of an embodiment of steps 47 , 48 , and 49 of the FIG. 6 embodiment of the inventive method.
  • FIG. 9 is a diagram of values generated in an implementation of the FIG. 4 system in which calculations are performed in place.
  • FIG. 10 is a block diagram of a system including an encoder (including an embodiment of the inventive multistage filter) and a decoder which is an embodiment of the inventive decoder.
  • Embodiments of the inventive method and systems e.g., encoders and decoders configured to implement the inventive method will be described with reference to FIGS. 3, 4, 5, 6, 7, and 8 .
  • FIG. 2 we describe a conventional method for filtering data samples (e.g., blocks of audio data samples) with a multistage filter comprising a cascade of M biquad filters (where M is a number that is referred to as “nsections” below and in FIG. 2 ).
  • M is a number that is referred to as “nsections” below and in FIG. 2 .
  • An example of such a conventional multistage biquad filter is the filter of above-described FIG. 1A .
  • each new block of N samples to be filtered is initially buffered (in step 20 ).
  • Each sample in a block is identified by index j, where 0 ⁇ j ⁇ N ⁇ 1.
  • Each stage (section) in the multistage filter is identified by index i, where 0 ⁇ i ⁇ M ⁇ 1.
  • step 21 index i is initialized to zero, and in step 22 , index j is initialized to zero.
  • step 23 the “j”th input sample is filtered in the “i”th biquad filter, and then, in step 24 , the index j is incremented.
  • Step 25 determines whether the incremented index j (equal to j+1) is less than N. If it is determined in step 25 that the incremented index j is less than N, step 23 is again performed to filter the next (“(j+1)”th) sample in the “i”th biquad filter.
  • step 25 If it is determined in step 25 that the incremented index j is equal to N (so that all samples in the current block have been filtered in the current biquad filter, then, in step 26 , the index i is incremented.
  • Step 27 determines whether the most recently incremented index i (equal to i+1) is less than the number “nsections” (which is equal to M). If it is determined in step 27 that the most recently incremented index i is less than M, another iteration of steps 22 - 26 is then performed to filter the latest block of intermediate values (the outputs of the previous (“i”th) biquad filter, generated in the previous biquad filter in the previous iteration of steps 22 - 25 ) in the next ((“(i+1)”th) biquad filter.
  • step 28 If it is determined in step 27 that the most recently incremented index i is equal to M, so that processing of all samples in the current block in all the biquad filters is complete, then step 28 is performed.
  • step 28 the N filtered samples generated by filtering the current block of input samples in the multistage filter are output. At this point, any additional block of N samples to be filtered is buffered (in a new performance of step 20 ) and the FIG. 2 method is repeated to filter the new block of samples in the multistage filter.
  • each new block of N samples to be filtered is buffered (e.g., in memory 10 of FIG. 4 ) so as to be available for use in subsequent steps (including steps 31 , 33 , and 34 ).
  • Each sample in a block is identified by index j, where 0 ⁇ j ⁇ N ⁇ 1.
  • Each stage (section) in the multistage filter is identified by index i, where 0 ⁇ i ⁇ 1.
  • the value generated by this step is buffered (e.g., in memory 10 of FIG. 4 ) so as to be available for subsequent use (e.g., in subsequent performances of steps 33 and/or 34 ).
  • step 32 index j is set to 1.
  • steps 33 and 34 are performed in parallel.
  • Step 35 the index j is incremented.
  • Step 36 determines whether the incremented index j (equal to j+1) is less than N. If it is determined in step 36 that the incremented index j is less than N, steps 33 and 34 are again performed to filter the next input sample to the first biquad filter (in step 33 ) and the next input sample to the second biquad filter (in step 34 ). At least one (e.g., each) value (an “intermediate” value) generated by each iteration of each of steps 33 and 34 is buffered (e.g., in memory 10 of FIG. 4 ) so as to be available for use in subsequent steps. For example, one or more intermediate values generated in one or more previous iterations of step 33 may be retrieved from the buffer for use in a performance of step 34 .
  • step 36 If it is determined in step 36 that the incremented index j is equal to N (so that all input samples in the current block have been filtered in the first biquad filter, then step 37 is performed.
  • the value generated by this step is buffered (e.g., in memory 10 of FIG. 4 ) so as to be available for subsequent use (e.g., for output in step 38 ).
  • step 38 the N filtered samples generated by the second biquad filter are output (as the output of the multistage filter in response to the current block of N input samples).
  • any additional block of N samples to be filtered is buffered (in a new performance of step 30 ) and the FIG. 3 method is repeated to filter the new block of samples in the multistage filter.
  • N the number of output samples to be generated by filtering a block of N samples in the multistage filter
  • outputstage1[k] is the output of the first stage of the multistage filter in response to the kth input sample
  • outputstage2[k] is the output of the second stage of the multistage filter corresponding to the kth input sample
  • input[k] is the kth input sample to the first stage of the multistage filter:
  • Outputstage1 [j] function ( outputstage1[j ⁇ 1], outputstage1[j ⁇ 2], input[j] , input[j ⁇ 1], input[j ⁇ 2] );
  • Outputstage2 [j ⁇ 1] function ( outputstage2[j ⁇ 2], outputstage2[j ⁇ 3], outputstage1[j ⁇ 1] , outputstage1[j ⁇ 2], outputstage1[j ⁇ 3] );
  • processing in both stages of the multistage filter is combined in a single sample loop (steps 33 , 34 , 35 , and 36 of FIG. 3 ).
  • a one sample latency between the two stages in the case of a two-stage biquad filter
  • a one sample latency between each stage of a multistage filter having two or more biquad filter stages processing in all stages of the multistage filter may be fully parallelized in accordance with the invention. Processing of a block of samples in all biquad filter stages of a multistage filter may thus be parallelized in a single sample loop (combined for all stages), in accordance with the described embodiment of the invention.
  • FIG. 3 embodiment of the inventive method for filtering a block of data samples (e.g., a block of audio data samples) with a multistage filter comprising a cascade of M biquad filters (where M is greater than 2) are contemplated.
  • a block of data samples e.g., a block of audio data samples
  • M is greater than 2
  • Such variations are typically implemented in a manner to be described with reference to FIGS. 6, 7, and 8 .
  • each new block of N samples to be filtered is buffered (e.g., in memory 10 of FIG. 4 ) so as to be available for use in subsequent steps (including steps 41 , 43 - 45 , and 48 ).
  • Each sample in a block is identified by index j, where 0 ⁇ j ⁇ N ⁇ 1.
  • Each biquad stage (section) in the multistage filter is identified by index i, where 0 ⁇ i ⁇ M ⁇ 1.
  • the values generated by this step are buffered (e.g., in memory 10 of FIG. 4 ) so as to be available for subsequent use (e.g., in subsequent performances of steps 43 - 45 ).
  • index j is set to M ⁇ 1.
  • steps 43 - 45 are performed in parallel.
  • at least one (e.g., each) value (an “intermediate” value) generated by each such step is buffered so as to be available for use in subsequent steps.
  • step 46 the index j is incremented, and step 47 determines whether the incremented index j (equal to j+1) is less than N. If it is determined in step 47 that the incremented index j is less than N, steps 43 - 45 (and any other step(s) performed in parallel with steps 43 - 45 ) are again performed to filter the next sample in the first biquad filter (in step 43 ), the next sample in the second biquad filter (in step 44 ), and so on for each additional biquad filter stage. At least one (e.g., each) value (an “intermediate” value) generated by each iteration of each of steps 43 - 45 is buffered (e.g., in memory 10 of FIG. 4 ) so as to be available for use in subsequent steps. For example, one or more intermediate values generated in one or more previous iterations of step 43 may be retrieved from the buffer for use in a performance of step 44 .
  • steps 43 - 45 and any other step(s) performed in parallel with steps 43
  • the value(s) generated by this step are buffered (e.g., in memory 10 of FIG. 4 ) so as to be available for subsequent use (e.g., for output in step 49 ).
  • any additional block of N samples to be filtered is buffered (in a new performance of step 40 ) and the FIG. 6 method is repeated to filter the new block of samples in the multistage filter.
  • FIG. 7 is a flow chart of steps 40 and 42 , and details of an embodiment of step 41 , of the FIG. 6 embodiment of the inventive method.
  • Steps 50 - 58 of FIG. 7 are an implementation of pre-loop filtering step 41 of FIG. 6 .
  • Steps 51 and 52 are preferably performed in parallel (in response to the same instruction or sequence of instructions asserted to the first and second stages).
  • steps 51 and 52 are preferably performed in parallel (in response to the same instruction or sequence of instructions asserted to the relevant stages).
  • FIG. 8 is a flow chart of an embodiment of steps 47 and 49 , and details of an embodiment of step 48 , of the FIG. 6 embodiment of the inventive method. Steps 60 - 66 of FIG. 8 are an implementation of post-loop filtering step 48 of FIG. 6 .
  • steps 64 and 65 are preferably performed in parallel (in response to the same instruction or sequence of instructions asserted to the relevant stages).
  • the FIG. 3 method (and variations thereon for filtering a block of data samples with a multistage filter comprising a cascade of more than two biquad filters) performs multistage filtering of a block of N input samples in a single loop with iteration over a sample index (index j of FIG. 3 ) but without iteration over a biquadratic filter stage index.
  • the conventional method of FIG. 2 processes a block of data samples in two nested loops with iteration over both a sample index (index j of FIG. 2 ) and iteration over a biquadratic filter stage index (index i of FIG. 2 ).
  • the stages of the inventive multistage filter are combined with latency between the stages, such that all the stages can operate independently, allowing parallelization of the processing of the different stages. All the stages can operate in parallel (to filter a block of input data values), in response to a single, common stream of instructions from a controller, but with each stage operating on different data values, with at least one of the stages operating on data values which include buffered values (generated by another one of the stages in response to a subset of the input data values, and stored with different latencies in a buffer memory before being retrieved for processing in said one of the stages).
  • the multistage filter has a SIMD (single instruction, multiple data) architecture in which the individual biquad filter stages operate independently and in parallel in response to the single stream of instructions.
  • the multistage filter may include N stages, and one of the stages (the “M+1”th stage in the sequence) may operate on data values generated by a previous one of the stages (the “M”th stage in the sequence) at different times (e.g., in response to a sequence of different input data values of the block), stored in a buffer memory (at different times), and read (by the “(M+1)”th stage) from the buffer memory after residing in the buffer memory with different latency times.
  • SIMD single instruction, multiple data
  • the multistage filter of FIG. 4 includes multiple biquad filters (M biquad filters, where M is an integer greater than one) and is configured to perform a method of the type described with reference to FIG. 3 (or a variation on such a method, such as that shown in FIG. 6 ).
  • the FIG. 4 filter includes memory 10 , controller 11 , and biquad filters B 1 , B 2 , . . . , B M , connected as shown, and is configured to filter a block of N input data values x(n), where “n” is an index ranging from 1 through N, in response to a single stream of instructions asserted to the biquad filters by controller 11 .
  • Each of input data values x(n) may be an audio data sample.
  • a “single stream of instructions” is asserted to individual stages (e.g., each of which is a biquad filter) of a multistage filter, is used herein in a broad sense including both: cases in which a single stream of instructions is asserted to all the stages (e.g., on a single bus or conductor to which all the stages are coupled); and cases in which identical (or substantially identical) streams of instructions are asserted simultaneously (or substantially simultaneously) to the stages (e.g., each stream asserted on different bus or conductor coupled to a different one of the stages).
  • filter B 1 In response to the block of input data values x(n), filter B 1 generates N intermediate (biquad filtered) values x 1 (n), and asserts them to buffer memory locations in memory 10 .
  • filter B 2 retrieves required intermediate values x 1 (n) from memory 10 , generates intermediate (biquad filtered) values x 2 (n) in response thereto, and asserts the intermediate values that it generates to buffer memory locations in memory 10 .
  • each other one of the biquad filters retrieves intermediate values x i ⁇ 1 (n) from memory 10 , generates biquad filtered values x i (n) in response thereto, and asserts the values that it generates to buffer memory locations in memory 10 .
  • Memory 10 includes memory locations which store each block of input data x(n), and buffer memory locations which store intermediate values x 1 (n), . . . , x M ⁇ 1 (n) generated by the biquad filters B 1 , B 2 , . . . , B M ⁇ 1 (e.g., buffer locations that store intermediate values x 1 (n), . . . , x M ⁇ 1 (n) generated for each block of input data).
  • the same memory locations which are used to store input data x(n) may be used to store intermediate values x 1 (n), . . . , x M ⁇ 1 (n) once particular input data samples are no longer needed by the multistage filter.
  • memory 10 typically does not need to include more (or significantly more) memory locations than does a conventional memory (for implementing a conventional, non-parallelized version of the multistage filter), since such a conventional memory would typically include memory locations for storing each block of input data, x(n), to be filtered, and each output value generated by each of stages of the multistage filter that is required for operation of the stage itself and/or for operation of each subsequent stage of the filter.
  • sample x( 0 ) is filtered through filter B 0 (first stage biquad) to produce sample x 1 ( 0 ).
  • Sample x 1 ( 0 ) is stored in memory in the location previously occupied by sample x( 0 ). All other memory locations are unchanged.
  • sample x 1 ( 0 ) is filtered through filter B 1 (second stage biquad) to produce sample y( 0 ).
  • Sample y( 0 ) is stored in memory in the location previously occupied by sample x 1 ( 0 ).
  • sample x( 1 ) is filtered through filter B 0 to produce sample x 1 ( 1 ).
  • Sample x 1 ( 1 ) is stored in memory in the location previously occupied by sample x( 1 ).
  • processing continues until all input samples x( 0 ) . . . x( 3 ) have been replaced by output samples y( 0 ) . . . y( 3 ).
  • each filter e.g., each of filters B 0 and B 1
  • each filter requires access to memory locations which store the two samples (corresponding to s 1 (n) and s 2 (n) in FIG. 1 ) that it generates (in response to the “j ⁇ 1”th and “j ⁇ 2”th input samples of the current block of N input samples) for use in filtering the “j”th input sample of the current block.
  • These memory locations could be within memory 10 of the FIG. 4 system (or could be other buffer memory locations).
  • each pair of stored samples (corresponding to s 1 (n) and s 2 (n) in FIG. 1 ) that have been generated by the filter are updated each time a new input sample (with an incremented index j) is asserted to the filter.
  • the stored samples (corresponding to s 1 (n) and s 2 (n) in FIG. 1 ) are examples of “intermediate values” (as this phrase is used elsewhere herein) that are generated by the filter (which is one stage of a multistage filter) and buffered for subsequent use in accordance with the invention, but they are subsequently used by the filter stage which generated them (not by a different filter stage of the multistage filter).
  • FIG. 9 shows a specific example of the inventive method using in place filtering, in which the block size (N) is equal to 4 and the number of biquad filter stages (M) in the inventive filter is equal to 2, embodiments of the inventive method using in place filtering are contemplated for any values of M and N subject to the constraints that M>1 and N>M.
  • the same memory locations e.g., in memory 10 of FIG. 4
  • which are used to store input data x(n) may be used to store intermediate values x 1 (n), . . . , x M ⁇ 1 (n) once particular input data samples are no longer needed by the multistage filter.
  • the FIG. 4 filter can be implemented by programming a digital signal processor (DSP) or other processor which includes a memory (functioning as memory 10 ), a controller (functioning as controller 11 ), and ALUs (arithmetic logic units) or AMUs (arithmetic manipulation units), with each of biquad filters B 1 , B 2 , . . . , B M being implemented as an appropriately configured one of the ALUs or AMUs.
  • DSP digital signal processor
  • ALUs arithmetic logic units
  • AMUs arithmetic manipulation units
  • FIG. 4 filter includes:
  • buffer memory buffer locations in memory 10 ;
  • biquad filters B 1 , B 2 , . . . , B M at least two biquad filter stages (biquad filters B 1 , B 2 , . . . , B M ), including a first biquad filter stage (e.g., biquad filter B 1 ) and a subsequent biquad filter stage (e.g., biquad filter B 2 ); and
  • controller 11 coupled to the biquad filter stages and configured to assert a single stream of instructions to both the first biquad filter stage and the subsequent biquad filter stage.
  • the first biquad filter stage and the subsequent biquad filter stage (and each other biquad filter stage of the FIG. 4 filter) operate independently and in parallel in response to the stream of instructions.
  • the first biquad filter stage is coupled to the memory and configured to perform biquadratic filtering on a block of N input samples in response to the stream of instructions to generate intermediate values (e.g., the values x 1 (n)), and to assert the intermediate values to the memory (for storage in said memory).
  • These intermediate values include a filtered version of each one of the input samples.
  • no more than one intermediate value x 1 (n) need be present in memory 10 at any one time.
  • the subsequent biquad filter stage is coupled to the memory and configured to perform biquadratic filtering on buffered values retrieved from the memory in response to the stream of instructions to generate a block of output values (e.g., the values x 2 (n)), wherein the output values include an output value corresponding to each of the input samples in the block of N input samples, and the buffered values include at least some of the intermediate values generated in the first biquad filter stage in response to the block of N input samples.
  • a block of output values e.g., the values x 2 (n)
  • the subsequent biquad filter stage (e.g., filter B 2 of FIG. 4 ), in an embodiment in which the multistage filter has M stages, is configured to generate an output value corresponding to the “j”th one of the input samples in response to a subset of the buffered values retrieved from the memory, where j is an index in the range from M ⁇ 1 to N ⁇ 1, said subset including the filtered version of the “j”th one of the input samples, the filtered version of a “j ⁇ 1”th one of the input samples, and the filtered version of a “j ⁇ 2”th one of the input samples.
  • the subsequent biquad filter stage (e.g., filter B 2 of FIG. 4 ) is configured to generate an output value (x 2 (n)) corresponding to each of the input samples, x(n), in response to a different subset of the buffered values retrieved from the memory, each said subset includes at least two (e.g., three) of the intermediate values generated in the first biquad filter stage (e.g., the values x 1 (n), x 1 (n ⁇ 1), and x 1 (n ⁇ 2), indicated in FIG. 4 ) and retrieved from the memory after residing in said memory for different latency times.
  • the intermediate values generated in the first biquad filter stage e.g., the values x 1 (n), x 1 (n ⁇ 1), and x 1 (n ⁇ 2), indicated in FIG. 4
  • the subset of the buffered values retrieved by filter B 2 to generate the output value corresponding to a “j”th one of the input samples includes at least one value generated in the first biquad filter stage in response to the “j”th one of the input samples, at least one value generated in the first biquad filter stage in response to the “j ⁇ 1”th one of the input samples, and at least one value generated in the first biquad filter stage in response to the “j ⁇ 2”th one of the input samples.
  • the FIG. 4 filter is configured to perform multistage filtering on a block of N input samples (data values x(n)), including by performing the steps of:
  • step (b) performing a second biquadratic filtering operation on buffered values retrieved from the memory, to generate a block of output values (e.g., the values x 2 (n) indicated in FIG. 4 ), wherein the output values include an output value corresponding to each of the input samples in the block of N input samples, a different subset of the buffered values is retrieved and filtered to generate the output value corresponding to each of the input samples in the block, and each said subset of the buffered values includes at least two (e.g., three) of the intermediate values generated during performance of step (a) (e.g., the values x 1 (n), x 1 (n ⁇ 1), and x 1 (n ⁇ 2), indicated in FIG. 4 ) which are retrieved from the memory after residing in said memory for different latency times,
  • steps (a) and (b) are performed in response to a single stream of instructions, such that steps (a) and (b) are performed independently and in parallel in response to the single stream of instructions.
  • the buffered values retrieved in step (b) to generate the output value corresponding to a “j”th one of the input samples in an embodiment in which the filtering is performed in a multistage filter having M stages, where j is an index in the range from M ⁇ 1 to N ⁇ 1, include the filtered version of the “j”th one of the input samples generated in step (a), the filtered version of a “j ⁇ 1”th one of the input samples generated in step (a), and the filtered version of a “j ⁇ 2”th one of the input samples generated in step (a).
  • FIG. 5 is a block diagram of a system including an encoder (encoder 150 ) including an embodiment of the inventive multistage filter (“M B filter” 153 ).
  • filter 153 may be of the type shown in and described with reference to FIG. 4 .
  • Encoder 150 optionally includes two or more multistage filters, each of which is an embodiment of the inventive multistage filter.
  • encoder 150 In response to input audio data samples, encoder 150 generates encoded audio data and asserts the encoded audio data to delivery subsystem 151 .
  • Delivery subsystem 151 is configured to store the encoded audio data and/or to transmit a signal indicative of the encoded audio data.
  • Decoder 152 is coupled and configured (e.g., programmed) to receive the encoded audio data from subsystem 151 (e.g., by reading or retrieving the encoded audio data from storage in subsystem 151 , or receiving a signal indicative of the encoded audio data that has been transmitted by subsystem 151 ).
  • Decoder 152 includes an embodiment of the inventive multistage filter (“M B filter” 154 ).
  • filter 154 may be of the type shown in and described with reference to FIG. 4 .
  • Decoder 152 optionally includes two or more multistage filters, each of which is an embodiment of the inventive multistage filter. Decoder 152 operates to decode the encoded audio data, thereby generating decoded audio data.
  • the FIG. 5 system also includes audio pre-processing subsystem (“pre-processor”) 155 configured to perform preliminary processing of audio data to be encoded by encoder 150 .
  • Pre-processor 155 includes an embodiment of the inventive multistage filter (“M B filter” 157 ).
  • M B filter inventive multistage filter
  • filter 157 may be of the type shown in and described with reference to FIG. 4 .
  • the FIG. 5 system also includes audio post-processing subsystem (“post-processor”) 156 configured to perform post-processing of decoded audio data that has been decoded by decoder 154 .
  • Post-processor 156 includes an embodiment of the inventive multistage filter (“M B filter” 158 ).
  • filter 158 may be of the type shown in and described with reference to FIG. 4 .
  • encoder 150 is an AC-3 (or enhanced AC-3, or Dolby E) encoder, which is configured to generate an AC-3 (or enhanced AC-3, or Dolby E) encoded audio bitstream in response to time-domain input audio data
  • decoder 52 is an AC-3 (or enhanced AC-3, or Dolby E) decoder
  • the invention is an audio encoder (e.g., encoder 150 of FIG. 5 ) configured to generate encoded audio data in response to input audio data, said encoder including at least one multistage filter (which is any embodiment of the inventive multistage filter) coupled and configured to filter the audio data (e.g., to filter a preliminarily processed version of the audio data).
  • Encoder 150 is configured to encode audio data to generate encoded audio data, including by performing an embodiment of the inventive multistage filtering method on the audio data (e.g., on a preliminarily processed version of the audio data).
  • the invention is an audio decoder (e.g., decoder 152 of FIG. 5 ) configured to generate decoded audio data in response to encoded audio data, said decoder including at least one multistage filter (which is any embodiment of the inventive multistage filter) coupled and configured to filter the encoded audio data (e.g., to filter a preliminarily processed version of the encoded audio data).
  • Decoder 152 is configured to decode encoded audio data to generate decoded audio data, including by performing an embodiment of the inventive multistage filtering method on the encoded audio data (e.g., on a preliminarily processed version of the encoded audio data).
  • a pre-processor for performing preliminary processing of audio data (e.g., audio data to be encoded by an encoder), wherein the pre-processor includes at least one multistage filter (which is any embodiment of the inventive multistage filter) coupled and configured to filter the audio data (e.g., data that is input to the pre-processor or a preliminarily processed version of such input data).
  • the pre-processor includes at least one multistage filter (which is any embodiment of the inventive multistage filter) coupled and configured to filter the audio data (e.g., data that is input to the pre-processor or a preliminarily processed version of such input data).
  • Another embodiment of the invention is a post-processor (e.g., post-processor 156 of FIG. 5 ) for performing post-processing of decoded audio data that has been decoded by an decoder, wherein the post-processor includes at least one multistage filter (which is any embodiment of the inventive multistage filter) coupled and configured to filter audio data (e.g., decoded data that is input to the post-processor or a processed version of such input data).
  • the post-processor includes at least one multistage filter (which is any embodiment of the inventive multistage filter) coupled and configured to filter audio data (e.g., decoded data that is input to the post-processor or a processed version of such input data).
  • FIG. 10 is a block diagram of a system including an encoder (encoder 150 ) including an embodiment of the inventive multistage filter (“M B filter” 153 ).
  • Encoder 150 of FIG. 10 is identical to encoder 150 of FIG. 5 , and may be implemented in any of the ways in which encoder 150 of FIG. 5 may be implemented.
  • Multistage filter 153 may implement any embodiment of the inventive multistage filter.
  • encoder 150 In response to input audio data samples, encoder 150 generates encoded audio data (representing one or more input audio channels) and asserts the encoded audio data to delivery subsystem 151 .
  • Delivery subsystem 151 is configured to store the encoded audio data and/or to transmit a signal indicative of the encoded audio data.
  • Subsystem 151 of FIG. 10 is identical to subsystem 151 of FIG. 5 and may be implemented in any of the ways in which subsystem 151 of FIG. 5 may be implemented.
  • Decoder 252 of FIG. 10 has an input coupled to receive the encoded audio data from subsystem 151 (e.g., by reading or retrieving the encoded audio data from storage in subsystem 151 , or receiving a signal indicative of the encoded audio data that has been transmitted by subsystem 151 ).
  • Decoder 252 is configured (e.g., programmed) to extract (from the received encoded bitstream) encoded data representing one or more channels of audio information processed by multistage filter 153 , and to decode the encoded data to provide decoded representations of the one or more channels of audio information.
  • SIMD instructions are used to program a processor (e.g., a digital signal processor or general purpose processor) to implement a multistage filter.
  • the multistage filter may implement bandwidth limiting low pass filtering, low pass filtering (e.g., in an LFE subsystem of an audio encoder), high pass filtering (e.g., in a transient detector subsystem of an audio encoder), or other filtering.
  • inventive system can be or include a programmable general purpose processor, digital signal processor, or microprocessor, programmed with software or firmware and/or otherwise configured to perform any of a variety of operations on data, including an embodiment of the inventive method or steps thereof.
  • a general purpose processor may be or include a computer system including an input device, a memory, and processing circuitry programmed (and/or otherwise configured) to perform an embodiment of the inventive method (or steps thereof) in response to data asserted thereto.
  • encoders e.g., encoders which encode audio data in accordance with the Dolby Digital Plus, AC-3, or Dolby E format
  • decoders implemented as programmed processors (e.g., ARM neon processors, each of which is an ARM Cortex processor with a Neon SIMD engine allowing parallel processing, or other processors having SIMD (single instruction, multiple data) units and/or multiple ALUs (arithmetic logic units) or AMUs (arithmetic manipulation units)) or programmed (and/or otherwise configured) digital signal processors (e.g., DSPs having SIMD units and/or multiple ALUs or AMUs).
  • programmed processors e.g., ARM neon processors, each of which is an ARM Cortex processor with a Neon SIMD engine allowing parallel processing, or other processors having SIMD (single instruction, multiple data) units and/or multiple ALUs (arithmetic logic units) or AMUs (arithmetic manipulation units)) or
  • Typical embodiments of the inventive method for implementing a multistage biquad filter do not affect the precision of the output or stability of the filter (relative to the precision and stability attainable by a conventional implementation of the filter).
  • an encoder configured to encode audio data in accordance with the Dolby Digital Plus format, and implemented as a Texas Instruments C64 digital signal processor programmed to include an embodiment of the inventive two-stage biquad filter (implementing high pass filtering in a transient detector subsystem of the encoder) required only an average of 1846 cycles to filter a typical block of audio data, in contrast with the average number of cycles (4141) required to filter the block when the encoder was instead conventionally programmed to include a conventional (non-parallelized) implementation of the two-stage filter.
  • an encoder configured to encode audio data in accordance with the Dolby Digital Plus format, and implemented as a Texas Instruments C64 digital signal processor programmed to include an embodiment of the inventive four-stage biquad filter (implementing low pass filtering in a low frequency effects (“LFE”) subsystem of the encoder) required only an average of 5802 cycles to filter a typical block of audio data, in contrast with the average number of cycles (10375) required to filter the block when the encoder was instead conventionally programmed to include a conventional (non-parallelized) implementation of the four-stage filter.
  • LFE low frequency effects
  • the invention can also provide similar performance benefits when the inventive filter is implemented by appropriately programming other processors (having other core processor architectures). It is also expected that the degree of performance improvement will depend on the processor architecture, the number of stages of the filter, and number of poles in the filter.
  • the invention may be implemented in hardware, firmware, or software, or a combination of both (e.g., as a programmable logic array). Unless otherwise specified, the algorithms or processes included as part of the invention are not inherently related to any particular computer or other apparatus. In particular, various general-purpose machines may be used with programs written in accordance with the teachings herein, or it may be more convenient to construct more specialized apparatus (e.g., integrated circuits) to perform the required method steps. Thus, the invention may be implemented in one or more computer programs executing on one or more programmable computer systems (e.g., a computer system which implements the encoder of FIG.
  • programmable computer systems e.g., a computer system which implements the encoder of FIG.
  • Program code is applied to input data to perform the functions described herein and generate output information.
  • the output information is applied to one or more output devices, in known fashion.
  • Each such program may be implemented in any desired computer language (including machine, assembly, or high level procedural, logical, or object oriented programming languages) to communicate with a computer system.
  • the language may be a compiled or interpreted language.
  • various functions and steps of embodiments of the invention may be implemented by multithreaded software instruction sequences running in suitable digital signal processing hardware, in which case the various devices, steps, and functions of the embodiments may correspond to portions of the software instructions.
  • Each such computer program is preferably stored on or downloaded to a storage media or device (e.g., solid state memory or media, or magnetic or optical media) readable by a general or special purpose programmable computer, for configuring and operating the computer when the storage media or device is read by the computer system to perform the procedures described herein.
  • a storage media or device e.g., solid state memory or media, or magnetic or optical media
  • the inventive system may also be implemented as a computer-readable storage medium, configured with (i.e., storing) a computer program, where the storage medium so configured causes a computer system to operate in a specific and predefined manner to perform the functions described herein.
  • multistage filters whose individual stages are IIR filters but are not biquad filters (as they are in the specific embodiments described herein), may be implemented in accordance with the invention so that processing of its individual stages is parallelized (e.g., so that all its stages are operable independently in response to a single, common stream of instructions, to perform fully parallelized processing of data in said stages).
  • 26, 2012 may be modified in accordance with an embodiment of the present invention so that the processing of its individual stages is parallelized (e.g., so that all its stages are operable independently in response to a single, common stream of instructions, to perform fully parallelized processing of data in said stages).
  • some or all of the steps described herein are performed simultaneously or in a different order than specified in the examples described herein. Although steps are performed in a particular order in some embodiments of the inventive method, some steps may be performed simultaneously or in a different order in other embodiments.

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