US20160233270A1 - Memory device with comb- shaped electrode having a plurality of electrode fingers and method of making thereof - Google Patents
Memory device with comb- shaped electrode having a plurality of electrode fingers and method of making thereof Download PDFInfo
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- US20160233270A1 US20160233270A1 US14/614,709 US201514614709A US2016233270A1 US 20160233270 A1 US20160233270 A1 US 20160233270A1 US 201514614709 A US201514614709 A US 201514614709A US 2016233270 A1 US2016233270 A1 US 2016233270A1
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
- H10B63/34—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the vertical channel field-effect transistor type
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
- H10B63/845—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays the switching components being connected to a common vertical conductor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
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Definitions
- the present description relates generally to the field of semiconductor devices and specifically to three dimensional memory devices and methods of making thereof.
- variable resistance memory elements that may be set to either low or high resistance states, and can remain in that state until subsequently re-set to the initial condition.
- the variable resistance memory elements are individually connected between two orthogonally extending conductors (typically bit and word lines) where they cross each other in a two-dimensional array. The state of such a memory element is typically changed by proper voltages being placed on the intersecting conductors.
- An example of an array of variable resistive elements and associated diodes is given in U.S. Patent Application Publication No. US 2009/0001344 A1, which is incorporated herein by reference in its entirety.
- U.S. Patent Application Publication No. 2012/0147648 A1 published Jun.
- ReRAM resistive RAM
- NVM non-volatile memory element
- One embodiment relates to a memory device, including: a first bit line interconnect; a second bit line interconnect; a first plurality of electrically conductive local bit lines extending in a substantially vertical direction into a memory cell region, wherein each local bit line in the first plurality of electrically conductive local bit lines is electrically connected to the first bit line interconnect; a second plurality of electrically conductive local bit lines extending in the substantially vertical direction into the memory cell region and horizontally offset from the first plurality of electrically conductive local bit lines, wherein each local bit line in the second plurality of electrically conductive local bit lines is electrically connected to the second bit line interconnect; a first select transistor electrically connected to the first bit line interconnect, wherein the first select transistor is configured to select the first plurality of electrically conductive local bit lines; a second select transistor electrically connected to the second bit line interconnect, wherein the second select transistor is configured to select the second plurality of electrically conductive local bit lines; a plurality of word lines extending in a substantially horizontal direction
- a memory device including: a memory cell region; a plurality of memory cells located in the memory cell region; a plurality of word lines extending in a substantially horizontal direction into the memory cell region; and a plurality of bit lines extending in a substantially vertical direction into the memory cell region.
- the plurality of word lines include a first, second, third and forth word line comb; each word line comb includes a plurality of electrically conductive fingers; the plurality of electrically conductive fingers for each word line comb electrically contact other electrically conductive fingers of the same word line comb and are electrically insulated from the electrically conductive fingers of the other word line combs; the fingers of the first and second word line combs extend in a first substantially horizontal direction from a first interconnect region into a first side of the memory cell region; the fingers of the third and forth word line combs extend in a second substantially horizontal direction from a second interconnect region into a second side of the memory cell region opposite to the first side of the memory cell region; and the fingers of the first, second, third and forth word line comb are alternately interdigitated in the memory cell region.
- a method of making an interconnect between electrodes in a three dimensional device, the method including: providing a first stack of electrodes including a first electrode located in a first device level, a second electrode located in a second device level above the first device level, a third electrode located in a third device level above the second device level, and a fourth electrode located in a fourth device level above the third device level; providing a second stack of electrodes which is offset in a substantially horizontal direction from the first stack of electrodes, the second stack of electrodes including a first electrode located in the first device level, a second electrode located in the second device level above the first device level, a third electrode located in the third device level above the second device level, and a fourth electrode located in the fourth device level above the third device level; forming an insulating fill layer over the first and the second stacks of electrodes forming a first opening to the fourth electrode in the first stack of electrodes through the insulating fill layer; forming a second opening through the insulating fill layer and through the fourth
- a method of making a contact to a semiconductor device including: forming a conductive layer over a semiconductor layer; forming a first mask pattern over the conductive layer; etching portions of the conductive layer and the semiconductor layer exposed in the first mask pattern to form a plurality of pillars, wherein each pillar includes a lower semiconductor region and an upper conductive region; forming an insulating fill layer between the plurality of pillars; forming a second mask pattern over the plurality of pillars and the insulating fill layer, wherein the second mask pattern is offset with respect to the first mask pattern such that the second mask pattern covers both adjacent first edge portions of the upper conductive region in each adjacent pair of the plurality of pillars and the insulating fill layer between each adjacent pair of the plurality of pillars, while leaving opposing second edge portions of the upper conductive region in each pair of the plurality of pillars uncovered; etching the second edge portions of the upper conductive regions of each pair of the plurality of pillars to
- a semiconductor device including: a first, second, third and fourth transistors, each transistor having a channel region of a second conductivity type located in a horizontal plane between source region and first drain region of a first conductivity type, wherein: the second transistor is located adjacent to the first transistor in a first horizontal direction in the horizontal plane, such that a first channel edge containing the source region of the first transistor faces a second channel edge containing the source region of the second transistor; the third transistor is located adjacent to the first transistor in a second horizontal direction in the horizontal plane, such that a third channel edge containing the first drain region of the first transistor faces a fourth channel edge containing the first drain region of the third transistor; the fourth transistor is located adjacent to the second transistor in the second horizontal direction in the horizontal plane, such that a third channel edge containing the first drain region of the second transistor faces a fourth channel edge containing the first drain region of the fourth transistor; the fourth transistor is located adjacent to adjacent to the third transistor in the first horizontal direction in the horizontal plane, such that a first channel edge containing the first drain region of
- the device may also include: a common source line which extends in the second direction between the first and the second transistors and between the third and the fourth transistors, and which is electrically connected to the source regions of each of the first, second, third and fourth transistors; a first common gate electrode which extends in the first direction over the channel regions between respective source regions and first drain regions of the first and the second transistors; and a second common gate electrode which extends in the first direction over the channel regions between respective source regions and first drain regions of the third and the fourth transistors.
- FIG. 1A is a side cross sectional view along line A-A′ in FIG. 1B and FIG. 1B is a top view of a memory device according to an embodiment.
- FIG. 1C is perspective view
- FIG. 1D is a side cross sectional view
- FIG. 1E is a top view of a memory device according to another embodiment.
- FIGS. 2A and 2B are side cross sectional views along rear plane (A) and front plane (B), respectively, of FIG. 2D
- FIGS. 2C-2F are perspective views a memory device according to another embodiment.
- FIGS. 3A, 3D, 3E and 3F are perspective views, FIG. 3B is modified circuit schematic and FIG. 3C is a top view of a memory device according to another embodiment.
- FIGS. 4A-4S are side cross sectional views and FIGS. 4T, 4U, 4W and 4X are perspective views of steps in a method of making a memory device according to the embodiment of FIGS. 3A-3F .
- FIGS. 5A, 5C-5E, 5G-5H, 5J and 5L-5O are side cross sectional views and FIGS. 5B, 5F, 5I and 5K are top cross sectional views of steps in a method of making a memory device according to another embodiment.
- a memory device 100 of one embodiment includes plural (e.g., at least two, such as four) interdigitated word lines and a single select transistor controlling plural (e.g., at least two) local bit lines.
- the device 100 includes a memory cell region 102 containing a plurality of memory cells 104 located in the memory cell region 102 .
- the memory device includes two identical memory device modules (e.g., sections) 101 a and 101 b , arranged side by side.
- various embodiments may include more or fewer memory device modules 101 , e.g., 1, 10, 100, 1,000 or more, e.g., in the range of one to a trillion or any sub-range thereof.
- the memory device modules 101 may be arranged, e.g., in two dimensional planar array (e.g., a rectangular array), or in any other suitable regular, irregular, or random pattern.
- the memory device 100 also includes a first bit line interconnect 106 a and a second bit line interconnect 106 b in module 101 a .
- Module 101 b contains similar bit line interconnects.
- a first plurality of electrically conductive local bit lines 108 a extend in a substantially vertical direction into the memory cell region 102 (e.g., in the z-direction in FIG. 1A ).
- a substantially vertical direction includes the vertical direction (e.g., perpendicular to the top substrate surface) and directions within 20 degrees from the vertical direction.
- two local bit lines 108 a are provided per module 101 a , but in other embodiments more maybe be used, e.g., 3, 4, 5, 6, 7 8, 9, 10 or more such as in the range of 2-100 or any sub-range thereof.
- Each local bit line 108 a e.g., both lines 108 a
- a second plurality of electrically conductive local bit lines 108 b extend in the substantially vertical direction into the memory cell region 102 and are horizontally offset from the first plurality of electrically conductive local bit lines 108 a .
- two local bit lines 108 b are provided per module 101 b , but in other embodiments more maybe be used, e.g., 3, 4, 5, 6, 7 8, 9, 10 or more such as in the range of 2-100 or any sub-range thereof.
- Each local bit line 108 b in the second plurality of electrically conductive local bit lines is electrically connected to the second bit line interconnect 106 b .
- the first plurality of electrically conductive local bit lines 108 b extend substantially 180 degrees (e.g., 180 degrees or within 160-200 degrees) from the second plurality of electrically conductive local bit lines 108 b .
- the lines 108 a may extend from the interconnect 106 a upward
- the lines 108 b may extend from the interconnect 106 b downward.
- the first plurality of local bit 108 a and first bit line interconnect 106 a may be electrically insulated from the second plurality of local bit lines 108 b and second bit line interconnect 106 b .
- a first insulating layer 109 a e.g., an oxide or nitride layer, such as a horizontal silicon nitride etch stop layer
- a second insulating layer 109 b (e.g., an oxide or nitride layer such as a horizontal silicon nitride etch stop layer) prevents the second bit line interconnect 106 b from contacting the first plurality of local bit lines 108 a.
- a first select transistor 110 a is electrically connected to the first bit line interconnect 106 a , and is configured to select the first plurality of electrically conductive local bit lines 108 a .
- a second select transistor 110 b is electrically connected to the second bit line interconnect 106 b , and is configured to select the second plurality of electrically conductive local bit lines 108 b .
- the transistors 110 may be located below the memory cell region 102 .
- a plurality of word lines 112 extend in a substantially horizontal direction into the memory cell region 102 (the y-direction in FIG. 1B ).
- a substantially horizontal direction includes the horizontal direction (e.g., parallel to the top substrate surface) and directions within 20 degrees from the horizontal direction.
- four word lines 112 are provided, but in other embodiments more or fewer maybe be used, e.g., 2, 3, 4, 5, 6, 7 8, 9, 10 or more such as in the range of 2-100 or any sub-range thereof.
- each word line 112 may include one or more word line combs 114 .
- each of the plurality of word lines shown in FIG. 1B comprises a first word line comb 114 a , a second word line comb 114 b , a third word line comb 114 c and a forth word line comb 114 d .
- four word lines combs 114 are provided, but in other embodiments more or fewer maybe be used, e.g., 2, 3, 4, 5, 6, 7 8, 9, 10 or more such as in the range of 2-100 or any sub-range thereof.
- the location and direction of the comb 114 a by the dashed line 114 a in FIG. 1A and its electrical connection between the word line fingers 116 is shown by the black circles in the line 114 a .
- the diagonal direction of the comb which extends in both vertical and horizontal directions will be explained in more detail with respect to FIGS. 3A-3F below.
- Each word line comb 114 comprises a plurality of electrically conductive fingers 116 .
- the plurality of electrically conductive fingers 116 for each word line comb 114 electrically contact other electrically conductive fingers of the same word line comb 114 and are electrically insulated from the electrically conductive fingers of the other word line combs 114 .
- the electrically conductive fingers 116 of the word line comb 114 a are in electrical connection with each other, but insulated from word line combs 114 b - 114 d .
- the fingers 116 of the same comb 114 may be electrically connected to each other by a word line interconnect 113 , such as a sidewall bridge described below in reference to FIGS. 3A-3F .
- this is accomplished by providing vertically offset crossings for the word line combs 114 .
- word line comb 114 b crosses over or under word line comb 114 a in the region 115 .
- Detailed techniques for implementing crossovers of this type using the sidewall bridge are described in more detail below in reference to FIGS. 3A-3F .
- the fingers 116 of some of the word line 112 combs 114 extend in a first substantially horizontal direction (as shown, the y-direction) from a first interconnect region 120 a into a first side of the memory cell region 102 .
- the fingers 116 of the remaining word line combs 114 extend in a second substantially horizontal direction (the opposite of the y-direction as shown in FIG. 1B ) from a second interconnect region 120 b into a second side of the memory cell region 102 opposite to the first side of the memory cell region.
- the first substantially horizontal direction extends an angle of about 180 degrees (e.g., 160-200 degrees) with respect to the second horizontal direction.
- the fingers 116 of the word line combs are alternately interdigitated in the memory cell region 102 .
- each finger 116 is separated from an overlying and/or underlying finger by a respective insulating layer 117 .
- a row through the memory cell region 102 along a horizontal direction substantially perpendicular to the first and the second substantially horizontal directions comprises at least four fingers of the word line combs, at least four local bit lines, and at least eight memory cells arranged in a following order: a first finger 116 - 1 of the first word line comb 114 a , a first memory cell 104 a , a first local bit line 108 a 1 of the first plurality of electrically conductive local bit lines 108 a , a second memory cell 104 b , a first finger 116 - 3 of the third word line comb 114 c , a third memory cell 104 c , a first local bit line 108 b 1 of the second plurality of electrically conductive local bit lines 108 b , a fourth memory cell 104 d , a first finger 116 - 2 of the second word
- Each memory cell 104 is in contact with one finger 116 of one word line comb 114 and with one local bit line 108 , and so may be individually addressed.
- the memory cells 104 may be any type of memory cells know in the art including, e.g., transistor based memory sells (e.g., NAND cells) or variable resistivity state memory cells.
- the memory device 100 comprises a monolithic, three dimensional resistive random access (ReRAM) non-volatile memory device, where the plurality of memory cells 104 comprise a plurality of variable resistance elements that include a resistivity switching material 103 located at an intersection of and in contact with one finger 116 of one word line comb 114 and one local bit line 108 .
- ReRAM resistive random access
- the material 103 may be a material layer which extends along the sidewalls of the local bit lines 108 .
- the material 103 may comprise any suitable variable resistivity material that can have different electrical resistivity depending on the state, the phase, or the density of microscopic structures such as filaments, within the material.
- the variable resistivity material 103 is a read/write non-volatile memory (NVM) material selected from a chalcogenide and a metal oxide material, and exhibits a stable, reversible shift in resistance in response to an external voltage applied to the material or to a current passed through the material.
- NVM read/write non-volatile memory
- the material 103 may comprise a metal oxide, such as TiOx, HfOx, ZrOx, WOx, NiOx, CoOx, CoAlOx, MnOx, ZnMn 2 O 4 , ZnOx, TaOx, NbOx, HfSiOx, or HfAlOx, where “x” indicates either a stoichiometric metal oxide (e.g., HfO 2 ) or a non-stoichiometric metal oxide (e.g., HfO 2-y ).
- a metal oxide such as TiOx, HfOx, ZrOx, WOx, NiOx, CoOx, CoAlOx, MnOx, ZnMn 2 O 4 , ZnOx, TaOx, NbOx, HfSiOx, or HfAlOx, where “x” indicates either a stoichiometric metal oxide (e.g., HfO 2
- the bit line interconnects 106 may be on opposing sides of the memory cell region 102 .
- the first bit line interconnect 106 a is located below memory cell region 102 and the second bit line interconnect 106 b is located above the memory cell region.
- the first plurality of electrically conductive local bit lines 108 a extend into the memory cell region 102 from below and the second plurality of electrically conductive local bit lines 108 b extend into the memory cell region from above.
- the first bit line interconnect 106 a electrically connected to the first plurality of electrically conductive local bit lines 108 a comprises a first bit line comb 122 a .
- the second bit line interconnect 106 b electrically connected to the second plurality of electrically conductive local bit lines 108 b comprises a second bit line comb 122 b.
- the first and second bit line combs 122 a and 122 b may be arranged such that a local bit line 108 a in the first bit line comb 122 a is interdigitated between two electrically conductive local bit lines 108 b in the second bit line comb 122 b , and a local bit line 108 b in the second bit line comb 122 b is interdigitated between two electrically conductive local bit lines 108 a in the first bit line comb 122 a.
- the memory device 100 may include a plurality of global bit lines 150 , e.g., a first global bit line 150 a and a second global bit line 150 b .
- the device 100 may also include additional global bit lines 150 c , 150 d , etc.
- the first select transistor 110 a comprises a first vertical thin film transistor having an upper source or drain region 111 u of a first conductivity type located above a channel region 111 c of a second conductivity type, a lower drain or source region 111 d of the first conductivity type located below the channel region (e.g., in electrical contact with a global bit line 150 a ), and a first gate electrode 130 a located adjacent to the channel region 111 c.
- the second select transistor 110 b comprises a second vertical thin film transistor having an upper a source or drain region 111 u of the first conductivity type located above a channel region 111 c of the second conductivity type, a lower drain or source region 111 d of the first conductivity type located below the channel region (e.g., in electrical contact with a global bit line 150 b ), and a second gate electrode 130 b located adjacent to the channel region.
- the upper source or drain region 111 u of the first select transistor 110 a is electrically connected to the first bit line interconnect 106 a .
- the lower drain or source region 111 d of the first select transistor 110 a is electrically connected to the first global bit line 150 a which is located below the first select transistor 110 a.
- the upper source or drain region 111 u of the second select transistor 110 b is electrically connected to the second bit line interconnect 106 b , as shown in FIG. 1A .
- the lower drain or source region 111 d of the second select transistor 110 b is electrically connected to the second global bit line 150 b which is located below the second select transistor 110 b.
- the first and the second global bit lines 150 a and 150 b each comprise elongated electrically conductive lines extending in a direction substantially parallel to the fingers 116 of the word line combs 114 (e.g., the y-direction).
- the first and the second gate electrodes 130 a and 130 b comprise first and second portions of a first select gate line 131 a located adjacent to the respective first select transistor 110 a and second select transistor 110 b .
- the first select gate line 131 comprises an elongated electrically conductive line extending in a substantially horizontal direction (the x-direction in FIG. 1A ) substantially perpendicular to the first and the second global bit lines 150 a and 150 b and to the fingers 116 of the word lines combs 114 .
- additional select transistors 110 , select gate lines 131 , and global bit lines 150 may be provided.
- each TFT select transistor 110 is a shared gate transistor with relatively wide channel regions extending over two adjacent global bit lines 150 but electrically contacting only one of the two global bit lines 150 .
- Each select transistor 110 may have two gate electrodes 130 located on opposite side of the channel of the transistor.
- a gate insulating layer may be located between the channel and the gate electrode.
- 1C and 1D includes a third select transistor 110 c which comprises a third vertical thin film transistor, a fourth select transistor 110 d which comprises a fourth vertical thin film transistor, a third global bit line 150 c located between the first and the second global bit lines 150 a and 150 b , and a fourth global bit line 150 d located adjacent to the second global bit line 150 b .
- Some embodiments further include a second select gate line 131 b and a third select gate line 131 c.
- Some embodiments are arranged such that the first, the second, the third and the fourth global bit lines 150 a - 150 d extend substantially parallel to each other in a substantially horizontal direction (as shown the y-direction) below the memory cell region 102 .
- Optional respective electrodes 151 a - 151 d electrically connect the source or drain region 111 d of each transistor 110 to a respective global bit line 150 a - 150 d .
- the electrodes 151 may be omitted and the source or drain region 111 d of each transistor 110 may be located directly on the respective global bit line 150 a - 150 d , as shown in FIG. 1A .
- the first, the second and the third select gate lines 131 a , 131 b , and 131 c extend substantially parallel to each other in a substantially horizontal direction (as shown the x-direction) substantially perpendicular to the first, the second, the third and the fourth global bit lines 150 a - 150 d.
- the first select transistor 110 a is located above the first and the third global bit lines 150 a and 150 c , and between the first and the second select gate lines 131 a and 131 b .
- the second select transistor 110 b is located above the second and the fourth global bit lines 150 b and 150 d , and between the first and the second select gate lines 131 a and 131 b .
- the third select transistor 110 c is located above the first and the third global bit lines 150 a and 150 c and between the second and the third select gate lines 131 b and 131 c .
- the fourth select transistor is 110 a is located above the second and the fourth global bit lines 150 b and 150 d , and between the second and the third select gate lines 131 b and 131 c.
- each select transistor 110 may be used to select a respective bit line interconnect 106 and associated plurality of local bit lines 108 .
- the first select transistor 110 a may be selected by switching on the first and second gate lines 131 a and 131 b along with the first global bit line 150 a .
- the second select transistor 110 b may be selected by switching on the first and second gate lines 131 a and 131 b along with the second global bit line 150 b .
- the third select transistor 110 c may be selected by switching on the second and third gate lines 131 b and 131 c along with the third global bit line 150 c .
- the fourth select transistor 110 d may be selected by switching on the second and third gate lines 131 b and 131 c along with the fourth global bit line 150 d.
- the width of the first select transistor 110 a is about 3 F in a direction (as shown the x-direction) substantially parallel to the first and second select gate lines, where F is a minimum feature size in a semiconductor process used to fabricate the memory device 100 .
- the width of the channel 111 c of the transistor 110 a may be about 3 F.
- the period between a corresponding point in the first and the second transistors 110 a and 110 b is about 4 F in a direction (as shown the x direction) substantially parallel to the first and the second select gate lines 131 a and 131 b .
- the period between a corresponding point in the first and the third transistors 110 a and 110 c is about 2 F in a direction (as shown, the y-direction) substantially perpendicular to the first and the second select gate lines 131 a and 131 b .
- the area of a select transistor module (indicated with dashed lines) containing one of the transistors 110 is about 8 F 2 .
- the area of a memory device module 101 (not shown) located over the select transistor module is about 4 F 2 .
- the word line finger 116 spacing in the memory cell 102 region is about 1 F.
- the shared gate line configuration allows for two memory device modules 101 per select transistor module, reducing the memory device module area by a factor of two relative to the select transistor module area.
- this scaling is advantageous because relatively wide channel thin film transistors may be used, mitigating or reducing potential imperfections or malfunctions (e.g., current leakage) related to using relatively thin channels (e.g., with a width of less than 3 F) for the select transistors 110 .
- FIGS. 2A-D show views of an alternate embodiment of the memory device 200 which is different from the device 100 of FIGS. 1A, 1C and 1E .
- FIGS. 2A and 2B are vertical (i.e., side) cross sectional views along rear plane (A) and front plane (B), respectively, in the perspective view of FIG. 2D .
- FIG. 2D is a close up perspective view of a rear portion of FIG. 2C bounded by the planes (A) and (B) in FIG. 2C .
- the word lines and resistivity switching material components of the device 200 are omitted in the perspective view of FIGS. 2C and 2D .
- the device 200 of FIGS. 2A-2D differs from the device 100 shown in FIGS. 1A, 1C and 1E in several ways.
- the select transistors of the memory device may be planar transistors, e.g., formed at least partially in the upper portion of a substrate 220 , rather than vertical TFTs formed over the global bit lines.
- at least some of the electrodes connecting the select transistors and the bit line interconnects may extend in both vertical and horizontal directions.
- the first select transistor 210 a is planar transistor having a channel region 201 a made of a semiconductor material of a second conductivity type located in a horizontal plane between source region 203 a and drain region 205 a made of a semiconductor region of a first conductivity type.
- the source region may be located out of the plane of FIG. 2A and the drain regions may be located out of the plane of FIG. 2B .
- each is shown in both FIGS. 2A and 2 b to illustrate the relationship between the source and the drain.
- a gate electrode 207 a for the first select transistor 210 a is located adjacent to the channel region 201 a , and is separated from the channel by a gate insulating layer (not shown for clarity).
- the transistor 210 a is a dual gate transistor containing two gates 207 a , 207 aa , two drain regions 205 a , 205 aa , and two channels 201 a , 201 aa on either side of the common source region 203 a .
- the second select transistor 210 b is planar transistor having a channel region 201 b made of a semiconductor material of the second conductivity type located in a horizontal plane between source region 203 b and drain region 205 b made of a semiconductor region of the first conductivity type.
- a gate electrode 207 b for the second select transistor 210 b is located adjacent to the channel region 201 b .
- the transistor 210 b is also dual gate transistor containing two gates 207 b , 207 bb , two drain regions 205 b , 205 bb , and two channels 201 b , 201 bb on either side of the common source region 203 b.
- the channel, source, and drain regions may be formed in an upper portion of the substrate 220 (e.g., proximal the major surface of the substrate), such as a silicon substrate.
- the source and drain regions may be formed using any suitable doping techniques, such as ion implantation.
- the substrate 220 may comprise a p-type doped silicon wafer such that the channel comprises a p-type silicon channel, while the source and drain regions comprise n-type doped regions, such as phosphorus or arsenic implanted regions.
- the adjacent transistors may be isolated from each other by any suitable isolation regions, such as shallow trench isolation (STI) regions 222 .
- STI shallow trench isolation
- the source region 203 a of the first select transistor 210 a is electrically connected to the source line 209 which extends in level M 1 (i.e., the first/lower metal level).
- the first (e.g., left side) drain region 205 a of the first select transistor 210 a is electrically connected to an upper bit line interconnect 106 bb located in level M 4 (i.e., the fourth/top metal level) in the front vertical plane (B) by the electrode 151 a which has a horizontal portion extending in level M 2 (i.e., the second/middle metal level) from the rear vertical plane (A) to the front vertical plane (B).
- the second (e.g., right side) drain region 205 aa of the first select transistor 210 a is electrically connected to a lower bit line interconnect 106 aa located in level M 3 (i.e., the third/upper metal level) in the front vertical plane (B) by the electrode 151 aa which has a horizontal portion extending in level M 2 (i.e., the second/middle metal level) from the rear vertical plane (A) to the front vertical plane (B).
- the first (e.g., left side) gate electrode 207 a of the first select transistor is connected to or comprises a portion of the global bit line 150 a which is located below level M 1 .
- the second (e.g., right side) gate electrode 207 aa of the first select transistor is connected to or comprises a portion of the global bit line 150 aa which is located below level M 1 .
- the source region 203 b of the second select transistor 210 b is electrically connected to the source line 209 which extends in level M 1 (i.e., the first/lower metal level).
- the first (e.g., left side) drain region 205 b of the second select transistor 210 b is electrically connected to another lower bit line interconnect 106 a located in level M 3 (i.e., the third/upper metal level) in the rear vertical plane (A) by the electrode 151 b which extends vertically through level M 2 (i.e., the second/middle metal level).
- the second (e.g., right side) drain region 205 bb of the second select transistor 210 b is electrically connected to another upper bit line interconnect 106 b located in level M 4 (i.e., the fourth/top metal level) the rear vertical plane (A) by the electrode 151 bb which extends vertically through level M 2 (i.e., the second/middle metal level).
- the first (e.g., left side) gate electrode 207 b is connected to or comprises a portion of a global bit line 150 b which is located below level M 1 .
- the second (e.g., right side) gate electrode 207 bb is connected to or comprises a portion of a global bit line 150 bb which is located below level M 1 .
- the electrodes 151 b , 151 bb extend vertically in the rear vertical plane (A).
- the electrodes 151 a , 151 aa start out vertically in the rear vertical plane (A), then extend horizontally in level M 2 from plane (A) to the front vertical plane (B) and then again extend vertically in plane (B).
- the gate electrode 207 a of the first select transistor comprises a portion of the global bit line 150 a .
- the global bit line 150 a extends in a first horizontal direction (e.g., y-direction) over the first planar select transistor 210 a and an imaginary straight line 224 signifying the charge carrier (e.g., electron) flow direction in the channel between the source 203 a and the drain 205 a of the first planar select transistor 210 a extends in a second horizontal direction at an angle with respect to the first horizontal direction, e.g., an angle in the range of 20 to 70 degrees, as shown in FIG. 2C .
- a similar imaginary line signifies the charge carrier flow direction between the source 203 a and drain 205 aa.
- the gate electrode 207 b of the second select transistor 210 b comprises a portion of the global bit line 150 b .
- the third global bit line extends in the first horizontal direction over the planar second select transistor 210 b and an imaginary straight line between the source 203 b and the drain 205 b of the second planar select transistor 210 b extends in a second horizontal direction at an angle with respect to the first horizontal direction, e.g., an angle in the range of 20 to 70 degrees, similar to line 224 for transistor 210 a.
- the source line 209 extends in a third horizontal direction (e.g., x-direction) which is substantially perpendicular to the first horizontal direction.
- the source line 209 may contain horizontally and/or vertically extending electrodes 219 which contact the source regions 203 a , 203 b.
- FIG. 2E illustrates the details of the four transistors 210 a , 210 b , 210 c and 210 d from FIG. 2C without illustrating the electrodes, interconnects and bit lines for clarity.
- each transistor 210 a - 210 d has a first channel region 201 aa , 201 b , 201 cc and 201 d of a second conductivity type (e.g., p-type) located in a horizontal plane between respective source region 203 a , 203 b , 203 c and 203 d and a first drain region 205 aa , 205 b , 205 cc , 205 d of a first conductivity type (e.g., n-type).
- a second conductivity type e.g., p-type
- Transistor 210 c is located adjacent to transistor 210 a in a first horizontal direction (e.g., the y-direction) in the horizontal plane.
- a first channel edge 261 a containing the source region 203 a of the transistor 210 a faces a second channel edge 262 c containing the source region 203 c of transistor 210 c .
- Transistor 210 b is located adjacent to transistor 210 a in a second horizontal direction (e.g., the x-direction) in the horizontal plane.
- a third channel edge 263 a containing the first drain region 205 aa of transistor 210 a faces a fourth channel edge 264 b containing the first drain region 205 b of transistor 210 b .
- the second horizontal direction (e.g., the direction) is substantially perpendicular to the first horizontal direction (e.g., the direction).
- Transistor 210 d is located adjacent to transistor 210 c in the second horizontal direction (e.g., the x-direction) in the horizontal plane.
- a third channel edge 263 c containing the first drain region 205 cc of transistor 210 c faces a fourth channel edge 264 d containing the first drain region 205 d of transistor 210 d .
- Transistor 210 d is also located adjacent to adjacent to transistor 210 b in the first horizontal direction (e.g., the y-direction) in the horizontal plane.
- a first channel edge 261 b containing the source region 203 b transistor 210 b faces a second channel edge 262 d containing the source region 203 d of transistor 210 d.
- the first channel edge 261 of each transistor is located opposite the second channel edge 262 the same transistor, while the third channel edge 263 of each transistor is located opposite the fourth channel edge 264 of the same transistor.
- in the source region of each transistor 203 is offset in both the first and the second directions (i.e., in both the y and the x directions) with respect to the first drain region 205 of the same transistor (e.g., along line 224 shown in FIG. 2C ).
- the common source line 209 extends in the second direction (e.g., the x-direction) between transistors 210 a and 210 c and between transistors 210 b and 210 d .
- the source line 209 is electrically connected to the source regions 203 a - 203 d of the respective transistors 210 a - 210 d , as shown in FIG. 2C .
- a first common gate electrode 150 aa extends in the first direction (e.g., the y-direction) over the channel regions 201 aa , 201 cc between respective source regions 203 a , 203 c and the first drain regions 205 aa , 205 cc of transistors 210 a , 210 c .
- a second common gate electrode 150 b extends in the first direction over the channel regions 201 b , 201 d between respective source regions 203 b , 203 d and first drain regions 205 b , 205 d of transistors 210 b , 210 d.
- the transistors 210 a - 210 d may be dual channel/dual gate transistors.
- a second drain region 205 a is located in a fourth channel edge 264 a of transistor 210 a
- a second drain region 205 c is located in a fourth channel edge 264 c of transistor 201 c
- a second drain region 205 bb is located in a third channel edge 263 b of transistor 210 b
- a second drain region 205 dd is located in a third channel edge 263 d of transistor 210 d .
- a third common gate electrode 150 a extends in the first direction (e.g., the y-direction) over the channel regions 201 a , 201 c between respective source regions 203 a , 203 c and second drain regions 205 a , 205 c of transistors 210 a , 210 c .
- a fourth common gate electrode 150 bb extends in the first direction over the channel regions 201 bb , 201 dd between respective source regions 203 b , 203 d and second drain regions 205 bb , 205 dd of transistors 210 b , 210 d .
- the first common gate 150 aa electrode is connected to or comprises a portion of the first global bit line
- the second common gate electrode 150 b is connected to or comprises a portion of the second global bit line
- the third common gate electrode 150 a is connected to or comprises a portion of the third global bit line
- the fourth common gate electrode 150 bb is connected to or comprises a portion of the fourth global bit line.
- FIG. 2F is a close up perspective view of a front portion of FIGS. 2C and 2E bounded by the planes (C) and (D) in FIGS. 2C and 2E .
- the first drain region 205 aa , 205 b , 205 cc , 205 d of the respective select transistors 210 a , 210 b , 210 c and 210 d is electrically connected to a respective first 106 aa , second 106 a , third 106 a 3 and fourth 106 a 4 lower bit line interconnects.
- the second drain region 205 a , 205 bb , 205 c , 205 dd of the respective select transistors 210 a , 210 b , 210 c and 210 d is electrically connected to a respective first 106 bb , second 106 b , third 106 b 3 and fourth 106 b 4 upper bit line interconnects.
- the third 106 a 3 and fourth 106 a 4 lower bit line interconnects are connected to the respective drain regions by respective electrodes 151 c 3 and 151 d 3 .
- the third 106 b 3 and fourth 106 b 4 upper bit line interconnects are connected to the respective drain regions by respective electrodes 151 c 4 and 151 d 4 , as shown in FIG. 2F .
- the first 106 aa , second 106 a , third 106 a 3 and fourth 106 a 4 lower bit line interconnects are located below memory cell region 102
- the first 106 bb , second 106 b , third 106 b 3 and fourth 106 b 4 upper bit line interconnects are located above the memory cell region 102 , as shown in FIGS. 2A-2B .
- a first plurality of electrically conductive local bit lines 108 a are located in the vertical plane (C). These bit lines extend into the memory cell region 102 from below and are electrically connected to the lower bit line interconnect 106 a 3 , as shown in FIG. 2F .
- a second plurality of electrically conductive local bit lines 108 a are located in the vertical plane (D). These bit lines extend into the memory cell region 102 from below and are electrically connected to the lower bit line interconnect 106 a 4 , as shown in FIG. 2F .
- a third plurality of electrically conductive local bit lines 108 a are located in the vertical plane (B). These bit lines extend into the memory cell region 102 from below and are electrically connected to the lower bit line interconnect 106 aa , as shown in FIGS. 2C and 2D .
- a fourth plurality of electrically conductive local bit lines 108 a are located in the vertical plane (A). These bit lines extend into the memory cell region 102 from below and are electrically connected to the lower bit line interconnect 106 a , as shown in FIG. 2C .
- a fifth plurality of electrically conductive local bit lines 108 b are interdigitated with the second plurality of electrically conductive local bit lines 108 a in the vertical plane (D). These bit lines 108 b extend into the memory cell region 102 from above and are electrically connected to the upper bit line interconnect 106 b 3 , as shown in FIG. 2F .
- a sixth plurality of electrically conductive local bit lines 108 b are interdigitated with the first plurality of electrically conductive local bit lines 108 a in the vertical plane (C). These bit lines 108 b extend into the memory cell region 102 from above and are electrically connected to the second upper bit line interconnect 106 b 4 , as shown in FIG. 2F .
- a seventh plurality of electrically conductive local bit lines 108 b are interdigitated with the third plurality of electrically conductive local bit lines 108 a in the vertical plane (B). These bit lines 108 b extend into the memory cell region 102 from above and are electrically connected to the upper bit line interconnect 106 bb .
- An eighth plurality of electrically conductive local bit lines 108 b are interdigitated with the fourth plurality of electrically conductive local bit lines 108 a in the vertical plane (A). These bit lines 108 b extend into the memory cell region 102 from above and are electrically connected to the upper bit line interconnect 106 b , as shown in FIGS. 2C-2D .
- FIGS. 3A-3F illustrate a word line 112 contact scheme for a memory device of the types described herein, such as the devices of FIGS. 1A-1E or FIGS. 2A-2F .
- FIGS. 3A-3F illustrate how the fingers 116 of the same comb 114 may be electrically connected to each other by a word line interconnect 113 , such as a sidewall bridge word line interconnect in region 115 which is shown in FIG. 1B .
- FIG. 3A is a schematic perspective view of the word line combs and word line interconnects
- FIGS. 3B and 3C are respective electrical schematic view and top view of the word line combs and word line interconnects shown in FIG. 3A .
- FIGS. 3D, 3E and 3F are close up perspective views of a portion the word line combs and word line interconnects of FIGS. 3A and 3C .
- each of the first 114 - 1 , second 114 - 2 , third 114 - 3 and fourth 114 - 4 word line combs may be positioned diagonally with respect to the horizontal direction (e.g., the x-direction), such that one side of the comb (e.g., the left or the right side) is located below the opposite side (e.g., the other one of the left or the right side in FIGS. 3B and 3F ) of the same comb.
- each comb extends in both the vertical direction (e.g., z-direction) and a first horizontal direction (e.g., the x-direction).
- the fingers 116 extend away from the interconnect 113 in the second horizontal direction (e.g., the y-direction) which is perpendicular to the first horizontal direction.
- FIG. 3F shows one part of a word line comb 114 containing four contact pads and four associated fingers.
- the word line comb 114 may corresponds to one of word line combs 114 a to 114 d in FIG. 1B or it may correspond to one of the word line combs 114 - 1 to 114 - 4 in FIGS. 3A-3C .
- the word line combs 114 a to 114 d in FIG. 1B may be the same as the respective word line combs 114 - 1 to 114 - 4 in FIGS. 3A-3C .
- each may extend in the same horizontal x-y plane and thus be different from the diagonal word line combs 114 - 1 to 114 - 4 in FIGS. 3A-3C which do not extend in the same horizontal plane and instead c as shown in FIGS. 3A, 3B and 3F .
- a four finger portion of one exemplary word line comb 114 of an embodiment of the present disclosure which may correspond to one of the combs 114 - 1 to 114 - 4 or to one of the combs 114 a to 114 d is shown in FIG. 3F .
- the comb 114 includes a first finger 116 a located in a first device level (i.e., in level “a” or L 1 ), a second finger 116 b located in a second device level (i.e., in level “b” or L 2 ) above the first device level, a third finger 116 c located in a third device level (i.e., in level “c” or L 3 ) above the second device level, and a fourth finger 116 d located in a fourth device level (i.e., in level “d” or L 4 ) above the third device level.
- the first, second, third and fourth fingers are offset from each other in a horizontal direction (e.g., the x-direction).
- a word line interconnect 113 (e.g., the sidewall bridge interconnect shown in FIGS. 3D and 3E ) electrically connects the first, second, third and fourth fingers at their respective contact pads 316 a , 316 b , 316 c and 316 d , which are located in respective device levels a-d (e.g., L 1 -L 4 ).
- each comb 114 is connected to a driver circuit (e.g., via global word line 350 ) by a single electrode 351 connected to the lowest contact pad 316 a .
- each word line comb is connected to a global word line 350 located below the memory cell region 102 by a respective electrode 351 .
- This means that outside electrical connection to the upper levels of the word lines is not required and all outside electrical connections to diagonally stacked word line combs can be formed on the bottom side of the combs 114 and below the second level (e.g., level “b”/L 2 ) of the memory cell region 102 .
- the first word line comb 114 - 1 includes a first finger 116 - la located in the first device level, a second finger 116 - 1 b located in the second device level above the first device level, a third finger 116 - 1 c located in the third device level above the second device level, and a fourth finger 116 - 1 d located in the fourth device level above the third device level.
- the first, second, third and fourth fingers are offset from each other in a horizontal direction (e.g., the x-direction).
- the word line interconnect 113 - 1 electrically connects the first, second, third and fourth fingers.
- the word line interconnects 113 - 1 , 113 - 2 , 113 - 3 and 113 - 4 are located outside the memory cell region 102 in one of the interconnect regions 120 a or 120 b which are spaced from the memory cell region 102 in a perpendicular horizontal direction (e.g., the y-direction).
- the word line interconnect 113 - 1 of word line comb 114 - 1 shown in FIGS. 3A and 3B is located in interconnect region 120 a in area 3 A shown by the dashed lines in FIG. 3C .
- Interconnect 113 - 2 is also located in region 120 a .
- Interconnects 113 - 3 and 113 - 4 are located in interconnect region 120 b located on the opposite side of the memory cell region 102 from region 120 a.
- each word line finger 116 may include a contact pad 316 which is located in electrical contact with the respective finger 116 .
- the contact pad 316 is located in the same vertical device level as its respective finger 116 .
- each respective finger 116 - 1 , 116 - 2 , 116 - 3 and 116 - 4 contacts a respective contact pad 316 - 1 , 316 - 2 , 316 - 3 and 316 - 4 located in one of the interconnect regions 120 a or 120 b .
- the pads 316 are also located in the various vertical device levels.
- the first word line comb 114 - 1 includes the first finger 116 - la which contacts pad 316 - la located in the first device level, the second finger 116 - 1 b which contacts pad 316 - 1 b located in the second device level above the first device level, the third finger 116 - 1 c which contacts pad 316 - 1 c located in the third device level above the second device level, and the fourth finger 116 - 1 d which contacts pad 316 - 1 ad located in the fourth device level above the third device level, as shown in FIGS. 3A and 3B .
- each word line comb 114 includes fingers 116 , pads 316 and interconnect 113 which electrically connects the fingers 116 together into a single word line electrode by physically connecting the pads 316 of each finger 116 in the comb 114 .
- the first (lowest) device level contact pads 316 - 1 a , 316 - 2 a , 316 - 3 a and 316 - 4 a may have a bottom surface in contact with an optional respective word line electrode 350 - 1 , 350 - 2 , 350 - 3 and 350 - 4 .
- Each word line electrode 350 - 1 , 350 - 2 , 350 - 3 and 350 - 4 is electrically connected to a respective global word line 351 - 1 , 351 - 2 , 351 - 3 and 351 - 4 .
- the global word lines may extend in a horizontal direction (e.g., y-direction) below the memory cell region 102 , and either above, below or co-planar with the global bit lines 150 .
- FIGS. 3D and 3E are mirror image type views from the views of FIGS. 3A and 3B .
- region 3 D in FIG. 3A is a mirror image type close up of the interconnect shown in FIG. 3D .
- the word line interconnect 113 (e.g., interconnect 113 - 1 shown in region 3 D in FIG. 3A ) includes a first conductive vertical rail 12 a which extends in the first or the second horizontal direction (e.g., the horizontal y-direction or 180 degrees from the y-direction) and contacts a contact pad 316 - 1 aa of the first finger 116 - 1 aa in the first device level (e.g., in the lowest level “a” which corresponds to word line level “L 1 ”).
- the word line interconnect 113 also includes a second conductive vertical rail 12 b which extends in the same first or the second horizontal direction as the first rail (e.g., in the y-direction or 180 degrees from the y-direction) and contacts a contact pad 316 - 1 b of the second finger 116 - 1 b in the second device level.
- a first conductive sidewall bridge 12 c extends in a third horizontal direction (e.g., in the x-direction) substantially perpendicular to the first and the second horizontal directions. The conductive sidewall bridge 12 c contacts both the first 12 a and the second 12 b conductive vertical rails.
- the conductive sidewall bridge, the conductive vertical rails, the contact pads and the fingers may comprise any one or more c
- the interconnect pattern of two rails contacting the contact pads in adjacent device levels and a sidewall bridge connecting the two rails is then repeated for the remaining contact pads in the remaining device levels.
- a third conductive vertical rail 23 a extends in the first or the second horizontal direction and contacts another contact pad 316 - 1 bb of another second finger 116 - 1 bb in the second device level (e.g., device level “b” which corresponds to word line level “L 2 ”).
- the third conductive vertical rail 23 a contains two portions which are located on opposite sides of the first rail 12 a .
- the first rail 12 a extends to pad 316 - 1 aa through an opening the pads 316 - 1 bb and 316 - 1 cc , while the third rail 23 a portions extend only partially through the opening in pad 316 - 1 cc.
- a fourth conductive vertical rail 23 b extends in the first or the second horizontal direction and contacts a contact pad 316 - 1 c of the third finger 116 - 1 c in the third device level.
- the fourth conductive vertical rail 23 b contains two portions which are located on opposite sides of the second rail 12 b .
- the second rail 12 b extends to pad 316 - 1 b through an opening the pads 316 - 1 c and 316 - 1 d , while the fourth rail 23 b portions extend only partially through the opening in pad 316 - 1 d.
- a second conductive sidewall bridge 23 c extends in a third horizontal direction substantially perpendicular to the first and the second horizontal directions.
- the second bridge 23 c contains two portions which are located on opposite sides of the first bridge 12 c .
- the second bridge 23 c contacts both the third 23 a and the fourth 23 b conductive vertical rails.
- a fifth conductive vertical rail 34 a extends in the first or the second horizontal direction and contacts a contact pad 316 - 1 cc of the third finger 116 - 1 cc in the third device level (e.g., device level “c” which corresponds to word line level “L 3 ”).
- a sixth conductive vertical rail 34 b extends in the first or the second horizontal direction and contacts a contact pad 316 - 1 d of the fourth finger 316 - 1 d in the fourth device level (e.g., device level “d” which corresponds to word line level “L 4 ”).
- a third conductive sidewall bridge 34 c extends in a third horizontal direction substantially perpendicular to the first and the second horizontal directions, and contacts both the fifth 34 a and the sixth 34 b conductive vertical rails.
- the contact pads 316 - 1 aa , 316 - 1 bb and 316 - 1 cc are stacked above each other in stack 322 .
- the contact pads 316 - 1 a , 316 - 1 b , 316 - 1 c and 316 - 1 d are stacked above each other in stack 324 which is horizontally separated from stack 322 in the third horizontal direction (e.g., the x-direction).
- the fingers 116 - 2 a , 116 - 2 b , 116 - 2 c and 116 - 2 d of another word line comb 114 - 2 extend in the first or the second horizontal direction between the stacks 322 and 324 .
- the conductive sidewall bridges 12 c , 23 c and 34 c of the word line interconnect 113 - 1 of word line comb 114 - 1 extend over the fingers 116 - 2 a , 116 - 2 b , 116 - 2 c and 116 - 2 d of the word line comb 114 - 2 .
- the fingers 116 - 2 a , 116 - 2 b , 116 - 2 c and 116 - 2 d of word line comb 114 - 2 may be covered by an insulating layer 330 , such as a silicon nitride hard mask layer, which electrically isolates the upper finger 116 - 2 d from the conductive sidewall bridges 12 c , 23 c and 34 c of the word line interconnect 113 - 1 of word line comb 114 - 1 .
- an insulating layer 330 such as a silicon nitride hard mask layer
- the fingers 116 - 2 a , 116 - 2 b , 116 - 2 c and 116 - 2 d of word line comb 114 - 2 extend to a different word line interconnect 113 - 2 which is offset from the interconnect 113 - 1 in the first or the second horizontal directions in the interconnect region 120 a , as shown in FIG. 3A .
- the above pattern is repeated in the third horizontal direction (i.e., the x-direction), as shown in FIG. 3E .
- the contact pads 316 - 1 aa , 316 - 1 bb , 316 - 1 cc and 316 - dd in stack 322 extend in the first or the second horizontal directions (e.g., the y-direction or 180 degrees from the y-direction) past the sidewall bridges 12 c , 23 c and 34 c.
- a set vertical conductive rails 12 bb , 23 bb and 34 bb contacts rear (or front depending on the viewpoint) of the respective contact pads 316 - 1 bb , 316 - 1 cc and 316 - 1 dd in stack 322 .
- Another set of conductive rails 12 aa , 23 aa and 34 aa contacts rear (or front depending on the viewpoint) of the respective contact pads 316 - 1 a 3 , 316 - 1 b 3 and 316 - 1 c 3 in stack 326 .
- Another set of sidewall bridges 12 cc , 23 cc and 34 cc connects the respective set of rails 12 aa - 12 bb , 23 aa - 23 bb and 34 aa - 34 bb to each other.
- Fingers 116 - 2 aa , 116 - 2 bb , 116 - 2 cc and 116 - 2 dd of another word line comb 114 - 2 extend in the first or the second horizontal direction between the stacks 322 and 326 .
- the conductive sidewall bridges 12 cc , 23 cc and 34 cc of the word line interconnect 113 - 1 of word line comb 114 - 1 extend over the fingers 116 - 2 aa , 116 - 2 bb , 116 - 2 cc and 116 - 2 dd of the word line comb 114 - 2 .
- the above pattern is repeated for all interconnects in the third horizontal direction (i.e., the x-direction), as shown in FIGS. 3A-3C .
- each pair of finger 116 and pad 316 in a stack are separated from an overlying and/or underlying finger and pad pair by a respective insulating layer.
- the insulating layers 117 are not shown in FIGS. 3A-3F for clarity.
- the interconnect is described above as the word line interconnect 113 which includes the rails and the sidewall bridges for a three dimensional ReRAM device, it should be understood that the interconnect may be used for any other suitable device, such another memory device (e.g., a NAND memory device) or a non-memory device, such as a logic device. Furthermore, the interconnect does not have to connect word line portions, such as combs, and may be used to connect bit line portions or any other conductors.
- FIGS. 4A-4X illustrate a method of making an interconnect between electrodes in a three dimensional device.
- the method of making the interconnect will be described below as the method of making the word line interconnect 113 which includes the rails and the sidewall bridges for a three dimensional ReRAM device of FIGS. 3A-3F , it should be understood that the method may be used to make an interconnect for any other suitable device, such another memory device (e.g., a NAND memory device) or a non-memory device, such as a logic device. Furthermore, the interconnect does not have to connect word line portions and may be used to connect bit line portions or any other conductors.
- the method includes providing the first stack 324 of electrodes 316 comprising a first electrode (e.g., contact pad) 316 - la located in the first device level, a second electrode (e.g., contact pad) 316 - 1 b located in the second device level above the first device level, a third electrode (e.g., contact pad) 316 - 1 c located in the third device level above the second device level, and a fourth electrode (e.g., contact pad) 316 - 1 d located in a fourth device level above the third device level.
- a first electrode e.g., contact pad
- a second electrode e.g., contact pad
- 316 - 1 b located in the second device level above the first device level
- a third electrode e.g., contact pad
- a fourth electrode e.g., contact pad
- the method also includes providing the second stack 322 of electrodes 316 which is offset in a substantially horizontal direction (e.g., in the x-direction) from the first stack 324 of electrodes.
- the second stack 322 of electrodes comprises a first electrode (e.g., contact pad) 316 - 1 aa located in the first device level, a second electrode (e.g., contact pad) 316 - 1 bb located in the second device level above the first device level, a third electrode (e.g., contact pad) 316 - 1 cc located in the third device level above the second device level, and a fourth electrode (e.g., contact pad) 316 - 1 dd located in the fourth device level above the third device level.
- the method also includes forming an insulating fill layer 402 over the first 324 and the second 322 stacks of electrodes.
- a first opening 404 is formed to the fourth electrode 316 d in the first stack 324 of electrodes through the insulating fill layer 402 .
- the first opening 404 may be formed using any suitable patterning method, such as photolithography and etching through a first mask 406 .
- a second opening 408 is formed through the insulating fill layer 402 and through the fourth electrode 316 dd to the third electrode 316 cc in the second stack 322 of electrodes, as shown in FIG. 4C .
- the second opening 408 may be formed using any suitable patterning method, such as photolithography and etching through a second mask 410 .
- the center portion of the insulating fill layer 402 between the stacks 322 and 324 may then be removed to form a connecting opening 412 which connects the upper parts of the first 404 and the second 408 openings.
- the connecting opening 412 may be formed using any suitable patterning method, such as photolithography and etching through a third mask 414 .
- the etching may be selective to the insulating layer 402 (e.g., silicon oxide) and may stop on the silicon nitride etch stop layer 330 located over the word line fingers 116 - 2 , and on the exposed portions of the electrodes 316 - 1 d and 316 - 1 cc in the respective openings 404 and 408 .
- a first insulating layer 416 is formed in the first 404 and the second 408 openings.
- Any suitable insulating material may be used, such as silicon oxide, silicon nitride, etc.
- the first insulating layer 416 may be a silicon oxide isolation layer located on sidewalls of the first 404 and the second 408 openings.
- the first insulating layer 416 is located on sidewalls and bottoms of the first, the second and the connecting openings.
- the first insulating layer 416 may be etched using an anisotropic sidewall spacer anisotropic etch to remove layer 416 from the horizontal surfaces (e.g., from the bottoms of the first and the second openings) and to leave insulating sidewall spacers (i.e., spacer portions) 416 S on the sidewalls of the openings 404 and 408 .
- the fourth electrode 316 - 1 d is exposed in the bottom of the first opening 404 and the third electrode 316 - 1 cc is exposed in the bottom of the second opening 408 between the insulating sidewalls spacers 416 S.
- FIG. 4T is a perspective view of FIG. 4F .
- a first conductive layer 418 is conformally formed in the first 404 , the second 408 and the connecting 412 openings such that the first conductive layer 418 is located on the first insulating layer (e.g., over the insulating spacer 416 S portions of layer 416 ) over the sidewalls of the first, second and the connecting openings.
- the first conductive layer 418 may be any suitable conductive layer described above for forming the rails and bridges, such as tungsten, tungsten nitride, titanium, titanium nitride, aluminum, copper, their alloys, etc.
- the first conductive layer 418 electrically contacts and connects the fourth electrode 316 - 1 d exposed in the first opening 404 and the third electrode 316 - 1 cc exposed in the second opening 408 .
- the first conductive layer 418 may be etched using an anisotropic sidewall spacer anisotropic etch to remove layer 418 from the horizontal surfaces (i.e., from the bottoms of the first and the second openings) and to leave conductive sidewall spacers (e.g., spacer portions) 418 S on the sidewalls of the openings 404 , 408 and 412 .
- anisotropic sidewall spacer anisotropic etch to remove layer 418 from the horizontal surfaces (i.e., from the bottoms of the first and the second openings) and to leave conductive sidewall spacers (e.g., spacer portions) 418 S on the sidewalls of the openings 404 , 408 and 412 .
- Each spacer 418 S forms the fifth pillar 34 a portions in the second opening 408 in contact with the edge portions of the third electrode 316 - 1 cc , sixth pillar 34 b portions in the first opening 404 in contact with the edge portions of the fourth electrode 316 - 1 d , and third bridge portions 34 c in the connecting opening 412 (i.e., the spacers 418 S form an interconnection between word lines levels L 3 and L 4 shown in FIG. 3D ).
- FIG. 4U is a perspective view of FIG. 4H .
- the first opening 404 is extended by selective anisotropic etching through the fourth electrode 316 - 1 d and through the underlying interlayer insulating layer 117 to expose the third electrode 316 - c in the first electrode stack 324 without removing the first conductive layer 418 (i.e., the first conductive spacers 418 S) from over the sidewalls of the first opening 404 .
- the second opening 408 is also extended at the same time by the selective etching through the third electrode 316 - 1 cc to expose the second electrode 316 - 1 bb in the second electrode stack 322 without removing the first conductive layer 418 (i.e., the first conductive spacers 418 S) from over the sidewalls of the second opening 408 .
- FIG. 4W is a perspective view of FIG. 4I .
- a second insulating layer 426 (e.g., a silicon oxide layer) is formed in the first 404 and the second 408 openings such that the second insulating layer is located on sidewalls of the first, the second and the connecting openings (i.e., over the first conductive sidewall spacers 418 S).
- the second insulating layer 426 may be etched using a sidewall spacer anisotropic etch to remove layer 426 from the horizontal surfaces and to leave second insulating sidewall spacers 426 S on the sidewalls of the openings 404 , 408 and 412 (i.e., over the first conductive sidewall spacers 418 S).
- the third electrode 316 - 1 c is exposed in the bottom of the first opening 404 and the second electrode 316 - 1 bb is exposed in the bottom of the second opening 408 between the insulating sidewalls spacers 426 S.
- FIG. 4X is a perspective view of FIG. 4K .
- a second conductive layer 428 is formed in the first 404 and the second 408 openings.
- the second conductive layer 428 is located on the second insulating layer 426 (e.g., on the spacers 426 S) over the sidewalls of the first, the second and the connecting openings.
- the second conductive layer 428 electrically contacts and connects the third electrode 316 - 1 c exposed in the first opening 404 and the second electrode 316 - 1 bb exposed in the second opening 408 .
- the second conductive layer 428 may be etched using a sidewall spacer anisotropic etch to remove layer 428 from the horizontal surfaces and to leave conductive sidewall spacers 428 S on the sidewalls of the openings 404 , 408 and 412 .
- Each spacer 428 S forms the third pillar 23 a portions in the second opening 408 in contact with the edge portions of the second electrode 316 - 1 bb , fourth pillar 23 b portions in the first opening 404 in contact with the edge portions of the third electrode 316 - 1 c , and second bridge portions 23 c in the connecting opening 412 (i.e., the spacers 428 S form an interconnection between word lines levels L 2 and L 3 shown in FIG.
- the middle part of the third electrode 316 - 1 c is exposed in the bottom of the first opening 404 and the middle part second electrode 316 - 1 bb is exposed in the bottom of the second opening 408 between the conductive sidewalls spacers 428 S (i.e., the between the pillar 23 a , 23 b portions).
- the first opening 404 is extended by selective etching through the third electrode 316 - 1 c to expose the second electrode 316 - 1 b in the first electrode stack 324 without removing the second conductive layer 428 (e.g., the spacers 428 S) from over the sidewalls of the first opening.
- the second opening 408 is also extended during the same selective etch through the second electrode 316 - 1 bb to expose the first electrode 316 - aa in the second electrode stack 322 without removing the second conductive layer 428 (e.g., the spacers 428 S) from over the sidewalls of the second opening.
- a third insulating layer 436 is formed in the first 404 and the second 408 openings such that the third insulating layer is located on sidewalls of the first, the second and the connecting openings.
- the third insulating layer 436 may be etched using a sidewall spacer anisotropic etch to remove layer 436 from the horizontal surfaces and to leave third insulating sidewall spacers 436 S on the sidewalls of the openings 404 , 408 and 412 (i.e., over the second conductive sidewall spacers 428 S).
- the second electrode 316 - 1 b is exposed in the bottom of the first opening 404 and the first electrode 316 - 1 aa is exposed in the bottom of the second opening 408 between the insulating sidewalls spacers 436 S.
- a third conductive layer 438 is formed in the first 404 , the second 408 and the connecting 412 openings.
- the third conductive layer 438 is located on the third insulating layer 436 (e.g., the spacers 436 S) over the sidewalls of the first, the second and the connecting openings.
- the third conductive layer 438 electrically contacts and connects the second electrode 316 - 1 b exposed in the first opening 404 and the first electrode 316 - 1 aa exposed in the second opening 408 .
- the third conductive layer 438 may be etched back to remove layer 438 from the connecting opening 412 while leaving the layer 438 to fill the remaining volume of the first 404 and the second 408 opening.
- the remaining portions of layer 438 form the first pillar 12 a portions in the second opening 408 in contact with the middle portion of the first electrode 316 - 1 aa , second pillar 12 b portions in the first opening 404 in contact with the middle portion of the second electrode 316 - 1 b , and first bridge 12 c in the connecting opening 412 (i.e., layer 438 forms an interconnection between word lines levels L 1 and L 2 shown in FIG. 3D ).
- gap fill insulating layer 440 (e.g., silicon oxide) is formed over layer 438 to fill the connecting opening 412 .
- gap fill insulating layer may include a liner and a filler material located over the liner.
- the first, second, third and fourth electrodes in the first stack 324 comprise a first stack of word line fingers 116 and contact pads 316 .
- the first, second, third and fourth electrodes in the second stack 322 comprise a second stack of word line fingers 116 and contact pads 316 .
- the first 418 , second 428 and third 438 conductive layers comprise respective first, second and third word line interconnects which connect one word line finger in one level in the first stack with a word line finger in another level in the second stack of a three dimensional device, such as a monolithic, three dimensional resistive random access (ReRAM) non-volatile memory device.
- a three dimensional device such as a monolithic, three dimensional resistive random access (ReRAM) non-volatile memory device.
- ReRAM resistive random access
- FIGS. 5A-5O show steps in a method of making a contact to a semiconductor device according to another embodiment.
- the method of making the contacts will be described below as the method of making the contacts to the select TFTs 110 of a three dimensional ReRAM device of FIGS. 1C-1D , it should be understood that the method may be used to make contacts to any other suitable device, such another memory device (e.g., a NAND memory device) or a non-memory device, such as a logic device.
- a memory device e.g., a NAND memory device
- a non-memory device such as a logic device.
- an in-process memory device is provided in step 50 .
- the device includes the global bit lines 150 and the electrodes 151 separated by an insulating fill 500 .
- the lines 150 and electrodes 151 may comprise any suitable conductive material, such as tungsten, tungsten nitride, titanium, titanium nitride, aluminum, copper, their alloys, etc.
- the insulating fill 500 may comprise any suitable insulating material, such as silicon oxide.
- Step 50 includes forming a conductive layer 501 over a semiconductor containing stack 503 .
- the conductive layer 501 may be a metal (e.g., tungsten, etc.) layer formed over a stack 503 including a lower barrier layer (e.g., TiN, or WN) 503 a , a semiconductor layer (e.g., polysilicon layer) 503 b and an upper barrier layer (e.g., TiN or WN) 503 c .
- a lower barrier layer e.g., TiN, or WN
- a semiconductor layer e.g., polysilicon layer
- an upper barrier layer e.g., TiN or WN
- the metal layer 501 may be relatively thin in comparison to the semiconductor layer 503 .
- Some embodiments may include forming a mask layer 504 over the conductive layer 501 .
- the mask layer 504 may be a hard mask layer, such as a silicon nitride layer.
- FIG. 5B shows the top view of the device and FIG. 5A is a side (i.e., vertical) cross section along line a-a′ in FIG. 5B .
- step 51 includes forming a first mask pattern (e.g., in the mask layer 504 ) over the conductive layer 501 (e.g., using photolithographic techniques) that exposes selected portion of the conductive layer 501 .
- the first mask pattern 505 includes a first plurality of openings 505 a , such as line shaped openings extending in a first horizontal direction and a second plurality of line shaped openings extending in a second horizontal direction substantially parallel to the first, such that the exposed portions are an array of rectangular exposed regions on the conductive layer 501 .
- other geometries for the first mask pattern may be used (e.g., exposing circular rather than rectangular regions of the conductive layer 501 ).
- step 52 includes etching portions of the conductive layer 501 and the semiconductor containing stack 503 exposed in the first mask pattern 505 to form a plurality of pillars 507 .
- Each pillar comprises a lower semiconductor region 507 a (e.g., polysilicon pillar having top and bottom TiN barrier portions) and an upper conductive region 507 b .
- plurality of pillars 507 includes an array of rectangular pillars. However, it is to be understood that other pillar shapes may be used, e.g., circular pillars.
- step 53 includes forming an insulating fill layer 509 between the plurality of pillars 507 .
- the insulating fill layer may be made of any suitable electrically insulating material, e.g., silicon oxide.
- step 53 may further include planarizing the device (e.g., using an etch back or chemical mechanical polishing process) to form a planar surface that exposes the tops of the pillars 507 (which, in some embodiments will include a residual portion of the mask layer 504 ).
- Each region 507 b form the channel 211 of the TFT select gate transistor 210 shown in FIGS. 1C and 1D .
- FIG. 5F shows the top view of the device and FIG. 5E is a side (i.e., vertical) cross section along line a-a′ in FIG. 5F .
- step 54 includes forming a second mask pattern 511 having openings 511 a (e.g., using photolithographic techniques) over the plurality of pillars (e.g., in mask layer 504 , or in an additional mask layer deposited over the device) and the insulating fill layer 509 .
- the second mask pattern of 511 comprises a plurality of lines 511 b (shown in FIG.
- step 55 includes etching the second edge portions 512 b of the upper conductive regions 507 a of each pair of the plurality of pillars 507 to leave a plurality of upper contacts 514 comprising the first edge portions 512 a of the upper conductive regions 507 a .
- Each of the plurality of upper contacts 514 is located on the respective lower semiconductor region 507 b in each of the plurality of pillars 507 .
- each of the plurality of upper contacts 514 is narrower than the respective lower semiconductor region 507 b of the pillar 507 .
- the use of two offset mask patterns 505 and 511 to form the upper contacts 514 may be advantageous in that the resulting the upper contacts 514 may be narrower in at least one horizontal direction than the minimum line with for the pattern forming process (e.g., photolithographic process) used to for the mask patterns.
- FIG. 5I shows the top view of the device and FIG. 5H is a side (i.e., vertical) cross section along line a-a′ in FIG. 5I .
- step 56 includes covering the plurality of upper contacts 514 with an electrically insulating fill layer 516 (e.g., silicon oxide), and planarizing the fill layer to expose a horizontal surface 518 that includes portions of the upper contacts 514 . Additional device layers may then be formed on the surface that use the upper contacts 514 to establish electrical connections with lower device layers.
- an electrically insulating fill layer 516 e.g., silicon oxide
- the method described above may be used to form interconnects in monolithic, three dimensional resistive random access (ReRAM) non-volatile memory device, e.g., of the type described herein.
- ReRAM resistive random access
- each of the plurality of lower semiconductor regions 507 b comprises a channel of a vertical thin film select gate transistor 110 .
- Each select gate transistor further comprises a global bit line 150 located below the channel and a gate line 131 which is located adjacent to a side of the channel 111 c .
- Source and drain regions may also be formed in the channel during the stack 503 deposition.
- Each of the plurality of upper contacts 514 comprises a lower portion of one of a plurality of local bit line interconnects 106 a of the memory device.
- the memory device may have a select gate and bit line structure similar to that of the lower portion of the device 100 shown in FIGS. 1C-1D .
- the rest of the device 100 may be constructed by forming a plurality of upper potions of the local bit line interconnects over the respective lower portions of the local bit line interconnects 106 a , as shown in FIG. 5L , and forming a memory cell region 102 over the upper portions of the plurality of local bit line interconnects 106 a , as shown in FIG. 5M .
- Region 102 may include the word lines 112 separated by insulating layers 117 as shown in FIGS. 1A-1C , as well as the word line interconnects 113 shown in FIGS. 3A-3F .
- a plurality of vertically extending openings 520 are formed through the memory cell region 102 (i.e., through the word lines 112 and layers 117 ), as shown in FIG. 5N .
- the resistivity switching material 103 layers and the plurality of local bit lines 108 a , 108 b are formed in the openings 520 such that the plurality of local bit lines extend vertically into the memory cell region 102 .
- the respective lines 108 a , 108 b are formed in contact with each of the plurality of local bit line interconnects 106 a , 106 b (which is formed on top of the memory cell region 102 ), as shown in FIG. 5O .
Abstract
Description
- The present description relates generally to the field of semiconductor devices and specifically to three dimensional memory devices and methods of making thereof.
- One example of non-volatile memory uses variable resistance memory elements that may be set to either low or high resistance states, and can remain in that state until subsequently re-set to the initial condition. The variable resistance memory elements are individually connected between two orthogonally extending conductors (typically bit and word lines) where they cross each other in a two-dimensional array. The state of such a memory element is typically changed by proper voltages being placed on the intersecting conductors. An example of an array of variable resistive elements and associated diodes is given in U.S. Patent Application Publication No. US 2009/0001344 A1, which is incorporated herein by reference in its entirety. U.S. Patent Application Publication No. 2012/0147648 A1, published Jun. 14, 2012 and incorporated by reference herein in its entirety, describes a three dimensional resistive RAM (“ReRAM”) device containing non-volatile memory element (“NVM”) material that is non-conductive when first deposited. Since the material is initially non-conductive, there is no necessity to isolate the memory elements at the cross-points of the word and bit lines from each other. Several memory elements may be implemented by a single continuous layer of material, which may be strips of NVM material oriented vertically along opposite sides of the vertical bit lines in the horizontal and extending upwards through all the planes in the vertical direction.
- One embodiment relates to a memory device, including: a first bit line interconnect; a second bit line interconnect; a first plurality of electrically conductive local bit lines extending in a substantially vertical direction into a memory cell region, wherein each local bit line in the first plurality of electrically conductive local bit lines is electrically connected to the first bit line interconnect; a second plurality of electrically conductive local bit lines extending in the substantially vertical direction into the memory cell region and horizontally offset from the first plurality of electrically conductive local bit lines, wherein each local bit line in the second plurality of electrically conductive local bit lines is electrically connected to the second bit line interconnect; a first select transistor electrically connected to the first bit line interconnect, wherein the first select transistor is configured to select the first plurality of electrically conductive local bit lines; a second select transistor electrically connected to the second bit line interconnect, wherein the second select transistor is configured to select the second plurality of electrically conductive local bit lines; a plurality of word lines extending in a substantially horizontal direction into the memory cell region; and a plurality of memory cells located in the memory cell region.
- In another embodiment, a memory device is disclosed, including: a memory cell region; a plurality of memory cells located in the memory cell region; a plurality of word lines extending in a substantially horizontal direction into the memory cell region; and a plurality of bit lines extending in a substantially vertical direction into the memory cell region. In some embodiments, the plurality of word lines include a first, second, third and forth word line comb; each word line comb includes a plurality of electrically conductive fingers; the plurality of electrically conductive fingers for each word line comb electrically contact other electrically conductive fingers of the same word line comb and are electrically insulated from the electrically conductive fingers of the other word line combs; the fingers of the first and second word line combs extend in a first substantially horizontal direction from a first interconnect region into a first side of the memory cell region; the fingers of the third and forth word line combs extend in a second substantially horizontal direction from a second interconnect region into a second side of the memory cell region opposite to the first side of the memory cell region; and the fingers of the first, second, third and forth word line comb are alternately interdigitated in the memory cell region.
- In another embodiment, a method is disclosed of making an interconnect between electrodes in a three dimensional device, the method including: providing a first stack of electrodes including a first electrode located in a first device level, a second electrode located in a second device level above the first device level, a third electrode located in a third device level above the second device level, and a fourth electrode located in a fourth device level above the third device level; providing a second stack of electrodes which is offset in a substantially horizontal direction from the first stack of electrodes, the second stack of electrodes including a first electrode located in the first device level, a second electrode located in the second device level above the first device level, a third electrode located in the third device level above the second device level, and a fourth electrode located in the fourth device level above the third device level; forming an insulating fill layer over the first and the second stacks of electrodes forming a first opening to the fourth electrode in the first stack of electrodes through the insulating fill layer; forming a second opening through the insulating fill layer and through the fourth electrode to the third electrode in the second stack of electrodes; forming a first insulating layer in the first and the second openings such that the first insulating layer is located on sidewalls of the first and the second openings and such that the fourth electrode is exposed in the first opening and the third electrode is exposed in the second opening; forming a first conductive layer in the first and the second openings such that the first conductive layer is located on the first insulating layer over the sidewalls of the first and second openings and such that the first conductive layer electrically contacts and connects the fourth electrode exposed in the first opening and the third electrode exposed in the second opening; extending the first opening through the fourth electrode to expose the third electrode in the first electrode stack without removing the first conductive layer from over the sidewalls of the first opening; extending the second opening through the third electrode to expose the second electrode in the second electrode stack without removing the first conductive layer from over the sidewalls of the second opening; forming a second insulating layer in the first and the second openings such that the second insulating layer is located on sidewalls of the first and the second openings and such that the third electrode is exposed in the first opening and the second electrode is exposed in the second opening; forming a second conductive layer in the first and the second openings such that the second conductive layer is located on the second insulating layer over the sidewalls of the first and second openings and such that the second conductive layer electrically contacts and connects the third electrode exposed in the first opening and the second electrode exposed in the second opening; extending the first opening through the third electrode to expose the second electrode in the first electrode stack without removing the second conductive layer from over the sidewalls of the first opening; extending the second opening through the second electrode to expose the first electrode in the second electrode stack without removing the second conductive layer from over the sidewalls of the second opening; forming a third insulating layer in the first and the second openings such that the third insulating layer is located on sidewalls of the first and the second openings and such that the second electrode is exposed in the first opening and the first electrode is exposed in the second opening; and forming a third conductive layer in the first and the second openings such that the third conductive layer is located on the third insulating layer over the sidewalls of the first and second openings and such that the third conductive layer electrically contacts and connects the second electrode exposed in the first opening and the first electrode exposed in the second opening.
- In another embodiment, a method of making a contact to a semiconductor device is disclosed, the method including: forming a conductive layer over a semiconductor layer; forming a first mask pattern over the conductive layer; etching portions of the conductive layer and the semiconductor layer exposed in the first mask pattern to form a plurality of pillars, wherein each pillar includes a lower semiconductor region and an upper conductive region; forming an insulating fill layer between the plurality of pillars; forming a second mask pattern over the plurality of pillars and the insulating fill layer, wherein the second mask pattern is offset with respect to the first mask pattern such that the second mask pattern covers both adjacent first edge portions of the upper conductive region in each adjacent pair of the plurality of pillars and the insulating fill layer between each adjacent pair of the plurality of pillars, while leaving opposing second edge portions of the upper conductive region in each pair of the plurality of pillars uncovered; etching the second edge portions of the upper conductive regions of each pair of the plurality of pillars to leave a plurality of upper contacts including the first edge portions of the upper conductive regions, wherein each of the plurality of upper contacts is located on the respective lower semiconductor region in each of the plurality of pillars.
- In another embodiment, a semiconductor device is disclosed, including: a first, second, third and fourth transistors, each transistor having a channel region of a second conductivity type located in a horizontal plane between source region and first drain region of a first conductivity type, wherein: the second transistor is located adjacent to the first transistor in a first horizontal direction in the horizontal plane, such that a first channel edge containing the source region of the first transistor faces a second channel edge containing the source region of the second transistor; the third transistor is located adjacent to the first transistor in a second horizontal direction in the horizontal plane, such that a third channel edge containing the first drain region of the first transistor faces a fourth channel edge containing the first drain region of the third transistor; the fourth transistor is located adjacent to the second transistor in the second horizontal direction in the horizontal plane, such that a third channel edge containing the first drain region of the second transistor faces a fourth channel edge containing the first drain region of the fourth transistor; the fourth transistor is located adjacent to adjacent to the third transistor in the first horizontal direction in the horizontal plane, such that a first channel edge containing the source region of the third transistor faces a second channel edge containing the source region of the fourth transistor; the first channel edge of each transistor is located opposite the second channel edge of each transistor; the third channel edge of each transistor is located opposite the fourth channel edge of each transistor; the second horizontal direction is substantially perpendicular to the first horizontal direction; and the source region of each transistor is offset in both the first and the second directions with respect to the first drain region of each transistor. The device may also include: a common source line which extends in the second direction between the first and the second transistors and between the third and the fourth transistors, and which is electrically connected to the source regions of each of the first, second, third and fourth transistors; a first common gate electrode which extends in the first direction over the channel regions between respective source regions and first drain regions of the first and the second transistors; and a second common gate electrode which extends in the first direction over the channel regions between respective source regions and first drain regions of the third and the fourth transistors.
-
FIG. 1A is a side cross sectional view along line A-A′ inFIG. 1B andFIG. 1B is a top view of a memory device according to an embodiment. -
FIG. 1C is perspective view,FIG. 1D is a side cross sectional view andFIG. 1E is a top view of a memory device according to another embodiment. -
FIGS. 2A and 2B are side cross sectional views along rear plane (A) and front plane (B), respectively, ofFIG. 2D , andFIGS. 2C-2F are perspective views a memory device according to another embodiment. -
FIGS. 3A, 3D, 3E and 3F are perspective views,FIG. 3B is modified circuit schematic andFIG. 3C is a top view of a memory device according to another embodiment. -
FIGS. 4A-4S are side cross sectional views andFIGS. 4T, 4U, 4W and 4X are perspective views of steps in a method of making a memory device according to the embodiment ofFIGS. 3A-3F . -
FIGS. 5A, 5C-5E, 5G-5H, 5J and 5L-5O are side cross sectional views andFIGS. 5B, 5F, 5I and 5K are top cross sectional views of steps in a method of making a memory device according to another embodiment. - Embodiments of the present description will be described below with reference to the accompanying drawings. It should be understood that the following description is intended to describe exemplary embodiments of the description, and not to limit the description
- Referring to
FIGS. 1A and 1B , amemory device 100 of one embodiment includes plural (e.g., at least two, such as four) interdigitated word lines and a single select transistor controlling plural (e.g., at least two) local bit lines. Thedevice 100 includes amemory cell region 102 containing a plurality ofmemory cells 104 located in thememory cell region 102. As shown, the memory device includes two identical memory device modules (e.g., sections) 101 a and 101 b, arranged side by side. However, it is to be understood that various embodiments may include more or fewer memory device modules 101, e.g., 1, 10, 100, 1,000 or more, e.g., in the range of one to a trillion or any sub-range thereof. In some embodiments, the memory device modules 101 may be arranged, e.g., in two dimensional planar array (e.g., a rectangular array), or in any other suitable regular, irregular, or random pattern. - The
memory device 100 also includes a firstbit line interconnect 106 a and a secondbit line interconnect 106 b inmodule 101 a.Module 101 b contains similar bit line interconnects. A first plurality of electrically conductivelocal bit lines 108 a extend in a substantially vertical direction into the memory cell region 102 (e.g., in the z-direction inFIG. 1A ). A substantially vertical direction includes the vertical direction (e.g., perpendicular to the top substrate surface) and directions within 20 degrees from the vertical direction. As shown, twolocal bit lines 108 a are provided permodule 101 a, but in other embodiments more maybe be used, e.g., 3, 4, 5, 6, 7 8, 9, 10 or more such as in the range of 2-100 or any sub-range thereof. Eachlocal bit line 108 a (e.g., bothlines 108 a) in the first plurality of electrically conductive local bit lines is electrically connected to the firstbit line interconnect 106 a. - A second plurality of electrically conductive
local bit lines 108 b extend in the substantially vertical direction into thememory cell region 102 and are horizontally offset from the first plurality of electrically conductivelocal bit lines 108 a. As shown, twolocal bit lines 108 b are provided permodule 101 b, but in other embodiments more maybe be used, e.g., 3, 4, 5, 6, 7 8, 9, 10 or more such as in the range of 2-100 or any sub-range thereof. Eachlocal bit line 108 b in the second plurality of electrically conductive local bit lines is electrically connected to the secondbit line interconnect 106 b. The first plurality of electrically conductivelocal bit lines 108 b extend substantially 180 degrees (e.g., 180 degrees or within 160-200 degrees) from the second plurality of electrically conductivelocal bit lines 108 b. For example, thelines 108 a may extend from theinterconnect 106 a upward, while thelines 108 b may extend from theinterconnect 106 b downward. - The first plurality of
local bit 108 a and first bit line interconnect 106 a may be electrically insulated from the second plurality oflocal bit lines 108 b and secondbit line interconnect 106 b. For example as shown inFIG. 1A , a first insulatinglayer 109 a (e.g., an oxide or nitride layer, such as a horizontal silicon nitride etch stop layer) prevents the firstbit line interconnect 106 a from contacting the second plurality oflocal bit lines 108 b. Similarly, a second insulatinglayer 109 b (e.g., an oxide or nitride layer such as a horizontal silicon nitride etch stop layer) prevents the secondbit line interconnect 106 b from contacting the first plurality oflocal bit lines 108 a. - A first
select transistor 110 a is electrically connected to the firstbit line interconnect 106 a, and is configured to select the first plurality of electrically conductivelocal bit lines 108 a. A secondselect transistor 110 b is electrically connected to the secondbit line interconnect 106 b, and is configured to select the second plurality of electrically conductivelocal bit lines 108 b. Thetransistors 110 may be located below thememory cell region 102. - A plurality of
word lines 112 extend in a substantially horizontal direction into the memory cell region 102 (the y-direction inFIG. 1B ). A substantially horizontal direction includes the horizontal direction (e.g., parallel to the top substrate surface) and directions within 20 degrees from the horizontal direction. As shown inFIG. 1B , fourword lines 112 are provided, but in other embodiments more or fewer maybe be used, e.g., 2, 3, 4, 5, 6, 7 8, 9, 10 or more such as in the range of 2-100 or any sub-range thereof. - In some embodiments each
word line 112 may include one or more word line combs 114. For example each of the plurality of word lines shown inFIG. 1B comprises a firstword line comb 114 a, a secondword line comb 114 b, a thirdword line comb 114 c and a forthword line comb 114 d. As shown, four word lines combs 114 are provided, but in other embodiments more or fewer maybe be used, e.g., 2, 3, 4, 5, 6, 7 8, 9, 10 or more such as in the range of 2-100 or any sub-range thereof. The location and direction of thecomb 114 a by the dashedline 114 a inFIG. 1A and its electrical connection between theword line fingers 116 is shown by the black circles in theline 114 a. The diagonal direction of the comb which extends in both vertical and horizontal directions will be explained in more detail with respect toFIGS. 3A-3F below. - Each
word line comb 114 comprises a plurality of electricallyconductive fingers 116. The plurality of electricallyconductive fingers 116 for eachword line comb 114 electrically contact other electrically conductive fingers of the sameword line comb 114 and are electrically insulated from the electrically conductive fingers of the other word line combs 114. For example, the electricallyconductive fingers 116 of theword line comb 114 a are in electrical connection with each other, but insulated from word line combs 114 b-114 d. For example, thefingers 116 of thesame comb 114 may be electrically connected to each other by aword line interconnect 113, such as a sidewall bridge described below in reference toFIGS. 3A-3F . In some embodiments this is accomplished by providing vertically offset crossings for the word line combs 114. For example, inFIG. 1B ,word line comb 114 b crosses over or underword line comb 114 a in theregion 115. Detailed techniques for implementing crossovers of this type using the sidewall bridge are described in more detail below in reference toFIGS. 3A-3F . - In some embodiments, the
fingers 116 of some of theword line 112 combs 114 (as shown, the first and second word line combs 114 a and 114 b) extend in a first substantially horizontal direction (as shown, the y-direction) from afirst interconnect region 120 a into a first side of thememory cell region 102. - In some embodiments, the
fingers 116 of the remaining word line combs 114 (as shown the third and forth word line combs 114 c, 114 d) extend in a second substantially horizontal direction (the opposite of the y-direction as shown inFIG. 1B ) from asecond interconnect region 120 b into a second side of thememory cell region 102 opposite to the first side of the memory cell region. The first substantially horizontal direction extends an angle of about 180 degrees (e.g., 160-200 degrees) with respect to the second horizontal direction. In some embodiments, thefingers 116 of the word line combs (as shown, the first, second, third and forth word line combs 114 a-114 d) are alternately interdigitated in thememory cell region 102. - The word lines are separated from each other in the vertical direction (z-direction) by insulating
layers 117. Thus, eachfinger 116 is separated from an overlying and/or underlying finger by a respective insulatinglayer 117. - In some embodiments a row through the
memory cell region 102 along a horizontal direction substantially perpendicular to the first and the second substantially horizontal directions (the x-direction, indicated with a dashed line A-A′ inFIG. 1B ) comprises at least four fingers of the word line combs, at least four local bit lines, and at least eight memory cells arranged in a following order: a first finger 116-1 of the firstword line comb 114 a, afirst memory cell 104 a, a firstlocal bit line 108 a 1 of the first plurality of electrically conductivelocal bit lines 108 a, asecond memory cell 104 b, a first finger 116-3 of the thirdword line comb 114 c, athird memory cell 104 c, a firstlocal bit line 108b 1 of the second plurality of electrically conductivelocal bit lines 108 b, afourth memory cell 104 d, a first finger 116-2 of the secondword line comb 114 b, afifth memory cell 104 e, a secondlocal bit line 108 a 2 of the first plurality of electrically conductivelocal bit lines 108 a, asixth memory cell 104 f, a first finger 116-4 of the fourthword line comb 114 d, aseventh memory cell 104 g, a secondlocal bit line 108b 2 of the second plurality of electrically conductivelocal bit lines 108 b, and aneighth memory cell 104 h. The pattern then repeats itself in the x-direction one or more times. - Each
memory cell 104 is in contact with onefinger 116 of oneword line comb 114 and with one local bit line 108, and so may be individually addressed. In various embodiments, thememory cells 104 may be any type of memory cells know in the art including, e.g., transistor based memory sells (e.g., NAND cells) or variable resistivity state memory cells. For example, in some embodiments, thememory device 100 comprises a monolithic, three dimensional resistive random access (ReRAM) non-volatile memory device, where the plurality ofmemory cells 104 comprise a plurality of variable resistance elements that include aresistivity switching material 103 located at an intersection of and in contact with onefinger 116 of oneword line comb 114 and one local bit line 108. Thematerial 103 may be a material layer which extends along the sidewalls of the local bit lines 108. Thematerial 103 may comprise any suitable variable resistivity material that can have different electrical resistivity depending on the state, the phase, or the density of microscopic structures such as filaments, within the material. In one embodiment, thevariable resistivity material 103 is a read/write non-volatile memory (NVM) material selected from a chalcogenide and a metal oxide material, and exhibits a stable, reversible shift in resistance in response to an external voltage applied to the material or to a current passed through the material. For example, thematerial 103 may comprise a metal oxide, such as TiOx, HfOx, ZrOx, WOx, NiOx, CoOx, CoAlOx, MnOx, ZnMn2O4, ZnOx, TaOx, NbOx, HfSiOx, or HfAlOx, where “x” indicates either a stoichiometric metal oxide (e.g., HfO2) or a non-stoichiometric metal oxide (e.g., HfO2-y). Alternatively, thematerial 103 may be a chalcogenide material, such as a chalcogenide glass, for example GexSbyTez, where preferably x=2, y=2 and z=5, GeSb, AgInSbTe, GeTe, GaSb, BaSbTe, InSbTe and various other combinations of these basic elements. - In some embodiments, the bit line interconnects 106 may be on opposing sides of the
memory cell region 102. For example, as shown inFIG. 1A , the firstbit line interconnect 106 a is located belowmemory cell region 102 and the secondbit line interconnect 106 b is located above the memory cell region. The first plurality of electrically conductivelocal bit lines 108 a extend into thememory cell region 102 from below and the second plurality of electrically conductivelocal bit lines 108 b extend into the memory cell region from above. - In some embodiments, the first
bit line interconnect 106 a electrically connected to the first plurality of electrically conductivelocal bit lines 108 a comprises a firstbit line comb 122 a. The secondbit line interconnect 106 b electrically connected to the second plurality of electrically conductivelocal bit lines 108 b comprises a secondbit line comb 122 b. - The first and second bit line combs 122 a and 122 b may be arranged such that a
local bit line 108 a in the firstbit line comb 122 a is interdigitated between two electrically conductivelocal bit lines 108 b in the secondbit line comb 122 b, and alocal bit line 108 b in the secondbit line comb 122 b is interdigitated between two electrically conductivelocal bit lines 108 a in the firstbit line comb 122 a. - The
memory device 100 may include a plurality ofglobal bit lines 150, e.g., a firstglobal bit line 150 a and a secondglobal bit line 150 b. Thedevice 100 may also include additionalglobal bit lines - In some embodiments, the first
select transistor 110 a comprises a first vertical thin film transistor having an upper source or drainregion 111 u of a first conductivity type located above achannel region 111 c of a second conductivity type, a lower drain orsource region 111 d of the first conductivity type located below the channel region (e.g., in electrical contact with aglobal bit line 150 a), and afirst gate electrode 130 a located adjacent to thechannel region 111 c. - In some embodiments, the second
select transistor 110 b comprises a second vertical thin film transistor having an upper a source or drainregion 111 u of the first conductivity type located above achannel region 111 c of the second conductivity type, a lower drain orsource region 111 d of the first conductivity type located below the channel region (e.g., in electrical contact with aglobal bit line 150 b), and asecond gate electrode 130 b located adjacent to the channel region. - In some embodiments, the upper source or drain
region 111 u of the firstselect transistor 110 a is electrically connected to the firstbit line interconnect 106 a. The lower drain orsource region 111 d of the firstselect transistor 110 a is electrically connected to the firstglobal bit line 150 a which is located below the firstselect transistor 110 a. - In some embodiments, the upper source or drain
region 111 u of the secondselect transistor 110 b is electrically connected to the secondbit line interconnect 106 b, as shown inFIG. 1A . The lower drain orsource region 111 d of the secondselect transistor 110 b is electrically connected to the secondglobal bit line 150 b which is located below the secondselect transistor 110 b. - In some embodiments, the first and the second
global bit lines fingers 116 of the word line combs 114 (e.g., the y-direction). - In some embodiments, the first and the
second gate electrodes select gate line 131 a located adjacent to the respective firstselect transistor 110 a and secondselect transistor 110 b. In some embodiments, the firstselect gate line 131 comprises an elongated electrically conductive line extending in a substantially horizontal direction (the x-direction inFIG. 1A ) substantially perpendicular to the first and the secondglobal bit lines fingers 116 of the word lines combs 114. - Referring to
FIGS. 1C and 1D , in some embodiments, e.g., where the memory device features four ormore memory modules 102 arranged in a two dimensional array, such as in a rectangular planar array, additionalselect transistors 110,select gate lines 131, andglobal bit lines 150 may be provided. - For example, in the embodiment shown in
FIGS. 1C and 1D , each TFTselect transistor 110 is a shared gate transistor with relatively wide channel regions extending over two adjacentglobal bit lines 150 but electrically contacting only one of the two global bit lines 150. Eachselect transistor 110 may have two gate electrodes 130 located on opposite side of the channel of the transistor. A gate insulating layer may be located between the channel and the gate electrode. The array shown inFIGS. 1C and 1D includes a thirdselect transistor 110 c which comprises a third vertical thin film transistor, a fourthselect transistor 110 d which comprises a fourth vertical thin film transistor, a thirdglobal bit line 150 c located between the first and the secondglobal bit lines global bit line 150 d located adjacent to the secondglobal bit line 150 b. Some embodiments further include a secondselect gate line 131 b and a thirdselect gate line 131 c. - Some embodiments are arranged such that the first, the second, the third and the fourth
global bit lines 150 a-150 d extend substantially parallel to each other in a substantially horizontal direction (as shown the y-direction) below thememory cell region 102. Optional respective electrodes 151 a-151 d electrically connect the source or drainregion 111 d of eachtransistor 110 to a respectiveglobal bit line 150 a-150 d. Alternatively, the electrodes 151 may be omitted and the source or drainregion 111 d of eachtransistor 110 may be located directly on the respectiveglobal bit line 150 a-150 d, as shown inFIG. 1A . - In some embodiments, the first, the second and the third
select gate lines global bit lines 150 a-150 d. - In some embodiments, the first
select transistor 110 a is located above the first and the thirdglobal bit lines select gate lines select transistor 110 b is located above the second and the fourthglobal bit lines select gate lines select transistor 110 c is located above the first and the thirdglobal bit lines select gate lines global bit lines select gate lines - As will be understood by one skilled in the art in view of the present disclosure, the above described embodiment allows each
select transistor 110 to be used to select a respective bit line interconnect 106 and associated plurality of local bit lines 108. For example, the firstselect transistor 110 a may be selected by switching on the first andsecond gate lines global bit line 150 a. The secondselect transistor 110 b may be selected by switching on the first andsecond gate lines global bit line 150 b. The thirdselect transistor 110 c may be selected by switching on the second andthird gate lines global bit line 150 c. The fourthselect transistor 110 d may be selected by switching on the second andthird gate lines global bit line 150 d. - Moreover, some such embodiments may provide advantageous scaling. For example, referring to the embodiment shown in
FIG. 1E , the width of the firstselect transistor 110 a is about 3 F in a direction (as shown the x-direction) substantially parallel to the first and second select gate lines, where F is a minimum feature size in a semiconductor process used to fabricate thememory device 100. In other words, the width of thechannel 111 c of thetransistor 110 a may be about 3 F. The period between a corresponding point in the first and thesecond transistors select gate lines third transistors select gate lines transistors 110 is about 8 F2. The area of a memory device module 101 (not shown) located over the select transistor module is about 4 F2. Theword line finger 116 spacing in thememory cell 102 region is about 1 F. In other words, the shared gate line configuration allows for two memory device modules 101 per select transistor module, reducing the memory device module area by a factor of two relative to the select transistor module area. In some embodiments, this scaling is advantageous because relatively wide channel thin film transistors may be used, mitigating or reducing potential imperfections or malfunctions (e.g., current leakage) related to using relatively thin channels (e.g., with a width of less than 3 F) for theselect transistors 110. -
FIGS. 2A-D show views of an alternate embodiment of thememory device 200 which is different from thedevice 100 ofFIGS. 1A, 1C and 1E .FIGS. 2A and 2B are vertical (i.e., side) cross sectional views along rear plane (A) and front plane (B), respectively, in the perspective view ofFIG. 2D .FIG. 2D is a close up perspective view of a rear portion ofFIG. 2C bounded by the planes (A) and (B) inFIG. 2C . For clarity, the word lines and resistivity switching material components of thedevice 200 are omitted in the perspective view ofFIGS. 2C and 2D . - The
device 200 ofFIGS. 2A-2D differs from thedevice 100 shown inFIGS. 1A, 1C and 1E in several ways. First, the select transistors of the memory device may be planar transistors, e.g., formed at least partially in the upper portion of asubstrate 220, rather than vertical TFTs formed over the global bit lines. Furthermore, at least some of the electrodes connecting the select transistors and the bit line interconnects may extend in both vertical and horizontal directions. - In the embodiments shown in
FIGS. 2A-2D , the firstselect transistor 210 a is planar transistor having achannel region 201 a made of a semiconductor material of a second conductivity type located in a horizontal plane betweensource region 203 a anddrain region 205 a made of a semiconductor region of a first conductivity type. The source region may be located out of the plane ofFIG. 2A and the drain regions may be located out of the plane ofFIG. 2B . However, each is shown in bothFIGS. 2A and 2 b to illustrate the relationship between the source and the drain. Agate electrode 207 a for the firstselect transistor 210 a is located adjacent to thechannel region 201 a, and is separated from the channel by a gate insulating layer (not shown for clarity). Optionally, thetransistor 210 a is a dual gate transistor containing twogates 207 a, 207 aa, twodrain regions 205 a, 205 aa, and twochannels 201 a, 201 aa on either side of thecommon source region 203 a. The secondselect transistor 210 b is planar transistor having achannel region 201 b made of a semiconductor material of the second conductivity type located in a horizontal plane betweensource region 203 b and drainregion 205 b made of a semiconductor region of the first conductivity type. Agate electrode 207 b for the secondselect transistor 210 b is located adjacent to thechannel region 201 b. Optionally, thetransistor 210 b is also dual gate transistor containing twogates 207 b, 207 bb, twodrain regions 205 b, 205 bb, and twochannels 201 b, 201 bb on either side of thecommon source region 203 b. - For example, in some embodiments, the channel, source, and drain regions may be formed in an upper portion of the substrate 220 (e.g., proximal the major surface of the substrate), such as a silicon substrate. The source and drain regions may be formed using any suitable doping techniques, such as ion implantation. For example, if the transistors are NMOS transistors, then the
substrate 220 may comprise a p-type doped silicon wafer such that the channel comprises a p-type silicon channel, while the source and drain regions comprise n-type doped regions, such as phosphorus or arsenic implanted regions. The adjacent transistors may be isolated from each other by any suitable isolation regions, such as shallow trench isolation (STI)regions 222. - As shown in
FIGS. 2B and 2C , thesource region 203 a of the firstselect transistor 210 a is electrically connected to thesource line 209 which extends in level M1 (i.e., the first/lower metal level). The first (e.g., left side)drain region 205 a of the firstselect transistor 210 a is electrically connected to an upper bit line interconnect 106 bb located in level M4 (i.e., the fourth/top metal level) in the front vertical plane (B) by theelectrode 151 a which has a horizontal portion extending in level M2 (i.e., the second/middle metal level) from the rear vertical plane (A) to the front vertical plane (B). The second (e.g., right side) drain region 205 aa of the firstselect transistor 210 a is electrically connected to a lower bit line interconnect 106 aa located in level M3 (i.e., the third/upper metal level) in the front vertical plane (B) by the electrode 151 aa which has a horizontal portion extending in level M2 (i.e., the second/middle metal level) from the rear vertical plane (A) to the front vertical plane (B). The first (e.g., left side)gate electrode 207 a of the first select transistor is connected to or comprises a portion of theglobal bit line 150 a which is located below level M1. The second (e.g., right side) gate electrode 207 aa of the first select transistor is connected to or comprises a portion of theglobal bit line 150 aa which is located below level M1. - As shown in
FIGS. 2A and 2C , thesource region 203 b of the secondselect transistor 210 b is electrically connected to thesource line 209 which extends in level M1 (i.e., the first/lower metal level). The first (e.g., left side)drain region 205 b of the secondselect transistor 210 b is electrically connected to another lowerbit line interconnect 106 a located in level M3 (i.e., the third/upper metal level) in the rear vertical plane (A) by theelectrode 151 b which extends vertically through level M2 (i.e., the second/middle metal level). The second (e.g., right side) drain region 205 bb of the secondselect transistor 210 b is electrically connected to another upperbit line interconnect 106 b located in level M4 (i.e., the fourth/top metal level) the rear vertical plane (A) by the electrode 151 bb which extends vertically through level M2 (i.e., the second/middle metal level). The first (e.g., left side)gate electrode 207 b is connected to or comprises a portion of aglobal bit line 150 b which is located below level M1. The second (e.g., right side) gate electrode 207 bb is connected to or comprises a portion of aglobal bit line 150 bb which is located below level M1. - Thus, the
electrodes 151 b, 151 bb extend vertically in the rear vertical plane (A). In contrast, theelectrodes 151 a, 151 aa start out vertically in the rear vertical plane (A), then extend horizontally in level M2 from plane (A) to the front vertical plane (B) and then again extend vertically in plane (B). - In some embodiments, the
gate electrode 207 a of the first select transistor comprises a portion of theglobal bit line 150 a. Theglobal bit line 150 a extends in a first horizontal direction (e.g., y-direction) over the first planarselect transistor 210 a and an imaginarystraight line 224 signifying the charge carrier (e.g., electron) flow direction in the channel between thesource 203 a and thedrain 205 a of the first planarselect transistor 210 a extends in a second horizontal direction at an angle with respect to the first horizontal direction, e.g., an angle in the range of 20 to 70 degrees, as shown inFIG. 2C . A similar imaginary line signifies the charge carrier flow direction between thesource 203 a and drain 205 aa. - Similarly, the
gate electrode 207 b of the secondselect transistor 210 b comprises a portion of theglobal bit line 150 b. The third global bit line extends in the first horizontal direction over the planar secondselect transistor 210 b and an imaginary straight line between thesource 203 b and thedrain 205 b of the second planarselect transistor 210 b extends in a second horizontal direction at an angle with respect to the first horizontal direction, e.g., an angle in the range of 20 to 70 degrees, similar toline 224 fortransistor 210 a. - The
source line 209 extends in a third horizontal direction (e.g., x-direction) which is substantially perpendicular to the first horizontal direction. Thesource line 209 may contain horizontally and/or vertically extendingelectrodes 219 which contact thesource regions -
FIG. 2E illustrates the details of the fourtransistors FIG. 2C without illustrating the electrodes, interconnects and bit lines for clarity. A discussed above, each transistor 210 a-210 d has a first channel region 201 aa, 201 b, 201 cc and 201 d of a second conductivity type (e.g., p-type) located in a horizontal plane betweenrespective source region -
Transistor 210 c is located adjacent totransistor 210 a in a first horizontal direction (e.g., the y-direction) in the horizontal plane. Afirst channel edge 261 a containing thesource region 203 a of thetransistor 210 a faces asecond channel edge 262 c containing thesource region 203 c oftransistor 210 c.Transistor 210 b is located adjacent totransistor 210 a in a second horizontal direction (e.g., the x-direction) in the horizontal plane. Athird channel edge 263 a containing the first drain region 205 aa oftransistor 210 a faces afourth channel edge 264 b containing thefirst drain region 205 b oftransistor 210 b. The second horizontal direction (e.g., the direction) is substantially perpendicular to the first horizontal direction (e.g., the direction). -
Transistor 210 d is located adjacent totransistor 210 c in the second horizontal direction (e.g., the x-direction) in the horizontal plane. Athird channel edge 263 c containing the first drain region 205 cc oftransistor 210 c faces afourth channel edge 264 d containing thefirst drain region 205 d oftransistor 210 d.Transistor 210 d is also located adjacent to adjacent totransistor 210 b in the first horizontal direction (e.g., the y-direction) in the horizontal plane. Afirst channel edge 261 b containing thesource region 203b transistor 210 b faces asecond channel edge 262 d containing thesource region 203 d oftransistor 210 d. - In general, the first channel edge 261 of each transistor is located opposite the second channel edge 262 the same transistor, while the third channel edge 263 of each transistor is located opposite the fourth channel edge 264 of the same transistor. As shown in
FIG. 2E , in the source region of each transistor 203 is offset in both the first and the second directions (i.e., in both the y and the x directions) with respect to the first drain region 205 of the same transistor (e.g., alongline 224 shown inFIG. 2C ). - As described above, the
common source line 209 extends in the second direction (e.g., the x-direction) betweentransistors transistors source line 209 is electrically connected to the source regions 203 a-203 d of the respective transistors 210 a-210 d, as shown inFIG. 2C . - A first
common gate electrode 150 aa extends in the first direction (e.g., the y-direction) over the channel regions 201 aa, 201 cc betweenrespective source regions transistors common gate electrode 150 b extends in the first direction over thechannel regions respective source regions first drain regions transistors - As described above, the transistors 210 a-210 d may be dual channel/dual gate transistors. In this embodiment shown in
FIG. 1E , asecond drain region 205 a is located in afourth channel edge 264 a oftransistor 210 a, asecond drain region 205 c is located in afourth channel edge 264 c oftransistor 201 c, a second drain region 205 bb is located in athird channel edge 263 b oftransistor 210 b, and a second drain region 205 dd is located in athird channel edge 263 d oftransistor 210 d. A thirdcommon gate electrode 150 a extends in the first direction (e.g., the y-direction) over thechannel regions respective source regions second drain regions transistors common gate electrode 150 bb extends in the first direction over the channel regions 201 bb, 201 dd betweenrespective source regions transistors common gate 150 aa electrode is connected to or comprises a portion of the first global bit line, the secondcommon gate electrode 150 b is connected to or comprises a portion of the second global bit line, the thirdcommon gate electrode 150 a is connected to or comprises a portion of the third global bit line, and the fourthcommon gate electrode 150 bb is connected to or comprises a portion of the fourth global bit line. -
FIG. 2F is a close up perspective view of a front portion ofFIGS. 2C and 2E bounded by the planes (C) and (D) inFIGS. 2C and 2E . As shown inFIGS. 2C and 2F , the first drain region 205 aa, 205 b, 205 cc, 205 d of the respectiveselect transistors second drain region 205 a, 205 bb, 205 c, 205 dd of the respectiveselect transistors respective electrodes 151 c 3 and 151 d 3. The third 106 b 3 and fourth 106 b 4 upper bit line interconnects are connected to the respective drain regions byrespective electrodes 151 c 4 and 151 d 4, as shown inFIG. 2F . - The first 106 aa, second 106 a, third 106 a 3 and fourth 106 a 4 lower bit line interconnects are located below
memory cell region 102, while the first 106 bb, second 106 b, third 106 b 3 and fourth 106 b 4 upper bit line interconnects are located above thememory cell region 102, as shown inFIGS. 2A-2B . - A first plurality of electrically conductive
local bit lines 108 a are located in the vertical plane (C). These bit lines extend into thememory cell region 102 from below and are electrically connected to the lowerbit line interconnect 106 a 3, as shown inFIG. 2F . A second plurality of electrically conductivelocal bit lines 108 a are located in the vertical plane (D). These bit lines extend into thememory cell region 102 from below and are electrically connected to the lowerbit line interconnect 106 a 4, as shown inFIG. 2F . - A third plurality of electrically conductive
local bit lines 108 a are located in the vertical plane (B). These bit lines extend into thememory cell region 102 from below and are electrically connected to the lower bit line interconnect 106 aa, as shown inFIGS. 2C and 2D . A fourth plurality of electrically conductivelocal bit lines 108 a are located in the vertical plane (A). These bit lines extend into thememory cell region 102 from below and are electrically connected to the lowerbit line interconnect 106 a, as shown inFIG. 2C . - A fifth plurality of electrically conductive
local bit lines 108 b are interdigitated with the second plurality of electrically conductivelocal bit lines 108 a in the vertical plane (D). These bitlines 108 b extend into thememory cell region 102 from above and are electrically connected to the upperbit line interconnect 106 b 3, as shown inFIG. 2F . A sixth plurality of electrically conductivelocal bit lines 108 b are interdigitated with the first plurality of electrically conductivelocal bit lines 108 a in the vertical plane (C). These bitlines 108 b extend into thememory cell region 102 from above and are electrically connected to the second upperbit line interconnect 106 b 4, as shown inFIG. 2F . - A seventh plurality of electrically conductive
local bit lines 108 b are interdigitated with the third plurality of electrically conductivelocal bit lines 108 a in the vertical plane (B). These bitlines 108 b extend into thememory cell region 102 from above and are electrically connected to the upper bit line interconnect 106 bb. An eighth plurality of electrically conductivelocal bit lines 108 b are interdigitated with the fourth plurality of electrically conductivelocal bit lines 108 a in the vertical plane (A). These bitlines 108 b extend into thememory cell region 102 from above and are electrically connected to the upperbit line interconnect 106 b, as shown inFIGS. 2C-2D . -
FIGS. 3A-3F illustrate aword line 112 contact scheme for a memory device of the types described herein, such as the devices ofFIGS. 1A-1E orFIGS. 2A-2F . Specifically,FIGS. 3A-3F illustrate how thefingers 116 of thesame comb 114 may be electrically connected to each other by aword line interconnect 113, such as a sidewall bridge word line interconnect inregion 115 which is shown inFIG. 1B .FIG. 3A is a schematic perspective view of the word line combs and word line interconnects, whileFIGS. 3B and 3C are respective electrical schematic view and top view of the word line combs and word line interconnects shown inFIG. 3A .FIGS. 3D, 3E and 3F are close up perspective views of a portion the word line combs and word line interconnects ofFIGS. 3A and 3C . - As shown in
FIGS. 3A, 3B and 3F , each of the first 114-1, second 114-2, third 114-3 and fourth 114-4 word line combs may be positioned diagonally with respect to the horizontal direction (e.g., the x-direction), such that one side of the comb (e.g., the left or the right side) is located below the opposite side (e.g., the other one of the left or the right side inFIGS. 3B and 3F ) of the same comb. Thus, each comb extends in both the vertical direction (e.g., z-direction) and a first horizontal direction (e.g., the x-direction). Thefingers 116 extend away from theinterconnect 113 in the second horizontal direction (e.g., the y-direction) which is perpendicular to the first horizontal direction. -
FIG. 3F shows one part of aword line comb 114 containing four contact pads and four associated fingers. Theword line comb 114 may corresponds to one of word line combs 114 a to 114 d inFIG. 1B or it may correspond to one of the word line combs 114-1 to 114-4 inFIGS. 3A-3C . In general, the word line combs 114 a to 114 d inFIG. 1B may be the same as the respective word line combs 114-1 to 114-4 inFIGS. 3A-3C . Alternatively, the word line combs 114 a to 114 d inFIG. 1B each may extend in the same horizontal x-y plane and thus be different from the diagonal word line combs 114-1 to 114-4 inFIGS. 3A-3C which do not extend in the same horizontal plane and instead c as shown inFIGS. 3A, 3B and 3F . - A four finger portion of one exemplary
word line comb 114 of an embodiment of the present disclosure, which may correspond to one of the combs 114-1 to 114-4 or to one of thecombs 114 a to 114 d is shown inFIG. 3F . Thecomb 114 includes afirst finger 116 a located in a first device level (i.e., in level “a” or L1), asecond finger 116 b located in a second device level (i.e., in level “b” or L2) above the first device level, athird finger 116 c located in a third device level (i.e., in level “c” or L3) above the second device level, and afourth finger 116 d located in a fourth device level (i.e., in level “d” or L4) above the third device level. The first, second, third and fourth fingers are offset from each other in a horizontal direction (e.g., the x-direction). A word line interconnect 113 (e.g., the sidewall bridge interconnect shown inFIGS. 3D and 3E ) electrically connects the first, second, third and fourth fingers at theirrespective contact pads - This diagonal word line comb configuration shown in
FIGS. 3A, 3B and 3F allows eachcomb 114 to be connected to a driver circuit (e.g., via global word line 350) by asingle electrode 351 connected to thelowest contact pad 316 a. In other words, each word line comb is connected to a global word line 350 located below thememory cell region 102 by arespective electrode 351. This means that outside electrical connection to the upper levels of the word lines is not required and all outside electrical connections to diagonally stacked word line combs can be formed on the bottom side of thecombs 114 and below the second level (e.g., level “b”/L2) of thememory cell region 102. - For example, as shown in
FIGS. 3A and 3B , the first word line comb 114-1 includes a first finger 116-la located in the first device level, a second finger 116-1 b located in the second device level above the first device level, a third finger 116-1 c located in the third device level above the second device level, and a fourth finger 116-1 d located in the fourth device level above the third device level. The first, second, third and fourth fingers are offset from each other in a horizontal direction (e.g., the x-direction). The word line interconnect 113-1 electrically connects the first, second, third and fourth fingers. - As shown in
FIG. 3C , the word line interconnects 113-1, 113-2, 113-3 and 113-4 are located outside thememory cell region 102 in one of theinterconnect regions memory cell region 102 in a perpendicular horizontal direction (e.g., the y-direction). For example, the word line interconnect 113-1 of word line comb 114-1 shown inFIGS. 3A and 3B is located ininterconnect region 120 a inarea 3A shown by the dashed lines inFIG. 3C . Interconnect 113-2 is also located inregion 120 a. Interconnects 113-3 and 113-4 are located ininterconnect region 120 b located on the opposite side of thememory cell region 102 fromregion 120 a. - As shown in
FIGS. 3A-3F , eachword line finger 116 may include a contact pad 316 which is located in electrical contact with therespective finger 116. Preferably, the contact pad 316 is located in the same vertical device level as itsrespective finger 116. For example, as shown inFIG. 3C , each respective finger 116-1, 116-2, 116-3 and 116-4 contacts a respective contact pad 316-1, 316-2, 316-3 and 316-4 located in one of theinterconnect regions FIGS. 3A and 3B . - As shown in
FIG. 3F , theword line interconnect 113 contacts the contact pads 316 to form the word line combs 114. Thus, eachword line comb 114 includesfingers 116, pads 316 and interconnect 113 which electrically connects thefingers 116 together into a single word line electrode by physically connecting the pads 316 of eachfinger 116 in thecomb 114. - As further shown in
FIGS. 3A and 3B , the first (lowest) device level contact pads 316-1 a, 316-2 a, 316-3 a and 316-4 a may have a bottom surface in contact with an optional respective word line electrode 350-1, 350-2, 350-3 and 350-4. Each word line electrode 350-1, 350-2, 350-3 and 350-4 is electrically connected to a respective global word line 351-1, 351-2, 351-3 and 351-4. The global word lines may extend in a horizontal direction (e.g., y-direction) below thememory cell region 102, and either above, below or co-planar with the global bit lines 150. - The details of sidewall bridge
word line interconnect 113 inregion 115 are illustrated inFIGS. 3D and 3E .FIGS. 3D and 3E are mirror image type views from the views ofFIGS. 3A and 3B . Specifically,region 3D inFIG. 3A is a mirror image type close up of the interconnect shown inFIG. 3D . - The word line interconnect 113 (e.g., interconnect 113-1 shown in
region 3D inFIG. 3A ) includes a first conductive vertical rail 12 a which extends in the first or the second horizontal direction (e.g., the horizontal y-direction or 180 degrees from the y-direction) and contacts a contact pad 316-1 aa of the first finger 116-1 aa in the first device level (e.g., in the lowest level “a” which corresponds to word line level “L1”). Theword line interconnect 113 also includes a second conductive vertical rail 12 b which extends in the same first or the second horizontal direction as the first rail (e.g., in the y-direction or 180 degrees from the y-direction) and contacts a contact pad 316-1 b of the second finger 116-1 b in the second device level. A firstconductive sidewall bridge 12 c extends in a third horizontal direction (e.g., in the x-direction) substantially perpendicular to the first and the second horizontal directions. Theconductive sidewall bridge 12 c contacts both the first 12 a and the second 12 b conductive vertical rails. - The conductive sidewall bridge, the conductive vertical rails, the contact pads and the fingers may comprise any one or more c The interconnect pattern of two rails contacting the contact pads in adjacent device levels and a sidewall bridge connecting the two rails is then repeated for the remaining contact pads in the remaining device levels.
- Thus, a third conductive vertical rail 23 a extends in the first or the second horizontal direction and contacts another contact pad 316-1 bb of another second finger 116-1 bb in the second device level (e.g., device level “b” which corresponds to word line level “L2”). The third conductive vertical rail 23 a contains two portions which are located on opposite sides of the first rail 12 a. The first rail 12 a extends to pad 316-1 aa through an opening the pads 316-1 bb and 316-1 cc, while the third rail 23 a portions extend only partially through the opening in pad 316-1 cc.
- A fourth conductive vertical rail 23 b extends in the first or the second horizontal direction and contacts a contact pad 316-1 c of the third finger 116-1 c in the third device level. The fourth conductive vertical rail 23 b contains two portions which are located on opposite sides of the second rail 12 b. The second rail 12 b extends to pad 316-1 b through an opening the pads 316-1 c and 316-1 d, while the fourth rail 23 b portions extend only partially through the opening in pad 316-1 d.
- A second
conductive sidewall bridge 23 c extends in a third horizontal direction substantially perpendicular to the first and the second horizontal directions. Thesecond bridge 23 c contains two portions which are located on opposite sides of thefirst bridge 12 c. Thesecond bridge 23 c contacts both the third 23 a and the fourth 23 b conductive vertical rails. - Furthermore, a fifth conductive
vertical rail 34 a extends in the first or the second horizontal direction and contacts a contact pad 316-1 cc of the third finger 116-1 cc in the third device level (e.g., device level “c” which corresponds to word line level “L3”). A sixth conductivevertical rail 34 b extends in the first or the second horizontal direction and contacts a contact pad 316-1 d of the fourth finger 316-1 d in the fourth device level (e.g., device level “d” which corresponds to word line level “L4”). A thirdconductive sidewall bridge 34 c extends in a third horizontal direction substantially perpendicular to the first and the second horizontal directions, and contacts both the fifth 34 a and the sixth 34 b conductive vertical rails. - The contact pads 316-1 aa, 316-1 bb and 316-1 cc are stacked above each other in
stack 322. The contact pads 316-1 a, 316-1 b, 316-1 c and 316-1 d are stacked above each other instack 324 which is horizontally separated fromstack 322 in the third horizontal direction (e.g., the x-direction). The fingers 116-2 a, 116-2 b, 116-2 c and 116-2 d of another word line comb 114-2 extend in the first or the second horizontal direction between thestacks - The conductive sidewall bridges 12 c, 23 c and 34 c of the word line interconnect 113-1 of word line comb 114-1 extend over the fingers 116-2 a, 116-2 b, 116-2 c and 116-2 d of the word line comb 114-2. The fingers 116-2 a, 116-2 b, 116-2 c and 116-2 d of word line comb 114-2 may be covered by an insulating
layer 330, such as a silicon nitride hard mask layer, which electrically isolates the upper finger 116-2 d from the conductive sidewall bridges 12 c, 23 c and 34 c of the word line interconnect 113-1 of word line comb 114-1. The fingers 116-2 a, 116-2 b, 116-2 c and 116-2 d of word line comb 114-2 extend to a different word line interconnect 113-2 which is offset from the interconnect 113-1 in the first or the second horizontal directions in theinterconnect region 120 a, as shown inFIG. 3A . - The above pattern is repeated in the third horizontal direction (i.e., the x-direction), as shown in
FIG. 3E . The contact pads 316-1 aa, 316-1 bb, 316-1 cc and 316-dd instack 322 extend in the first or the second horizontal directions (e.g., the y-direction or 180 degrees from the y-direction) past the sidewall bridges 12 c, 23 c and 34 c. - As shown in
FIG. 3E , a set verticalconductive rails 12 bb, 23 bb and 34 bb contacts rear (or front depending on the viewpoint) of the respective contact pads 316-1 bb, 316-1 cc and 316-1 dd instack 322. Another set ofconductive rails 12 aa, 23 aa and 34 aa contacts rear (or front depending on the viewpoint) of the respective contact pads 316-1 a 3, 316-1 b 3 and 316-1 c 3 instack 326. Another set of sidewall bridges 12 cc, 23 cc and 34 cc connects the respective set ofrails 12 aa-12 bb, 23 aa-23 bb and 34 aa-34 bb to each other. - Fingers 116-2 aa, 116-2 bb, 116-2 cc and 116-2 dd of another word line comb 114-2 extend in the first or the second horizontal direction between the
stacks FIGS. 3A-3C . - It should be noted that the word lines are separated from each other in the vertical direction (z-direction) by insulating
layers 117 shown inFIGS. 1A and 2A , such as silicon oxide or silicon nitride layers. Thus, each pair offinger 116 and pad 316 in a stack are separated from an overlying and/or underlying finger and pad pair by a respective insulating layer. The insulatinglayers 117 are not shown inFIGS. 3A-3F for clarity. - While the interconnect is described above as the
word line interconnect 113 which includes the rails and the sidewall bridges for a three dimensional ReRAM device, it should be understood that the interconnect may be used for any other suitable device, such another memory device (e.g., a NAND memory device) or a non-memory device, such as a logic device. Furthermore, the interconnect does not have to connect word line portions, such as combs, and may be used to connect bit line portions or any other conductors. -
FIGS. 4A-4X illustrate a method of making an interconnect between electrodes in a three dimensional device. - While the method of making the interconnect will be described below as the method of making the
word line interconnect 113 which includes the rails and the sidewall bridges for a three dimensional ReRAM device ofFIGS. 3A-3F , it should be understood that the method may be used to make an interconnect for any other suitable device, such another memory device (e.g., a NAND memory device) or a non-memory device, such as a logic device. Furthermore, the interconnect does not have to connect word line portions and may be used to connect bit line portions or any other conductors. - As shown in
FIG. 4A , the method includes providing thefirst stack 324 of electrodes 316 comprising a first electrode (e.g., contact pad) 316-la located in the first device level, a second electrode (e.g., contact pad) 316-1 b located in the second device level above the first device level, a third electrode (e.g., contact pad) 316-1 c located in the third device level above the second device level, and a fourth electrode (e.g., contact pad) 316-1 d located in a fourth device level above the third device level. - The method also includes providing the
second stack 322 of electrodes 316 which is offset in a substantially horizontal direction (e.g., in the x-direction) from thefirst stack 324 of electrodes. Thesecond stack 322 of electrodes comprises a first electrode (e.g., contact pad) 316-1 aa located in the first device level, a second electrode (e.g., contact pad) 316-1 bb located in the second device level above the first device level, a third electrode (e.g., contact pad) 316-1 cc located in the third device level above the second device level, and a fourth electrode (e.g., contact pad) 316-1 dd located in the fourth device level above the third device level. The method also includes forming an insulatingfill layer 402 over the first 324 and the second 322 stacks of electrodes. - Then, as shown in
FIG. 4B , afirst opening 404 is formed to thefourth electrode 316 d in thefirst stack 324 of electrodes through the insulatingfill layer 402. Thefirst opening 404 may be formed using any suitable patterning method, such as photolithography and etching through afirst mask 406. - A
second opening 408 is formed through the insulatingfill layer 402 and through the fourth electrode 316 dd to the third electrode 316 cc in thesecond stack 322 of electrodes, as shown inFIG. 4C . Thesecond opening 408 may be formed using any suitable patterning method, such as photolithography and etching through asecond mask 410. - As shown in
FIG. 4D , the center portion of the insulatingfill layer 402 between thestacks opening 412 which connects the upper parts of the first 404 and the second 408 openings. The connectingopening 412 may be formed using any suitable patterning method, such as photolithography and etching through athird mask 414. The etching may be selective to the insulating layer 402 (e.g., silicon oxide) and may stop on the silicon nitrideetch stop layer 330 located over the word line fingers 116-2, and on the exposed portions of the electrodes 316-1 d and 316-1 cc in therespective openings - As shown in
FIG. 4E , a first insulatinglayer 416 is formed in the first 404 and the second 408 openings. Any suitable insulating material may be used, such as silicon oxide, silicon nitride, etc. For example, the first insulatinglayer 416 may be a silicon oxide isolation layer located on sidewalls of the first 404 and the second 408 openings. The first insulatinglayer 416 is located on sidewalls and bottoms of the first, the second and the connecting openings. - As shown in
FIGS. 4F and 4T , the first insulatinglayer 416 may be etched using an anisotropic sidewall spacer anisotropic etch to removelayer 416 from the horizontal surfaces (e.g., from the bottoms of the first and the second openings) and to leave insulating sidewall spacers (i.e., spacer portions) 416S on the sidewalls of theopenings first opening 404 and the third electrode 316-1 cc is exposed in the bottom of thesecond opening 408 between the insulating sidewalls spacers 416S.FIG. 4T is a perspective view ofFIG. 4F . - As shown in
FIG. 4G , a firstconductive layer 418 is conformally formed in the first 404, the second 408 and the connecting 412 openings such that the firstconductive layer 418 is located on the first insulating layer (e.g., over the insulatingspacer 416S portions of layer 416) over the sidewalls of the first, second and the connecting openings. The firstconductive layer 418 may be any suitable conductive layer described above for forming the rails and bridges, such as tungsten, tungsten nitride, titanium, titanium nitride, aluminum, copper, their alloys, etc. The firstconductive layer 418 electrically contacts and connects the fourth electrode 316-1 d exposed in thefirst opening 404 and the third electrode 316-1 cc exposed in thesecond opening 408. - As shown in
FIGS. 4H and 4U , the firstconductive layer 418 may be etched using an anisotropic sidewall spacer anisotropic etch to removelayer 418 from the horizontal surfaces (i.e., from the bottoms of the first and the second openings) and to leave conductive sidewall spacers (e.g., spacer portions) 418S on the sidewalls of theopenings spacer 418S forms thefifth pillar 34 a portions in thesecond opening 408 in contact with the edge portions of the third electrode 316-1 cc,sixth pillar 34 b portions in thefirst opening 404 in contact with the edge portions of the fourth electrode 316-1 d, andthird bridge portions 34 c in the connecting opening 412 (i.e., thespacers 418S form an interconnection between word lines levels L3 and L4 shown inFIG. 3D ). After the sidewall spacer etch, the middle part of the fourth electrode 316-1 d is exposed in the bottom of thefirst opening 404 and the middle part third electrode 316-1 cc is exposed in the bottom of thesecond opening 408 between theconductive sidewalls spacers 418S (i.e., the between thepillar FIG. 4U is a perspective view ofFIG. 4H . - As shown in
FIGS. 4I and 4W , thefirst opening 404 is extended by selective anisotropic etching through the fourth electrode 316-1 d and through the underlyinginterlayer insulating layer 117 to expose the third electrode 316-c in thefirst electrode stack 324 without removing the first conductive layer 418 (i.e., the firstconductive spacers 418S) from over the sidewalls of thefirst opening 404. Thesecond opening 408 is also extended at the same time by the selective etching through the third electrode 316-1 cc to expose the second electrode 316-1 bb in thesecond electrode stack 322 without removing the first conductive layer 418 (i.e., the firstconductive spacers 418S) from over the sidewalls of thesecond opening 408.FIG. 4W is a perspective view ofFIG. 4I . - As shown in
FIG. 4J , a second insulating layer 426 (e.g., a silicon oxide layer) is formed in the first 404 and the second 408 openings such that the second insulating layer is located on sidewalls of the first, the second and the connecting openings (i.e., over the firstconductive sidewall spacers 418S). - As shown in
FIGS. 4K and 4X , the second insulatinglayer 426 may be etched using a sidewall spacer anisotropic etch to removelayer 426 from the horizontal surfaces and to leave second insulatingsidewall spacers 426S on the sidewalls of theopenings conductive sidewall spacers 418S). After the sidewall spacer etch, the third electrode 316-1 c is exposed in the bottom of thefirst opening 404 and the second electrode 316-1 bb is exposed in the bottom of thesecond opening 408 between the insulating sidewalls spacers 426S.FIG. 4X is a perspective view ofFIG. 4K . - The steps shown in
FIGS. 4T through 4X are then repeated several times to form the rest of the rails (e.g., 23 a, 23 b, 12 a, 12 b) and bridges (23 c, 12 c) to complete the interconnect 113-1. - As shown in
FIG. 4L , a secondconductive layer 428 is formed in the first 404 and the second 408 openings. The secondconductive layer 428 is located on the second insulating layer 426 (e.g., on thespacers 426S) over the sidewalls of the first, the second and the connecting openings. The secondconductive layer 428 electrically contacts and connects the third electrode 316-1 c exposed in thefirst opening 404 and the second electrode 316-1 bb exposed in thesecond opening 408. - As shown in
FIG. 4M , the secondconductive layer 428 may be etched using a sidewall spacer anisotropic etch to removelayer 428 from the horizontal surfaces and to leaveconductive sidewall spacers 428S on the sidewalls of theopenings spacer 428S forms the third pillar 23 a portions in thesecond opening 408 in contact with the edge portions of the second electrode 316-1 bb, fourth pillar 23 b portions in thefirst opening 404 in contact with the edge portions of the third electrode 316-1 c, andsecond bridge portions 23 c in the connecting opening 412 (i.e., thespacers 428S form an interconnection between word lines levels L2 and L3 shown inFIG. 3D ). After the sidewall spacer etch, the middle part of the third electrode 316-1 c is exposed in the bottom of thefirst opening 404 and the middle part second electrode 316-1 bb is exposed in the bottom of thesecond opening 408 between theconductive sidewalls spacers 428S (i.e., the between the pillar 23 a, 23 b portions). - Then, as shown in
FIG. 4N , thefirst opening 404 is extended by selective etching through the third electrode 316-1 c to expose the second electrode 316-1 b in thefirst electrode stack 324 without removing the second conductive layer 428 (e.g., thespacers 428S) from over the sidewalls of the first opening. Thesecond opening 408 is also extended during the same selective etch through the second electrode 316-1 bb to expose the first electrode 316-aa in thesecond electrode stack 322 without removing the second conductive layer 428 (e.g., thespacers 428S) from over the sidewalls of the second opening. - As shown in
FIG. 4O , a thirdinsulating layer 436 is formed in the first 404 and the second 408 openings such that the third insulating layer is located on sidewalls of the first, the second and the connecting openings. - As shown in
FIG. 4P , the third insulatinglayer 436 may be etched using a sidewall spacer anisotropic etch to removelayer 436 from the horizontal surfaces and to leave third insulatingsidewall spacers 436S on the sidewalls of theopenings conductive sidewall spacers 428S). After the sidewall spacer etch, the second electrode 316-1 b is exposed in the bottom of thefirst opening 404 and the first electrode 316-1 aa is exposed in the bottom of thesecond opening 408 between the insulating sidewalls spacers 436S. - As shown in
FIG. 4Q , a thirdconductive layer 438 is formed in the first 404, the second 408 and the connecting 412 openings. The thirdconductive layer 438 is located on the third insulating layer 436 (e.g., thespacers 436S) over the sidewalls of the first, the second and the connecting openings. The thirdconductive layer 438 electrically contacts and connects the second electrode 316-1 b exposed in thefirst opening 404 and the first electrode 316-1 aa exposed in thesecond opening 408. - As shown in
FIG. 4R , the thirdconductive layer 438 may be etched back to removelayer 438 from the connectingopening 412 while leaving thelayer 438 to fill the remaining volume of the first 404 and the second 408 opening. The remaining portions oflayer 438 form the first pillar 12 a portions in thesecond opening 408 in contact with the middle portion of the first electrode 316-1 aa, second pillar 12 b portions in thefirst opening 404 in contact with the middle portion of the second electrode 316-1 b, andfirst bridge 12 c in the connecting opening 412 (i.e.,layer 438 forms an interconnection between word lines levels L1 and L2 shown inFIG. 3D ). - Finally, as shown in
FIG. 4S , a gap fill insulating layer 440 (e.g., silicon oxide) is formed overlayer 438 to fill the connectingopening 412. If desired, gap fill insulating layer may include a liner and a filler material located over the liner. The first, second, third and fourth electrodes in thefirst stack 324 comprise a first stack ofword line fingers 116 and contact pads 316. The first, second, third and fourth electrodes in thesecond stack 322 comprise a second stack ofword line fingers 116 and contact pads 316. The first 418, second 428 and third 438 conductive layers comprise respective first, second and third word line interconnects which connect one word line finger in one level in the first stack with a word line finger in another level in the second stack of a three dimensional device, such as a monolithic, three dimensional resistive random access (ReRAM) non-volatile memory device. -
FIGS. 5A-5O show steps in a method of making a contact to a semiconductor device according to another embodiment. - While the method of making the contacts will be described below as the method of making the contacts to the
select TFTs 110 of a three dimensional ReRAM device ofFIGS. 1C-1D , it should be understood that the method may be used to make contacts to any other suitable device, such another memory device (e.g., a NAND memory device) or a non-memory device, such as a logic device. - Referring to
FIGS. 5A and 5B , an in-process memory device is provided instep 50. The device includes theglobal bit lines 150 and the electrodes 151 separated by an insulating fill 500. Thelines 150 and electrodes 151 may comprise any suitable conductive material, such as tungsten, tungsten nitride, titanium, titanium nitride, aluminum, copper, their alloys, etc. The insulating fill 500 may comprise any suitable insulating material, such as silicon oxide. -
Step 50 includes forming aconductive layer 501 over asemiconductor containing stack 503. For example, as shown, theconductive layer 501 may be a metal (e.g., tungsten, etc.) layer formed over astack 503 including a lower barrier layer (e.g., TiN, or WN) 503 a, a semiconductor layer (e.g., polysilicon layer) 503 b and an upper barrier layer (e.g., TiN or WN) 503 c. One or both barrier layers may be omitted. In some embodiments, themetal layer 501 may be relatively thin in comparison to thesemiconductor layer 503. Some embodiments may include forming amask layer 504 over theconductive layer 501. Themask layer 504 may be a hard mask layer, such as a silicon nitride layer.FIG. 5B shows the top view of the device andFIG. 5A is a side (i.e., vertical) cross section along line a-a′ inFIG. 5B . - Referring to
FIG. 5C ,step 51 includes forming a first mask pattern (e.g., in the mask layer 504) over the conductive layer 501 (e.g., using photolithographic techniques) that exposes selected portion of theconductive layer 501. As shown, the first mask pattern 505 includes a first plurality ofopenings 505 a, such as line shaped openings extending in a first horizontal direction and a second plurality of line shaped openings extending in a second horizontal direction substantially parallel to the first, such that the exposed portions are an array of rectangular exposed regions on theconductive layer 501. However, it is to be understood that other geometries for the first mask pattern may be used (e.g., exposing circular rather than rectangular regions of the conductive layer 501). - Referring to
FIG. 5D ,step 52 includes etching portions of theconductive layer 501 and thesemiconductor containing stack 503 exposed in the first mask pattern 505 to form a plurality ofpillars 507. Each pillar comprises alower semiconductor region 507 a (e.g., polysilicon pillar having top and bottom TiN barrier portions) and an upperconductive region 507 b. In the example shown, plurality ofpillars 507 includes an array of rectangular pillars. However, it is to be understood that other pillar shapes may be used, e.g., circular pillars. - Referring to
FIGS. 5E and 5F ,step 53 includes forming an insulatingfill layer 509 between the plurality ofpillars 507. The insulating fill layer may be made of any suitable electrically insulating material, e.g., silicon oxide. In some embodiments, step 53 may further include planarizing the device (e.g., using an etch back or chemical mechanical polishing process) to form a planar surface that exposes the tops of the pillars 507 (which, in some embodiments will include a residual portion of the mask layer 504). Eachregion 507 b form the channel 211 of the TFT select gate transistor 210 shown inFIGS. 1C and 1D .FIG. 5F shows the top view of the device andFIG. 5E is a side (i.e., vertical) cross section along line a-a′ inFIG. 5F . - Referring to
FIG. 5G ,step 54 includes forming a second mask pattern 511 havingopenings 511 a (e.g., using photolithographic techniques) over the plurality of pillars (e.g., inmask layer 504, or in an additional mask layer deposited over the device) and the insulatingfill layer 509. The second mask pattern of 511 comprises a plurality oflines 511 b (shown inFIG. 5I ) which are offset with respect to the first mask pattern openings 505 such that thelines 511 b of the second mask pattern 511 cover both adjacentfirst edge portions 512 a of the upperconductive region 507 a in each adjacent pair of the plurality of pillars and the insulatingfill layer 509 between each adjacent pair of the plurality ofpillars 507, while leaving opposingsecond edge portions 512 b of the upperconductive region 507 a in each pair of the plurality ofpillars 507 uncovered. - Referring to
FIGS. 5H and 5I , step 55 includes etching thesecond edge portions 512 b of the upperconductive regions 507 a of each pair of the plurality ofpillars 507 to leave a plurality ofupper contacts 514 comprising thefirst edge portions 512 a of the upperconductive regions 507 a. Each of the plurality ofupper contacts 514 is located on the respectivelower semiconductor region 507 b in each of the plurality ofpillars 507. In some embodiments, each of the plurality ofupper contacts 514 is narrower than the respectivelower semiconductor region 507 b of thepillar 507. In some embodiments, the use of two offset mask patterns 505 and 511 to form theupper contacts 514 may be advantageous in that the resulting theupper contacts 514 may be narrower in at least one horizontal direction than the minimum line with for the pattern forming process (e.g., photolithographic process) used to for the mask patterns.FIG. 5I shows the top view of the device andFIG. 5H is a side (i.e., vertical) cross section along line a-a′ inFIG. 5I . - Referring to
FIGS. 5J and 5K ,step 56 includes covering the plurality ofupper contacts 514 with an electrically insulating fill layer 516 (e.g., silicon oxide), and planarizing the fill layer to expose a horizontal surface 518 that includes portions of theupper contacts 514. Additional device layers may then be formed on the surface that use theupper contacts 514 to establish electrical connections with lower device layers. - The method described above may be used to form interconnects in monolithic, three dimensional resistive random access (ReRAM) non-volatile memory device, e.g., of the type described herein.
- For example, as shown, each of the plurality of
lower semiconductor regions 507 b comprises a channel of a vertical thin filmselect gate transistor 110. Each select gate transistor further comprises aglobal bit line 150 located below the channel and agate line 131 which is located adjacent to a side of thechannel 111 c. Source and drain regions may also be formed in the channel during thestack 503 deposition. Each of the plurality ofupper contacts 514 comprises a lower portion of one of a plurality of local bit line interconnects 106 a of the memory device. Accordingly, the memory device may have a select gate and bit line structure similar to that of the lower portion of thedevice 100 shown inFIGS. 1C-1D . - In some embodiments, the rest of the
device 100 may be constructed by forming a plurality of upper potions of the local bit line interconnects over the respective lower portions of the local bit line interconnects 106 a, as shown inFIG. 5L , and forming amemory cell region 102 over the upper portions of the plurality of local bit line interconnects 106 a, as shown inFIG. 5M .Region 102 may include the word lines 112 separated by insulatinglayers 117 as shown inFIGS. 1A-1C , as well as the word line interconnects 113 shown inFIGS. 3A-3F . Then, a plurality of vertically extendingopenings 520 are formed through the memory cell region 102 (i.e., through the word lines 112 and layers 117), as shown inFIG. 5N . Finally, theresistivity switching material 103 layers and the plurality oflocal bit lines openings 520 such that the plurality of local bit lines extend vertically into thememory cell region 102. Therespective lines FIG. 5O . - Although the foregoing refers to particular preferred embodiments, it will be understood that the description is not so limited. It will occur to those of ordinary skill in the art that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the description. All of the publications, patent applications and patents cited herein are incorporated herein by reference in their entirety.
Claims (31)
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US14/614,709 US9419058B1 (en) | 2015-02-05 | 2015-02-05 | Memory device with comb-shaped electrode having a plurality of electrode fingers and method of making thereof |
EP15808055.6A EP3254312B1 (en) | 2015-02-05 | 2015-11-24 | Memory device with comb electrode and method of making thereof |
PCT/US2015/062545 WO2016126307A1 (en) | 2015-02-05 | 2015-11-24 | Memory device with comb electrode and method of making thereof |
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US14/614,709 US9419058B1 (en) | 2015-02-05 | 2015-02-05 | Memory device with comb-shaped electrode having a plurality of electrode fingers and method of making thereof |
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170084624A1 (en) * | 2015-09-18 | 2017-03-23 | Changhyun LEE | Three-dimensional semiconductor device with vertical and horizontal channels in stack structure having electrodes vertically stacked on the substrate |
US10593402B2 (en) * | 2016-11-01 | 2020-03-17 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and operating method thereof |
WO2020113578A1 (en) * | 2018-12-07 | 2020-06-11 | Yangtze Memory Technologies Co., Ltd. | Novel 3d nand memory device and method of forming the same |
US20200219804A1 (en) * | 2019-01-09 | 2020-07-09 | Intel Corporation | Selectable vias for back end of line interconnects |
US10825516B2 (en) | 2018-02-27 | 2020-11-03 | Nantero, Inc. | Resistive change element cells sharing selection devices |
US11295810B2 (en) | 2019-06-07 | 2022-04-05 | Nantero, Inc. | Combinational resistive change elements |
US11942154B2 (en) * | 2021-11-22 | 2024-03-26 | Samsung Electronics Co., Ltd. | Non-volatile memory device and method of operating nonvolatile memory device |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016225614A (en) | 2015-05-26 | 2016-12-28 | 株式会社半導体エネルギー研究所 | Semiconductor device |
US9805805B1 (en) | 2016-08-23 | 2017-10-31 | Sandisk Technologies Llc | Three-dimensional memory device with charge carrier injection wells for vertical channels and method of making and using thereof |
US10224372B2 (en) | 2017-05-24 | 2019-03-05 | Sandisk Technologies Llc | Three-dimensional memory device with vertical bit lines and replacement word lines and method of making thereof |
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US10879260B2 (en) | 2019-02-28 | 2020-12-29 | Sandisk Technologies Llc | Bonded assembly of a support die and plural memory dies containing laterally shifted vertical interconnections and methods for making the same |
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Family Cites Families (56)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5915167A (en) | 1997-04-04 | 1999-06-22 | Elm Technology Corporation | Three dimensional structure memory |
CN101179079B (en) | 2000-08-14 | 2010-11-03 | 矩阵半导体公司 | Rail stack array of charge storage devices and method of making same |
TWI266386B (en) | 2001-10-03 | 2006-11-11 | Hannstar Display Corp | Dual vertical cannel thin film transistor for SRAM and manufacturing method thereof |
KR100448899B1 (en) | 2002-08-20 | 2004-09-16 | 삼성전자주식회사 | Phase changeable memory device |
US7233522B2 (en) | 2002-12-31 | 2007-06-19 | Sandisk 3D Llc | NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same |
US7005350B2 (en) | 2002-12-31 | 2006-02-28 | Matrix Semiconductor, Inc. | Method for fabricating programmable memory array structures incorporating series-connected transistor strings |
US7221588B2 (en) | 2003-12-05 | 2007-05-22 | Sandisk 3D Llc | Memory array incorporating memory cells arranged in NAND strings |
US7023739B2 (en) | 2003-12-05 | 2006-04-04 | Matrix Semiconductor, Inc. | NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same |
US7177191B2 (en) | 2004-12-30 | 2007-02-13 | Sandisk 3D Llc | Integrated circuit including memory array incorporating multiple types of NAND string structures |
US7535060B2 (en) | 2006-03-08 | 2009-05-19 | Freescale Semiconductor, Inc. | Charge storage structure formation in transistor with vertical channel region |
JP5016832B2 (en) | 2006-03-27 | 2012-09-05 | 株式会社東芝 | Nonvolatile semiconductor memory device and manufacturing method thereof |
US7808038B2 (en) | 2007-03-27 | 2010-10-05 | Sandisk 3D Llc | Method of making three dimensional NAND memory |
US7848145B2 (en) | 2007-03-27 | 2010-12-07 | Sandisk 3D Llc | Three dimensional NAND memory |
US7514321B2 (en) | 2007-03-27 | 2009-04-07 | Sandisk 3D Llc | Method of making three dimensional NAND memory |
US7745265B2 (en) | 2007-03-27 | 2010-06-29 | Sandisk 3D, Llc | Method of making three dimensional NAND memory |
US7851851B2 (en) | 2007-03-27 | 2010-12-14 | Sandisk 3D Llc | Three dimensional NAND memory |
US7575973B2 (en) | 2007-03-27 | 2009-08-18 | Sandisk 3D Llc | Method of making three dimensional NAND memory |
US7902537B2 (en) | 2007-06-29 | 2011-03-08 | Sandisk 3D Llc | Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same |
US7846782B2 (en) | 2007-09-28 | 2010-12-07 | Sandisk 3D Llc | Diode array and method of making thereof |
KR101226685B1 (en) | 2007-11-08 | 2013-01-25 | 삼성전자주식회사 | Vertical type semiconductor device and Method of manufacturing the same |
JP5142692B2 (en) | 2007-12-11 | 2013-02-13 | 株式会社東芝 | Nonvolatile semiconductor memory device |
KR101418434B1 (en) | 2008-03-13 | 2014-08-14 | 삼성전자주식회사 | Non-volatile memory device, method of fabricating the same, and processing system comprising the same |
KR101065140B1 (en) | 2008-03-17 | 2011-09-16 | 가부시끼가이샤 도시바 | Semiconductor storage device |
JP2010027870A (en) | 2008-07-18 | 2010-02-04 | Toshiba Corp | Semiconductor memory and manufacturing method thereof |
JP4802313B2 (en) | 2008-08-01 | 2011-10-26 | ニッコー株式会社 | Holding device for piezoelectric vibrator |
JP5288936B2 (en) | 2008-08-12 | 2013-09-11 | 株式会社東芝 | Nonvolatile semiconductor memory device |
KR101478678B1 (en) | 2008-08-21 | 2015-01-02 | 삼성전자주식회사 | Non-volatile memory device and method of fabricating the same |
US8395206B2 (en) | 2008-10-09 | 2013-03-12 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
US7994011B2 (en) | 2008-11-12 | 2011-08-09 | Samsung Electronics Co., Ltd. | Method of manufacturing nonvolatile memory device and nonvolatile memory device manufactured by the method |
KR101527192B1 (en) | 2008-12-10 | 2015-06-10 | 삼성전자주식회사 | Non-volatile memory device and method for fabricating the same |
US20100155818A1 (en) | 2008-12-24 | 2010-06-24 | Heung-Jae Cho | Vertical channel type nonvolatile memory device and method for fabricating the same |
KR101495806B1 (en) | 2008-12-24 | 2015-02-26 | 삼성전자주식회사 | Non-volatile memory device |
KR101481104B1 (en) | 2009-01-19 | 2015-01-13 | 삼성전자주식회사 | Nonvolatile memory devices and method for fabricating the same |
KR101579587B1 (en) | 2009-04-01 | 2015-12-22 | 삼성전자주식회사 | Semiconductor device and method of forming the same |
US8284601B2 (en) | 2009-04-01 | 2012-10-09 | Samsung Electronics Co., Ltd. | Semiconductor memory device comprising three-dimensional memory cell array |
KR101548674B1 (en) | 2009-08-26 | 2015-09-01 | 삼성전자주식회사 | 3 Three dimensional semiconductor memory device and method for fabricating the same |
KR101616089B1 (en) | 2009-06-22 | 2016-04-28 | 삼성전자주식회사 | Three dimensional semiconductor memory device |
JP5121792B2 (en) | 2009-08-06 | 2013-01-16 | 株式会社東芝 | Manufacturing method of semiconductor device |
KR101584113B1 (en) | 2009-09-29 | 2016-01-13 | 삼성전자주식회사 | 3 Three Dimensional Semiconductor Memory Device And Method Of Fabricating The Same |
KR101559958B1 (en) | 2009-12-18 | 2015-10-13 | 삼성전자주식회사 | 3 3 Method for manufacturing three dimensional semiconductor device and three dimensional semiconductor device manufactured by the method |
JP2011142276A (en) | 2010-01-08 | 2011-07-21 | Toshiba Corp | Nonvolatile semiconductor memory device and method of manufacturing the same |
US8427859B2 (en) | 2010-04-22 | 2013-04-23 | Micron Technology, Inc. | Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells |
US8520425B2 (en) | 2010-06-18 | 2013-08-27 | Sandisk 3D Llc | Resistive random access memory with low current operation |
US8349681B2 (en) | 2010-06-30 | 2013-01-08 | Sandisk Technologies Inc. | Ultrahigh density monolithic, three dimensional vertical NAND memory device |
US8198672B2 (en) | 2010-06-30 | 2012-06-12 | SanDisk Technologies, Inc. | Ultrahigh density vertical NAND memory device |
US8193054B2 (en) | 2010-06-30 | 2012-06-05 | SanDisk Technologies, Inc. | Ultrahigh density vertical NAND memory device and method of making thereof |
US8187932B2 (en) | 2010-10-15 | 2012-05-29 | Sandisk 3D Llc | Three dimensional horizontal diode non-volatile memory array and method of making thereof |
US8885381B2 (en) | 2010-12-14 | 2014-11-11 | Sandisk 3D Llc | Three dimensional non-volatile storage with dual gated vertical select devices |
US9419217B2 (en) | 2011-08-15 | 2016-08-16 | Unity Semiconductor Corporation | Vertical cross-point memory arrays |
US8847302B2 (en) | 2012-04-10 | 2014-09-30 | Sandisk Technologies Inc. | Vertical NAND device with low capacitance and silicided word lines |
US9171584B2 (en) | 2012-05-15 | 2015-10-27 | Sandisk 3D Llc | Three dimensional non-volatile storage with interleaved vertical select devices above and below vertical bit lines |
US8828884B2 (en) | 2012-05-23 | 2014-09-09 | Sandisk Technologies Inc. | Multi-level contact to a 3D memory array and method of making |
US9147439B2 (en) | 2012-06-15 | 2015-09-29 | Sandisk 3D Llc | Non-volatile memory having 3D array architecture with staircase word lines and vertical bit lines and methods thereof |
KR101989514B1 (en) | 2012-07-11 | 2019-06-14 | 삼성전자주식회사 | Semiconductor device and method of forming the same |
US9425237B2 (en) * | 2014-03-11 | 2016-08-23 | Crossbar, Inc. | Selector device for two-terminal memory |
KR20150118648A (en) * | 2014-04-14 | 2015-10-23 | 삼성전자주식회사 | Nonvolatile memory device |
-
2015
- 2015-02-05 US US14/614,709 patent/US9419058B1/en active Active
- 2015-11-24 WO PCT/US2015/062545 patent/WO2016126307A1/en active Application Filing
- 2015-11-24 EP EP15808055.6A patent/EP3254312B1/en not_active Not-in-force
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170084624A1 (en) * | 2015-09-18 | 2017-03-23 | Changhyun LEE | Three-dimensional semiconductor device with vertical and horizontal channels in stack structure having electrodes vertically stacked on the substrate |
US9685452B2 (en) * | 2015-09-18 | 2017-06-20 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor device with vertical and horizontal channels in stack structure having electrodes vertically stacked on the substrate |
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WO2020113578A1 (en) * | 2018-12-07 | 2020-06-11 | Yangtze Memory Technologies Co., Ltd. | Novel 3d nand memory device and method of forming the same |
US10950623B2 (en) | 2018-12-07 | 2021-03-16 | Yangtze Memory Technologies Co., Ltd. | 3D NAND memory device and method of forming the same |
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US11430811B2 (en) | 2018-12-07 | 2022-08-30 | Yangtze Memory Technologies Co., Ltd. | 3D NAND memory device with select gate cut |
US11825656B2 (en) | 2018-12-07 | 2023-11-21 | Yangtze Memory Technologies Co., Ltd. | 3D NAND memory device and method of forming the same |
US20200219804A1 (en) * | 2019-01-09 | 2020-07-09 | Intel Corporation | Selectable vias for back end of line interconnects |
US11670588B2 (en) * | 2019-01-09 | 2023-06-06 | Intel Corporation | Selectable vias for back end of line interconnects |
US11295810B2 (en) | 2019-06-07 | 2022-04-05 | Nantero, Inc. | Combinational resistive change elements |
US11942154B2 (en) * | 2021-11-22 | 2024-03-26 | Samsung Electronics Co., Ltd. | Non-volatile memory device and method of operating nonvolatile memory device |
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EP3254312B1 (en) | 2018-10-31 |
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WO2016126307A1 (en) | 2016-08-11 |
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