US20160233229A1 - 3d nonvolatile memory device - Google Patents

3d nonvolatile memory device Download PDF

Info

Publication number
US20160233229A1
US20160233229A1 US14/833,801 US201514833801A US2016233229A1 US 20160233229 A1 US20160233229 A1 US 20160233229A1 US 201514833801 A US201514833801 A US 201514833801A US 2016233229 A1 US2016233229 A1 US 2016233229A1
Authority
US
United States
Prior art keywords
region
slimming
word line
word lines
line stack
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US14/833,801
Other versions
US9419009B1 (en
Inventor
Sung Lae OH
Dae Sung EOM
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
SK Hynix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SK Hynix Inc filed Critical SK Hynix Inc
Assigned to SK Hynix Inc. reassignment SK Hynix Inc. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: EOM, DAE SUNG, OH, SUNG LAE
Publication of US20160233229A1 publication Critical patent/US20160233229A1/en
Application granted granted Critical
Publication of US9419009B1 publication Critical patent/US9419009B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H01L27/11578—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L27/11526—
    • H01L27/11551—
    • H01L27/11573—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

Definitions

  • Embodiments relate to a three-dimensional (3D) nonvolatile memory device, and more particularly, to a 3D nonvolatile memory device with a stepped slimming region which is formed only in one side of a stack of word lines and has a larger width than a cell region.
  • Nonvolatile semiconductor memory devices are memory devices in which stored data is retained even when power is interrupted.
  • 2D semiconductor devices in which memory cells are two-dimensionally formed on a silicon substrate reaches its limit
  • 3D semiconductor nonvolatile devices in which memory cells are vertically stacked on a silicon substrate have been proposed.
  • a desired memory cell is driven by applying biases to multi-layered word lines stacked on the substrate.
  • Pad parts are formed in the word lines by patterning the word lines formed in the slimming region in the stepped form.
  • the word lines stacked in the multiple layers may be controlled by forming contact plugs and metal interconnections electrically coupled to the word lines.
  • the slimming region is arranged in both sides of the word line to ensure the margin as in the 3D nonvolatile memory device in the related art.
  • Pass transistors are arranged in both sides of the cell region.
  • the slimming regions are formed in the both sides of the word line and the pass transistors are arranged in both sides of the cell region, a plurality of wells for the pass transistors having the same power are formed, thus increasing an area of the slimming regions.
  • One or more exemplary embodiments are directed to providing a structure of a slimming region.
  • the slimming region is formed only in one side of a stack of word lines, three-dimensionally stacked, and has a larger width than a cell region.
  • the 3D nonvolatile memory device may include a word line stack in which a plurality of word lines are stacked therein and includes a cell region and a slimming region; and pass transistors located below the word line stack, and electrically coupled to the slim ng region.
  • a width of the slimming region may be larger than that of the cell region.
  • a three-dimensional (3D) nonvolatile memory device may include a first word line stack in which a plurality of word lines are stacked therein and includes a first cell region and a first slimming region; and a second word line stack in which a plurality of word lines are stacked therein and includes a second cell region and a second slimming region.
  • the first slimming region and the second slimming region may be patterned in a stepped form to face each other.
  • a slimming region may be formed only in one side of a word line, and an area of the device may be reduced.
  • the space of the slimming region may be largely ensured due to the improved structure of the slimming region, and a process margin may be ensured.
  • FIG. 1 is a schematic perspective view illustrating a configuration of a semiconductor device according to an embodiment of the inventive concept
  • FIG. 2 is a schematic plan view illustrating a configuration of a semiconductor device according to an embodiment of the inventive concept
  • FIG. 3A is a plan view illustrating a connection relationship between word lines and pass transistors in a slimming region according to an embodiment of the inventive concept
  • FIG. 3B is a perspective view illustrating a connection relationship between word lines and pass transistors in a slimming region of any one block according to an embodiment of the inventive concept
  • FIG. 4 is a schematic perspective view illustrating a configuration of a semiconductor device according to another embodiment of the inventive concept.
  • FIG. 5 is an illustrative view illustrating a structure of a contact formed in a slimming region in FIG. 4 .
  • inventive concept is described herein with reference to cross-section and/or plan illustrations that are schematic illustrations of exemplary embodiments of the inventive concept. However, embodiments of the inventive concept should not be construed as limited to the inventive concept. Although a few embodiments of the inventive concept will be shown and described, it will be appreciated by those of ordinary skill in the art that changes may be made in these exemplary embodiments without departing from the principles and spirit of the inventive concept. Functions or operations described in specific blocks may be performed in an order different from the order described in a flowchart when some embodiments are differently implemented. Far example, two continuous blocks may be substantially simultaneously performed, or the blocks may be reversely performed according to related functions or operations.
  • FIGS. 1 and 2 are a schematic perspective view and a schematic plan view illustrating a configuration of a 3D nonvolatile semiconductor device according to an embodiment of the inventive concept. For clarity, in the embodiment, the configuration of transistors will be omitted, and only word lines are illustrated.
  • a word line stack in which a plurality of word lines WL are stacked with interlayer insulating layers (not shown) being interposed therebetween may be formed on a semiconductor substrate (not shown).
  • the word line stack in each block BLK may include a cell region 100 and a slimming region 200 .
  • the cell region 100 may be a region in which a cell structure is formed, and may include channel layers CH.
  • the slimming region 200 may be a region electrically coupled to pass transistors (not shown) which supply programming voltages to the word lines WL of the word line stack, and the word line stack is patterned in a stepped form in the slimming region 200 .
  • the slimming region 200 in each block BLK may be formed only in one side of the cell region 100 to which the programming voltage is supplied through the corresponding slimming region 200 , and the pass transistors may be arranged below the slimming region 200 .
  • the slimming region 200 patterned as the stepped form in each block may be formed to have a width Ws larger than a width Wc of the cell region 100 .
  • the word line stack may be patterned as a stepped form descending in a right direction, in one of slimming regions 200 formed in two adjacent blocks BLK.
  • the word line stack may be patterned as a stepped form ascending in the right direction in the other of the slimming regions 200 . Therefore, the two slimming regions 200 may be formed to be symmetrical to each other.
  • the slimming region 200 may be formed to have the width larger than that of the cell region 100 without an increase in an entire area of the block. Thus, a process margin may be ensured in a subsequent process for forming contacts electrically coupled to the slimming region 200 .
  • FIG. 3A is a plan view illustrating a connection relationship between word lines and pass transistors in the slimming region 200 of FIGS. 1 and 2 .
  • FIG. 3B is a perspective view illustrating a connection relationship between word lines and pass transistors in a slimming region of any one block in FIG. 3A .
  • Pass transistors Pass Tr which supply programming voltages to the word lines WL of the word line stack may be located below the word line stack in the slimming region 200 .
  • the pass transistors Pass Tr may be electrically coupled to the word lines WL in the slimming region 200 through contact plugs.
  • junction regions for example, source and drain regions of the pass transistors Pass Tr, junction regions which are electrically coupled to the word lines WL may be formed in a slit region, that is, in a space between adjacent word lines WL.
  • junction regions arranged in one side of the gates of the pass transistors Pass Tr may be located in the slit region for device isolation between word lines WL of adjacent blocks.
  • the contact plugs for example, local word lines, configured to couple the corresponding junction regions and the word lines WL may be formed to pass through the slit region, and the pass transistors Pass Tr and the word lines WL may be electrically coupled through the contact plugs.
  • junction regions arranged in the other side of the gates among the junction regions formed in both sides of the gates may be coupled to global word lines (not shown) below the word lines WL.
  • FIG. 4 is a schematic perspective view illustrating a configuration of a 3D nonvolatile memory device according to another embodiment.
  • the slimming regions of two adjacent blocks may be patterned in a stepped form and arranged symmetrical to each other. That is, in the embodiment, the slimming region formed in each block may be patterned as the stepped form so that the word line stack may be inclined only to one direction for example, the right downward direction or the right upward direction, and the slimming regions in the adjacent blocks may be formed symmetrically to face each other.
  • a word line stack in a slimming region of each block may be patterned in a stepped form and have a V-shaped cross-sectional profile. That is, a cross-section taken along a longitudinal direction of the word line of the slimming region in each block has a V-shape.
  • the slimming region in each block may include a first slimming region patterned in a stepped form inclined to the right downward direction and a second slimming region patterned in a stepped form inclined to the right upward direction.
  • the first slimming region and the second slimming region may be formed to symmetrically face each other.
  • contacts for coupling pass transistors and word lines WL may be formed on the word lines WL.
  • the contacts may be alternately formed in the first slimming region and the second slimming region as illustrated in FIG. 5 . Therefore, the pitch between adjacent contacts may be increased.
  • insulating layers are not illustrated between the word lines WL, but it is obvious that the insulating layers for insulation between the word lines may be provided.

Abstract

A 3D nonvolatile memory device is disclosed. The 3D nonvolatile memory device includes a word line stack in which a plurality of word lines are stacked therein and includes a cell region and a slimming region, and pass transistors located below the word line stack, and electrically coupled to the slimming region. A width of the slimming region is larger than that of the cell region.

Description

    CROSS-REFERENCES TO RELATED APPLICATION
  • The present application claims priority to Korean patent application No. 10-2015-0017764, filed on Feb. 5, 2015, which is herein incorporated by reference in its entirety.
    • BACKGROUND OF THE INVENTION
  • 1. Technical Field
  • Embodiments relate to a three-dimensional (3D) nonvolatile memory device, and more particularly, to a 3D nonvolatile memory device with a stepped slimming region which is formed only in one side of a stack of word lines and has a larger width than a cell region.
  • 2. Related Art
  • Nonvolatile semiconductor memory devices are memory devices in which stored data is retained even when power is interrupted. Currently, as a degree of integration in the 2D semiconductor devices in which memory cells are two-dimensionally formed on a silicon substrate reaches its limit, 3D semiconductor nonvolatile devices in which memory cells are vertically stacked on a silicon substrate have been proposed.
  • In the 3D nonvolatile semiconductor devices, a desired memory cell is driven by applying biases to multi-layered word lines stacked on the substrate. Pad parts are formed in the word lines by patterning the word lines formed in the slimming region in the stepped form. The word lines stacked in the multiple layers may be controlled by forming contact plugs and metal interconnections electrically coupled to the word lines.
  • As the pitch of cell blocks is gradually reduced due to the increase in the degree of integration of the semiconductor devices, the slimming region is arranged in both sides of the word line to ensure the margin as in the 3D nonvolatile memory device in the related art. Pass transistors are arranged in both sides of the cell region.
  • However, when the slimming regions are formed in the both sides of the word line and the pass transistors are arranged in both sides of the cell region, a plurality of wells for the pass transistors having the same power are formed, thus increasing an area of the slimming regions.
    • SUMMARY
  • One or more exemplary embodiments are directed to providing a structure of a slimming region. The slimming region is formed only in one side of a stack of word lines, three-dimensionally stacked, and has a larger width than a cell region.
  • According to an aspect of an exemplary embodiment, there is provided a three-dimensional (3D) nonvolatile memory device. The 3D nonvolatile memory device may include a word line stack in which a plurality of word lines are stacked therein and includes a cell region and a slimming region; and pass transistors located below the word line stack, and electrically coupled to the slim ng region. A width of the slimming region may be larger than that of the cell region.
  • According to an aspect of an exemplary embodiment, there is provided a three-dimensional (3D) nonvolatile memory device. The 3D nonvolatile memory device may include a first word line stack in which a plurality of word lines are stacked therein and includes a first cell region and a first slimming region; and a second word line stack in which a plurality of word lines are stacked therein and includes a second cell region and a second slimming region. The first slimming region and the second slimming region may be patterned in a stepped form to face each other.
  • According to an embodiment, a slimming region may be formed only in one side of a word line, and an area of the device may be reduced.
  • According to an embodiment, the space of the slimming region may be largely ensured due to the improved structure of the slimming region, and a process margin may be ensured.
  • These and other features, aspects, and embodiments are described below in the section entitled “DETAILED DESCRIPTION”.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and other aspects, features and other advantages of the subject matter of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:
  • FIG. 1 is a schematic perspective view illustrating a configuration of a semiconductor device according to an embodiment of the inventive concept;
  • FIG. 2 is a schematic plan view illustrating a configuration of a semiconductor device according to an embodiment of the inventive concept;
  • FIG. 3A is a plan view illustrating a connection relationship between word lines and pass transistors in a slimming region according to an embodiment of the inventive concept;
  • FIG. 3B is a perspective view illustrating a connection relationship between word lines and pass transistors in a slimming region of any one block according to an embodiment of the inventive concept;
  • FIG. 4 is a schematic perspective view illustrating a configuration of a semiconductor device according to another embodiment of the inventive concept; and
  • FIG. 5 is an illustrative view illustrating a structure of a contact formed in a slimming region in FIG. 4.
    •  DETAILED DESCRIPTION
  • Hereinafter, exemplary embodiments will be described in greater detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements, and overlapping descriptions for the same elements will be omitted.
  • The inventive concept is described herein with reference to cross-section and/or plan illustrations that are schematic illustrations of exemplary embodiments of the inventive concept. However, embodiments of the inventive concept should not be construed as limited to the inventive concept. Although a few embodiments of the inventive concept will be shown and described, it will be appreciated by those of ordinary skill in the art that changes may be made in these exemplary embodiments without departing from the principles and spirit of the inventive concept. Functions or operations described in specific blocks may be performed in an order different from the order described in a flowchart when some embodiments are differently implemented. Far example, two continuous blocks may be substantially simultaneously performed, or the blocks may be reversely performed according to related functions or operations.
  • FIGS. 1 and 2 are a schematic perspective view and a schematic plan view illustrating a configuration of a 3D nonvolatile semiconductor device according to an embodiment of the inventive concept. For clarity, in the embodiment, the configuration of transistors will be omitted, and only word lines are illustrated.
  • In the 3D nonvolatile semiconductor device according to an embodiment, a word line stack in which a plurality of word lines WL are stacked with interlayer insulating layers (not shown) being interposed therebetween may be formed on a semiconductor substrate (not shown). The word line stack in each block BLK may include a cell region 100 and a slimming region 200.
  • The cell region 100 may be a region in which a cell structure is formed, and may include channel layers CH. The slimming region 200 may be a region electrically coupled to pass transistors (not shown) which supply programming voltages to the word lines WL of the word line stack, and the word line stack is patterned in a stepped form in the slimming region 200. The slimming region 200 in each block BLK may be formed only in one side of the cell region 100 to which the programming voltage is supplied through the corresponding slimming region 200, and the pass transistors may be arranged below the slimming region 200.
  • In an embodiment, the slimming region 200 patterned as the stepped form in each block may be formed to have a width Ws larger than a width Wc of the cell region 100. In an embodiment, the word line stack may be patterned as a stepped form descending in a right direction, in one of slimming regions 200 formed in two adjacent blocks BLK. The word line stack may be patterned as a stepped form ascending in the right direction in the other of the slimming regions 200. Therefore, the two slimming regions 200 may be formed to be symmetrical to each other.
  • According to the structure and arrangement of the slimming region 200, the slimming region 200 may be formed to have the width larger than that of the cell region 100 without an increase in an entire area of the block. Thus, a process margin may be ensured in a subsequent process for forming contacts electrically coupled to the slimming region 200.
  • FIG. 3A is a plan view illustrating a connection relationship between word lines and pass transistors in the slimming region 200 of FIGS. 1 and 2. FIG. 3B is a perspective view illustrating a connection relationship between word lines and pass transistors in a slimming region of any one block in FIG. 3A.
  • Pass transistors Pass Tr which supply programming voltages to the word lines WL of the word line stack may be located below the word line stack in the slimming region 200. The pass transistors Pass Tr may be electrically coupled to the word lines WL in the slimming region 200 through contact plugs. Among junction regions for example, source and drain regions of the pass transistors Pass Tr, junction regions which are electrically coupled to the word lines WL may be formed in a slit region, that is, in a space between adjacent word lines WL.
  • For example, among the junction regions formed in both sides of gates of the pass transistors Pass Tr, junction regions arranged in one side of the gates of the pass transistors Pass Tr may be located in the slit region for device isolation between word lines WL of adjacent blocks. The contact plugs for example, local word lines, configured to couple the corresponding junction regions and the word lines WL may be formed to pass through the slit region, and the pass transistors Pass Tr and the word lines WL may be electrically coupled through the contact plugs.
  • Junction regions arranged in the other side of the gates among the junction regions formed in both sides of the gates may be coupled to global word lines (not shown) below the word lines WL.
  • FIG. 4 is a schematic perspective view illustrating a configuration of a 3D nonvolatile memory device according to another embodiment.
  • In the embodiment of FIGS. 1 to 3B, the slimming regions of two adjacent blocks may be patterned in a stepped form and arranged symmetrical to each other. That is, in the embodiment, the slimming region formed in each block may be patterned as the stepped form so that the word line stack may be inclined only to one direction for example, the right downward direction or the right upward direction, and the slimming regions in the adjacent blocks may be formed symmetrically to face each other.
  • However, in an embodiment of FIG. 4, a word line stack in a slimming region of each block may be patterned in a stepped form and have a V-shaped cross-sectional profile. That is, a cross-section taken along a longitudinal direction of the word line of the slimming region in each block has a V-shape. The slimming region in each block may include a first slimming region patterned in a stepped form inclined to the right downward direction and a second slimming region patterned in a stepped form inclined to the right upward direction. The first slimming region and the second slimming region may be formed to symmetrically face each other.
  • When the slimming region is formed in the V-shaped stepped form, contacts for coupling pass transistors and word lines WL may be formed on the word lines WL. In an embodiment, the contacts may be alternately formed in the first slimming region and the second slimming region as illustrated in FIG. 5. Therefore, the pitch between adjacent contacts may be increased.
  • In the above-described embodiments, insulating layers are not illustrated between the word lines WL, but it is obvious that the insulating layers for insulation between the word lines may be provided.
  • The above embodiment of the present invention is illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the embodiment described herein. Nor is the invention limited to any specific type of semiconductor device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.

Claims (8)

1-4. (canceled)
5. A three-dimensional (3D) nonvolatile memory device comprising:
a first word line stack including a plurality of first word lines and extending from a first cell region to a first slimming region; and
a second word line stack including a plurality of second word lines and extending from a second cell region to a second slimming region,
wherein each of the first slimming region and the second slimming region are in a stepped form, and
wherein the first slimming region and the second slimming region face each other.
6. The 3D nonvolatile memory device of claim 5, further comprising:
first pass transistors located below the first word line stack and electrically coupled to the plurality of first word lines in the first slimming region; and
second pass transistors located below the second word line stack, and electrically coupled to the plurality of second word lines in the second slimming region.
7. The 3D nonvolatile memory device of claim 6, further comprising:
a slit region between the first word line stack and the second word line stack; and
contact plugs located in the slit region and configured to electrically couple the plurality of first word lines in the first slimming region to the first pass transistors and electrically couple the plurality of second word lines in the second slimming region to the second pass transistors.
8. The 3D nonvolatile memory device of claim 5,
wherein the first slimming region is in a stepped form,
wherein the first word line stack is inclined in a right downward direction,
wherein the second slimming region is in a stepped form, and
wherein the second word line stack is inclined in a right upward direction.
9. The 3D nonvolatile memory device of claim 5,
wherein a width of the first slimming region is larger than a width of the first cell region, and
a width of the second slimming region is larger than a width of the second cell region.
10. A three-dimensional (3D) nonvolatile memory device comprising:
a cell region and a slimming region, wherein the sliming region is formed at one side of the cell region;
a first word line stack including a plurality of first word lines and extending from the cell region to the slimming region along a first direction;
a second word line stack including a plurality of second word lines and extending from the cell region to the slimming region along the first direction;
a first opening formed in the sliming region and exposing the plurality of first word lines, wherein the plurality of first word lines exposed by the first opening has a stepped structure; and
a second opening formed in the sliming region and exposing the plurality of second word lines, wherein the plurality of second word lines exposed by the second opening has a stepped structure,
wherein the second word line stack in the slimming region is interlocked with the first word line in the slimming region, and
wherein the first and the second openings are arranged side by side along the first direction.
11. The three-dimensional (3D) nonvolatile memory device of claim 10,
wherein the first word line stack in the cell region is located at a first row,
wherein the second word line stack in the cell region is located at a second row,
wherein the first row and the second row are arranged in a second direction perpendicular to the first direction,
wherein the first word line stack in the slimming region protrudes from the first row and extends to the second row along the second direction, and
wherein the second word line stack in the slimming region protrudes from the second row and extends to the first row along the second direction.
US14/833,801 2015-02-05 2015-08-24 3D nonvolatile memory device Active US9419009B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020150017764A KR20160096309A (en) 2015-02-05 2015-02-05 3-dimension non-volatile semiconductor device
KR10-2015-0017764 2015-02-05

Publications (2)

Publication Number Publication Date
US20160233229A1 true US20160233229A1 (en) 2016-08-11
US9419009B1 US9419009B1 (en) 2016-08-16

Family

ID=56566183

Family Applications (1)

Application Number Title Priority Date Filing Date
US14/833,801 Active US9419009B1 (en) 2015-02-05 2015-08-24 3D nonvolatile memory device

Country Status (2)

Country Link
US (1) US9419009B1 (en)
KR (1) KR20160096309A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9905514B2 (en) * 2016-04-11 2018-02-27 Micron Technology, Inc. Semiconductor device structures including staircase structures, and related methods and electronic systems
WO2018222234A1 (en) * 2017-06-01 2018-12-06 Sandisk Technologies Llc Connection region between adjacent memory arrays for three-dimensional memory device with terrace regions and method of making thereof
CN109314112A (en) * 2018-06-28 2019-02-05 长江存储科技有限责任公司 The method for forming the hierarchic structure for the wiring of three-dimensional storage part bilateral
US10373970B2 (en) * 2016-03-02 2019-08-06 Micron Technology, Inc. Semiconductor device structures including staircase structures, and related methods and electronic systems
CN110718553A (en) * 2018-07-12 2020-01-21 爱思开海力士有限公司 Semiconductor memory device and method of forming the same
CN111758162A (en) * 2020-05-15 2020-10-09 长江存储科技有限责任公司 Three-dimensional NAND memory device and method of forming the same
US10847534B2 (en) 2018-06-28 2020-11-24 Yangtze Memory Technologies Co., Ltd. Staircase structures for three-dimensional memory device double-sided routing
WO2021158252A1 (en) * 2020-02-05 2021-08-12 Sandisk Technologies Llc Three-dimensional memory device containing horizontal and vertical word line interconnections and methods of forming the same
US20220028731A1 (en) * 2017-08-21 2022-01-27 Samsung Electronics Co., Ltd. Three-dimensional semiconductor device
US11296108B2 (en) * 2019-02-05 2022-04-05 Kioxia Corporation Semiconductor memory device and manufacturing method of semiconductor memory device
EP4167701A1 (en) * 2021-10-12 2023-04-19 Macronix International Co., Ltd. 3d circuit structure with stairstep contact configuration

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102408648B1 (en) 2015-11-05 2022-06-14 에스케이하이닉스 주식회사 3-dimension nonvolatile memory device
KR102508918B1 (en) 2016-12-22 2023-03-10 삼성전자주식회사 Vertical semiconductor devices
KR102573272B1 (en) 2018-06-22 2023-09-01 삼성전자주식회사 Three-dimensional semiconductor memory device
KR20200047882A (en) 2018-10-25 2020-05-08 삼성전자주식회사 Three-dimensional semiconductor device
KR20200114285A (en) 2019-03-28 2020-10-07 에스케이하이닉스 주식회사 Semiconductor memory device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5091526B2 (en) 2007-04-06 2012-12-05 株式会社東芝 Semiconductor memory device and manufacturing method thereof
KR101502584B1 (en) 2008-10-16 2015-03-17 삼성전자주식회사 Nonvolatile memory device
KR20130072522A (en) * 2011-12-22 2013-07-02 에스케이하이닉스 주식회사 Three dimension non-volatile memory device and method for manufacturing the same

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11653499B2 (en) 2016-03-02 2023-05-16 Micron Technology, Inc. Semiconductor devices including staircase structures
US10373970B2 (en) * 2016-03-02 2019-08-06 Micron Technology, Inc. Semiconductor device structures including staircase structures, and related methods and electronic systems
US10910395B2 (en) 2016-03-02 2021-02-02 Micron Technology, Inc. Methods of forming semiconductor device structures
US9905514B2 (en) * 2016-04-11 2018-02-27 Micron Technology, Inc. Semiconductor device structures including staircase structures, and related methods and electronic systems
US11600631B2 (en) * 2016-04-11 2023-03-07 Micron Technology, Inc. Devices including staircase structures, and related memory devices and electronic systems
US10748918B2 (en) 2016-04-11 2020-08-18 Micron Technology, Inc. Methods of forming semiconductor device structures including staircase structures
US20200357813A1 (en) * 2016-04-11 2020-11-12 Micron Technology, Inc. Devices including staircase structures, and related memory devices and electronic systems
WO2018222234A1 (en) * 2017-06-01 2018-12-06 Sandisk Technologies Llc Connection region between adjacent memory arrays for three-dimensional memory device with terrace regions and method of making thereof
US10269817B2 (en) 2017-06-01 2019-04-23 Sandisk Technologies Llc Mid-plane word line switch connection for CMOS under three-dimensional memory device and method of making thereof
US20220028731A1 (en) * 2017-08-21 2022-01-27 Samsung Electronics Co., Ltd. Three-dimensional semiconductor device
US10847534B2 (en) 2018-06-28 2020-11-24 Yangtze Memory Technologies Co., Ltd. Staircase structures for three-dimensional memory device double-sided routing
US10453860B1 (en) 2018-06-28 2019-10-22 Yangtze Memory Technologies Co., Ltd. Method of forming staircase structures for three-dimensional memory device double-sided routing
CN109314112A (en) * 2018-06-28 2019-02-05 长江存储科技有限责任公司 The method for forming the hierarchic structure for the wiring of three-dimensional storage part bilateral
CN110718553A (en) * 2018-07-12 2020-01-21 爱思开海力士有限公司 Semiconductor memory device and method of forming the same
US11296108B2 (en) * 2019-02-05 2022-04-05 Kioxia Corporation Semiconductor memory device and manufacturing method of semiconductor memory device
WO2021158252A1 (en) * 2020-02-05 2021-08-12 Sandisk Technologies Llc Three-dimensional memory device containing horizontal and vertical word line interconnections and methods of forming the same
US11133252B2 (en) 2020-02-05 2021-09-28 Sandisk Technologies Llc Three-dimensional memory device containing horizontal and vertical word line interconnections and methods of forming the same
CN111758162A (en) * 2020-05-15 2020-10-09 长江存储科技有限责任公司 Three-dimensional NAND memory device and method of forming the same
EP4167701A1 (en) * 2021-10-12 2023-04-19 Macronix International Co., Ltd. 3d circuit structure with stairstep contact configuration
JP2023057995A (en) * 2021-10-12 2023-04-24 旺宏電子股▲ふん▼有限公司 Three-dimensional circuit structure having stepped contact configuration

Also Published As

Publication number Publication date
KR20160096309A (en) 2016-08-16
US9419009B1 (en) 2016-08-16

Similar Documents

Publication Publication Date Title
US9419009B1 (en) 3D nonvolatile memory device
US11778828B2 (en) Three-dimensional semiconductor memory device
US10256251B2 (en) Nonvolatile memory device and method for fabricating the same
US9362299B2 (en) Method of fabricating a nonvolatile memory device with a vertical semiconductor pattern between vertical source lines
US8331149B2 (en) 3D nonvolatile memory device and method for fabricating the same
US8503213B2 (en) Memory architecture of 3D array with alternating memory string orientation and string select structures
US9425205B2 (en) Semiconductor memory device
US8981567B2 (en) 3-D IC device with enhanced contact area
US9165654B1 (en) Nonvolatile memory device having page buffer units under a cell
TW201939716A (en) Memory device
US10483277B2 (en) Semiconductor memory device and method for manufacturing the same
TW201733081A (en) Semiconductor memory device
KR20130072076A (en) Nonvolatile memory device and method for fabricating the same
US10211152B2 (en) Semiconductor device and method of manufacturing the same
US10910392B2 (en) Semiconductor memory device
US9356039B2 (en) Nonvolatile memory device including a source line having a three-dimensional shape
KR20160011095A (en) Three dimensional non-volatile memory device
US9679913B1 (en) Memory structure and method for manufacturing the same
US9030020B2 (en) Semiconductor memory device
KR20120131687A (en) Nonvolatile memory device and method for fabricating the same
US9666597B2 (en) Semiconductor memory device
US8525246B2 (en) Semiconductor storage device and method of manufacturing the same
US20150069485A1 (en) Semiconductor device and method of manufacturing the same
JP2010114153A (en) Nonvolatile semiconductor memory device

Legal Events

Date Code Title Description
AS Assignment

Owner name: SK HYNIX INC., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OH, SUNG LAE;EOM, DAE SUNG;SIGNING DATES FROM 20150820 TO 20150821;REEL/FRAME:036403/0723

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8