US20160233216A1 - Semiconductor device and preparation method therefor - Google Patents

Semiconductor device and preparation method therefor Download PDF

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US20160233216A1
US20160233216A1 US15/023,049 US201415023049A US2016233216A1 US 20160233216 A1 US20160233216 A1 US 20160233216A1 US 201415023049 A US201415023049 A US 201415023049A US 2016233216 A1 US2016233216 A1 US 2016233216A1
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diffusion
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US10818655B2 (en
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Guangsheng Zhang
Sen Zhang
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CSMC Technologies Fab2 Co Ltd
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Definitions

  • the present invention relates to a technical field of semiconductor manufacturing, and particularly relates to a semiconductor device and a manufacturing method thereof.
  • the semiconductor device is parasitized to obtain a certain threshold voltage according to inherent process conditions, and thus the threshold voltage is unadjustable.
  • a method of manufacturing a semiconductor device with changeable thresholds is also provided.
  • a semiconductor device includes a substrate; a buried layer formed on the substrate; a diffusion layer formed on the buried layer, wherein the diffusion layer comprises a first diffusion region and a second diffusion region, and an impurity type of the second diffusion region is opposite to an impurity type of the first diffusion region; the diffusion layer further comprises a plurality of third diffusion regions formed in the second diffusion region, wherein an impurity type of the third diffusion region is opposite to the impurity type of the second diffusion region; and a gate formed on the diffusion layer.
  • the plurality of third diffusion regions are arranged regularly spaced from each other.
  • a side length of the third diffusion region is less than or equal to a width of a space between two adjacent third diffusion regions.
  • the impurity type of the third diffusion region is opposite to an impurity type of the gate.
  • the buried layer comprises a first buried layer region and a second buried layer region, an impurity type of the first buried layer region is opposite to an impurity type of the second buried layer region, the impurity type of the first buried layer region is the same as the impurity type of the first diffusion region.
  • the semiconductor device includes: a normally-on type device region and a normally-off type device region, wherein the normally-on type device region and the normally-off type device region each has a first buried layer region and share a second buried layer region, and the normally-on type device region and the normally-off type device region each has a first diffusion region and share a second diffusion region; and a shared drain lead-out region formed at a common boundary of the normally-on type device region and the normally-off type device region in the second diffusion region, wherein the shared drain lead-out region serves as a common drain lead-out region of the normally-on type device region and the normally-off type device region, and an impurity type of the shared drain lead-out region is the same as the impurity type of the second diffusion region.
  • a substrate lead-out region is formed in the first diffusion region of the normally-on type device region, and a source lead-out region is formed in the second diffusion region of the normally-on type device region; an impurity type of the source lead-out region is opposite to an impurity type of the substrate lead-out region, a width of a space between the source lead-out region and the substrate lead-out region is greater than zero.
  • a source lead-out region and a substrate lead-out region are formed in the first diffusion region of the normally-off type device region, and a width of a space between the source lead-out region and the substrate lead-out region is greater than or equal to zero.
  • the semiconductor device is a lateral diffusion metal oxide semiconductor device.
  • a method of manufacturing a semiconductor device includes: providing a substrate, and forming a buried layer on the substrate; forming a diffusion layer having a first diffusion region and a second diffusion region on the buried layer, wherein an impurity type of the second diffusion region is opposite to an impurity type of the first diffusion region; forming a plurality of third diffusion regions in the second diffusion region, wherein an impurity type of the third diffusion region is opposite to the impurity type of the second diffusion region; and forming a gate, a drain lead-out region, and a source lead-out region of the semiconductor device on the second diffusion region.
  • the semiconductor device described above since the plurality of third diffusion regions are formed in the second diffusion region, and the impurity type of the third diffusion region is opposite to the impurity type of the second diffusion region, a concentration of the second diffusion region can be adjusted and controlled by adjusting the size of the third diffusion region, thereby achieving the control of the threshold voltage of the semiconductor device, and thus the semiconductor device with changeable thresholds is obtained.
  • FIG. 1 is a partial cross-sectional view of a semiconductor device in accordance with one embodiment
  • FIG. 2 is a partial cross-sectional view of a semiconductor device in accordance with other embodiment
  • FIGS. 3 is a flow chart of a method of manufacturing the semiconductor device in accordance with one embodiment.
  • FIG. 4 is a schematic diagram of forming a plurality of third diffusion regions during the method of manufacturing the semiconductor device in accordance with one embodiment.
  • FIG. 1 is a cross-section view of a semiconductor device 100 in accordance with one embodiment.
  • the semiconductor device 100 is a lateral diffusion metal oxide semiconductor device.
  • the semiconductor device 100 includes a substrate 110 .
  • the substrate 110 is made of semiconductor materials known by those skilled in the art.
  • a buried layer 120 is formed on the substrate 110 ,
  • the buried layer 120 includes a first buried layer region 122 and a second buried layer region 124 .
  • the first buried layer region 122 and the second buried layer region 124 are doped via ion implantation, and a dopant impurity type of the first buried layer region 122 is opposite to a dopant impurity type of the second buried layer region 124 .
  • the buried layer 120 is formed by twice of implantation, which can avoid using too much driving-in to form the buried layer 120 .
  • the first buried layer region 122 and the second buried layer region 124 cooperatively form a high voltage withstand region of the device, and the voltage resistance property of the device is improved.
  • a diffusion layer 130 is formed on the buried layer 120 .
  • the diffusion layer 130 includes a first diffusion region 132 and a second diffusion region 134 .
  • An impurity type of the first diffusion region 132 is the same as the impurity type of the first buried layer region 122
  • an impurity type of the second diffusion region 134 is opposite to the impurity type of the first diffusion region 132 .
  • a plurality of third diffusion regions 136 are formed in the second diffusion region 134 .
  • An impurity type of the third diffusion region 136 is opposite to the impurity type of the second diffusion region 134 .
  • the plurality of third diffusion regions 136 are formed, and an impurity concentration of the second diffusion region 134 can be adjusted and controlled by adjusting the size of the third diffusion region 136 and the concentration and dose of the implanted ions, thereby achieving the control of the threshold voltage of the semiconductor device 100 .
  • the third diffusion regions 136 are formed via ion implantation.
  • the third diffusion regions 136 are arranged regularly spaced from each other, and a side length of the third diffusion region 136 is less than or equal to a width of a space between two adjacent third diffusion regions.
  • the side length of the third diffusion region 136 should not be too large, otherwise islands of opposed impurity types will be easily formed in the second diffusion region 134 .
  • a gate 144 is formed on the second diffusion region of the semiconductor device 100 .
  • the impurity type of the third diffusion region is opposite to an impurity type of the gate.
  • a thickness of the oxide layer between the gate 144 and the silicon substrate can be configured according to actual needs.
  • a drain lead-out region 142 and a source lead-out region 146 is also formed on the second diffusion region 134 , and an impurity type of the drain lead-out region 142 is the same as the impurity type of the second diffusion region 134 .
  • a substrate lead-out region 148 is formed on the first diffusion region 132 , and an impurity type of the source lead-out region 146 is opposite to an impurity type of the substrate lead-out region 148 .
  • the semiconductor device may include a normally-on type device region and a normally-off type device region.
  • a semiconductor device 200 includes a normally-on type device region 10 and a normally-off type device region 20 .
  • the normally-on type device region 10 and the normally-off type device region 20 each has a first buried layer region 122 and share a second buried layer region 124 .
  • the normally-on type device region 10 and the normally-off type device region 20 each has a first diffusion region 132 and share a second diffusion region 134 .
  • the semiconductor device 200 further includes a shared drain lead-out region 142 formed at a common boundary of the normally-on type device region 10 and the normally-off type device region 20 in the second diffusion region 134 .
  • the shared drain lead-out region 142 serves as a common drain lead-out region of the normally-on type device region 10 and the normally-off type device region 20 , thus during layout designing, the area of the device can be greatly reduced, and the design and the commonality of the device is improved. In addition, the normally-on type device and normally-off devices can be obtained at the same time, which greatly simplifies the manufacturing process, and saves the cost.
  • an impurity type of the shared drain lead-out region 142 is the same as the impurity type of the second diffusion region 134 .
  • the second diffusion region 134 where the normally-on type device region 10 located is provided with the third diffusion regions 136 , the gate 144 and the source lead-out region 146 .
  • the first diffusion region 132 is provided with the substrate lead-out region 148 .
  • a width of a space between the source lead-out region 146 of the normally-on type device region 10 and the substrate lead-out region 148 is greater than zero. When the width of the space between the source lead-out region 146 and the substrate lead-out region 148 equal to zero, the breakdown voltage between them is extremely low, and the device cannot be used.
  • the first diffusion region 232 where the normally-off type device region 20 located is provided with the substrate lead-out region 246 and the source lead-out region 248 .
  • the impurity concentration of the substrate lead-out region 246 and the source lead-out region 248 is relatively high, and the width of the space between them is greater than or equal to zero.
  • the second diffusion region 134 where the normally-off type device region 20 located is provided with the third diffusion regions 236 , so as to adjust the concentration of the second diffusion region 134 , and improve the performance of the device.
  • a method of manufacturing a semiconductor device is also provided, which includes the following steps.
  • step S 310 a substrate is provided, and a buried layer is implanted and formed on the substrate.
  • the substrate is made of semiconductor materials known by those skilled in the art
  • a buried layer is formed on the substrate via ion implantation.
  • the buried layer is implanted for twice, i.e. a first buried layer region is formed before a second buried layer region is formed.
  • An impurity type of the first buried layer region is opposite to an impurity type of the second buried layer region.
  • twice of implantation too much driving-in can be avoided during forming the buried layer.
  • the first buried layer region and the second buried layer region cooperatively form a high voltage tolerant region of the device, and the voltage resistance properly of the device is improved.
  • step S 320 a diffusion layer having a first diffusion region and a second diffusion region is formed on an upper surface of the buried layer.
  • the diffusion layer is formed on the upper surface of the buried layer, and the diffusion layer includes the first diffusion region and the second diffusion region.
  • An impurity type of the second diffusion region is opposite to an impurity type of the first diffusion region.
  • the impurity type of the first diffusion region is the same as the impurity type of the first buried layer region.
  • step S 330 a plurality of third diffusion regions are formed on the second diffusion region.
  • a layer of photoresist is formed on the second diffusion region, and a plurality of implanting windows are defined on the second diffusion region corresponding to the photoresist.
  • FIG. 4 is a top view of the photoresist having the implanting windows.
  • the photoresist 410 is located on the diffusion region, and the plurality of implanting windows 420 of the third diffusion regions are defined on the second diffusion region.
  • Dopant impurities are implanted via the implanting windows 420 ; a dopant impurity type of the third diffusion region is opposite to the impurity type of the second diffusion region.
  • the implanting windows 420 are arranged regularly spaced from each other.
  • the shape of the implanting window 420 can be designed according to actual need.
  • the implanting window has a shape of square, and in alternative embodiments, the implanting window may also be other shapes.
  • the size of the implanting windows and the width of the space between the implanting windows can be adjusted according to different threshold voltages. Different threshold voltages correspond to different sizes of the implanting windows and different widths of the space between the implanting windows.
  • the implanting windows shall not be too large, the side length of the implanting window should be less than or equal to the width of the width of the space between the implanting windows, otherwise, when the implanting window is too large, islands of opposed impurity types will be easily formed in the second diffusion region.
  • step S 340 a gate, a drain lead-out region, a source lead-out region, and a substrate lead-out region of the semiconductor device are formed on the second diffusion region.
  • the gate, the drain lead-out region, and the source lead-out region are formed on the second diffusion region, and the substrate lead-out region is formed in the first diffusion region.
  • An impurity type of the drain lead-out region is the same as the impurity type of the second diffusion region, while an impurity type of the source lead-out region is opposite to an impurity type of the substrate lead-out region.
  • the semiconductor device is a device including a normally-on type device region and a normally-off type device region
  • the normally-on type device region and the normally-off type device region are manufactured at the same time.
  • the normally-on type device region and the normally-off type device region each has a first buried layer region and share a second buried layer region; the normally-on type device region and the normally-off type device region each has a first diffusion region and share a second diffusion region.
  • the method further includes a step of forming a shared drain lead-out region, which is formed at a common boundary of the normally-on type device region and the normally-off type device region in the second diffusion region.
  • An impurity type of the shared drain lead-out region is the same as the impurity type of the second diffusion region.
  • the shared drain lead-out region serves as a common drain lead-out region of the normally-on type device region and the normally-off type device region, during designing, the area of the device can be greatly reduced, and the design of the device is improved.
  • the normally-on type device and normally-off type device can be obtained at the same time, which greatly simplifies the manufacturing process, and saves the cost.
  • the method further includes a step of forming the gate, the drain lead-out region, and the source lead-out region is formed on the second diffusion layer where the normally-on type device region located, and forming the substrate lead-out region in the first diffusion region.
  • a width of a space between the source lead-out region of the normally-on type device region and the substrate lead-out region is greater than zero. When the width of the space between the source lead-out region and the substrate lead-out region equal to zero, the breakdown voltage between them is extremely low, and the device cannot be used.
  • the first diffusion region where the normally-off type device region located is provided with the substrate lead-out region and the source lead-out region.
  • the impurity concentration of the substrate lead-out region and the source lead-out region is relatively high, and the width of the space between them is greater than or equal to zero.
  • the second diffusion region where the normally-off type device region located is provided with the third diffusion regions, so as to adjust the concentration of the second diffusion region, and improve the performance of the device.

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Abstract

A semiconductor device includes a substrate (110); a buried layer (120) formed on the substrate (110), a diffusion layer (130) formed on the buried layer (120), wherein the diffusion layer (130) includes a first diffusion region (132) and a second diffusion region (134), and an impurity type of the second diffusion region (134) is opposite to an impurity type of the first diffusion region (132); the diffusion layer (134) further comprises a plurality of third diffusion regions (136) formed in the second diffusion region, wherein an impurity type of the third diffusion region (136) is opposite to the impurity type of the second diffusion region (134); and a gate (144) formed on the diffusion layer (130).

Description

    FIELD OF THE INVENTION
  • The present invention relates to a technical field of semiconductor manufacturing, and particularly relates to a semiconductor device and a manufacturing method thereof.
    • BACKGROUND OF THE INVENTION
  • During a manufacturing process of a conventional semiconductor device for a start-up circuit, generally, the semiconductor device is parasitized to obtain a certain threshold voltage according to inherent process conditions, and thus the threshold voltage is unadjustable.
    • SUMMARY OF THE INVENTION
  • Accordingly, it is necessary to provide a semiconductor device with changeable thresholds.
  • A method of manufacturing a semiconductor device with changeable thresholds is also provided.
  • A semiconductor device includes a substrate; a buried layer formed on the substrate; a diffusion layer formed on the buried layer, wherein the diffusion layer comprises a first diffusion region and a second diffusion region, and an impurity type of the second diffusion region is opposite to an impurity type of the first diffusion region; the diffusion layer further comprises a plurality of third diffusion regions formed in the second diffusion region, wherein an impurity type of the third diffusion region is opposite to the impurity type of the second diffusion region; and a gate formed on the diffusion layer.
  • In one of embodiments, the plurality of third diffusion regions are arranged regularly spaced from each other.
  • In one of embodiments, a side length of the third diffusion region is less than or equal to a width of a space between two adjacent third diffusion regions.
  • In one of embodiments, the impurity type of the third diffusion region is opposite to an impurity type of the gate.
  • In one of embodiments, the buried layer comprises a first buried layer region and a second buried layer region, an impurity type of the first buried layer region is opposite to an impurity type of the second buried layer region, the impurity type of the first buried layer region is the same as the impurity type of the first diffusion region.
  • In one of embodiments, the semiconductor device includes: a normally-on type device region and a normally-off type device region, wherein the normally-on type device region and the normally-off type device region each has a first buried layer region and share a second buried layer region, and the normally-on type device region and the normally-off type device region each has a first diffusion region and share a second diffusion region; and a shared drain lead-out region formed at a common boundary of the normally-on type device region and the normally-off type device region in the second diffusion region, wherein the shared drain lead-out region serves as a common drain lead-out region of the normally-on type device region and the normally-off type device region, and an impurity type of the shared drain lead-out region is the same as the impurity type of the second diffusion region.
  • In one of embodiments, a substrate lead-out region is formed in the first diffusion region of the normally-on type device region, and a source lead-out region is formed in the second diffusion region of the normally-on type device region; an impurity type of the source lead-out region is opposite to an impurity type of the substrate lead-out region, a width of a space between the source lead-out region and the substrate lead-out region is greater than zero.
  • In one of embodiments, a source lead-out region and a substrate lead-out region are formed in the first diffusion region of the normally-off type device region, and a width of a space between the source lead-out region and the substrate lead-out region is greater than or equal to zero.
  • In one of embodiments, the semiconductor device is a lateral diffusion metal oxide semiconductor device.
  • A method of manufacturing a semiconductor device includes: providing a substrate, and forming a buried layer on the substrate; forming a diffusion layer having a first diffusion region and a second diffusion region on the buried layer, wherein an impurity type of the second diffusion region is opposite to an impurity type of the first diffusion region; forming a plurality of third diffusion regions in the second diffusion region, wherein an impurity type of the third diffusion region is opposite to the impurity type of the second diffusion region; and forming a gate, a drain lead-out region, and a source lead-out region of the semiconductor device on the second diffusion region.
  • In the semiconductor device described above, since the plurality of third diffusion regions are formed in the second diffusion region, and the impurity type of the third diffusion region is opposite to the impurity type of the second diffusion region, a concentration of the second diffusion region can be adjusted and controlled by adjusting the size of the third diffusion region, thereby achieving the control of the threshold voltage of the semiconductor device, and thus the semiconductor device with changeable thresholds is obtained.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a partial cross-sectional view of a semiconductor device in accordance with one embodiment;
  • FIG. 2 is a partial cross-sectional view of a semiconductor device in accordance with other embodiment;
  • FIGS. 3 is a flow chart of a method of manufacturing the semiconductor device in accordance with one embodiment; and
  • FIG. 4 is a schematic diagram of forming a plurality of third diffusion regions during the method of manufacturing the semiconductor device in accordance with one embodiment.
    •  DETAILED DESCRIPTION OF THE EMBODIMENTS
  • The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings.
  • FIG. 1 is a cross-section view of a semiconductor device 100 in accordance with one embodiment. In the illustrated embodiment, the semiconductor device 100 is a lateral diffusion metal oxide semiconductor device. The semiconductor device 100 includes a substrate 110. The substrate 110 is made of semiconductor materials known by those skilled in the art. A buried layer 120 is formed on the substrate 110, The buried layer 120 includes a first buried layer region 122 and a second buried layer region 124. The first buried layer region 122 and the second buried layer region 124 are doped via ion implantation, and a dopant impurity type of the first buried layer region 122 is opposite to a dopant impurity type of the second buried layer region 124. In the illustrated embodiment, the buried layer 120 is formed by twice of implantation, which can avoid using too much driving-in to form the buried layer 120. The first buried layer region 122 and the second buried layer region 124 cooperatively form a high voltage withstand region of the device, and the voltage resistance property of the device is improved. A diffusion layer 130 is formed on the buried layer 120. In the illustrated embodiment, the diffusion layer 130 includes a first diffusion region 132 and a second diffusion region 134. An impurity type of the first diffusion region 132 is the same as the impurity type of the first buried layer region 122, and an impurity type of the second diffusion region 134 is opposite to the impurity type of the first diffusion region 132.
  • In the illustrated embodiment, a plurality of third diffusion regions 136 are formed in the second diffusion region 134. An impurity type of the third diffusion region 136 is opposite to the impurity type of the second diffusion region 134. The plurality of third diffusion regions 136 are formed, and an impurity concentration of the second diffusion region 134 can be adjusted and controlled by adjusting the size of the third diffusion region 136 and the concentration and dose of the implanted ions, thereby achieving the control of the threshold voltage of the semiconductor device 100. Specifically, the third diffusion regions 136 are formed via ion implantation. The third diffusion regions 136 are arranged regularly spaced from each other, and a side length of the third diffusion region 136 is less than or equal to a width of a space between two adjacent third diffusion regions. The side length of the third diffusion region 136 should not be too large, otherwise islands of opposed impurity types will be easily formed in the second diffusion region 134.
  • A gate 144 is formed on the second diffusion region of the semiconductor device 100. The impurity type of the third diffusion region is opposite to an impurity type of the gate. A thickness of the oxide layer between the gate 144 and the silicon substrate can be configured according to actual needs. A drain lead-out region 142 and a source lead-out region 146 is also formed on the second diffusion region 134, and an impurity type of the drain lead-out region 142 is the same as the impurity type of the second diffusion region 134. A substrate lead-out region 148 is formed on the first diffusion region 132, and an impurity type of the source lead-out region 146 is opposite to an impurity type of the substrate lead-out region 148.
  • In alternative embodiments, the semiconductor device may include a normally-on type device region and a normally-off type device region. Referring to FIG. 2, a semiconductor device 200 includes a normally-on type device region 10 and a normally-off type device region 20. The normally-on type device region 10 and the normally-off type device region 20 each has a first buried layer region 122 and share a second buried layer region 124. The normally-on type device region 10 and the normally-off type device region 20 each has a first diffusion region 132 and share a second diffusion region 134. The semiconductor device 200 further includes a shared drain lead-out region 142 formed at a common boundary of the normally-on type device region 10 and the normally-off type device region 20 in the second diffusion region 134. The shared drain lead-out region 142 serves as a common drain lead-out region of the normally-on type device region 10 and the normally-off type device region 20, thus during layout designing, the area of the device can be greatly reduced, and the design and the commonality of the device is improved. In addition, the normally-on type device and normally-off devices can be obtained at the same time, which greatly simplifies the manufacturing process, and saves the cost. In the illustrated embodiment, an impurity type of the shared drain lead-out region 142 is the same as the impurity type of the second diffusion region 134.
  • In the illustrated embodiment, the second diffusion region 134 where the normally-on type device region 10 located is provided with the third diffusion regions 136, the gate 144 and the source lead-out region 146. The first diffusion region 132 is provided with the substrate lead-out region 148. A width of a space between the source lead-out region 146 of the normally-on type device region 10 and the substrate lead-out region 148 is greater than zero. When the width of the space between the source lead-out region 146 and the substrate lead-out region 148 equal to zero, the breakdown voltage between them is extremely low, and the device cannot be used. The first diffusion region 232 where the normally-off type device region 20 located is provided with the substrate lead-out region 246 and the source lead-out region 248. The impurity concentration of the substrate lead-out region 246 and the source lead-out region 248 is relatively high, and the width of the space between them is greater than or equal to zero. The second diffusion region 134 where the normally-off type device region 20 located is provided with the third diffusion regions 236, so as to adjust the concentration of the second diffusion region 134, and improve the performance of the device.
  • Referring to FIG. 3, a method of manufacturing a semiconductor device is also provided, which includes the following steps.
  • In step S310, a substrate is provided, and a buried layer is implanted and formed on the substrate.
  • The substrate is made of semiconductor materials known by those skilled in the art, A buried layer is formed on the substrate via ion implantation. In the illustrated embodiment, the buried layer is implanted for twice, i.e. a first buried layer region is formed before a second buried layer region is formed. An impurity type of the first buried layer region is opposite to an impurity type of the second buried layer region. With twice of implantation, too much driving-in can be avoided during forming the buried layer. The first buried layer region and the second buried layer region cooperatively form a high voltage tolerant region of the device, and the voltage resistance properly of the device is improved.
  • In step S320, a diffusion layer having a first diffusion region and a second diffusion region is formed on an upper surface of the buried layer.
  • The diffusion layer is formed on the upper surface of the buried layer, and the diffusion layer includes the first diffusion region and the second diffusion region. An impurity type of the second diffusion region is opposite to an impurity type of the first diffusion region. The impurity type of the first diffusion region is the same as the impurity type of the first buried layer region.
  • In step S330, a plurality of third diffusion regions are formed on the second diffusion region.
  • A layer of photoresist is formed on the second diffusion region, and a plurality of implanting windows are defined on the second diffusion region corresponding to the photoresist. FIG. 4 is a top view of the photoresist having the implanting windows. The photoresist 410 is located on the diffusion region, and the plurality of implanting windows 420 of the third diffusion regions are defined on the second diffusion region. Dopant impurities are implanted via the implanting windows 420; a dopant impurity type of the third diffusion region is opposite to the impurity type of the second diffusion region. The implantation is performed according to a certain proportion, the plurality of third diffusion regions are formed in the second diffusion region to adjust an impurity concentration of the second diffusion region, and thus the threshold voltage of the semiconductor device is changeable. In the illustrated embodiment, the implanting windows 420 are arranged regularly spaced from each other. The shape of the implanting window 420 can be designed according to actual need. In the illustrated embodiment, the implanting window has a shape of square, and in alternative embodiments, the implanting window may also be other shapes. The size of the implanting windows and the width of the space between the implanting windows can be adjusted according to different threshold voltages. Different threshold voltages correspond to different sizes of the implanting windows and different widths of the space between the implanting windows. In the illustrated embodiment, the implanting windows shall not be too large, the side length of the implanting window should be less than or equal to the width of the width of the space between the implanting windows, otherwise, when the implanting window is too large, islands of opposed impurity types will be easily formed in the second diffusion region.
  • In step S340, a gate, a drain lead-out region, a source lead-out region, and a substrate lead-out region of the semiconductor device are formed on the second diffusion region.
  • The gate, the drain lead-out region, and the source lead-out region are formed on the second diffusion region, and the substrate lead-out region is formed in the first diffusion region. An impurity type of the drain lead-out region is the same as the impurity type of the second diffusion region, while an impurity type of the source lead-out region is opposite to an impurity type of the substrate lead-out region.
  • In another embodiment, if the semiconductor device is a device including a normally-on type device region and a normally-off type device region, during manufacturing, the normally-on type device region and the normally-off type device region are manufactured at the same time. When manufacturing the buried layer, the normally-on type device region and the normally-off type device region each has a first buried layer region and share a second buried layer region; the normally-on type device region and the normally-off type device region each has a first diffusion region and share a second diffusion region. After finishing manufacturing the buried layer and the diffusion layer, the method further includes a step of forming a shared drain lead-out region, which is formed at a common boundary of the normally-on type device region and the normally-off type device region in the second diffusion region. An impurity type of the shared drain lead-out region is the same as the impurity type of the second diffusion region. The shared drain lead-out region serves as a common drain lead-out region of the normally-on type device region and the normally-off type device region, during designing, the area of the device can be greatly reduced, and the design of the device is improved. In addition, the normally-on type device and normally-off type device can be obtained at the same time, which greatly simplifies the manufacturing process, and saves the cost.
  • In the illustrated embodiment, the method further includes a step of forming the gate, the drain lead-out region, and the source lead-out region is formed on the second diffusion layer where the normally-on type device region located, and forming the substrate lead-out region in the first diffusion region. A width of a space between the source lead-out region of the normally-on type device region and the substrate lead-out region is greater than zero. When the width of the space between the source lead-out region and the substrate lead-out region equal to zero, the breakdown voltage between them is extremely low, and the device cannot be used. The first diffusion region where the normally-off type device region located is provided with the substrate lead-out region and the source lead-out region. The impurity concentration of the substrate lead-out region and the source lead-out region is relatively high, and the width of the space between them is greater than or equal to zero. The second diffusion region where the normally-off type device region located is provided with the third diffusion regions, so as to adjust the concentration of the second diffusion region, and improve the performance of the device.
  • Although the invention is illustrated and described herein with reference to specific embodiments, the invention is not intended to be limited to the details shown. Rather, various modifications may be made in the details within the scope and range of equivalents of the claims and without departing from the invention.

Claims (10)

What is claimed is:
1. A semiconductor device, comprising:
a substrate;
a buried layer formed on the substrate;
a diffusion layer formed on the buried layer, wherein the diffusion layer comprises a first diffusion region and a second diffusion region, and an impurity type of the second diffusion region is opposite to an impurity type of the first diffusion region;
the diffusion layer further comprises a plurality of third diffusion regions formed in the second diffusion region, wherein an impurity type of the third diffusion region is opposite to the impurity type of the second diffusion region; and
a gate formed on the diffusion layer.
2. The semiconductor device of claim 1, wherein the plurality of third diffusion regions are arranged regularly spaced from each other.
3. The semiconductor device of claim 2, wherein a side length of the third diffusion region is less than or equal to a width of a width of a space between two adjacent third diffusion regions.
4. The semiconductor device of claim 1, wherein the impurity type of the third diffusion region is opposite to an impurity type of the gate.
5. The semiconductor device of claim 1, wherein the buried layer comprises a first buried layer region and a second buried layer region, an impurity type of the first buried layer region is opposite to an impurity type of the second buried layer region, the impurity type of the first buried layer region is the same as the impurity type of the first diffusion region.
6. The semiconductor device of claim 5, further comprising:
a normally-on type type device region and a normally-off type device region, wherein the normally-on type device region and the normally-off type device region each has a first buried layer region and share a second buried layer region, and the normally-on type device region and the normally-off type device region each has a first diffusion region and share a second diffusion region; and
a shared drain lead-out region formed at a common boundary of the normally-on type device region and the normally-off type device region in the second diffusion region, wherein the shared drain lead-out region serves as a common drain lead-out region of the normally-on type device region and the normally-off type device region, and an impurity type of the shared drain lead-out region is the same as the impurity type of the second diffusion region.
7. The semiconductor device of claim 6, wherein a substrate lead-out region is formed in the first diffusion region of the normally-on type device region, and a source lead-out region is formed in the second diffusion region of the normally-on type device region; an impurity type of the source lead-out region is opposite to an impurity type of the substrate lead-out region, a width of a space between the source lead-out region and the substrate lead-out region is greater than zero.
8. The semiconductor device of claim 6, wherein a source lead-out region and a substrate lead-out region are formed in the first diffusion region of the normally-off type device region, and a width of a space between the source lead-out region and the substrate lead-out region is greater than or equal to zero.
9. The semiconductor device of claim 1, wherein the semiconductor device is a lateral diffusion metal oxide semiconductor device.
10. A method of manufacturing a semiconductor device, comprising:
providing a substrate, and forming a buried layer on the substrate;
forming a diffusion layer having a first diffusion region and a second diffusion region on the buried layer, wherein an impurity type of the second diffusion region is opposite to an impurity type of the first diffusion region;
forming a plurality of third diffusion regions in the second diffusion region, wherein an impurity type of the third diffusion region is opposite to the impurity type of the second diffusion region; and
forming a gate, a drain lead-out region, and a source lead-out region of the semiconductor device on the second diffusion region.
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10347619B2 (en) 2015-10-28 2019-07-09 Csmc Technologies Fab2 Co., Ltd. Semiconductor device having electrostatic discharge protection structure with a trench under a connecting portion of a diode
US10505036B2 (en) 2015-11-30 2019-12-10 Csmc Technologies Fab2 Co., Ltd. Lateral diffused metal oxide semiconductor field effect transistor
US10521546B2 (en) 2015-09-02 2019-12-31 Csmc Technologies Fab2 Co., Ltd. Optical proximity correction method and system
US10815122B2 (en) 2016-06-03 2020-10-27 Csmc Technologies Fab2 Co., Ltd. MEMS microphone and preparation method thereof
US11171223B2 (en) * 2017-12-28 2021-11-09 Csmc Technologies Fab2 Co., Ltd. Method for manufacturing semiconductor device and integrated semiconductor device
US11257720B2 (en) 2017-12-28 2022-02-22 Csmc Technologies Fab2 Co., Ltd. Manufacturing method for semiconductor device and integrated semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5451799A (en) * 1992-12-28 1995-09-19 Matsushita Electric Industrial Co., Ltd. MOS transistor for protection against electrostatic discharge
US20060223257A1 (en) * 2002-08-14 2006-10-05 Advanced Analogic Technologies, Inc. Method Of Fabricating Isolated Semiconductor Devices In Epi-Less Substrate
US20100032731A1 (en) * 2008-07-14 2010-02-11 Babcock Jeffrey A Schottky junction-field-effect-transistor (jfet) structures and methods of forming jfet structures
US20100301413A1 (en) * 2009-05-29 2010-12-02 Silergy Technology Fabrication of lateral double-diffused metal oxide semiconductor (LDMOS) devices
US20110241083A1 (en) * 2010-03-30 2011-10-06 Freescale Semiconductor, Inc. Semiconductor device and method
US20130168766A1 (en) * 2011-12-30 2013-07-04 Dongbu Hitek Co., Ltd. Drain extended mos transistor and method for fabricating the same
US9190479B1 (en) * 2008-05-07 2015-11-17 Globalfoundries U.S. 2 Llc Transistor structure having an electrical contact structure with multiple metal interconnect levels staggering one another

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61133656A (en) 1984-12-03 1986-06-20 Hitachi Ltd Semiconductor device and manufacture thereof
KR100867574B1 (en) * 2002-05-09 2008-11-10 페어차일드코리아반도체 주식회사 Power device and method for manufacturing the same
CN101359664B (en) * 2007-07-31 2011-10-05 上海贝岭股份有限公司 N type LDMOS device in BCD process, layout making and manufacturing method
KR100930150B1 (en) * 2007-09-07 2009-12-07 주식회사 동부하이텍 Semiconductor device and manufacturing method thereof
US8088656B2 (en) * 2009-08-14 2012-01-03 International Business Machines Corporation Fabricating ESD devices using MOSFET and LDMOS
CN104332494B (en) 2013-07-22 2018-09-21 无锡华润上华科技有限公司 A kind of igbt and its manufacturing method
CN104347401B (en) 2013-07-29 2017-05-10 无锡华润上华半导体有限公司 Manufacturing method of insulated gate bipolar transistor
CN104425245B (en) 2013-08-23 2017-11-07 无锡华润上华科技有限公司 Reverse-conducting insulated gate bipolar transistor npn npn manufacture method
CN104425259B (en) 2013-09-02 2017-09-15 无锡华润上华半导体有限公司 Reverse-conducting insulated gate bipolar transistor npn npn manufacture method
CN104760925B (en) 2014-01-07 2016-05-25 无锡华润上华半导体有限公司 A kind of preparation method of film support beam

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5451799A (en) * 1992-12-28 1995-09-19 Matsushita Electric Industrial Co., Ltd. MOS transistor for protection against electrostatic discharge
US20060223257A1 (en) * 2002-08-14 2006-10-05 Advanced Analogic Technologies, Inc. Method Of Fabricating Isolated Semiconductor Devices In Epi-Less Substrate
US9190479B1 (en) * 2008-05-07 2015-11-17 Globalfoundries U.S. 2 Llc Transistor structure having an electrical contact structure with multiple metal interconnect levels staggering one another
US20100032731A1 (en) * 2008-07-14 2010-02-11 Babcock Jeffrey A Schottky junction-field-effect-transistor (jfet) structures and methods of forming jfet structures
US20100301413A1 (en) * 2009-05-29 2010-12-02 Silergy Technology Fabrication of lateral double-diffused metal oxide semiconductor (LDMOS) devices
US20110241083A1 (en) * 2010-03-30 2011-10-06 Freescale Semiconductor, Inc. Semiconductor device and method
US20130168766A1 (en) * 2011-12-30 2013-07-04 Dongbu Hitek Co., Ltd. Drain extended mos transistor and method for fabricating the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Zheng, The Analysis of Double Doping Polysilicon Gate Lightly-Doped-Drain (LDD) MOSFET, ICIMA 2010 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10521546B2 (en) 2015-09-02 2019-12-31 Csmc Technologies Fab2 Co., Ltd. Optical proximity correction method and system
US10347619B2 (en) 2015-10-28 2019-07-09 Csmc Technologies Fab2 Co., Ltd. Semiconductor device having electrostatic discharge protection structure with a trench under a connecting portion of a diode
US10505036B2 (en) 2015-11-30 2019-12-10 Csmc Technologies Fab2 Co., Ltd. Lateral diffused metal oxide semiconductor field effect transistor
US10815122B2 (en) 2016-06-03 2020-10-27 Csmc Technologies Fab2 Co., Ltd. MEMS microphone and preparation method thereof
US11171223B2 (en) * 2017-12-28 2021-11-09 Csmc Technologies Fab2 Co., Ltd. Method for manufacturing semiconductor device and integrated semiconductor device
US11257720B2 (en) 2017-12-28 2022-02-22 Csmc Technologies Fab2 Co., Ltd. Manufacturing method for semiconductor device and integrated semiconductor device

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