US20160172432A1 - Integrated circuits with capacitors and methods of producing the same - Google Patents
Integrated circuits with capacitors and methods of producing the same Download PDFInfo
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- US20160172432A1 US20160172432A1 US14/699,083 US201514699083A US2016172432A1 US 20160172432 A1 US20160172432 A1 US 20160172432A1 US 201514699083 A US201514699083 A US 201514699083A US 2016172432 A1 US2016172432 A1 US 2016172432A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5225—Shielding layers formed together with wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the technical field generally relates to integrated circuits with capacitors and methods of producing the same, and more particularly relates to integrated circuits with metal/insulator/metal capacitors and methods of producing the same.
- Capacitors are used in many integrated circuits for storing data, such as for dynamic random access memory. Capacitors are also used for many analog to digital or digital to analog conversions, as well as many other purposes.
- Metal/insulator/metal (MIM) capacitors are desirable because they are stable over a range of applied voltages and temperatures. MIM capacitors have metallic base and top plates separated by an insulator. A nearby metallic shield can reduce “noise” and interference from nearby electronic components, and the metallic shield becomes more important as the size of semiconductors becomes smaller with closer packing of the electronic components.
- Transistors or other electronic components are also used in many integrated circuits, and the transistors, capacitors, and other electronic components are interconnected in various ways for desired purposes.
- Vertical contacts are typically formed through insulating layers, and horizontal interconnects are formed within an insulating layer to electrically connect different components.
- Contacts, interconnects, and capacitors use conductive materials, and the same material can be used for each these components. More efficient manufacturing methods for the production of electronic components can reduce costs and improve manufacturing rates.
- a method for producing an integrated circuit includes forming a capacitor trench through a dielectric layer, and forming a base layer overlying the dielectric layer and within the capacitor trench.
- a base layer via gap is formed in the base layer, where the base layer via gap is positioned overlying the dielectric layer and the first contact.
- a base plate and a shield are formed from the base layer, where the base plate is within the capacitor trench.
- a capacitor insulating layer is formed overlying the base plate, the base layer, and within the base layer via gap, and a via is formed through the base layer via gap.
- a second contact and a top plate are simultaneously formed, where the second contact is formed in the via and the top plate is formed in the capacitor trench.
- a method for producing an integrated circuit is provided in another embodiment.
- a capacitor trench is formed through a dielectric layer, and a base layer is formed overlying the dielectric layer within the capacitor trench.
- the base layer is removed at a base plate gap within the capacitor trench to form a base plate and a shield from the base layer, where the base plate gap is defined between the base plate and the shield.
- the shield is electrically isolated from the base plate, extends horizontally from the base plate and bends at a shield bend point.
- a capacitor insulating layer is formed overlying the base plate and the base layer, and a top plate is formed overlying the base plate such that the capacitor insulating layer is positioned between the top plate and the base plate.
- the integrated circuit includes a base plate of a capacitor, and a capacitor insulating layer overlying the base plate.
- a top plate of the capacitor overlies the capacitor insulating layer, where the top plate has a top plate upper surface.
- a shield insulated from the base plate extends horizontally from the base plate, bends upward at a shield bend point, and is planar with the top plate upper surface.
- FIGS. 1-13 illustrate, in cross sectional views, a portion of an integrated circuit and methods for its fabrication in accordance with exemplary embodiments.
- an integrated circuit has a dielectric layer formed over a transistor and a first contact, both formed within an interlayer dielectric.
- a capacitor trench is formed in the dielectric layer such that the capacitor trench is not directly overlying the transistor.
- a capacitor base plate is formed within the capacitor trench simultaneously with a base layer via gap overlying a first contact.
- An organic or inorganic planarization layer is formed overlying the base plate and the transistor, where the planarization layer provides a smooth surface for accurate lithography.
- a via is formed properly aligned with the base layer via gap and the first contact, where the smooth surface or the planarization layer facilitates accurate alignment of the via.
- the planarization layer is removed, and a second contact is formed in the via simultaneously with a capacitor top plate overlying the base plate.
- an integrated circuit 10 includes an electronic component 12 overlying and optionally within a substrate 14 .
- substrate will be used to encompass semiconductor materials conventionally used in the semiconductor industry from which to make electrical devices.
- Semiconductor materials include monocrystalline silicon materials, such as the relatively pure or lightly impurity-doped monocrystalline silicon materials typically used in the semiconductor industry, as well as polycrystalline silicon materials, and silicon admixed with other elements such as germanium, carbon, and the like.
- Semiconductor material also includes other materials such as relatively pure and impurity-doped germanium, gallium arsenide, zinc oxide, glass, and the like.
- the semiconductor material is a monocrystalline silicon substrate 14 .
- the silicon substrate 14 may be a bulk silicon wafer (as illustrated) or may be a thin layer of silicon on an insulating layer (commonly known as silicon-on-insulator or SOI) that, in turn, is supported by a carrier wafer.
- SOI silicon-on-insulator
- the electronic component 12 is a transistor, as illustrated, but in alternate embodiments the electronic component 12 can be a wide variety of other electronic components, such as resistors, capacitors, interconnects, etc.
- An interlayer dielectric 16 overlies the substrate 14 and the electronic component 12 , and a first contact 18 extends through the interlayer dielectric 16 and is electrically connected to the electronic component 12 .
- the term “overlying” means “over” such that an intervening layer may lie between the interlayer dielectric 16 and the substrate 14 , and “on” such the interlayer dielectric 14 physically contacts the substrate 14 .
- the first contact 18 may be electrically connected to a source, drain, and/or gate of a transistor (as illustrated), or to different electronic components 12 .
- the plurality of first contacts 18 may make an electrical connection with one or more different electronic components 12 .
- the interlayer dielectric 16 is an insulating material, such as, for example, silicon dioxide, silicon nitride, or the like, and the first contact 18 is an electrically conductive material, such as copper, tungsten, or the like.
- a etch stop layer 20 is formed overlying the interlayer dielectric 16 and the first contact 18 .
- the etch stop layer 20 may be silicon nitride, but other materials can also be used.
- a etch stop layer with the general formula SiC x N y H z is useful in preventing copper migration, such as is common during annealing.
- a layer of SiC x N y H z can be deposited at about 1-10 Torr of pressure, and a temp of 100-400 degrees centigrade (° C.) using 2,2,5,5,-tetramethyl-2,5-disila-1-azacyclopentane as a precursor.
- the precursor is a cyclic molecule containing 1 N atom, 2 Si atoms and 2 C atoms in a 5 member ring. Other materials can also be used in the etch stop layer 20 .
- a dielectric layer 22 is formed overlying the etch stop layer 20 . As such, the dielectric layer 22 also overlies the interlayer dielectric 16 , the substrate 14 , and other components underlying the etch stop layer 20 .
- the dielectric layer 22 is silicon dioxide in an exemplary embodiment, but other electrically insulating materials can also be used.
- silicon dioxide for the dielectric layer 22 is deposited using octamethylcyclotetrasiloxane (OMCTS) as a precursor. Silicon dioxide can be deposited using OMCTS with silane with a plasma provided at about 50 watts (W) to about 3000 W of radio frequency (RF) power at a frequency of about 13.56 MHz and/or 350 KHz.
- OMCTS octamethylcyclotetrasiloxane
- the dielectric layer 22 is deposited by plasma enhanced chemical vapor deposition using dichlorosilane, silane, or tetraethyl orthosilicate (TEOS) as precursors, or other known lower dielectric constant (K) silicon dioxide deposition techniques.
- oxygen containing gas such as oxygen gas or nitrous oxide
- TEOS tetraethyl orthosilicate
- a first mask layer 24 is optionally formed overlying the dielectric layer 22 .
- the first mask layer 24 is silicon dioxide formed using ozone and TEOS as precursors in a chemical vapor deposition at less than atmospheric pressure, but other materials or other methods of forming silicon dioxide can also be used.
- the first mask layer 24 and the dielectric layer 22 are both electrically insulating materials in many embodiments.
- a capacitor trench 30 is formed through the first mask layer 24 , if present, and through the dielectric layer 22 to the etch stop layer 20 .
- a layer of photoresist (not illustrated) may be formed and patterned to expose the first mask layer 24 for the capacitor trench 30 .
- the capacitor trench 30 is formed using an etchant selective to the material of the insulating layer, and the first mask layer 24 if present.
- the capacitor trench 30 is formed with a reactive ion etch using carbon tetrafluoride, or a combination of the reactive ion etch with a wet etch using hydrofluoric acid, but many other etchants and etch techniques can be used in alternate embodiments.
- the capacitor trench 30 may stop on top of the etch stop layer 20 , or it may extend into the etch stop layer 20 for some distance (as illustrated in FIG. 1 ), or it may penetrate the etch stop layer 20 in various embodiments.
- the etch stop layer 20 may function as an etch stop during the formation of the capacitor trench 30 .
- the capacitor trench 30 is formed overlying the substrate 14 and the interlayer dielectric 16 , and the capacitor trench 30 is offset from the first contact 18 such that capacitor trench 30 is not directly over the first contact 18 .
- the capacitor trench 30 may overlie one or more electronic components (not illustrated) in some embodiments.
- An alternate embodiment is illustrated in FIG. 2 , where the capacitor trench 30 extends through the etch stop layer 20 and overlies a first contact 18 such that at least a portion of the first contact 18 is exposed in the capacitor trench 30 . This embodiment is described in more detail below.
- a base layer 32 is formed overlying the dielectric layer 22 and the first mask layer 24 (if present), and within the capacitor trench 30 .
- the base layer 32 is formed from an electrically conductive material, and may be metallic in some embodiments.
- the base layer 32 is titanium nitride, but other materials can also be used. Titanium nitride can be formed by chemical vapor deposition using tetramethylamidotitanium and nitrogen trifluoride at a pressure of about 0.1 to about 10 torr and a temperature of about 500° C., but other deposition process are also possible.
- the base layer 32 is conformally deposited in some embodiments.
- FIG. 4 illustrates the formation of a base plate 34 and a shield 36 from the base layer 32 while simultaneously forming a base layer via gap 38 .
- selected portions of the base layer 32 are protected lithographically, and the base layer 32 is removed at desired locations.
- the base layer 32 may be removed to form the base layer via gap 38 overlying the dielectric layer 22 , and to form a base plate gap 35 defined between the base plate 34 and the shield 36 .
- Selected portions of the base layer 32 may be removed with a reactive ion etch.
- the base plate 34 is positioned within the capacitor trench 30 and along the bottom of the capacitor trench 30 , so the shield 36 extends along the side walls of the capacitor trench 30 .
- the shield 36 may extend horizontally from the base plate 34 along the bottom of the capacitor trench 30 for a short distance in some embodiments, and the shield 36 may bend upwards at a shield bend point 37 to extend along the capacitor trench 30 side walls.
- the base layer via gap 38 may be a plurality of base layer via gaps 38 , where the base layer via gap 38 is positioned overlying a first contact 18 such that the base layer via gap 38 is aligned directly over the first contact 18 .
- An interconnect gap 40 may optionally be formed in the base layer 32 simultaneously with the base layer via gap 38 , the base plate 34 , and the shield 36 .
- the interconnect gap 40 is positioned at a desired location for an interconnect, as described more fully below.
- the interconnect gap 40 may or may not be positioned over a first contact 18 , and the interconnect gap 40 may extend such that it passes over a first contact 18 at some locations and does not pass over a first contact 18 at other locations (not illustrated).
- a capacitor insulating layer 42 is formed overlying the base layer 32 , the base plate 34 , the shield 36 , and within the base layer via gap 38 , the base plate gap 35 , and the interconnect gap 40 , as illustrated in FIG. 5 .
- the capacitor insulating layer 42 may be conformally formed from silicon dioxide, which may be deposited using TEOS, as described above. Other insulating materials can be used for the capacitor insulating layer 42 in alternate embodiments.
- the capacitor insulating layer 42 is formed with a desired thickness and a dielectric constant to provide the desired capacitor performance, as described more fully below.
- the capacitor insulating layer 42 may have a thickness of from about 5 nanometers to about 50 nanometers in various embodiments.
- a planarization layer 44 is formed overlying the capacitor insulating layer 42 .
- the planarization layer 44 forms a relatively smooth top surface.
- the planarization layer 44 is a polymer, and may be a photoresist such as DUV photoresist or I-line photoresist, which can be deposited by spin coating.
- the planarization layer 44 may be an inorganic material, as understood by those skilled in the art.
- a second mask layer 46 is formed overlying the planarization layer 44 , and a hard mask 48 is formed overlying the second mask layer 46 .
- the second mask layer 46 is silicon dioxide that may be formed by plasma-enhanced chemical vapor deposition using silane and nitrous oxide at a temperature of from about 300° C. to about 400° C.
- the hard mask 48 may be formed from titanium nitride, which can be deposited as described above.
- the second mask layer 46 and the hard mask 48 have smooth upper surfaces because they are formed overlying the planarization layer 44 .
- a via 50 is formed through the hard mask 48 , where the via 50 overlies the first contact 18 , so the via 50 is formed directly over the base layer via gap 38 and the first contact 18 .
- the via 50 is started by lithographically isolating the area of the hard mask 48 at the location of the via 50 , and then removing the hard mask 48 from that area, such as with a reactive ion etch. Lithography is more accurate and precise when performed on a flat surface as opposed to a surface that rises and falls.
- the planarization layer 44 provides a smooth, flat upper surface for the hard mask 48 , which improves the lithographic accuracy, as mentioned above.
- the planarization layer 44 and the overlying areas may not be perfectly flat over the base plate 34 , but the surface is smoother and flatter than if the planarization layer 44 had not been used.
- the hard mask 48 is maintained and remains in place overlying the interconnect gap 40 when the via 50 is formed through the hard mask 48 .
- the second mask layer 46 protects the planarization layer 44 during the etch through the hard mask 48 that initiates the via 50 .
- the via 50 can be extended through the second mask layer 46 after forming the via 50 through the hard mask 48 , so the hard mask 48 protects other areas while the via 50 is extended.
- a wet etch with hydrofluoric acid is used to remove the second mask layer 46 and to extend the via 50 , but other etchants or etching techniques can also be used.
- the via 50 is extended through the planarization layer 44 , the capacitor insulating layer 42 , through the base layer via gap 38 in the base layer 32 , the first mask layer 24 , and the dielectric layer 22 , until the via 50 terminates at the etch stop layer 20 , as illustrated in an exemplary embodiment in FIG. 8 .
- the base layer via gap 38 is the space previously formed in the base layer 32 and over the first mask layer 24 , which was later filled with the capacitor insulating layer 42 , so the via 50 passes through the previously formed space in the base layer 32 .
- the via 50 can be extended with one or more anisotropic etches, where the hard mask 48 is resistant to the anisotropic etch such that the hard mask 48 remains in place.
- the via 50 is extended with a reactive ion etch using carbon tetrafluoride, but other etchants are used in other embodiments.
- the via 50 may be extended using a plurality of etches, where the etchant and the etching technique are selected for the layer or layers being etched.
- reactive ion etches are used, and the hard mask 48 illustrated in FIG. 7 may also be removed at this time by the reactive ion etches.
- the hard mask 48 was removed, as described above.
- the planarization layer 44 is then removed from over the capacitor insulating layer 42 , but the planarization layer 44 remains within the bottom portion of the capacitor trench 30 .
- the planarization layer 44 forms a thicker layer within the capacitor trench 30 , and a blanket reactive ion etch can be used to remove a consistent thickness of material from all areas.
- the blanket reactive ion etch can be timed to leave a portion of the planarization layer 44 within the capacitor trench 30 while removing the thinner portions of the planarization layer 44 outside of the capacitor trench 30 .
- An interconnect trench 52 is formed after the planarization layer 44 is removed, where the interconnect trench 52 extends through the interconnect gap 40 in the base layer 32 .
- the interconnect trench 52 extends into the dielectric layer 22 , but does not penetrate the dielectric layer 22 to reach the etch stop layer 20 , so a portion of the dielectric layer 22 separates the interconnect trench 52 from the etch stop layer 20 .
- the interconnect trench 52 is formed after the planarization layer 44 is removed, such as by a reactive ion etch.
- the interconnect trench 52 is formed through the interconnect gap 40 , and etch stop layer 20 at the bottom of the via 50 may be about 90 percent removed during this etch step.
- the capacitor insulating layer 42 is removed where it is not covered by the remaining planarization layer 44 (which is outside of the bottom of the capacitor trench 30 ) as the interconnect trench 52 is formed.
- the via 50 is further extended through the etch stop layer 20 such that a top portion of the first contact 18 is exposed through the via 50 .
- the via 50 can be extended through the etch stop layer 20 with an etch selective to the etch stop layer 20 , such as a reactive ion etch using trifluoromethane.
- An etchant that preferentially etches the etch stop layer 20 over the base layer 32 is used, so the base layer 32 protects other components during the etching process.
- the planarization layer 44 that remained at the bottom of the capacitor trench 30 is removed by the etch that extends the via 50 through the etch stop layer 20 , but the capacitor insulating layer 42 remains at the bottom of the capacitor trench 30 .
- a second contact 60 , an interconnect 62 , and a top plate 64 are simultaneously formed, as illustrated in an exemplary embodiment in FIG. 11 with continuing reference to FIG. 10 .
- the second contact 60 is formed in the via 50
- the interconnect 62 is formed in the interconnect trench 52
- the top plate 64 is formed in the capacitor trench 30 overlying the capacitor insulating layer 42 and the base plate 34 .
- the second contact 60 , interconnect 62 , and top plate 64 are formed of a conductive material, and in an exemplary embodiment that conductive material is metallic.
- the second contact 60 , interconnect 62 , and top plate 64 may include copper, but other metals or other conductive materials are used in alternate embodiments.
- One technique for forming the second contact 60 , interconnect 62 , and top plate 64 from copper includes the damascene or dual damascene process.
- a barrier metal and seed layer 66 is formed overlying the exposed surfaces, and then a core 68 is formed overlying the barrier metal and seed layer 66 .
- the barrier metal and seed layer 66 may improve adhesion of the core 68 to dielectric materials and thereby improve reliability.
- the barrier metal and seed layer 66 may be formed of copper and manganese deposited by physical vapor deposition using copper amidinate and manganese amidinate. In alternate embodiments, the barrier metal and seed layer 66 may be formed from titanium, titanium nitride, or other materials.
- the core 68 may then be deposited, such as by electroplating.
- the core 68 may be about 90 mass percent or more copper in some embodiments, and various copper alloys can be used, some of which include less than 90 mass percent copper.
- the second contact 60 forms an electric connection with the first contact 18 .
- the overburden and excess material is removed, such as by chemical mechanical planarization, as illustrated in an exemplary embodiment in FIG. 12 with continuing reference to FIG. 10 .
- the capacitor insulating layer 42 , the base layer 32 , and the first mask layer 24 are removed in the areas outside of the capacitor trench 30 , and overburden is removed in the area overlying the capacitor trench 30 .
- the top plate 64 is planarized to a desired thickness
- a top plate upper surface 72 is planar with an upper surface of the dielectric layer 22 , the second contact 60 , and the interconnect 62 .
- the planarization removes excess material from the shield 36 , so the shield 36 is planar with the top plate upper surface 72 .
- the top plate 64 and the base plate 34 are separated by the capacitor insulating layer 42 , and this structure forms a capacitor 70 .
- the size of the top plate 64 and the base plate 34 as well as the thickness and dielectric constant of the capacitor insulating layer 42 partially determine the electrical performance characteristics of the capacitor 70 , and these properties are determined during the manufacturing process.
- the shield 36 forms a barrier to reduce electrical and magnetic noise that would otherwise reach the capacitor 70 , so the shield 36 is electrically isolated or insulated from the base plate 34 and the capacitor 70 by the capacitor insulating layer 42 .
- the shield 36 extends horizontally from the base plate 34 and bends upwards at a shield bend point 37 , as mentioned above.
- the interconnect 62 may be electrically isolated within the dielectric layer 22 to avoid unwanted electrical shorts.
- the second contact 60 is electrically connected to the first contact 18 , and these components can be incorporated into an integrated circuit 10 using techniques and methods known to those skilled in the art.
- the simultaneous formation of the second contact 60 , the interconnect 62 , and the top plate 64 of the capacitor 70 reduces the number of manufacturing steps over process that form these components separately.
- the capacitor trench 30 may have been formed to expose a portion of a first contact 18 , as described above. Proceeding as described above from the embodiment illustrated in FIG. 2 produces the embodiment illustrated in FIG. 13 , so the base layer 32 is formed in electrical contact with the first contact 18 .
- the base plate gap 35 is formed overlying the dielectric layer 22 such that the shield 36 is electrically connected with the first contact 18 and the base plate 34 is electrically isolated from the first contact 18 .
- the first contact 18 can be used to provide a desired potential or a ground to the shield 36 to better protect the capacitor 70 from unwanted electrical or magnetic noise.
Abstract
Description
- This Application claims the benefit of priority to U.S. Provisional Application Ser. No. 62/090,132, which was filed on Dec. 10, 2014, the contents of which are incorporated herein by reference in their entirety.
- The technical field generally relates to integrated circuits with capacitors and methods of producing the same, and more particularly relates to integrated circuits with metal/insulator/metal capacitors and methods of producing the same.
- The semiconductor industry is continuously moving toward the fabrication of smaller and more complex microelectronic components with higher performance. Capacitors are used in many integrated circuits for storing data, such as for dynamic random access memory. Capacitors are also used for many analog to digital or digital to analog conversions, as well as many other purposes. Metal/insulator/metal (MIM) capacitors are desirable because they are stable over a range of applied voltages and temperatures. MIM capacitors have metallic base and top plates separated by an insulator. A nearby metallic shield can reduce “noise” and interference from nearby electronic components, and the metallic shield becomes more important as the size of semiconductors becomes smaller with closer packing of the electronic components.
- Transistors or other electronic components are also used in many integrated circuits, and the transistors, capacitors, and other electronic components are interconnected in various ways for desired purposes. Vertical contacts are typically formed through insulating layers, and horizontal interconnects are formed within an insulating layer to electrically connect different components. Contacts, interconnects, and capacitors use conductive materials, and the same material can be used for each these components. More efficient manufacturing methods for the production of electronic components can reduce costs and improve manufacturing rates.
- Accordingly, it is desirable to provide integrated circuits and methods of producing integrated circuits with contacts, interconnects, and capacitors that are simultaneously formed to reduce manufacturing costs and improve manufacturing efficiencies. In addition, it is desirable to provide integrated circuits and methods of producing integrated circuits that simultaneously produce contacts, interconnects, and capacitors with metallic shields that isolate the capacitors and thereby reduce noise during circuit operations. Furthermore, other desirable features and characteristics of the present embodiment will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.
- Integrated circuits and methods for producing the same are provided. In an exemplary embodiment, a method for producing an integrated circuit includes forming a capacitor trench through a dielectric layer, and forming a base layer overlying the dielectric layer and within the capacitor trench. A base layer via gap is formed in the base layer, where the base layer via gap is positioned overlying the dielectric layer and the first contact. A base plate and a shield are formed from the base layer, where the base plate is within the capacitor trench. A capacitor insulating layer is formed overlying the base plate, the base layer, and within the base layer via gap, and a via is formed through the base layer via gap. A second contact and a top plate are simultaneously formed, where the second contact is formed in the via and the top plate is formed in the capacitor trench.
- A method for producing an integrated circuit is provided in another embodiment. A capacitor trench is formed through a dielectric layer, and a base layer is formed overlying the dielectric layer within the capacitor trench. The base layer is removed at a base plate gap within the capacitor trench to form a base plate and a shield from the base layer, where the base plate gap is defined between the base plate and the shield. The shield is electrically isolated from the base plate, extends horizontally from the base plate and bends at a shield bend point. A capacitor insulating layer is formed overlying the base plate and the base layer, and a top plate is formed overlying the base plate such that the capacitor insulating layer is positioned between the top plate and the base plate.
- An integrated circuit is provided in yet another embodiment. The integrated circuit includes a base plate of a capacitor, and a capacitor insulating layer overlying the base plate. A top plate of the capacitor overlies the capacitor insulating layer, where the top plate has a top plate upper surface. A shield insulated from the base plate extends horizontally from the base plate, bends upward at a shield bend point, and is planar with the top plate upper surface.
- The present embodiments will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and wherein:
-
FIGS. 1-13 illustrate, in cross sectional views, a portion of an integrated circuit and methods for its fabrication in accordance with exemplary embodiments. - The following detailed description is merely exemplary in nature and is not intended to limit the various embodiments or the application and uses thereof. Furthermore, there is no intention to be bound by any theory presented in the preceding background or the following detailed description.
- In accordance with various exemplary embodiments described herein, an integrated circuit has a dielectric layer formed over a transistor and a first contact, both formed within an interlayer dielectric. A capacitor trench is formed in the dielectric layer such that the capacitor trench is not directly overlying the transistor. A capacitor base plate is formed within the capacitor trench simultaneously with a base layer via gap overlying a first contact. An organic or inorganic planarization layer is formed overlying the base plate and the transistor, where the planarization layer provides a smooth surface for accurate lithography. A via is formed properly aligned with the base layer via gap and the first contact, where the smooth surface or the planarization layer facilitates accurate alignment of the via. The planarization layer is removed, and a second contact is formed in the via simultaneously with a capacitor top plate overlying the base plate.
- Referring to the exemplary embodiment illustrated in
FIG. 1 , anintegrated circuit 10 includes anelectronic component 12 overlying and optionally within asubstrate 14. As used herein, the term “substrate” will be used to encompass semiconductor materials conventionally used in the semiconductor industry from which to make electrical devices. Semiconductor materials include monocrystalline silicon materials, such as the relatively pure or lightly impurity-doped monocrystalline silicon materials typically used in the semiconductor industry, as well as polycrystalline silicon materials, and silicon admixed with other elements such as germanium, carbon, and the like. Semiconductor material also includes other materials such as relatively pure and impurity-doped germanium, gallium arsenide, zinc oxide, glass, and the like. In an exemplary embodiment, the semiconductor material is amonocrystalline silicon substrate 14. Thesilicon substrate 14 may be a bulk silicon wafer (as illustrated) or may be a thin layer of silicon on an insulating layer (commonly known as silicon-on-insulator or SOI) that, in turn, is supported by a carrier wafer. - In an exemplary embodiment, the
electronic component 12 is a transistor, as illustrated, but in alternate embodiments theelectronic component 12 can be a wide variety of other electronic components, such as resistors, capacitors, interconnects, etc. An interlayer dielectric 16 overlies thesubstrate 14 and theelectronic component 12, and afirst contact 18 extends through the interlayer dielectric 16 and is electrically connected to theelectronic component 12. As used herein, the term “overlying” means “over” such that an intervening layer may lie between the interlayer dielectric 16 and thesubstrate 14, and “on” such the interlayer dielectric 14 physically contacts thesubstrate 14. Thefirst contact 18 may be electrically connected to a source, drain, and/or gate of a transistor (as illustrated), or to differentelectronic components 12. In some embodiments, there are a plurality offirst contacts 18, and the plurality offirst contacts 18 may make an electrical connection with one or more differentelectronic components 12. The interlayer dielectric 16 is an insulating material, such as, for example, silicon dioxide, silicon nitride, or the like, and thefirst contact 18 is an electrically conductive material, such as copper, tungsten, or the like. - A
etch stop layer 20 is formed overlying the interlayer dielectric 16 and thefirst contact 18. Theetch stop layer 20 may be silicon nitride, but other materials can also be used. For example, a etch stop layer with the general formula SiCxNyHz is useful in preventing copper migration, such as is common during annealing. A layer of SiCxNyHz can be deposited at about 1-10 Torr of pressure, and a temp of 100-400 degrees centigrade (° C.) using 2,2,5,5,-tetramethyl-2,5-disila-1-azacyclopentane as a precursor. The precursor is a cyclic molecule containing 1 N atom, 2 Si atoms and 2 C atoms in a 5 member ring. Other materials can also be used in theetch stop layer 20. - A
dielectric layer 22 is formed overlying theetch stop layer 20. As such, thedielectric layer 22 also overlies theinterlayer dielectric 16, thesubstrate 14, and other components underlying theetch stop layer 20. Thedielectric layer 22 is silicon dioxide in an exemplary embodiment, but other electrically insulating materials can also be used. In an exemplary embodiment, silicon dioxide for thedielectric layer 22 is deposited using octamethylcyclotetrasiloxane (OMCTS) as a precursor. Silicon dioxide can be deposited using OMCTS with silane with a plasma provided at about 50 watts (W) to about 3000 W of radio frequency (RF) power at a frequency of about 13.56 MHz and/or 350 KHz. This exposure is followed with an oxygen purge using an oxygen containing gas, such as oxygen gas or nitrous oxide, and a plasma provided at about 50 W to about 3000 W for about 0.1 seconds to about 600 seconds. The OMCTS and purge steps can be repeated until thedielectric layer 22 is at the desired thickness, such as about 50 nanometers to about 500 nanometers. In alternate embodiments, thedielectric layer 22 may be deposited by plasma enhanced chemical vapor deposition using dichlorosilane, silane, or tetraethyl orthosilicate (TEOS) as precursors, or other known lower dielectric constant (K) silicon dioxide deposition techniques. - A
first mask layer 24 is optionally formed overlying thedielectric layer 22. In an exemplary embodiment, thefirst mask layer 24 is silicon dioxide formed using ozone and TEOS as precursors in a chemical vapor deposition at less than atmospheric pressure, but other materials or other methods of forming silicon dioxide can also be used. Thefirst mask layer 24 and thedielectric layer 22 are both electrically insulating materials in many embodiments. - A
capacitor trench 30 is formed through thefirst mask layer 24, if present, and through thedielectric layer 22 to theetch stop layer 20. A layer of photoresist (not illustrated) may be formed and patterned to expose thefirst mask layer 24 for thecapacitor trench 30. Thecapacitor trench 30 is formed using an etchant selective to the material of the insulating layer, and thefirst mask layer 24 if present. In an exemplary embodiment with a silicondioxide dielectric layer 22, thecapacitor trench 30 is formed with a reactive ion etch using carbon tetrafluoride, or a combination of the reactive ion etch with a wet etch using hydrofluoric acid, but many other etchants and etch techniques can be used in alternate embodiments. Thecapacitor trench 30 may stop on top of theetch stop layer 20, or it may extend into theetch stop layer 20 for some distance (as illustrated inFIG. 1 ), or it may penetrate theetch stop layer 20 in various embodiments. Theetch stop layer 20 may function as an etch stop during the formation of thecapacitor trench 30. Thecapacitor trench 30 is formed overlying thesubstrate 14 and theinterlayer dielectric 16, and thecapacitor trench 30 is offset from thefirst contact 18 such thatcapacitor trench 30 is not directly over thefirst contact 18. Thecapacitor trench 30 may overlie one or more electronic components (not illustrated) in some embodiments. An alternate embodiment is illustrated inFIG. 2 , where thecapacitor trench 30 extends through theetch stop layer 20 and overlies afirst contact 18 such that at least a portion of thefirst contact 18 is exposed in thecapacitor trench 30. This embodiment is described in more detail below. - Referring to the exemplary embodiment illustrated in
FIG. 3 , abase layer 32 is formed overlying thedielectric layer 22 and the first mask layer 24 (if present), and within thecapacitor trench 30. Thebase layer 32 is formed from an electrically conductive material, and may be metallic in some embodiments. In an exemplary embodiment, thebase layer 32 is titanium nitride, but other materials can also be used. Titanium nitride can be formed by chemical vapor deposition using tetramethylamidotitanium and nitrogen trifluoride at a pressure of about 0.1 to about 10 torr and a temperature of about 500° C., but other deposition process are also possible. Thebase layer 32 is conformally deposited in some embodiments. -
FIG. 4 illustrates the formation of abase plate 34 and ashield 36 from thebase layer 32 while simultaneously forming a base layer viagap 38. In an exemplary embodiment, selected portions of thebase layer 32 are protected lithographically, and thebase layer 32 is removed at desired locations. For example, thebase layer 32 may be removed to form the base layer viagap 38 overlying thedielectric layer 22, and to form abase plate gap 35 defined between thebase plate 34 and theshield 36. Selected portions of thebase layer 32 may be removed with a reactive ion etch. Thebase plate 34 is positioned within thecapacitor trench 30 and along the bottom of thecapacitor trench 30, so theshield 36 extends along the side walls of thecapacitor trench 30. Theshield 36 may extend horizontally from thebase plate 34 along the bottom of thecapacitor trench 30 for a short distance in some embodiments, and theshield 36 may bend upwards at ashield bend point 37 to extend along thecapacitor trench 30 side walls. The base layer viagap 38 may be a plurality of base layer viagaps 38, where the base layer viagap 38 is positioned overlying afirst contact 18 such that the base layer viagap 38 is aligned directly over thefirst contact 18. Aninterconnect gap 40 may optionally be formed in thebase layer 32 simultaneously with the base layer viagap 38, thebase plate 34, and theshield 36. Theinterconnect gap 40 is positioned at a desired location for an interconnect, as described more fully below. Theinterconnect gap 40 may or may not be positioned over afirst contact 18, and theinterconnect gap 40 may extend such that it passes over afirst contact 18 at some locations and does not pass over afirst contact 18 at other locations (not illustrated). - A
capacitor insulating layer 42 is formed overlying thebase layer 32, thebase plate 34, theshield 36, and within the base layer viagap 38, thebase plate gap 35, and theinterconnect gap 40, as illustrated inFIG. 5 . Thecapacitor insulating layer 42 may be conformally formed from silicon dioxide, which may be deposited using TEOS, as described above. Other insulating materials can be used for thecapacitor insulating layer 42 in alternate embodiments. Thecapacitor insulating layer 42 is formed with a desired thickness and a dielectric constant to provide the desired capacitor performance, as described more fully below. For example, thecapacitor insulating layer 42 may have a thickness of from about 5 nanometers to about 50 nanometers in various embodiments. - Referring to
FIG. 6 , aplanarization layer 44 is formed overlying thecapacitor insulating layer 42. Theplanarization layer 44 forms a relatively smooth top surface. In an exemplary embodiment, theplanarization layer 44 is a polymer, and may be a photoresist such as DUV photoresist or I-line photoresist, which can be deposited by spin coating. In alternate embodiments, theplanarization layer 44 may be an inorganic material, as understood by those skilled in the art. Asecond mask layer 46 is formed overlying theplanarization layer 44, and ahard mask 48 is formed overlying thesecond mask layer 46. In an exemplary embodiment, thesecond mask layer 46 is silicon dioxide that may be formed by plasma-enhanced chemical vapor deposition using silane and nitrous oxide at a temperature of from about 300° C. to about 400° C. Thehard mask 48 may be formed from titanium nitride, which can be deposited as described above. Thesecond mask layer 46 and thehard mask 48 have smooth upper surfaces because they are formed overlying theplanarization layer 44. - Reference is made to the exemplary embodiment illustrated in
FIG. 7 . A via 50 is formed through thehard mask 48, where the via 50 overlies thefirst contact 18, so the via 50 is formed directly over the base layer viagap 38 and thefirst contact 18. The via 50 is started by lithographically isolating the area of thehard mask 48 at the location of the via 50, and then removing thehard mask 48 from that area, such as with a reactive ion etch. Lithography is more accurate and precise when performed on a flat surface as opposed to a surface that rises and falls. Theplanarization layer 44 provides a smooth, flat upper surface for thehard mask 48, which improves the lithographic accuracy, as mentioned above. Theplanarization layer 44 and the overlying areas may not be perfectly flat over thebase plate 34, but the surface is smoother and flatter than if theplanarization layer 44 had not been used. Thehard mask 48 is maintained and remains in place overlying theinterconnect gap 40 when the via 50 is formed through thehard mask 48. Thesecond mask layer 46 protects theplanarization layer 44 during the etch through thehard mask 48 that initiates the via 50. The via 50 can be extended through thesecond mask layer 46 after forming the via 50 through thehard mask 48, so thehard mask 48 protects other areas while the via 50 is extended. In an exemplary embodiment, a wet etch with hydrofluoric acid is used to remove thesecond mask layer 46 and to extend the via 50, but other etchants or etching techniques can also be used. - The via 50 is extended through the
planarization layer 44, thecapacitor insulating layer 42, through the base layer viagap 38 in thebase layer 32, thefirst mask layer 24, and thedielectric layer 22, until the via 50 terminates at theetch stop layer 20, as illustrated in an exemplary embodiment inFIG. 8 . The base layer viagap 38 is the space previously formed in thebase layer 32 and over thefirst mask layer 24, which was later filled with thecapacitor insulating layer 42, so the via 50 passes through the previously formed space in thebase layer 32. The via 50 can be extended with one or more anisotropic etches, where thehard mask 48 is resistant to the anisotropic etch such that thehard mask 48 remains in place. In an exemplary embodiment, the via 50 is extended with a reactive ion etch using carbon tetrafluoride, but other etchants are used in other embodiments. In some embodiments, the via 50 may be extended using a plurality of etches, where the etchant and the etching technique are selected for the layer or layers being etched. In an exemplary embodiment, reactive ion etches are used, and thehard mask 48 illustrated inFIG. 7 may also be removed at this time by the reactive ion etches. - Reference is made to the exemplary embodiment illustrated in
FIG. 9 . Thehard mask 48 was removed, as described above. Theplanarization layer 44 is then removed from over thecapacitor insulating layer 42, but theplanarization layer 44 remains within the bottom portion of thecapacitor trench 30. Theplanarization layer 44 forms a thicker layer within thecapacitor trench 30, and a blanket reactive ion etch can be used to remove a consistent thickness of material from all areas. The blanket reactive ion etch can be timed to leave a portion of theplanarization layer 44 within thecapacitor trench 30 while removing the thinner portions of theplanarization layer 44 outside of thecapacitor trench 30. Aninterconnect trench 52 is formed after theplanarization layer 44 is removed, where theinterconnect trench 52 extends through theinterconnect gap 40 in thebase layer 32. Theinterconnect trench 52 extends into thedielectric layer 22, but does not penetrate thedielectric layer 22 to reach theetch stop layer 20, so a portion of thedielectric layer 22 separates theinterconnect trench 52 from theetch stop layer 20. Theinterconnect trench 52 is formed after theplanarization layer 44 is removed, such as by a reactive ion etch. Theinterconnect trench 52 is formed through theinterconnect gap 40, and etchstop layer 20 at the bottom of the via 50 may be about 90 percent removed during this etch step. Thecapacitor insulating layer 42 is removed where it is not covered by the remaining planarization layer 44 (which is outside of the bottom of the capacitor trench 30) as theinterconnect trench 52 is formed. - Referring to the exemplary embodiment illustrated in
FIG. 10 , the via 50 is further extended through theetch stop layer 20 such that a top portion of thefirst contact 18 is exposed through the via 50. The via 50 can be extended through theetch stop layer 20 with an etch selective to theetch stop layer 20, such as a reactive ion etch using trifluoromethane. An etchant that preferentially etches theetch stop layer 20 over thebase layer 32 is used, so thebase layer 32 protects other components during the etching process. Theplanarization layer 44 that remained at the bottom of thecapacitor trench 30 is removed by the etch that extends the via 50 through theetch stop layer 20, but thecapacitor insulating layer 42 remains at the bottom of thecapacitor trench 30. - A
second contact 60, aninterconnect 62, and atop plate 64 are simultaneously formed, as illustrated in an exemplary embodiment inFIG. 11 with continuing reference toFIG. 10 . Thesecond contact 60 is formed in the via 50, theinterconnect 62 is formed in theinterconnect trench 52, and thetop plate 64 is formed in thecapacitor trench 30 overlying thecapacitor insulating layer 42 and thebase plate 34. Thesecond contact 60,interconnect 62, andtop plate 64 are formed of a conductive material, and in an exemplary embodiment that conductive material is metallic. For example, thesecond contact 60,interconnect 62, andtop plate 64 may include copper, but other metals or other conductive materials are used in alternate embodiments. One technique for forming thesecond contact 60,interconnect 62, andtop plate 64 from copper includes the damascene or dual damascene process. In an exemplary embodiment, a barrier metal andseed layer 66 is formed overlying the exposed surfaces, and then acore 68 is formed overlying the barrier metal andseed layer 66. The barrier metal andseed layer 66 may improve adhesion of the core 68 to dielectric materials and thereby improve reliability. The barrier metal andseed layer 66 may be formed of copper and manganese deposited by physical vapor deposition using copper amidinate and manganese amidinate. In alternate embodiments, the barrier metal andseed layer 66 may be formed from titanium, titanium nitride, or other materials. The core 68 may then be deposited, such as by electroplating. The core 68 may be about 90 mass percent or more copper in some embodiments, and various copper alloys can be used, some of which include less than 90 mass percent copper. Thesecond contact 60 forms an electric connection with thefirst contact 18. - The overburden and excess material is removed, such as by chemical mechanical planarization, as illustrated in an exemplary embodiment in
FIG. 12 with continuing reference toFIG. 10 . In an exemplary embodiment, thecapacitor insulating layer 42, thebase layer 32, and thefirst mask layer 24 are removed in the areas outside of thecapacitor trench 30, and overburden is removed in the area overlying thecapacitor trench 30. As such, thetop plate 64 is planarized to a desired thickness, and a top plateupper surface 72 is planar with an upper surface of thedielectric layer 22, thesecond contact 60, and theinterconnect 62. The planarization removes excess material from theshield 36, so theshield 36 is planar with the top plateupper surface 72. Thetop plate 64 and thebase plate 34 are separated by thecapacitor insulating layer 42, and this structure forms acapacitor 70. The size of thetop plate 64 and thebase plate 34 as well as the thickness and dielectric constant of thecapacitor insulating layer 42 partially determine the electrical performance characteristics of thecapacitor 70, and these properties are determined during the manufacturing process. Theshield 36 forms a barrier to reduce electrical and magnetic noise that would otherwise reach thecapacitor 70, so theshield 36 is electrically isolated or insulated from thebase plate 34 and thecapacitor 70 by thecapacitor insulating layer 42. In some embodiments, theshield 36 extends horizontally from thebase plate 34 and bends upwards at ashield bend point 37, as mentioned above. Theinterconnect 62 may be electrically isolated within thedielectric layer 22 to avoid unwanted electrical shorts. Thesecond contact 60 is electrically connected to thefirst contact 18, and these components can be incorporated into anintegrated circuit 10 using techniques and methods known to those skilled in the art. The simultaneous formation of thesecond contact 60, theinterconnect 62, and thetop plate 64 of thecapacitor 70 reduces the number of manufacturing steps over process that form these components separately. - Referring to an exemplary embodiment in
FIG. 13 , and referring again toFIG. 2 , thecapacitor trench 30 may have been formed to expose a portion of afirst contact 18, as described above. Proceeding as described above from the embodiment illustrated inFIG. 2 produces the embodiment illustrated inFIG. 13 , so thebase layer 32 is formed in electrical contact with thefirst contact 18. Thebase plate gap 35 is formed overlying thedielectric layer 22 such that theshield 36 is electrically connected with thefirst contact 18 and thebase plate 34 is electrically isolated from thefirst contact 18. In this embodiment, thefirst contact 18 can be used to provide a desired potential or a ground to theshield 36 to better protect thecapacitor 70 from unwanted electrical or magnetic noise. - While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the application in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing one or more embodiments, it being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope, as set forth in the appended claims.
Claims (20)
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CN106952895B (en) * | 2017-02-22 | 2019-05-10 | 新昌县诺趣智能科技有限公司 | A kind of manufacturing method of MIM capacitor structure |
DE102019130124A1 (en) * | 2018-11-30 | 2020-06-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | FUNCTIONAL COMPONENT WITHIN A CONNECTING STRUCTURE OF A SEMICONDUCTOR DEVICE AND METHOD FOR MAKING SAME |
US11600519B2 (en) * | 2019-09-16 | 2023-03-07 | International Business Machines Corporation | Skip-via proximity interconnect |
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US5576240A (en) | 1994-12-09 | 1996-11-19 | Lucent Technologies Inc. | Method for making a metal to metal capacitor |
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US6025226A (en) | 1998-01-15 | 2000-02-15 | International Business Machines Corporation | Method of forming a capacitor and a capacitor formed using the method |
KR100305680B1 (en) | 1999-08-26 | 2001-11-01 | 윤종용 | method for fabricating capacitor of semiconductor integrated circuit |
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