US20160071843A1 - Semiconductor Device and Method of Fabricating the Same - Google Patents
Semiconductor Device and Method of Fabricating the Same Download PDFInfo
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- US20160071843A1 US20160071843A1 US14/943,595 US201514943595A US2016071843A1 US 20160071843 A1 US20160071843 A1 US 20160071843A1 US 201514943595 A US201514943595 A US 201514943595A US 2016071843 A1 US2016071843 A1 US 2016071843A1
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
Definitions
- the present invention relates to a semiconductor device and a method of fabricating the same.
- a dynamic random access memory (DRAM) device largely has a memory cell region configured to store and retain data and a peripheral circuit region configured to input and output data between the memory cell region and the outside of a device. Also, a sense amplifier circuit and a word line driver circuit are disposed in a region (or a connection portion) of the peripheral circuit region, which is disposed adjacent to the memory cell region.
- a sense amplifier circuit and a word line driver circuit are disposed in a region (or a connection portion) of the peripheral circuit region, which is disposed adjacent to the memory cell region.
- a semiconductor device may include, but is not limited to, the following elements.
- First and second diffusion regions are formed in a semiconductor substrate.
- An element isolation portion separates the first and second diffusion regions each other.
- a first insulating film is formed over the element isolation portion and the first and second diffusion regions.
- First and second contact plugs are formed over the first and second diffusion regions, respectively. The first and second contact plugs penetrate the first insulating film.
- a first conductive layer is formed over the first insulating film.
- a second insulating film is formed over the first conductive layer.
- a third contact plug penetrates the second insulating film.
- the third contact plug is connected to the first contact plug.
- a second conductive layer is formed over the second insulating film.
- the second conductive layer contacts the third contact plug.
- the first and second conductive layers partly overlap the element isolation portion.
- a semiconductor device may include, but is not limited to the following elements.
- a first transistor is formed in a memory cell region.
- Second and third transistors are formed in a peripheral circuit region.
- a first insulating film is formed over the first, second and third transistors.
- a first conductive layer contacts the first insulating film.
- the first conductive layer is electrically connected with the second transistor.
- a second insulating film is formed over the first conductive layer.
- a capacitance pad is on and in contact with the second insulating film.
- the capacitance pad is electrically connected to the first transistor.
- a second conductive layer is on and in contact with the second insulating film.
- the second conductive layer is electrically connected with the third transistor.
- a semiconductor device may include, but is not limited to, the following elements.
- a first transistor includes first and second diffusion regions in a memory cell region. Second and third transistors formed in a peripheral circuit region.
- the second transistor includes a third diffusion region.
- the third transistor includes a fourth diffusion region.
- a first contact plug is formed over the first diffusion region.
- a second contact plug is formed over the first contact plug.
- a bit line is connected to the first diffusion region of the first transistor via the first and second contact plugs.
- a third contact plug is formed over the third diffusion region.
- a first conductive layer is connected to the third diffusion region via the third contact plug.
- a fourth contact plug is formed over the second diffusion region.
- a fifth contact plug is formed over the fourth contact plug.
- a capacitor pad is connected to a second diffusion region of the first transistor via the fourth and fifth contact plugs.
- a sixth contact plug is formed over the fourth diffusion region.
- a seventh contact plug is formed over the sixth contact plug.
- a second conductive layer is connected to a fourth diffusion region via the sixth and seventh contact plugs.
- An eighth contact plug is formed over the second conductive layer.
- a third conductive layer is connected to the second conductive layer via the eighth contact plug.
- a method for forming a semiconductor device may include, but is not limited to the following processes.
- An element isolation portion is formed in a semiconductor substrate.
- First and second impurity regions are formed in the semiconductor substrate.
- the element isolation portion separates the first and second impurity regions.
- a first conductive layer connected to the first impurity region is formed to partially overlap the element isolation portion.
- a first insulating film is formed over the first conductive layer.
- a second conductive layer is formed over the first insulating film and the second impurity region to partially overlap the element isolation portion. The second conductive layer is connected to the second impurity region.
- a method for forming a semiconductor device may include, but is not limited to the following processes. First and second impurity regions are formed in a semiconductor substrate in a memory cell region while third and fourth impurity regions are formed in the semiconductor substrate in a peripheral circuit region. First and second contact plugs are formed over the first and second impurity regions, respectively while third and fourth contact plugs are formed over the third and fourth impurity regions, respectively. A first conductive layer is formed over the third contact plug while a bit wiring connecting the first contact plug is formed. The first conductive layer is connected to the third contact plug. An insulating film is formed over the bit wiring and the first conductive layer. A capacitance pad connecting the second contact plug is formed while a second conductive layer is formed over the insulating film, the second conductive layer being electrically connected to the fourth contact plug.
- FIG. 1A is a fragmentary cross sectional elevation view, taken along a D-D′ line of FIG. 10 , illustrating a memory cell in accordance with one embodiment of the present invention
- FIG. 1B is a fragmentary cross sectional elevation view, taken along a B-B′ line of FIG. 11 , illustrating a memory cell in accordance with one embodiment of the present invention
- FIG. 1C is a fragmentary cross sectional elevation view illustrating a memory cell in accordance with one embodiment of the present invention.
- FIG. 1D is a fragmentary cross sectional elevation view illustrating a memory cell in accordance with one embodiment of the present invention.
- FIG. 2A is a fragmentary cross sectional elevation view, taken along a D-D′ line of FIG. 10 , illustrating a memory in a step involved in a method of forming the semiconductor device of FIGS. 1A and 1B ;
- FIG. 2B is a fragmentary cross sectional elevation view, taken along a B-B′ line of FIG. 11 , illustrating a memory in a step involved in a method of forming the semiconductor device of FIGS. 1A and 1B ;
- FIG. 3A is a fragmentary cross sectional elevation view, taken along a D-D′ line of FIG. 10 , illustrating a memory in a step involved in a method of forming the semiconductor device of FIGS. 1A and 1B ;
- FIG. 3B is a fragmentary cross sectional elevation view, taken along a B-B′ line of FIG. 11 , illustrating a memory in a step involved in a method of forming the semiconductor device of FIGS. 1A and 1B ;
- FIG. 4A is a fragmentary cross sectional elevation view, taken along a D-D′ line of FIG. 10 , illustrating a memory in a step involved in a method of forming the semiconductor device of FIGS. 1A and 1B ;
- FIG. 4B is a fragmentary cross sectional elevation view, taken along a B-B′ line of FIG. 11 , illustrating a memory in a step involved in a method of forming the semiconductor device of FIGS. 1A and 1B ;
- FIG. 5A is a fragmentary cross sectional elevation view, taken along a D-D′ line of FIG. 10 , illustrating a memory in a step involved in a method of forming the semiconductor device of FIGS. 1A and 1B ;
- FIG. 5B is a fragmentary cross sectional elevation view, taken along a B-B′ line of FIG. 11 , illustrating a memory in a step involved in a method of forming the semiconductor device of FIGS. 1A and 1B ;
- FIG. 6A is a fragmentary cross sectional elevation view, taken along a D-D′ line of FIG. 10 , illustrating a memory in a step involved in a method of forming the semiconductor device of FIGS. 1A and 1B ;
- FIG. 6B is a fragmentary cross sectional elevation view, taken along a B-B′ line of FIG. 11 , illustrating a memory in a step involved in a method of forming the semiconductor device of FIGS. 1A and 1B ;
- FIG. 7A is a fragmentary cross sectional elevation view, taken along a D-D′ line of FIG. 10 , illustrating a memory in a step involved in a method of forming the semiconductor device of FIGS. 1A and 1B ;
- FIG. 7B is a fragmentary cross sectional elevation view, taken along a B-B′ line of FIG. 11 , illustrating a memory in a step involved in a method of forming the semiconductor device of FIGS. 1A and 1B ;
- FIG. 8A is a fragmentary cross sectional elevation view, taken along a D-D′ line of FIG. 10 , illustrating a memory in a step involved in a method of forming the semiconductor device of FIGS. 1A and 1B ;
- FIG. 8B is a fragmentary cross sectional elevation view, taken along a B-B′ line of FIG. 11 , illustrating a memory in a step involved in a method of forming the semiconductor device of FIGS. 1A and 1B ;
- FIG. 9A is a fragmentary cross sectional elevation view, taken along a D-D′ line of FIG. 10 , illustrating a memory in a step involved in a method of forming the semiconductor device of FIGS. 1A and 1B ;
- FIG. 9B is a fragmentary cross sectional elevation view, taken along a B-B′ line of FIG. 11 , illustrating a memory in a step involved in a method of forming the semiconductor device of FIGS. 1A and 1B ;
- FIG. 10 a fragmentary plan view integrally illustrating a memory cell including a semiconductor device in accordance with one embodiment of the present invention
- FIG. 11 a fragmentary plan view integrally illustrating a memory cell including a semiconductor device in accordance with one embodiment of the present invention
- FIG. 12 is a fragmentary cross sectional elevation view, taken along a B-B′ line of FIG. 11 , illustrating a memory in a step involved in a method of forming the semiconductor device of FIGS. 1A and 1B ;
- FIG. 13 a fragmentary plan view integrally illustrating a memory cell including a semiconductor device in accordance with another embodiment of the present invention.
- FIG. 14A is a fragmentary cross sectional elevation view illustrating a memory cell including a semiconductor device in accordance with a related art of the present invention.
- FIG. 14B is a fragmentary cross sectional elevation view illustrating a memory cell including a semiconductor device in accordance with a related art of the present invention.
- FIG. 15 is a fragmentary cross sectional elevation view illustrating a memory cell including a semiconductor device in accordance with a related art of the present invention.
- the electrode of the capacitor When the electrode of the capacitor is formed in a 3-dimensional structure, it becomes necessary to prepare an interlayer insulating layer with a very great thickness corresponding to the height of the capacitor. Also, in a peripheral circuit region, it is necessary to prepare a contact plug having a great enough height as to penetrate the thick interlayer insulating layer to connect a MOS transistor disposed on the surface of a semiconductor substrate with a metal interconnection layer disposed thereon.
- the metal interconnection layer is connected to the MOS transistor prepared on the surface of the semiconductor substrate using only one contact plug, it may be difficult to perform a processing operation because the contact plug has an excessively large aspect ratio. For this reason, an intermediate interconnection layer or pad may be prepared between the metal interconnection layer and the MOS transistor. It may be necessary to connect the metal interconnection layer and the MOS transistor by interposing a plurality of contact plugs in series therebetween.
- a bit line pad used as a memory cell or a lower electrode, which also refer to as an accumulation electrode, of a capacitor is employed as an intermediate interconnection layer of a peripheral circuit region (for example, refer to JP-A-11-214660, JP-A-2002-319632, and JP-A-2005-260254) because an obstacle is caused in an interconnection layout when a metal interconnection layer is only provided in an upper layer.
- bit lines used in a memory cell region and intermediate interconnection layers used in the peripheral circuit region it is easy to simultaneously process bit lines used in a memory cell region and intermediate interconnection layers used in the peripheral circuit region.
- a plurality of MOS transistors is disposed to connect interactive source and drain regions (or diffusion layers) and gate electrodes.
- the intermediate interconnection layers should be disposed at a higher density than in the memory cell region.
- interconnection layers cannot be disposed adjacent to one another at a line-width and interval below the design rule determined by the resolution of a photolithography technique used for the processing of the bit lines. Accordingly, when a pitch at which cells are disposed is reduced by downscaling memory cells, disposing the plurality of MOS transistors and the intermediate interconnection layers at the reduced pitch may become difficult, thus hindering the miniaturization of devices.
- a semiconductor device may include, but is not limited to, the following elements.
- First and second diffusion regions are formed in a semiconductor substrate.
- An element isolation portion separates the first and second diffusion regions each other.
- a first insulating film is formed over the element isolation portion and the first and second diffusion regions.
- First and second contact plugs are formed over the first and second diffusion regions, respectively. The first and second contact plugs penetrate the first insulating film.
- a first conductive layer is formed over the first insulating film.
- a second insulating film is formed over the first conductive layer.
- a third contact plug penetrates the second insulating film.
- the third contact plug is connected to the first contact plug.
- a second conductive layer is formed over the second insulating film.
- the second conductive layer contacts the third contact plug.
- the first and second conductive layers partly overlap the element isolation portion.
- the semiconductor device may include, but is not limited to, the first and second contact plugs connected to the first and second diffusion regions, respectively.
- the semiconductor device may further include, but is not limited to, a fourth contact plug.
- the second conductive layer is connected to the second diffusion region through fourth contact plug.
- the fourth contact plug comprises a material same as a material included in the third contact plug.
- the semiconductor device may further include, but is not limited to, the following elements.
- a third insulating film is formed over the second conductive layer.
- a fifth contact plug penetrates the third insulating film.
- the fifth contact plug is connected to the second conductive layer.
- a third conductive layer is formed over the third insulating film. The third conductive layer contacts the fifth contact plug.
- the semiconductor device may include, but is not limited to, the first diffusion region of a first transistor and the second diffusion region of a second transistor.
- a semiconductor device may include, but is not limited to the following elements.
- a first transistor is formed in a memory cell region.
- Second and third transistors are formed in a peripheral circuit region.
- a first insulating film is formed over the first, second and third transistors.
- a first conductive layer contacts the first insulating film.
- the first conductive layer is electrically connected with the second transistor.
- a second insulating film is formed over the first conductive layer.
- a capacitance pad is on and in contact with the second insulating film.
- the capacitance pad is electrically connected to the first transistor.
- a second conductive layer is on and in contact with the second insulating film.
- the second conductive layer is electrically connected with the third transistor.
- the semiconductor device may include, but is not limited to, the second transistor adjacent to the third transistor.
- the semiconductor device may further include, but is not limited to, an element isolation portion between the second transistor and the third transistor.
- the semiconductor device may include, but is not limited to, the first conductive layer whose width is greater than (5/3) ⁇ R 1 .
- R 1 is a width of the element isolation portion.
- the semiconductor device may include, but is not limited to, the first and second conductive films partially overlapping the element isolation portion.
- the semiconductor device may include, but is not limited to, the element isolation portion is the same in width as the first and second contact plugs.
- the semiconductor device may further include, but is not limited to, first and second contact plugs electrically connected to the first and second conductive layers, respectively.
- the first and second contact plugs are electrically connected to the first and second transistors, respectively.
- a semiconductor device may include, but is not limited to, the following elements.
- a first transistor includes first and second diffusion regions in a memory cell region. Second and third transistors formed in a peripheral circuit region.
- the second transistor includes a third diffusion region.
- the third transistor includes a fourth diffusion region.
- a first contact plug is formed over the first diffusion region.
- a second contact plug is formed over the first contact plug.
- a bit line is connected to the first diffusion region of the first transistor via the first and second contact plugs.
- a third contact plug is formed over the third diffusion region.
- a first conductive layer is connected to the third diffusion region via the third contact plug.
- a fourth contact plug is formed over the second diffusion region.
- a fifth contact plug is formed over the fourth contact plug.
- a capacitor pad is connected to a second diffusion region of the first transistor via the fourth and fifth contact plugs.
- a sixth contact plug is formed over the fourth diffusion region.
- a seventh contact plug is formed over the sixth contact plug.
- a second conductive layer is connected to a fourth diffusion region via the sixth and seventh contact plugs.
- An eighth contact plug is formed over the second conductive layer.
- a third conductive layer is connected to the second conductive layer via the eighth contact plug.
- the semiconductor device may further include, but is not limited to, an element isolation portion contacting the third and fourth diffusion regions.
- the semiconductor device may further include, but is not limited to, a first insulating film over the element isolation portion.
- the element isolation portion is substantially aligned to the first insulating film.
- the semiconductor device may include, but is not limited to, the first and second conductive layers partly overlapping the element isolation portion.
- the semiconductor device may include, but is not limited to, a distance between the third and fourth diffusion regions is substantially the same as a width of the element isolation portion.
- the semiconductor device may further include, but is not limited to, the following elements.
- a first gate electrode is of the second transistor.
- a second gate electrode is of the third transistor.
- a ninth contact plug is electrically connected with the first gate electrode.
- a fourth conductive layer is formed over the ninth contact plug. The fourth conductive layer is connected to the first gate electrode via the ninth contact plug.
- a tenth contact plug is electrically connected with the second gate electrode.
- An eleventh contact plug is formed over the tenth contact plug.
- a fifth conductive layer is formed over the eleventh contact plug. The fifth conductive layer is electrically connected to the second gate electrode via the tenth and eleventh contact plugs.
- the semiconductor device may include, but is not limited to, the first conductive layer and the bit line are formed in the same level.
- the semiconductor device may include, but is not limited to, the second conductive layer and the capacitor pad are formed in the same level.
- a method for forming a semiconductor device may include, but is not limited to the following processes.
- An element isolation portion is formed in a semiconductor substrate.
- First and second impurity regions are formed in the semiconductor substrate.
- the element isolation portion separates the first and second impurity regions.
- a first conductive layer connected to the first impurity region is formed to partially overlap the element isolation portion.
- a first insulating film is formed over the first conductive layer.
- a second conductive layer is formed over the first insulating film and the second impurity region to partially overlap the element isolation portion. The second conductive layer is connected to the second impurity region.
- the method for forming the semiconductor device may further include, but is not limited to, forming first and second contact plugs connected to the first and second impurity regions, respectively before forming the first conductive layer.
- the method for forming the semiconductor device may further include, but is not limited to, forming a third contact plug connected to the second contact plug before forming the second conductive layer.
- forming the first conductive layer further include, but is not limited to, etching a surface of the second contact plug.
- a method for forming a semiconductor device may include, but is not limited to the following processes. First and second impurity regions are formed in a semiconductor substrate in a memory cell region while third and fourth impurity regions are formed in the semiconductor substrate in a peripheral circuit region. First and second contact plugs are formed over the first and second impurity regions, respectively while third and fourth contact plugs are formed over the third and fourth impurity regions, respectively. A first conductive layer is formed over the third contact plug while a bit wiring connecting the first contact plug is formed. The first conductive layer is connected to the third contact plug. An insulating film is formed over the bit wiring and the first conductive layer. A capacitance pad connecting the second contact plug is formed while a second conductive layer is formed over the insulating film, the second conductive layer being electrically connected to the fourth contact plug.
- the method for forming the semiconductor device may further include, but is not limited to, forming an element isolation portion between the third and fourth impurity regions.
- forming the first conductive layer may further include, but is not limited to, etching a surface of the fourth contact plug.
- DRAM Dynamic Random Access Memory
- the semiconductor device will be described.
- illustrations are partially enlarged and shown, and the sizes and ratios of constituent elements are not limited to being the same as the actual dimensions. Materials, sizes, and the like exemplified in the following description are just examples, and the invention is not limited thereto and may be appropriately modified within the scope which does not deviate from the embodiments.
- FIGS. 1A , 1 B, and 12 are schematic cross-sectional views of a semiconductor device A as a DRAM device including a plurality of MOS transistors according to the first embodiment of the present invention.
- FIGS. 2A through 9A and 2 B through 9 B are schematic cross-sectional views illustrating respective processes of a method of fabricating a semiconductor device according to the present embodiment.
- FIGS. 1A through 9A are each cross-sectional views taken along section indication lines D-D′ of each schematic plan view of FIGS. 10 and 11
- FIGS. 1B through 9B and 12 are each cross-sectional views taken along section indication lines B-B′ of each of the schematic plan views of FIGS. 10 and 11 .
- FIGS. 1A , 1 B, 1 C, 1 D and 10 the construction of the semiconductor device A according to the present embodiment will be chiefly described hereinafter with reference to FIGS. 1A , 1 B, 1 C, 1 D and 10 .
- the semiconductor device A includes a memory cell region 7 and a peripheral circuit region 8 provided over a semiconductor substrate 1 .
- a portion of the semiconductor substrate 1 is doped with an impurity, thereby forming a memory cell diffusion layer (a first diffusion layer) 72 .
- a portion of the semiconductor substrate 1 is doped with an impurity, thereby forming a peripheral circuit diffusion layer (a second diffusion layer) 82 .
- a first level interconnection 10 is provided in the memory cell region 7 as a bit line 10 A connected to the memory cell diffusion layer 72 .
- the first level interconnection 10 is provided in the peripheral circuit region 8 as a first intermediate interconnection layer 10 B connected to any one of the peripheral circuit diffusion layer 82 and a gate electrode 4 ( 42 ).
- a second level interconnection 20 is provided in the memory cell region 7 as a capacitance pad 20 A for a capacitor connected to the memory cell diffusion layer 72 .
- the second level interconnection 20 is provided in the peripheral circuit region 8 as a second intermediate interconnection layer 20 B connected to any one of the peripheral circuit diffusion layer 82 and a gate electrode 4 ( 42 ) via a stack structure of at least two contact plugs (refer to a second contact plug 52 c and a third contact plug 53 b of FIG. 1B and a second contact plug 52 e and a third contact plug 53 c of FIG. 1D ).
- an element isolation portion 2 is formed in the semiconductor device A according to the present embodiment so that the element isolation portion 2 isolates active regions K from each other in the semiconductor substrate 1 .
- a first metal-oxide-semiconductor (MOS) transistor 3 is provided in the memory cell region 7 .
- Second and third MOS transistors 31 and 32 are provided in the peripheral circuit region 8 .
- a gate electrode (a first gate electrode) 41 is provided over the active region K of the semiconductor substrate 1 and forms a portion of a word line W.
- First contact plugs 51 a , 51 b , and 51 c are formed over the memory cell diffusion layer that performs one of first source and drain regions 72 .
- second contact plugs 52 b and 52 c are formed over the peripheral circuit diffusion layers 82 A and 82 B in the peripheral circuit region 8 .
- second contact plugs 52 d and 52 e are formed over the gate electrode 42 in the peripheral circuit region 8 .
- a second contact plug 52 a is formed in the memory cell region 7 .
- the second contact plug 52 a is connected to the first contact plug 51 a .
- the semiconductor device A includes third contact plugs 53 a , which are connected to the first contact plugs 51 b and 51 c , respectively, in the memory cell region 7 .
- the semiconductor device A includes a third contact plug 53 b connected to the second contact plug 52 c in the peripheral circuit region 8 .
- the semiconductor device A further includes a third contact plug 53 c connected to the second contact plug 52 e in the peripheral circuit region 8 .
- the semiconductor device A includes the first level interconnection 10 including the bit line 10 A in the memory cell region 7 and the first intermediate interconnection layer 10 B in the peripheral circuit region 8 .
- the bit line 10 A is separated from the first intermediate interconnection layer 10 B.
- the bit line 10 A is connected to the memory cell diffusion layer 72 via a stack structure of the first and second contact plugs 51 a and 52 a .
- the first intermediate interconnection layer 10 B is connected via the second contact plug 52 b to the peripheral circuit diffusion layers (second and third source and drain regions) 82 .
- the first intermediate interconnection layer 10 B is connected via the second contact plug 52 d to the gate electrode (second and third gate electrodes) 42 .
- the semiconductor device A includes the second level interconnection 20 including the capacitor pad 20 A in the memory cell region 7 and the second intermediate interconnection layer 20 B in the peripheral circuit region 8 .
- the capacitor pad 20 A is separated from the second intermediate interconnection layer 20 B.
- the capacitance pad 20 A for the capacitor is connected to the memory cell diffusion layer 72 via a stack structure of the first contact plugs 51 b and 51 c and the third contact plug 53 a .
- the second intermediate interconnection layer 20 B is connected to the peripheral diffusion layer 82 via a stack structure of the second contact plug 52 b and the third contact plug 53 b .
- the second intermediate interconnection layer 20 B is connected to the gate electrode 42 via a stack structure of the second contact plug 52 e and the third contact plug 53 c.
- the semiconductor device A according to the present embodiment may include a plurality of memory cell regions 7 .
- a plurality of memory cells 71 are disposed in the memory cell region 7 according to predetermined rules.
- FIG. 10 is a fragmentary and horizontally cross-sectional view showing some elements such as word lines W and sidewall insulating layers 47 in each of the memory cells 71 .
- a capacitor 9 is not shown in FIG. 10 but shown in FIG. 1 and FIGS. 8A , 8 B, 9 A, and 9 B, which are fragmentary cross-sectional elevation views for illustrating processes of the semiconductor device A.
- each of the memory cells 71 has a MOS transistor 3 and a capacitor 9 connected to the MOS transistor 3 via a plurality of contact plugs (refer to 51 b and 53 a of FIG. 1A ). Furthermore, the first level interconnection 10 including the bit line 10 A is connected to the memory cell diffusion layers 72 corresponding to source and drain regions of the MOS transistor 3 , which are not connected to the capacitor 9 , via a plurality of contact plugs (refer to 51 b and 52 a of FIG. 1A ).
- a portion of the semiconductor substrate 1 is doped with an impurity, thereby forming the memory cell diffusion layer 72 in the memory cell region 7 and forming the peripheral circuit diffusion layer 82 in the peripheral circuit region 8 . Also, a plurality of regions where MOS transistors 3 , 31 , and 32 are provided by element isolation portion 2 which isolates active regions K from each other in the semiconductor substrate 1 .
- a P-type silicon substrate may be used as the semiconductor substrate 1 .
- the present embodiment is not limited thereto and a germanium (Ge)-containing semiconductor substrate may be used as the semiconductor substrate 1 .
- the memory cell diffusion layer 72 is an impurity diffusion region doped with N-type impurity ions, which is provided in a predetermined position on a surface 1 a of the semiconductor substrate 1 as shown in FIG. 1A .
- phosphorus (P) or arsenic (As) ions are implanted at a predetermined concentration into the memory cell diffusion layer 72 of the present embodiment.
- the peripheral circuit diffusion layers 82 are impurity diffusion regions doped with N-type impurity ions, which are provided in predetermined positions on the surface 1 a of the semiconductor substrate 1 as shown in FIG. 1B .
- N-type impurity ions such as P or As ions, may be implanted at a predetermined concentration into the peripheral circuit diffusion layer 82 A of the present embodiment.
- a plurality of elongated strip-shaped active regions K are prepared in the surface of the semiconductor substrate 1 at predetermined intervals.
- Each elongated strip-shaped active region K extends in a direction inclined to a direction along which the word lines W extend.
- the active regions K are defined by the element isolation portions 2 surrounding the outer circumferences of the active regions K.
- FIG. 10 shows a memory-cell layout known as 6F2
- the layout of the active regions K according to the present embodiment is not limited thereto.
- another layout of active regions applied to typical memory cells e.g., a layout known as 8F2 may be selected and applied.
- Diffusion regions are formed in both end portions and a central portion of each of the active regions K. In the diffusion regions, N-type impurities are introduced.
- the diffusion regions may be the memory cell diffusion region 72 and the peripheral circuit diffusion layer 82 of FIGS. 1A and 1B .
- Each of the diffusion regions functions as a source or drain region of the first MOS transistor 3 as described above.
- the first contact plugs 51 are disposed directly on the diffusion regions functioning as the source and drain regions of the first MOS transistor 3 .
- the first contact plugs 51 may be first contact plugs 51 a , 51 b , and 51 c illustrated with dotted-and-broken lines in FIG. 10 .
- the gate electrodes 4 are provided on the active region K of the semiconductor substrate 1 .
- the first gate electrode 41 is provided in the memory cell region 7 and forms a portion of the word line W.
- the gate electrodes (second and third gate electrodes) 42 are provided in the peripheral circuit region 8 and intersect the active region K.
- the gate electrodes 41 and 42 may be formed of a known material used for conventional gate electrodes.
- a gate insulating layer 45 formed of a silicon oxide (SiO 2 ) layer is formed between each of the gate electrodes 41 and 42 shown in FIGS. 1A and 1B and the semiconductor substrate 1 .
- a gate mask insulating layer 46 formed of a silicon nitride (Si 3 N 4 ) layer is stacked on the surface of each of the gate electrodes 41 and 42 .
- a sidewall insulating layer 47 formed of a silicon nitride layer is formed on a side surface of each of stack structures obtained by sequentially stacking the gate insulating layer 45 , the gate electrodes 41 and 42 , and the gate mask insulating layer 46 .
- a plurality of wavy-shaped (or curved) bit lines (or first level interconnections) 10 A extend in an X direction and are spaced apart from one another at predetermined intervals in a Y direction.
- straight-line-shaped word lines W are disposed to extend in the Y direction of FIG. 10 .
- a plurality of word lines W are disposed at predetermined intervals in the X direction of FIG. 10 .
- Each of the plurality of word lines W extends across the active regions K as shown in FIG. 10 .
- Each of the plurality of word lines W has crossing points that cross over the active regions K.
- the crossing point of the word line W performs as a gate electrode 41 of the MOS transistor 3 .
- the gate electrode 41 of the MOS transistor 3 is a planar gate electrode, the gate electrode 41 may be modified to a grooved gate electrode.
- FIG. 11 shows a plan view of the second and third MOS transistors 31 and 32 disposed adjacent to each other in the peripheral circuit region 8 .
- the present embodiment describes a case where the second and third MOS transistors 31 and 32 are of the same conductivity type, that is, an N-type.
- the gate electrode 42 is disposed in the second MOS transistor 31 to intersect the active region K defined on the semiconductor substrate 1 by the element isolation portion 2 .
- the gate electrode 42 of the second MOS transistor 31 are independent in its extending direction from the word line W of the memory cell region 7 .
- an N-type impurity is introduced into a region of the active region K that is not covered with the gate electrode 42 , thereby forming peripheral circuit diffusion layers 82 A and 82 C functioning as a source or drain region.
- the gate electrode 42 extends across the active region K and peripheral circuit diffusion layers 82 B and 82 D are formed in the third MOS transistor 32 .
- the semiconductor device A includes first contact plugs 51 a , 51 b , 51 c , 51 d , and 51 e second contact plugs 52 b , 52 c , 52 d , and 52 e and third contact plugs 53 a , 53 b , and 53 c .
- an example of the semiconductor device A of FIGS. 1A , 1 B, 1 C, and 1 D further includes fourth contact plugs 54 a , 54 b , 54 c , and 54 d.
- Each of the first contact plugs 51 a , 51 b , and 51 c is provided on the memory cell diffusion layer 72 .
- the second contact plug 52 a which will be described later, is stacked over the first contact plug 51 .
- the third contact plugs 53 a which will be described later, are stacked over each of the first contact plugs 51 b and 51 c .
- each of the first contact plugs 51 b and 51 c has an upper portion that has an upper side surface contacting a first interlayer insulating film 11 .
- the remaining portion other than the upper portion of each of the first contact plugs 51 b and 51 c has a side surface that is covered by the sidewall insulating layer 47 a.
- the second contact plug 52 a is provided over the first contact plug 51 a in the memory cell region 7 .
- the first level interconnection 10 (the bit line 10 A) is disposed on the second contact plug 52 a and connected to the second contact plug 52 a .
- the second contact plugs 52 b and 52 c are provided over the peripheral circuit diffusion layers 82 ( 82 A and 82 B) of the peripheral circuit region 8 .
- the second contact plugs 52 d and 52 e are provided over the gate electrode 42 of the peripheral circuit region 8 .
- the second MOS transistor 31 includes the first intermediate interconnection layer 10 B which is disposed on the second contact plug 52 b and connected to the second contact plug 52 b .
- the third MOS transistor 32 includes the third contact plug 53 b which is stacked over the second contact plug 52 c . Also, each of the second contact plugs 52 a , 52 b , 52 c , 52 d , and 52 e has an upper portion that has an upper side surface contacting the first interlayer insulating film 11 . The remaining portion other than the upper portion of each of the second contact plugs 52 a , 52 b , 52 c , 52 d , and 52 e has a side surface that is covered by a second interlayer insulating film 12 .
- the third contact plug 53 a is formed over the first contact plugs 51 b and 51 c in the memory cell region 7 .
- a second level interconnection 20 (a capacitance pad 20 A) is disposed on the third contact plug 53 a and connected to the third contact plug 53 a .
- the third MOS transistor 32 includes the third contact plug 53 b which is disposed over the second contact plug 52 c in the peripheral circuit region 8 .
- the third MOS transistor 32 includes the third contact plug 53 c which is disposed over the second contact plug 52 e in the peripheral circuit region 8 .
- the second intermediate interconnection layer 20 B is disposed on the third contact plug 53 b and connected to the third contact plug 53 b .
- the second intermediate interconnection layer 20 B is disposed on the third contact plug 53 c and connected to the third contact plug 53 c .
- the third contact plug 53 a has an upper portion that has an upper side surface contacting a third interlayer insulating film 13 .
- the remaining portion other than the upper portion of the third contact plug 53 a has a side surface that is covered by the first interlayer insulating film 11 , the second interlayer insulating film 12 .
- the second MOS transistor 31 of the peripheral circuit region 8 includes the fourth contact plugs 54 a and 54 c provided on the first intermediate interconnection layer 10 B.
- a third level interconnection 30 is disposed on the fourth contact plugs 54 a and connected to the fourth contact plug 54 a .
- a third level interconnection 30 is disposed on the fourth contact plugs 54 c and connected to the fourth contact plug 54 c .
- the third MOS transistor 32 of the peripheral circuit region 8 includes the fourth contact plug 54 b and 54 d provided on the second intermediate interconnection layer 20 B.
- the third level interconnection 30 is disposed on the fourth contact plug 54 b and connected to the fourth contact plug 54 b as the fourth contact plug 54 a .
- the third level interconnection 30 is disposed on the fourth contact plug 54 d and connected to the fourth contact plug 54 d . Furthermore, a side surface of the fourth contact plugs 54 a and 54 c contacts the third interlayer 13 , a fourth interlayer 14 , and a fifth interlayer 15 . A side surface of the fourth contact plug 54 b and 54 d contacts the fourth and fifth interlayer insulating films 14 and 15 .
- the first through fourth contact plugs 51 , 52 , 53 , and 54 may be formed of materials including, but not limited to, the following materials.
- the first contact plug 51 may include, for example, polycrystalline silicon (poly-Si) containing impurities, such as P.
- poly-Si polycrystalline silicon
- the second contact plug 52 may be formed by sequentially stacking, for example, a titanium (Ti) layer, a titanium nitride (TiN) layer, and a tungsten (W) layer.
- the third contact plug 53 may be formed by sequentially stacking a Ti layer, a TiN layer, and a W layer.
- the third contact plug 53 may include a metal material having a high melting point or a poly-Si layer containing impurities.
- the fourth contact plug 54 may also be formed by sequentially stacking a Ti layer, a TiN layer, and a W layer.
- each of the first through fifth interlayers 11 through 15 may be formed of a silicon oxide layer.
- the first level interconnection 10 ( 10 A) is formed in the memory cell region 7 while the first level interconnection 10 ( 10 B) is formed in the peripheral circuit region 8 .
- the bit wiring 10 A is provided to be connected to memory cell diffusion layer 72 via a stack structure including the first and second contact plugs 51 a and 52 a in the memory cell region 7 .
- the first intermediate interconnection layer 10 B is provided to be connected to the peripheral circuit diffusion layer 82 via the second contact plug 52 b .
- the first intermediate interconnection layer 10 B is provided to be connected to the gate electrode 42 via the second contact plug 52 d.
- the first level interconnection 10 may be formed by sequentially stacking, for example, a tungsten nitride (tungsten nitride) layer and a W layer, the present embodiment is not limited thereto.
- the first level interconnection 10 may be formed of another metal layer having a high melting point or a metal silicide layer.
- the second level interconnection 20 is formed in the memory cell region 7 while the second level interconnection 20 ( 20 B) is formed in the peripheral circuit region 8 .
- the capacitor pad 20 A is provided to be connected to the memory cell diffusion layer 72 via a stack structure including the first and third contact plugs 51 and 53 in the memory cell region 7 .
- the second intermediate interconnection layer 20 B is provided to be connected to the peripheral circuit diffusion layer 82 42 via a stack structure including the second and third contact plugs 52 b and 53 b in the peripheral circuit region 8 .
- the second intermediate interconnection layer 20 B is provided to be connected to the gate electrode via a stack structure including the second and third contact plugs 52 e and 53 c in the peripheral circuit region 8 .
- the second level interconnection 20 may be formed using the same material and structure as the above-described first level interconnection 10 .
- the second MOS transistor 31 includes the peripheral circuit diffusion layer 82 connected to the first level interconnection 10 ( 10 B), which is an upper intermediate interconnection layer (a local interconnection layer), via the second contact plug 52 b .
- the third MOS transistor 32 includes the peripheral circuit diffusion layer 82 B connected to the second level interconnection 20 (a second intermediate interconnection layer 20 B), which is an upper intermediate interconnection layer (a local interconnection layer), via the second and third contact plugs 52 c and 53 b .
- each of the intermediate interconnection layers (the first and second level interconnections 10 and 20 ) is connected to the third level interconnection 30 disposed thereon via the fourth contact plugs 54 a and 54 b (the third level interconnection is not shown in FIG. 11 ).
- the capacitor 9 is provided over the capacitor pad 20 A, which forms a portion of the second level interconnection 20 .
- the capacitor 9 may be formed using known materials and structures used for conventional capacitors with no limitation. The material and structure of the capacitor 9 may be adopted in consideration of general characteristics of a semiconductor device.
- the capacitor 9 includes a first capacitor electrode 91 having an inside surface 91 a , a capacitance insulating layer 92 , and a second capacitor electrode 93 .
- the capacitance insulating layer is provided to cover the inside surface 91 a of the first capacitor electrode 91 .
- the second capacitor electrode 93 is provided to cover the capacitance insulating layer 92 and inside surface 91 a.
- the semiconductor device A includes the first level interconnection 10 including the bit line 10 A and the first intermediate interconnection layer 10 B which are disposed in the memory cell region 7 and the peripheral circuit region 8 , respectively.
- the bit line 10 A is disposed in the memory cell region 7 .
- the first intermediate interconnection layer 10 B is disposed in the peripheral circuit region 8 .
- the first intermediate interconnection layer 10 B is connected via the second contact plug 52 b to the peripheral circuit diffusion layer 82 of the second MOS transistor 31 .
- the first intermediate interconnection layer 10 B is connected via the second contact plug 52 d to the gate electrode 42 of the second MOS transistor 31 .
- the first level interconnection 10 forming the bit line 10 A is connected to the memory cell diffusion layer 72 of the first MOS transistor 3 via the second contact plug 52 .
- the second level interconnection 20 includes the capacitance pad 20 A and the second level interconnection layer 20 B which are disposed in the memory cell region 7 and the peripheral circuit region 8 , respectively.
- the second intermediate interconnection layer 20 B is connected to the peripheral circuit diffusion layer 82 of the third MOS transistor 32 via a stack structure of the second and third contact plugs 52 b and 53 b .
- the second intermediate interconnection layer 20 B is connected to the gate electrode 42 of the third MOS transistor 32 via a stack structure of the second and third contact plugs 52 e and 53 c.
- the above-described structure allows reducing the circuit area in the peripheral circuit region 8 in the semiconductor device A, such as a DRAM device. Shrinkage of the semiconductor device A can be obtained. Horizontal dimensions of the semiconductor device A can be reduced.
- FIGS. 2A through 9A and 2 B through 9 B and FIGS. 1A , 1 B, 10 , and 11 ).
- FIGS. 2A , 3 A, 4 A, 5 A, 6 A, 7 A, 8 A and 9 A are cross-sectional views taken along line D-D′ of the memory cell region 7 shown in the plan view of FIG. 10 .
- FIGS. 2 B, 3 B, 4 B, 5 B, 6 B, 7 B, 8 B, and 9 B are cross-sectional views taken along line B-B′ of the peripheral circuit region 8 shown in the plan view of FIG. 11 .
- the method of fabricating the semiconductor device A includes the following semiconductor-substrate forming process ( 1 ).
- the element isolation portion 2 is formed to isolate the active regions K from each other over the semiconductor substrate 1 .
- the gate electrode 4 formed over the corresponding active region K using a patterning process.
- the impurity is doped into a portion of the semiconductor substrate 1 in a self-aligned manner using the corresponding gate electrode 4 as a mask.
- the memory cell diffusion layer (first source and drain regions) 72 forming the memory cell region 7 and the peripheral circuit diffusion layer (second and third source and drain regions) 82 forming the peripheral circuit region 8 are formed.
- MOS metal-oxide-semiconductor
- an electrode-forming process ( 2 ) is performed as follows.
- a first interlayer insulating film 11 is formed by embedding an insulating layer between gate electrodes 4 ( 41 and 42 ).
- a first contact hole 11 a is formed in the first interlayer insulating film 11 to expose a top surface of the memory cell diffusion layer 72 in the memory cell region 7 .
- First contact plugs 51 a , 51 b , and 51 c are formed over the memory cell diffusion layer 72 to fill the first contact hole 11 a .
- a second interlayer insulating film 12 is formed to cover the surfaces of the first contact plugs 51 a , 51 b , and 51 c formed in the above-described order and the first interlayer insulating film 11 . Further, a second contact 12 a is formed through the second interlayer insulating film 12 to expose a surface of the first contact plug 51 a . Second contact holes 12 b are formed in the second interlayer insulating film 12 and the first interlayer insulating film 11 to expose surfaces of the peripheral circuit diffusion layers 82 A and 82 B.
- second contact plugs 52 b and 52 c are formed over the peripheral circuit diffusion layer 82 B to fill the second contact hole 12 b in the peripheral circuit region 8 .
- a second contact plug 52 a is formed over the first contact plug 51 a to fill the second contact hole 12 a in the memory cell region 7 .
- a first-interconnection forming process ( 3 ) is performed as follows.
- the first level interconnection 10 is formed as the bit line 10 A connected to the second contact plug 52 a in the memory cell region 7 by stacking a first level interconnection material to cover the second interlayer insulating film 12 and the second contact plugs 52 a , 52 b , and 52 c . Then, the first level interconnection material is patterned. Also, in the first-interconnection forming process ( 3 ), the first level interconnection 10 is formed in the memory cell region 7 while the first level interconnection 10 in the peripheral circuit region 8 is formed.
- a second-electrode forming process ( 4 ) is performed as follows.
- the third interlayer insulating film 13 is formed over the first level interconnection 10 .
- Third contact holes 13 a is formed in the third interlayer 13 and the second interlayer insulating film 12 in the memory cell region 7 to expose surfaces of the first contact plugs 51 b and 51 c .
- a third contact hole 13 b is formed in the third interlayer 13 in the peripheral circuit region 8 to expose a surface of the second contact plug 52 b .
- third contact plugs 53 a and 53 b are formed over the first contact plugs 51 b and 51 c of the memory cell region 7 , respectively.
- the second contact plugs 52 c of the peripheral circuit region 8 are formed to fill the third contact holes 13 a and 13 b , respectively, which are formed in the above-described order.
- the method of fabricating the semiconductor device A according to the present embodiment includes the following second-interconnection forming process ( 5 ).
- the capacitor pad 20 A is formed to be connected to the third contact plug 53 a in the memory cell region 7 by stacking an interconnection material to cover the third interlayer 13 and then patterning the interconnection material.
- the second level interconnection 20 is formed in the memory cell region 7 while the second level interconnection 20 in the peripheral circuit region 8 is formed.
- the method of fabricating the semiconductor device A according to the present embodiment includes the respective processes ( 1 ) through ( 5 ) in at least the above-described order. Also, in the present embodiment, an example will now be described of a method of fabricating the semiconductor device A.
- the process ( 5 ) is followed by a capacitor forming process ( 6 ) and a third-interconnection forming process ( 7 ) subsequently.
- each of the processes ( 1 ) through ( 7 ) will be described in detail.
- Each of the processes ( 1 ) through ( 7 ) may optionally be included in the method of fabricating the semiconductor device A according to the present embodiment.
- the semiconductor-substrate forming process includes the following processes.
- the element isolation portion 2 is formed over the semiconductor substrate 1 to isolate the active regions K from each other.
- the gate electrode 4 ( 41 and 42 ) is formed over the corresponding active region K using a patterning process.
- the impurity is doped into a portion of the semiconductor substrate 1 in a self-aligned manner using the gate electrode 4 as a mask.
- the memory cell diffusion layer 72 forming a memory cell region 7 and the peripheral circuit diffusion layer 82 forming a peripheral circuit region 8 are formed.
- a plurality of regions for first through third MOS transistors 3 , 31 , and 32 are prepared.
- the element isolation portion 2 is formed over the semiconductor substrate 1 to isolate the active regions K from each other using a shallow-trench-isolation (STI) technique (refer to FIG. 10 ).
- STI shallow-trench-isolation
- a P-type silicon substrate is used as the semiconductor substrate 1
- the present embodiment is not limited thereto.
- a Ge-containing semiconductor substrate may be used as the semiconductor substrate 1 .
- a gate insulating layer 45 including a silicon oxide (SiO 2 ) layer, a gate electrode 4 including a conductive layer, and a gate mask insulating layer 46 including a silicon nitride (Si 3 N 4 ) layer are sequentially formed over the active regions K.
- the stack structure is patterned, thereby forming the stacked structure having the gate insulating layer 45 , the gate electrode 4 ( 41 and 42 ), and the gate mask insulating layer 46 stacked in this order.
- the gate insulating layer 45 with a thickness of about 5 nm may be formed.
- the gate electrode 4 with a thickness of about 150 nm may be formed.
- the gate mask insulating layer 46 with a thickness of about 100 nm may be formed.
- processes of forming the gate electrodes are separately performed in the memory cell region 7 and the peripheral circuit region 8 .
- each of the peripheral circuit diffusion layers 82 ( 82 A and 82 B) functions as the source or drain region (second and third source and drain regions) of the first and second MOS transistors 31 and 32 in the peripheral circuit region 8 , respectively.
- one of the memory cell region 7 and the peripheral circuit region 8 may be covered with a mask using a photoresist layer.
- An impurity may be introduced using several ion implantation processes such that the impurity concentration of the memory cell diffusion layer 72 is different from that of the peripheral circuit diffusion layer 82 .
- a sidewall insulating layer 47 including a silicon nitride layer is formed on side surfaces of the gate electrodes 41 and 42 .
- the sidewall insulating layer 47 has a thickness of, for example, about 50 nm.
- an N-type impurity such as As ions, may be introduced into the active regions K, thereby forming LDD regions.
- the word line W extends in the X direction of FIG. 10 .
- the word line W has crossing points that cross over the active regions K.
- the crossing point of the word line W performs as the gate electrode 41 of the MOS transistor 3 in the memory cell region 7 .
- the word line W has been formed during the foregoing semiconductor-substrate forming process,
- the second and third MOS transistors 31 and 32 are disposed in parallel with the element isolation portion 2 interposed therebetween in the peripheral circuit region 8 .
- the second MOS transistor 31 has the peripheral circuit diffusion layer 82 A as second source or drain region
- the third MOS transistor 32 has the peripheral circuit diffusion layer 82 B as third source and drain regions.
- an element isolation width R 1 may be, for example, about 60 nm in the peripheral circuit area 8 .
- an insulating layer is buried between the gate electrodes 4 ( 41 and 42 ) to form the first interlayer insulating film 11 .
- the first contact hole 11 a is formed in the first interlayer insulating film 11 in the memory cell region 7 to expose a top surface of the memory cell diffusion layer 72 .
- the first contact plugs 51 a , 51 b , and 51 c are formed over the memory cell diffusion layer 72 to fill the first contact hole ha.
- the second interlayer insulating film 12 is formed to cover the surfaces of the first contact plugs 51 a , 51 b , and 51 c and the first interlayer insulating film 11 .
- the second contact hole 12 a is formed in the second interlayer insulating film 12 to expose a top surface of the first contact plug 51 a .
- the second contact hole 12 b is formed in the second interlayer insulating film 12 and the first interlayer insulating film 11 to expose a top surface of the peripheral circuit diffusion layer 82 .
- second contact plugs 52 b and 52 c are formed over the peripheral circuit diffusion layer 82 A and 82 B in the peripheral circuit region 8 to fill the second contact hole 12 b while a second contact plug 52 a is formed over the first contact plug 51 a in the memory cell region 7 to fill the second contact hole 12 a.
- an insulating layer such as a silicon oxide layer, is initially buried between the gate electrodes 41 and 42 to form the first interlayer insulating film 11 .
- the first interlayer insulating film 11 is planarized using a chemical mechanical polishing (CMP) technique.
- CMP chemical mechanical polishing
- the first interlayer insulating film 11 is formed to a height (or thickness) of, for example, about 500 nm, from a surface 1 a of the semiconductor substrate 1 .
- the first contact plugs 51 a , 51 b , and 51 c connected to the memory cell diffusion layer 72 through the first interlayer insulating film 11 are formed of, for example, poly-Si containing impurities, in the memory cell region 7 .
- positions of the first contact plugs 51 a , 51 b , and 51 c correspond to reference numerals 51 a , 51 b , and 51 c indicated by broken lines of FIG. 10 .
- a bit line 10 A (the first level interconnection 10 ) is connected to the first contact plug 51 a disposed in the center of the active region K during the first-interconnection forming process that will be described later. Also, a capacitor 9 formed by a capacitor-device forming process is connected to the first contact plugs 51 b and 51 c via a third contact plug 53 a and a capacitance pad 20 A (a second level interconnection 20 ), which will be described later.
- the first contact plugs 51 b and 51 c are disposed on both sides of the active region K.
- first contact plugs 51 a , 51 b , and 51 c may be performed by a self-alignment-contact (SAC) technique using a difference in etch rate between the gate mask insulating layers 45 a and 45 b and the sidewall insulating layers 47 a and 47 b , and the first interlayer insulating film 11 .
- SAC self-alignment-contact
- the second interlayer insulating film 12 includes a silicon oxide layer is formed to cover the surfaces of the first contact plugs 51 a , 51 b , and 51 c and the first interlayer insulating film 11 .
- the second interlayer insulating film 12 with a thickness of, for example, about 100 nm may be formed.
- the second contact hole 12 a is formed in the second interlayer insulating film 12 in the memory cell region 7 to expose a top surface of the first contact plug 51 a .
- a second contact hole 12 b is formed in the second interlayer insulating film 12 and the first interlayer insulating film 11 to expose top surfaces of the peripheral circuit diffusion layers 82 A and 82 B in the peripheral circuit region 8 .
- the second contact hole 12 a of the memory cell region 7 is formed to a small depth of about 100 nm so as not to reach the gate electrode 41 or the semiconductor substrate 1
- the second contact hole 12 b of the peripheral circuit region 8 is formed to a great depth of about 600 nm, which is different from the depth of the second contact hole 12 a of the memory cell region 7 .
- a Ti layer, a TiN layer, and a W layer are sequentially formed to fill the second contact holes 12 a and 12 b and cover the second interlayer insulating film 12 .
- the W layer, the TiN layer, and the Ti layer formed over the second interlayer insulating film 12 are removed using a CMP technique, thereby forming a second contact plug 52 a in the memory cell region 7 and forming second contact plugs 52 b and 52 c in the peripheral circuit region 8 .
- materials of the second contact plugs 52 a , 52 b , and 52 c are not limited thereto and may be formed of another metal material having a high melting point or a poly-Si layer containing impurities.
- the formation of the second contact plugs 52 a and 52 b may be performed using an etch-back technique instead of the CMP technique.
- the second contact plug connected to the peripheral circuit diffusion layer 82 A is indicated by reference numeral 52 b .
- the second contact plug connected to the peripheral circuit diffusion layer 82 B is indicated by reference numeral 52 c .
- the second contact plugs 52 b and 52 c are disposed to have a diameter and interval equal to the width R 1 of the element isolation portion 2 to minimize a contact pitch. Namely, a distance between the peripheral circuit diffusion layers 82 A and 82 B is substantially the same as a width of the second contact plugs 52 b and 52 c since the element isolation portion 2 contacts with the peripheral circuit diffusion layers 82 A and 82 B. Further, the first interlayer insulating film 11 and the second interlayer insulating film 12 between the second contact plugs 52 b and 52 c are aligned to the element isolation portion 2 .
- the second contact plugs 52 b and 52 c arranged in rows in a vertical direction in the plan view of FIG. 11 are connected to the same peripheral circuit diffusion layer.
- the first level interconnection 10 is formed as a bit line 10 A connected to the second contact plug 52 a in the memory cell region 7 .
- the first level interconnection material is stacked to cover the second interlayer insulating film 12 and the second contact plugs 52 a and 52 b and then patterning the first level interconnection material.
- the first level interconnection 10 is formed as a first intermediate interconnection layer 10 B connected to any one of the second contact plug 52 b and the gate electrode 42 in the peripheral circuit region 8 .
- the first level interconnection 10 is provided in the memory cell region 7 as the bit line 10 A and in the peripheral circuit region 8 as the first intermediate interconnection layer 10 B.
- an interconnection material is formed (refer to the first level interconnection 10 ).
- the interconnection material may be formed by sequentially depositing a WN layer and a W layer, the interconnection material is not limited thereto.
- the interconnection material may be another metal layer having a high melting point or a metal silicon layer.
- the interconnection material with a thickness of, for example, about 100 nm may be formed.
- the interconnection material is patterned using photolithography and dry etching techniques, thereby forming the first level interconnection 10 .
- the first level interconnection 10 includes the bit line 10 A connected to the surface of the second contact plug 52 a in the memory cell region 7 .
- the first level interconnection 10 includes the first intermediate interconnection layer 10 B connected to the surface of the second contact plug 52 b in the peripheral circuit region 8 .
- the patterning process is performed not to form the first level interconnection 10 (the first intermediate interconnection layer 10 B) on the second contact plug 52 c.
- the patterning of the first level interconnection 10 may be simultaneously performed using one photomask in both the memory cell region 7 and the peripheral circuit region 8 .
- the first level interconnection 10 (the bit line 10 A) formed in the memory cell region 7 functions as a bit line and has a pattern that extends in zigzag in the X direction from the plan view of FIG. 10 .
- the first level interconnection 10 (the first intermediate interconnection layer 10 B) formed in the peripheral circuit region 8 functions as an intermediate interconnection layer electrically connected to the peripheral circuit diffusion layer 82 ( 82 A).
- the first intermediate interconnection layer 10 B has a strip-shaped pattern that extends in a vertical direction from the plan view of FIG. 11 .
- the interconnection material formed on the surface of the second contact plug 52 c is removed by etching process to expose the surface of the second contact plug 52 c .
- the surface of the second contact plug 52 c is over-etched during the patterning of the first level interconnection 10 .
- the surface of the second contact plug 52 c may be recessed.
- the etching process of the first level interconnection 10 is performed by adjusting an over-etched amount such that a recessed amount is generally 200 nm or less.
- a width w 11 of the first intermediate interconnection layer 10 B ensures a one-side margin ⁇ 11 to prevent the fourth contact plug 54 b formed over the first intermediate interconnection layer 10 B from deviating from the first intermediate interconnection layer 10 B during a subsequent third-interconnection forming process.
- the first intermediate interconnection layer 10 B partly overlaps the element isolation portion 2 in plan view.
- the width w 11 is given by an equation ⁇ w 11 ⁇ R 1 +2 ⁇ 11 ⁇ .
- the margin ⁇ 11 may be determined in consideration of first, second, and third maximum values.
- the first maximum value is a maximum value of a position adjustment deviation amount between fourth contact holes 14 a and 14 b (refer to FIG. 9B ), which will be described later, and the first level interconnection 10 .
- the second maximum value is a maximum value of a dimension difference of the fourth contact holes 14 a and 14 b .
- the third maximum value is a maximum value of a dimension difference of the first level interconnections 10 .
- the margin ⁇ 11 it is experimentally preferable for the margin ⁇ 11 to have a minimum value equivalent to about 1 ⁇ 3 the width R 1 of the element isolation portion 2 . In this case, the margin ⁇ 11 is given by (5/3) ⁇ R 1 or more. The margin ⁇ 11 is given about 20 nm or more when the width R 1 is 60 nm.
- the margin ⁇ 12 is preferably set at a minimum value of 20 nm or more like the margin ⁇ 11 .
- each of the margins ⁇ 11 and ⁇ 12 may preferably be set to a minimum value equal to the width R 1 .
- the margin ⁇ 11 may be set to a minimum value of about 25 nm
- the margin ⁇ 12 may be set to a minimum value of about 35 nm.
- each of the margins ⁇ 11 and ⁇ 12 may preferably be set at a minimum value of about 20 nm or more.
- first intermediate interconnection layer 10 B may partially overlap the element isolation portion 2 in view of avoiding the first intermediate interconnection layer 10 B to contact the second intermediate interconnection layer 20 B which will be formed later.
- the third interlayer 13 is formed over the first level interconnection 10 .
- the third contact holes 13 a and 13 b are formed in the memory cell region 7 and the peripheral circuit region 8 , respectively.
- the third contact hole 13 a is formed in the third interlayer 13 and the second interlayer insulating film 12 to expose top surfaces of the first contact plugs 51 b and 51 c in the memory cell region 7 .
- the third contact hole 13 b is formed in the third interlayer 13 to expose a top surface of the second contact plug 52 b in the peripheral circuit region 8 .
- the third contact plugs 53 a and 53 b are formed in the memory cell region 7 and the peripheral circuit region 8 , respectively.
- the third contact plug 53 a is formed on the first contact plugs 51 b and 51 c to fill the third contact hole 13 a
- the third contact plug 53 b is formed over the second contact plug 52 b to fill the third contact hole 13 b.
- a material forming the third interlayer 13 such as a silicon oxide layer, is initially deposited over the first level interconnection 10 . Thereafter, the material forming the third interlayer 13 is polished using a CMP method and planarized. The third interlayer 13 with a thickness of about 400 nm is formed on the second interlayer insulating film 12 .
- third contact holes 13 a are formed in the third interlayer 13 and the second interlayer insulating film 12 in the memory cell region 7 to expose the insides of the first contact plugs 52 b and 51 c while a third contact hole 13 b is formed in the third interlayer 13 in the peripheral circuit region 8 to expose the inside of the second contact plug 52 c .
- no contact hole is formed over the second contact plug 52 b . Since there is only a small difference in depth between the third contact holes 13 a and 13 b formed in the memory cell region 7 and the peripheral circuit region 8 during the present process, the third contact holes 13 a and 13 b may be simultaneously formed in the memory cell region 7 and the peripheral circuit region 8 .
- a Ti layer, a TiN layer, and a W layer are sequentially formed to fill the third contact holes 13 a and 13 b and simultaneously cover the second interlayer insulating film 12 .
- the present embodiment is not limited to the above-described materials and a metal material having a high melting point or a doped silicon layer may be employed.
- the W layer, the TiN layer, and the Ti layer formed over the third interlayer 13 are removed using a CMP technique, thereby forming third contact plugs 53 a and 53 b in the memory cell region 7 and the peripheral circuit region 8 , respectively.
- the formation of the third contact plugs 53 a and 53 b may be performed using an etch-back process.
- the third contact plug 53 b is stacked directly on the second contact plug 52 c not to contact the adjacent first intermediate interconnection layer 10 B in the peripheral circuit region 8 .
- the third contact plug 53 b may be formed to have an outer diameter equal to or less than the outer diameter of the second contact plug 52 c to prevent the occurrence of an electrical short circuit between the third contact plug 53 b and the first intermediate interconnection layer 10 B.
- the third contact plugs 53 a and 53 b are formed on the first and second contact plugs, the third contact plugs 53 a and 53 b are directly on the first and second contact plugs without forming connection pads on the first and second contact plugs.
- the third interlayer 13 has a thickness of about 400 nm, even if the third interlayer 13 is over-etched by 50% of the thickness of the third interlayer 13 during the etching process for forming the third contact holes 13 a and 13 b , an over-etched amount of the third interlayer 13 corresponds to about 200 nm.
- the third contact plugs 13 a and 13 b do not reach the surface 1 a of the semiconductor substrate 1 . Furthermore, since the top and side surfaces of the gate electrodes 41 and 42 are protected by a silicon nitride layer, an anisotropic etching process for selectively removing an interlayer insulating layer (a silicon oxide layer) may be performed. Hence, the formation of an electrical short circuit between the third contact plugs 53 a and 53 b and the gate electrodes 41 and 42 can be prevented.
- a second level interconnection 20 is formed as a capacitance pad 20 A for a capacitor connected to the third contact plug 53 a in the memory cell region 7 .
- the second level interconnection 20 is formed as follows. An interconnection material is stacked to cover the third interlayer 13 . Then, the interconnection material is patterned. Further, the second level interconnection 20 is formed as a second intermediate interconnection layer 20 B connected to any one of the third contact plug 53 b and the gate electrode 42 in the peripheral circuit region 8 . Also, when the second level interconnection 20 is connected to the gate electrode 42 of the peripheral circuit region 8 , each contact plug is disposed to be connected to the gate electrode 42 via the third contact plug 53 b and the second contact plug 52 b.
- an interconnection material (refer to the second level interconnection 20 in FIGS. 7A and 7B ) is formed over the third interlayer 13 .
- the interconnection material is formed by sequentially depositing a TiN layer and a W layer.
- the interconnection material is not limited to the above-described materials and may be, for example, another metal layer having a high melting point or a metal silicide layer.
- the interconnection material with a thickness of, for example, about 100 nm may be formed.
- the interconnection material is patterned using photolithography and dry etching techniques, thereby forming the second level interconnection 20 .
- the capacitance pad 20 A which is a portion of the second level interconnection 20
- the second intermediate interconnection layer 20 B which is another portion of the second level interconnection 20
- the patterning of the capacitance pad 20 A and the first intermediate interconnection layer 20 B that form the second level interconnection 20 may be simultaneously performed using one photomask both in the memory cell region 7 and the peripheral circuit region 8 .
- the second level interconnection 20 (the capacitance pad 20 A) formed in the memory cell region 7 functions as a capacitance pad configured to connect the third contact plug 53 a with a capacitor 9 that will be described later.
- the capacitor 9 having a bottom size greater than the diameter of the surface of the third contact plug 53 a may be disposed. Also, it becomes easy to control positions of adjacent capacitors 9 and equalize intervals between the adjacent capacitors 9 in order to optimize the positions where the capacitors 9 are disposed.
- the second level interconnection 20 (the second intermediate interconnection layer 20 B) formed in the peripheral circuit region functions as an intermediate interconnection layer electrically connected to the peripheral circuit diffusion layer 82 B.
- the second intermediate interconnection layer 20 B in the peripheral circuit region 8 is formed as a strip-shaped pattern extending in the vertical direction.
- a width w 21 of the second intermediate interconnection layer 20 B is preferably set in consideration of the margin ⁇ 21 between the second intermediate interconnection layer 20 B and the third contact plug 53 b .
- the width w 21 of the second intermediate interconnection layer 20 B may be set to be equal to the width w 11 of the first intermediate interconnection layer 10 B.
- the second intermediate interconnection layer 20 B is formed to partially overlap the element isolation portion 2 .
- the capacitor 9 is formed over the second level interconnection 20 (the capacitance pad 20 A for the capacitor) formed over the third contact plug 53 a in the memory cell region 7 using the second-interconnection forming process ( 5 ).
- a fourth interlayer 14 is stacked over the second level interconnection 20 and the third interlayer 13 .
- a capacitor contact hole 14 a is formed in the fourth interlayer 14 to expose a top surface of the capacitance pad 20 A in the memory cell region 7 .
- a first capacitor electrode 91 is formed to cover the capacitance pad 20 A, which is exposed by the sidewalls and inside of the capacitor contact hole 14 a .
- the first capacitor electrode 91 is cylindrical shaped.
- the capacitance insulating layer 92 is formed to cover the inside surface 91 a of the first capacitor electrode 91 and the fourth interlayer 14 .
- a second capacitor electrode 93 is formed to cover the capacitance insulating layer 92 and fill the inside of the capacitor contact hole 14 a .
- the fourth interlayer 14 is formed of a silicon oxide layer over the third interlayer 13 and the second level interconnection 20 (the capacitance pad 20 A for the capacitor and the second intermediate layer 20 B).
- the fourth interlayer 14 is preferably formed to a great thickness to ensure a sufficient capacitance of the capacitor 9 disposed in the memory cell region 7 .
- the fourth interlayer 14 with a thickness of, for example, about 2 ⁇ m is preferably formed.
- a capacitor contact hole 14 a is formed in the fourth interlayer 14 in the memory cell region 7 to expose the inside of the capacitance pad 20 A.
- a first capacitor electrode material (refer to the first capacitor electrode 91 in FIG. 8A ) is formed to cover the capacitance pad 20 A exposed by the side surface and inside of the capacitor contact hole 14 a and the fourth interlayer 14 .
- the first capacitor electrode material may be formed of for example, a TN layer, the present embodiment is not limited thereto.
- the first capacitor electrode material may be another metal layer having a high melting point.
- the first capacitor electrode material formed over the fourth interlayer 14 is removed using a CMP method, thereby forming a first capacitor electrode (a lower electrode) 91 to cover the capacitance pad 20 A exposed by the side surface and inside of the capacitor contact hole 14 a.
- the capacitance insulating layer 92 is formed to cover the surface of the inside surface 91 a of the first capacitor electrode 91 and the fourth interlayer 14 .
- the capacitance insulating layer 92 may be formed of a high-dielectric (high-k) layer, such as a zirconium oxide (ZrO 2 ) layer, a hafnium oxide (HIO 2 ) layer, and an aluminum oxide (Al 2 O 5 ) layer, or a stack layer thereof.
- high-k high-dielectric
- a second capacitor electrode material (refer to a second capacitor electrode 93 of FIG. 8A ) is formed to cover the surface of the capacitance insulating layer 92 and the inside surface 91 a of the first capacitor electrode 91 within the capacitor contact hole 14 a .
- the second capacitor electrode material may be, for example, a TiN layer.
- the formation of the second capacitor electrode material may include forming a TiN layer to such a thickness so as not to cover the inside surface 91 a of the first capacitor electrode 91 and stacking another material, for example, poly-Si or W over the inside surface 91 a of the first capacitor electrode 91 .
- the present embodiment describes the cylindrical capacitor as an example of the capacitor 9 , the present embodiment is not limited thereto.
- the first capacitor electrode 91 may be modified to a crown or pillar shape.
- the second capacitor electrode material is patterned using photolithography and etching techniques, thereby forming the second capacitor electrode (a lower electrode) 93 .
- the capacitor 9 including the first capacitor electrode 91 , the capacitance insulating layer 92 , and the second capacitor electrode 93 is formed in the memory cell region 7 .
- the second capacitor electrode 93 is formed to cover the memory cell region 7 and functions as a plate electrode configured to apply a predetermined electric potential to the capacitor 9 .
- the first capacitor electrode 91 is in contact with the capacitance pad 20 A, which forms a portion of the second level interconnection 20 , so that the capacitor 9 can be connected to a first MOS transistor 3 .
- the second capacitor electrode material and the capacitance insulating layer are removed from the peripheral circuit region 8 .
- the fourth contact holes 14 b and 14 c are formed in the fourth interlayer 14 to expose a top surface of the first intermediate interconnection layer 10 B or the second intermediate interconnection layer 20 B in the peripheral circuit region 8 .
- the fourth contact plugs 54 a and 54 b are formed over the first and second intermediate interconnection layers 10 B and 20 B to fill the fourth contact holes 14 b and 14 c .
- an interconnection material is stacked to cover the fourth interlayer 14 and the fourth contact plugs 54 a and 54 b and patterned.
- the third level interconnection 30 connected to the first intermediate interconnection layer 10 B (the first level interconnection 10 ) or the second intermediate interconnection layer 20 B (the second level interconnection 20 ) via the fourth contact plugs 54 a and 54 b can be formed.
- the fifth interlayer insulating film 15 is formed of a silicon oxide layer to cover the second capacitor electrode 93 .
- the surface of the fifth interlayer insulating film 15 is planarized using a CMP method so that the fifth interlayer insulating film 15 with a thickness of, for example, about 400 nm can be formed.
- the fourth contact holes 14 b and 14 c are formed in the fifth interlayer insulating film 15 , the fourth interlayer insulating film 14 , and the third interlayer insulating film 13 to expose the first intermediate interconnection layer 10 B and the second intermediate interconnection layer 20 B, respectively.
- the first intermediate interconnection layer 10 B forms a portion of the first level interconnection 10 .
- the second intermediate interconnection layer 20 B forms a portion of the second level interconnection 20 .
- an etching process for forming the fourth contact holes 14 b and 14 c is preferably performed in consideration of a difference in interlayer thickness and a difference in etch rate.
- the second intermediate interconnection layer 20 B is over-etched during the formation of the fourth contact hole 14 c penetrating the fourth interlayer insulating film 14 since the second intermediate interconnection layer 20 B is disposed at a higher level than the first intermediate interconnection layer 10 B.
- a conductive material forming the second intermediate interconnection layer 20 B (the second level interconnection 20 ) is selected under such a condition as to selectively etch an insulating layer (a silicon oxide layer) forming the fourth interlayer 14 .
- the fourth contact holes 14 b and 14 c may be formed without causing problems.
- first intermediate interconnection layer 10 B ensures the margin ⁇ 11 and the second intermediate interconnection layer 20 B ensures the margin ⁇ 21 , even if differences in positions where the fourth contact holes 14 b and 14 c are formed occur, deviation of the first and second intermediate interconnection layers 10 B and 20 B may be prevented or reduced.
- the method of fabricating the semiconductor device according to the present embodiment includes filling the fourth contact holes 14 b and 14 c with a conductive material, thereby forming the fourth contact plugs 54 a and 54 b connected to the first and second intermediate interconnection layers 10 B and 20 B, respectively.
- a Ti layer, a TiN layer, and a W layer are sequentially deposited as the conductive material and processed using a CMP technique so that the conductive material left within the fourth contact holes 14 b and 14 c can serve as the fourth contact plugs 54 a and 54 b.
- the third level interconnection 30 connected to the fourth contact plugs 54 a and 54 b is formed of, for example, aluminum (Al) or copper (Cu).
- the formation of the third level interconnection 30 may be performed using a known conventional method with no limitations.
- the third level interconnection 30 may be formed by a conventional known method with no limitations.
- the third level interconnection 30 is not limited to the above-described materials and may be appropriately formed of a conventional contact material.
- a surface protection layer (not shown) is formed of, for example, a silicon oxynitride (SiON) layer on the surface of the stack structure shown in FIGS. 1A and 1B , thereby completing the fabrication of a DRAM device as the semiconductor device A.
- SiON silicon oxynitride
- another metal interconnection layer may be further disposed over the third level interconnection 30 if required.
- FIGS. 14A and 14B are cross-sectional views of a semiconductor device 100 according to a comparative example of the semiconductor device A of the present embodiment.
- the comparison of the semiconductor device 100 with the semiconductor device A will be described with reference to FIGS. 14A and 14B .
- a bit line (a first level interconnection) 110 A of a memory cell region 107 is disposed as an intermediate interconnection layer in a peripheral circuit region 108 .
- the semiconductor device 100 has the memory cell region 107 in common with the semiconductor device A according to the first embodiment of the present invention. Also, in the peripheral circuit region 108 , peripheral circuit diffusion layers 182 A and 182 B functioning as second and third source or drain regions of second and third MOS transistors 131 and 132 are connected to a third level interconnection 130 by a fourth contact plug 154 a via a first level interconnection 110 B.
- An interval R 3 between adjacent first level interconnections 110 B is determined by the resolution of an applied photolithography technique.
- a width R 1 of an element isolation portion 102 and an interval R 3 between the first level interconnections 110 B is about the same minimum value equivalent to the resolution limit. Consequently, further reducing the width R 1 and the interval R 3 is difficult.
- a peripheral circuit diffusion layer 82 C functioning as the source or drain region is preferably formed as follows.
- the peripheral circuit region 8 of the second MOS transistor 31 of the peripheral circuit diffusion layer 82 C may be formed to have the same structure as a peripheral circuit diffusion layer 82 B of the third MOS transistor 32 .
- the peripheral circuit diffusion layer 82 D functioning as the source or drain region, which of the third MOS transistor 32 of the peripheral circuit region 8 is preferably formed to have the same structure as a peripheral circuit diffusion layer 82 A of the second MOS transistor 31 .
- FIG. 12 is a cross-sectional view of a semiconductor device A including the peripheral circuit diffusion layers 82 C and 82 D.
- an example of the semiconductor device A shown in FIG. 11 includes two transistors.
- a first intermediate interconnection layers 10 B and a second intermediate interconnection layers 20 B it is preferable for a first intermediate interconnection layers 10 B and a second intermediate interconnection layers 20 B to be alternately and repetitively connected to the peripheral circuit diffusion layers 82 A, 82 B, 82 C, and 82 D.
- a distance between adjacent transistors may be shortened, thereby reducing the area occupied by the peripheral circuit region 8 .
- a gate electrode 42 may be prepared to be connected to a more suitable one of the first and second intermediate interconnection layers 10 B and 20 B as an intermediate interconnection according to a position of a contact plug connected to the gate electrode 42 .
- the first intermediate interconnection layer 10 B is connected to the gate electrode 42
- the first intermediate interconnection layer 10 B and the gate electrode 42 are connected to each other via a second contact plug 52 d prepared on the gate electrode 42 .
- the second intermediate interconnection layer 20 B is connected to the gate electrode 42
- the second intermediate interconnection layer 20 B and the gate electrode 42 are connected to each other via a stack structure of second and third contact plugs 52 e and 53 c prepared on the gate electrode 42 .
- the MOS transistors 31 and 32 disposed in the peripheral circuit region 8 may have p-type conductivity.
- the MOS transistors 31 and 32 may be disposed in an n-type well, and boron (B) ions may be introduced as p-type impurities into the peripheral circuit diffusion layer (a second diffusion layer).
- both n-type and p-type transistors may be disposed to prepare CMOS transistors.
- first and second contact plugs may not be directly in contact with a semiconductor substrate but may be connected to the semiconductor substrate via a selectively epitaxially grown silicon layer.
- the semiconductor device related with the present embodiment may be very effectively applied to formation of an intermediate interconnection layer of a peripheral circuit region (a connection portion) disposed adjacent to a memory cell region, such as a sense amplifier circuit or a word line driver circuit. Also, the semiconductor device related with the present embodiment may be applied to other peripheral circuit regions.
- the above-described method of fabricating the semiconductor device A according to the present embodiment may involve the respective processes, thereby enabling efficient fabrication of a DRAM device having a small chip size as the semiconductor device A with a high throughput.
- FIG. 13 is a schematic plan view of the semiconductor device B according to the second embodiment of the present invention, which illustrates the structure of a MOS transistor disposed in a peripheral circuit region.
- the semiconductor device B according to the present embodiment differs from the semiconductor device A according to the first embodiment in the following constitution.
- the semiconductor device B is mainly disposed in the peripheral circuit region and an upper interconnection connected to any one of a first level interconnection 10 B and a second level interconnection 20 B is not prepared.
- the semiconductor device B includes a plurality of ring-shaped gate electrodes 42 disposed in a rectangular active region K.
- FIG. 13 illustrates four gate electrodes 42 disposed in the active region K.
- a second contact plug 52 b is connected to a central peripheral circuit diffusion layer (source or drain regions) 82 E surrounded by the ring-shaped gate electrodes 42 .
- second contact plugs 52 b are provided to be connected to the gate electrodes 42 .
- first level interconnections 10 B extend in a lateral direction in the peripheral circuit region of the semiconductor device B.
- reference numerals (a) through (e) are respectively assigned to the five first level interconnections 10 B from above.
- the first level interconnection 10 B(a) connects the gate electrode 42 and the peripheral circuit diffusion layer 82 E of a transistor disposed adjacent thereto and simultaneously extends in a lateral direction of FIG. 13 to be connected to another circuit (not shown).
- Each of the first level interconnections 10 B(b), 10 B(d), and 10 B(e) is configured in the same manner as the first level interconnection 10 B(a).
- first level interconnection 10 B(c) disposed in the center in a vertical direction of FIG. 13 is not connected to transistors shown in FIG. 13 .
- first level interconnection 10 B(c) is disposed in the center to be connected to another transistor (not shown).
- a stack plug obtained by directly stacking the second contact plug 52 b and a third contact plug 53 b is connected to a peripheral circuit diffusion layer (source or drain region) 82 F disposed outside the ring-shaped gate electrode 42 ( FIG. 13 shows only the position of the third contact plug 53 b ).
- the second contact plugs 52 b connected respectively to the peripheral circuit diffusion layers 82 E and 82 F and the gate electrode 42 may be simultaneously formed using one photomask.
- a second level interconnection 20 B is provided on and connected to the third contact plug 53 b .
- the second level interconnection 20 B is electrically connected to the peripheral circuit diffusion layer 82 F via the third contact plug 53 b and the second contact plug 52 b.
- a fourth contact plug 54 b is connected to the second level interconnection 20 B and connected to an upper interconnection layer (not shown).
- the second level interconnection 20 B connected to the peripheral circuit diffusion layer 82 F may be disposed on the first level interconnection 10 B to intersect the first level interconnection 10 t from plan view, the first level interconnection 10 B and a transistor may be disposed at high density.
- FIG. 15 is a plan view of a semiconductor device 200 using only a first level interconnection 10 B according to a comparative example of the semiconductor device B of the present embodiment.
- the comparison of the semiconductor device 200 with the semiconductor device B will be described with reference to FIG. 15 .
- a first level interconnection 110 B(f) is connected to a peripheral circuit diffusion layer 182 F.
- a first level interconnection 110 B(c) is disposed away from the first level interconnection 110 B(f)
- a dimension required to dispose the first level interconnections 110 B(c) and 110 B(f) is enlarged in a vertical direction of FIG. 15 , thereby precluding the miniaturization of the semiconductor device 200 .
- the second contact plug 52 b and the third contact plug 53 b are disposed not to cause an electrical short circuit between the second and third contact plugs 52 b and 53 b .
- the first level interconnection 10 B, the first level interconnection 10 B and a transistor may be disposed at a higher density than the comparative example.
- the peripheral circuit region when a plurality of transistors are repetitively disposed in a connection portion (a region disposed adjacent to the memory cell region) where a sense amplifier circuit or a word line driver circuit is disposed, the area occupied by the sense amplifier circuit or the word line driver circuit may be reduced effectively.
- the semiconductor device B of the second embodiment may reduce the area occupied by a circuit disposed in the peripheral circuit region, thereby obtaining the semiconductor device B with a small chip size.
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- Semiconductor Memories (AREA)
Abstract
A semiconductor device includes the following elements. An element isolation portion separates first and second diffusion regions in a semiconductor substrate each other. A first insulating film is formed over the element isolation portion and the first and second diffusion regions. First and second contact plugs are formed over the first and second diffusion regions, respectively. The first and second contact plugs penetrate the first insulating film. A first conductive layer is formed over the first insulating film over the element isolation portion. A second insulating film is formed over the first conductive layer. A third contact plug penetrates the second insulating film, the third contact plug connecting the first contact plug. A second conductive layer is formed over the second insulating film contacting the third contact plug. The first and second conductive layers partly overlap the element isolation portion.
Description
- This application is a continuation of U.S. patent application Ser. No. 12/982,342, filed Dec. 30, 2010, which claims the benefit of priority from Japanese Patent Application No. 2010-002863, filed on Jan. 8, 2010, the contents of which are incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to a semiconductor device and a method of fabricating the same.
- 2. Description of the Related Art
- In general, a dynamic random access memory (DRAM) device largely has a memory cell region configured to store and retain data and a peripheral circuit region configured to input and output data between the memory cell region and the outside of a device. Also, a sense amplifier circuit and a word line driver circuit are disposed in a region (or a connection portion) of the peripheral circuit region, which is disposed adjacent to the memory cell region. Here, with miniaturization of the memory cell region, it is necessary to reduce the area occupied by the sense amplifier circuit and the word line driver circuit.
- Furthermore, in the field of semiconductor devices, such as DRAMs, an increase in the functionality of equipment using the semiconductor devices leads to new progress of highly integrated devices. With the development of miniaturization of semiconductor devices corresponding to an increase in the integration density of DRAMs, a method of increasing the height of an electrode of a capacitor by forming the electrode of the capacitor in a 3-dimensional shape, such as a cylindrical shape. This structure which increases the surface area of the electrode has typically been adopted in order to ensure the capacitance required for the capacitor constituting a memory cell region.
- In one embodiment, a semiconductor device may include, but is not limited to, the following elements. First and second diffusion regions are formed in a semiconductor substrate. An element isolation portion separates the first and second diffusion regions each other. A first insulating film is formed over the element isolation portion and the first and second diffusion regions. First and second contact plugs are formed over the first and second diffusion regions, respectively. The first and second contact plugs penetrate the first insulating film. A first conductive layer is formed over the first insulating film. A second insulating film is formed over the first conductive layer. A third contact plug penetrates the second insulating film. The third contact plug is connected to the first contact plug. A second conductive layer is formed over the second insulating film. The second conductive layer contacts the third contact plug. The first and second conductive layers partly overlap the element isolation portion.
- In another embodiment, a semiconductor device may include, but is not limited to the following elements. A first transistor is formed in a memory cell region. Second and third transistors are formed in a peripheral circuit region. A first insulating film is formed over the first, second and third transistors. A first conductive layer contacts the first insulating film. The first conductive layer is electrically connected with the second transistor. A second insulating film is formed over the first conductive layer. A capacitance pad is on and in contact with the second insulating film. The capacitance pad is electrically connected to the first transistor. A second conductive layer is on and in contact with the second insulating film. The second conductive layer is electrically connected with the third transistor.
- In still another embodiment, a semiconductor device may include, but is not limited to, the following elements. A first transistor includes first and second diffusion regions in a memory cell region. Second and third transistors formed in a peripheral circuit region. The second transistor includes a third diffusion region. The third transistor includes a fourth diffusion region. A first contact plug is formed over the first diffusion region. A second contact plug is formed over the first contact plug. A bit line is connected to the first diffusion region of the first transistor via the first and second contact plugs. A third contact plug is formed over the third diffusion region. A first conductive layer is connected to the third diffusion region via the third contact plug. A fourth contact plug is formed over the second diffusion region. A fifth contact plug is formed over the fourth contact plug. A capacitor pad is connected to a second diffusion region of the first transistor via the fourth and fifth contact plugs. A sixth contact plug is formed over the fourth diffusion region. A seventh contact plug is formed over the sixth contact plug. A second conductive layer is connected to a fourth diffusion region via the sixth and seventh contact plugs. An eighth contact plug is formed over the second conductive layer. A third conductive layer is connected to the second conductive layer via the eighth contact plug.
- In still another embodiment, a method for forming a semiconductor device may include, but is not limited to the following processes. An element isolation portion is formed in a semiconductor substrate. First and second impurity regions are formed in the semiconductor substrate. The element isolation portion separates the first and second impurity regions. A first conductive layer connected to the first impurity region is formed to partially overlap the element isolation portion. A first insulating film is formed over the first conductive layer. A second conductive layer is formed over the first insulating film and the second impurity region to partially overlap the element isolation portion. The second conductive layer is connected to the second impurity region.
- In still another embodiment, a method for forming a semiconductor device may include, but is not limited to the following processes. First and second impurity regions are formed in a semiconductor substrate in a memory cell region while third and fourth impurity regions are formed in the semiconductor substrate in a peripheral circuit region. First and second contact plugs are formed over the first and second impurity regions, respectively while third and fourth contact plugs are formed over the third and fourth impurity regions, respectively. A first conductive layer is formed over the third contact plug while a bit wiring connecting the first contact plug is formed. The first conductive layer is connected to the third contact plug. An insulating film is formed over the bit wiring and the first conductive layer. A capacitance pad connecting the second contact plug is formed while a second conductive layer is formed over the insulating film, the second conductive layer being electrically connected to the fourth contact plug.
- The above features and advantages of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:
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FIG. 1A is a fragmentary cross sectional elevation view, taken along a D-D′ line ofFIG. 10 , illustrating a memory cell in accordance with one embodiment of the present invention; -
FIG. 1B is a fragmentary cross sectional elevation view, taken along a B-B′ line ofFIG. 11 , illustrating a memory cell in accordance with one embodiment of the present invention; -
FIG. 1C is a fragmentary cross sectional elevation view illustrating a memory cell in accordance with one embodiment of the present invention; -
FIG. 1D is a fragmentary cross sectional elevation view illustrating a memory cell in accordance with one embodiment of the present invention; -
FIG. 2A is a fragmentary cross sectional elevation view, taken along a D-D′ line ofFIG. 10 , illustrating a memory in a step involved in a method of forming the semiconductor device ofFIGS. 1A and 1B ; -
FIG. 2B is a fragmentary cross sectional elevation view, taken along a B-B′ line ofFIG. 11 , illustrating a memory in a step involved in a method of forming the semiconductor device ofFIGS. 1A and 1B ; -
FIG. 3A is a fragmentary cross sectional elevation view, taken along a D-D′ line ofFIG. 10 , illustrating a memory in a step involved in a method of forming the semiconductor device ofFIGS. 1A and 1B ; -
FIG. 3B is a fragmentary cross sectional elevation view, taken along a B-B′ line ofFIG. 11 , illustrating a memory in a step involved in a method of forming the semiconductor device ofFIGS. 1A and 1B ; -
FIG. 4A is a fragmentary cross sectional elevation view, taken along a D-D′ line ofFIG. 10 , illustrating a memory in a step involved in a method of forming the semiconductor device ofFIGS. 1A and 1B ; -
FIG. 4B is a fragmentary cross sectional elevation view, taken along a B-B′ line ofFIG. 11 , illustrating a memory in a step involved in a method of forming the semiconductor device ofFIGS. 1A and 1B ; -
FIG. 5A is a fragmentary cross sectional elevation view, taken along a D-D′ line ofFIG. 10 , illustrating a memory in a step involved in a method of forming the semiconductor device ofFIGS. 1A and 1B ; -
FIG. 5B is a fragmentary cross sectional elevation view, taken along a B-B′ line ofFIG. 11 , illustrating a memory in a step involved in a method of forming the semiconductor device ofFIGS. 1A and 1B ; -
FIG. 6A is a fragmentary cross sectional elevation view, taken along a D-D′ line ofFIG. 10 , illustrating a memory in a step involved in a method of forming the semiconductor device ofFIGS. 1A and 1B ; -
FIG. 6B is a fragmentary cross sectional elevation view, taken along a B-B′ line ofFIG. 11 , illustrating a memory in a step involved in a method of forming the semiconductor device ofFIGS. 1A and 1B ; -
FIG. 7A is a fragmentary cross sectional elevation view, taken along a D-D′ line ofFIG. 10 , illustrating a memory in a step involved in a method of forming the semiconductor device ofFIGS. 1A and 1B ; -
FIG. 7B is a fragmentary cross sectional elevation view, taken along a B-B′ line ofFIG. 11 , illustrating a memory in a step involved in a method of forming the semiconductor device ofFIGS. 1A and 1B ; -
FIG. 8A is a fragmentary cross sectional elevation view, taken along a D-D′ line ofFIG. 10 , illustrating a memory in a step involved in a method of forming the semiconductor device ofFIGS. 1A and 1B ; -
FIG. 8B is a fragmentary cross sectional elevation view, taken along a B-B′ line ofFIG. 11 , illustrating a memory in a step involved in a method of forming the semiconductor device ofFIGS. 1A and 1B ; -
FIG. 9A is a fragmentary cross sectional elevation view, taken along a D-D′ line ofFIG. 10 , illustrating a memory in a step involved in a method of forming the semiconductor device ofFIGS. 1A and 1B ; -
FIG. 9B is a fragmentary cross sectional elevation view, taken along a B-B′ line ofFIG. 11 , illustrating a memory in a step involved in a method of forming the semiconductor device ofFIGS. 1A and 1B ; -
FIG. 10 a fragmentary plan view integrally illustrating a memory cell including a semiconductor device in accordance with one embodiment of the present invention; -
FIG. 11 a fragmentary plan view integrally illustrating a memory cell including a semiconductor device in accordance with one embodiment of the present invention; -
FIG. 12 is a fragmentary cross sectional elevation view, taken along a B-B′ line ofFIG. 11 , illustrating a memory in a step involved in a method of forming the semiconductor device ofFIGS. 1A and 1B ; -
FIG. 13 a fragmentary plan view integrally illustrating a memory cell including a semiconductor device in accordance with another embodiment of the present invention; -
FIG. 14A is a fragmentary cross sectional elevation view illustrating a memory cell including a semiconductor device in accordance with a related art of the present invention; -
FIG. 14B is a fragmentary cross sectional elevation view illustrating a memory cell including a semiconductor device in accordance with a related art of the present invention; and -
FIG. 15 is a fragmentary cross sectional elevation view illustrating a memory cell including a semiconductor device in accordance with a related art of the present invention. - Before describing the present invention, the related art will be explained in detail, with reference to drawings, in order to facilitate the understanding of the present invention.
- When the electrode of the capacitor is formed in a 3-dimensional structure, it becomes necessary to prepare an interlayer insulating layer with a very great thickness corresponding to the height of the capacitor. Also, in a peripheral circuit region, it is necessary to prepare a contact plug having a great enough height as to penetrate the thick interlayer insulating layer to connect a MOS transistor disposed on the surface of a semiconductor substrate with a metal interconnection layer disposed thereon.
- Furthermore, when the metal interconnection layer is connected to the MOS transistor prepared on the surface of the semiconductor substrate using only one contact plug, it may be difficult to perform a processing operation because the contact plug has an excessively large aspect ratio. For this reason, an intermediate interconnection layer or pad may be prepared between the metal interconnection layer and the MOS transistor. It may be necessary to connect the metal interconnection layer and the MOS transistor by interposing a plurality of contact plugs in series therebetween.
- The following method has been proposed. A bit line pad used as a memory cell or a lower electrode, which also refer to as an accumulation electrode, of a capacitor is employed as an intermediate interconnection layer of a peripheral circuit region (for example, refer to JP-A-11-214660, JP-A-2002-319632, and JP-A-2005-260254) because an obstacle is caused in an interconnection layout when a metal interconnection layer is only provided in an upper layer.
- However, when a lower electrode of a capacitor is processed in a cylindrical shape, it is necessary to form the lower electrode using an inner wall of a previously prepared contact hole. Accordingly, it becomes troublesome to simultaneously process the lower electrode of the capacitor and an interconnection layer of a peripheral circuit region as in JP-A-2002-319632 and JP-A-2005-2602543.
- Here, it is easy to simultaneously process bit lines used in a memory cell region and intermediate interconnection layers used in the peripheral circuit region. However, for example, for forming a sense amplifier circuit, a plurality of MOS transistors is disposed to connect interactive source and drain regions (or diffusion layers) and gate electrodes. Accordingly, the intermediate interconnection layers should be disposed at a higher density than in the memory cell region. Also, when the bit lines are used as the intermediate interconnection layers in the peripheral circuit region, interconnection layers cannot be disposed adjacent to one another at a line-width and interval below the design rule determined by the resolution of a photolithography technique used for the processing of the bit lines. Accordingly, when a pitch at which cells are disposed is reduced by downscaling memory cells, disposing the plurality of MOS transistors and the intermediate interconnection layers at the reduced pitch may become difficult, thus hindering the miniaturization of devices.
- Embodiments of the invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teaching of the embodiments of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purpose.
- In one embodiment, a semiconductor device may include, but is not limited to, the following elements. First and second diffusion regions are formed in a semiconductor substrate. An element isolation portion separates the first and second diffusion regions each other. A first insulating film is formed over the element isolation portion and the first and second diffusion regions. First and second contact plugs are formed over the first and second diffusion regions, respectively. The first and second contact plugs penetrate the first insulating film. A first conductive layer is formed over the first insulating film. A second insulating film is formed over the first conductive layer. A third contact plug penetrates the second insulating film. The third contact plug is connected to the first contact plug. A second conductive layer is formed over the second insulating film. The second conductive layer contacts the third contact plug. The first and second conductive layers partly overlap the element isolation portion.
- In some cases, the semiconductor device may include, but is not limited to, the first and second contact plugs connected to the first and second diffusion regions, respectively.
- In some cases, the semiconductor device may further include, but is not limited to, a fourth contact plug. The second conductive layer is connected to the second diffusion region through fourth contact plug. The fourth contact plug comprises a material same as a material included in the third contact plug.
- In some cases, the semiconductor device may further include, but is not limited to, the following elements. A third insulating film is formed over the second conductive layer. A fifth contact plug penetrates the third insulating film. The fifth contact plug is connected to the second conductive layer. A third conductive layer is formed over the third insulating film. The third conductive layer contacts the fifth contact plug.
- In some cases, the semiconductor device may include, but is not limited to, the first diffusion region of a first transistor and the second diffusion region of a second transistor.
- In another embodiment, a semiconductor device may include, but is not limited to the following elements. A first transistor is formed in a memory cell region. Second and third transistors are formed in a peripheral circuit region. A first insulating film is formed over the first, second and third transistors. A first conductive layer contacts the first insulating film. The first conductive layer is electrically connected with the second transistor. A second insulating film is formed over the first conductive layer. A capacitance pad is on and in contact with the second insulating film. The capacitance pad is electrically connected to the first transistor. A second conductive layer is on and in contact with the second insulating film. The second conductive layer is electrically connected with the third transistor.
- In some cases, the semiconductor device may include, but is not limited to, the second transistor adjacent to the third transistor.
- In some cases, the semiconductor device may further include, but is not limited to, an element isolation portion between the second transistor and the third transistor. In some cases, the semiconductor device may include, but is not limited to, the first conductive layer whose width is greater than (5/3)×R1. R1 is a width of the element isolation portion.
- In some cases, the semiconductor device may include, but is not limited to, the first and second conductive films partially overlapping the element isolation portion.
- In some cases, the semiconductor device may include, but is not limited to, the element isolation portion is the same in width as the first and second contact plugs.
- In some cases, the semiconductor device may further include, but is not limited to, first and second contact plugs electrically connected to the first and second conductive layers, respectively. The first and second contact plugs are electrically connected to the first and second transistors, respectively.
- In still another embodiment, a semiconductor device may include, but is not limited to, the following elements. A first transistor includes first and second diffusion regions in a memory cell region. Second and third transistors formed in a peripheral circuit region. The second transistor includes a third diffusion region. The third transistor includes a fourth diffusion region. A first contact plug is formed over the first diffusion region. A second contact plug is formed over the first contact plug. A bit line is connected to the first diffusion region of the first transistor via the first and second contact plugs. A third contact plug is formed over the third diffusion region. A first conductive layer is connected to the third diffusion region via the third contact plug. A fourth contact plug is formed over the second diffusion region. A fifth contact plug is formed over the fourth contact plug. A capacitor pad is connected to a second diffusion region of the first transistor via the fourth and fifth contact plugs. A sixth contact plug is formed over the fourth diffusion region. A seventh contact plug is formed over the sixth contact plug. A second conductive layer is connected to a fourth diffusion region via the sixth and seventh contact plugs. An eighth contact plug is formed over the second conductive layer. A third conductive layer is connected to the second conductive layer via the eighth contact plug.
- In some cases, the semiconductor device may further include, but is not limited to, an element isolation portion contacting the third and fourth diffusion regions.
- In some cases, the semiconductor device may further include, but is not limited to, a first insulating film over the element isolation portion. The element isolation portion is substantially aligned to the first insulating film.
- In some cases, the semiconductor device may include, but is not limited to, the first and second conductive layers partly overlapping the element isolation portion.
- In some cases, the semiconductor device may include, but is not limited to, a distance between the third and fourth diffusion regions is substantially the same as a width of the element isolation portion.
- In some cases, the semiconductor device may further include, but is not limited to, the following elements. A first gate electrode is of the second transistor. A second gate electrode is of the third transistor. A ninth contact plug is electrically connected with the first gate electrode. A fourth conductive layer is formed over the ninth contact plug. The fourth conductive layer is connected to the first gate electrode via the ninth contact plug. A tenth contact plug is electrically connected with the second gate electrode. An eleventh contact plug is formed over the tenth contact plug. A fifth conductive layer is formed over the eleventh contact plug. The fifth conductive layer is electrically connected to the second gate electrode via the tenth and eleventh contact plugs.
- In some cases, the semiconductor device may include, but is not limited to, the first conductive layer and the bit line are formed in the same level.
- In some cases, the semiconductor device may include, but is not limited to, the second conductive layer and the capacitor pad are formed in the same level.
- In still another embodiment, a method for forming a semiconductor device may include, but is not limited to the following processes. An element isolation portion is formed in a semiconductor substrate. First and second impurity regions are formed in the semiconductor substrate. The element isolation portion separates the first and second impurity regions. A first conductive layer connected to the first impurity region is formed to partially overlap the element isolation portion. A first insulating film is formed over the first conductive layer. A second conductive layer is formed over the first insulating film and the second impurity region to partially overlap the element isolation portion. The second conductive layer is connected to the second impurity region.
- In some cases, the method for forming the semiconductor device may further include, but is not limited to, forming first and second contact plugs connected to the first and second impurity regions, respectively before forming the first conductive layer.
- In some cases, the method for forming the semiconductor device may further include, but is not limited to, forming a third contact plug connected to the second contact plug before forming the second conductive layer.
- In some cases, forming the first conductive layer further include, but is not limited to, etching a surface of the second contact plug.
- In still another embodiment, a method for forming a semiconductor device may include, but is not limited to the following processes. First and second impurity regions are formed in a semiconductor substrate in a memory cell region while third and fourth impurity regions are formed in the semiconductor substrate in a peripheral circuit region. First and second contact plugs are formed over the first and second impurity regions, respectively while third and fourth contact plugs are formed over the third and fourth impurity regions, respectively. A first conductive layer is formed over the third contact plug while a bit wiring connecting the first contact plug is formed. The first conductive layer is connected to the third contact plug. An insulating film is formed over the bit wiring and the first conductive layer. A capacitance pad connecting the second contact plug is formed while a second conductive layer is formed over the insulating film, the second conductive layer being electrically connected to the fourth contact plug.
- In some cases, the method for forming the semiconductor device may further include, but is not limited to, forming an element isolation portion between the third and fourth impurity regions.
- In some cases, forming the first conductive layer may further include, but is not limited to, etching a surface of the fourth contact plug.
- Hereinafter, in one embodiment, a DRAM (Dynamic Random Access Memory) as the semiconductor device will be described. In the drawings used for the following description, to facilitate understanding of the embodiments, illustrations are partially enlarged and shown, and the sizes and ratios of constituent elements are not limited to being the same as the actual dimensions. Materials, sizes, and the like exemplified in the following description are just examples, and the invention is not limited thereto and may be appropriately modified within the scope which does not deviate from the embodiments.
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FIGS. 1A , 1B, and 12 are schematic cross-sectional views of a semiconductor device A as a DRAM device including a plurality of MOS transistors according to the first embodiment of the present invention.FIGS. 2A through 9A and 2B through 9B are schematic cross-sectional views illustrating respective processes of a method of fabricating a semiconductor device according to the present embodiment.FIGS. 1A through 9A are each cross-sectional views taken along section indication lines D-D′ of each schematic plan view ofFIGS. 10 and 11 , andFIGS. 1B through 9B and 12 are each cross-sectional views taken along section indication lines B-B′ of each of the schematic plan views ofFIGS. 10 and 11 . - <Structure of Semiconductor Device>
- To begin with, the construction of the semiconductor device A according to the present embodiment will be chiefly described hereinafter with reference to
FIGS. 1A , 1B, 1C, 1D and 10. - The semiconductor device A according to the present embodiment includes a
memory cell region 7 and aperipheral circuit region 8 provided over asemiconductor substrate 1. In thememory cell region 7, a portion of thesemiconductor substrate 1 is doped with an impurity, thereby forming a memory cell diffusion layer (a first diffusion layer) 72. In theperipheral circuit region 8, a portion of thesemiconductor substrate 1 is doped with an impurity, thereby forming a peripheral circuit diffusion layer (a second diffusion layer) 82. Afirst level interconnection 10 is provided in thememory cell region 7 as abit line 10A connected to the memorycell diffusion layer 72. Also thefirst level interconnection 10 is provided in theperipheral circuit region 8 as a firstintermediate interconnection layer 10B connected to any one of the peripheralcircuit diffusion layer 82 and a gate electrode 4(42). Furthermore, asecond level interconnection 20 is provided in thememory cell region 7 as acapacitance pad 20A for a capacitor connected to the memorycell diffusion layer 72. Also, thesecond level interconnection 20 is provided in theperipheral circuit region 8 as a secondintermediate interconnection layer 20B connected to any one of the peripheralcircuit diffusion layer 82 and a gate electrode 4 (42) via a stack structure of at least two contact plugs (refer to asecond contact plug 52 c and athird contact plug 53 b ofFIG. 1B and asecond contact plug 52 e and a third contact plug 53 c ofFIG. 1D ). - More specifically, an
element isolation portion 2 is formed in the semiconductor device A according to the present embodiment so that theelement isolation portion 2 isolates active regions K from each other in thesemiconductor substrate 1. A first metal-oxide-semiconductor (MOS)transistor 3 is provided in thememory cell region 7. Second andthird MOS transistors peripheral circuit region 8. - Also, in the
memory cell region 7 of the semiconductor device A, a gate electrode (a first gate electrode) 41 is provided over the active region K of thesemiconductor substrate 1 and forms a portion of a word line W. First contact plugs 51 a, 51 b, and 51 c are formed over the memory cell diffusion layer that performs one of first source and drainregions 72. Also, second contact plugs 52 b and 52 c are formed over the peripheralcircuit diffusion layers peripheral circuit region 8. Further, second contact plugs 52 d and 52 e are formed over thegate electrode 42 in theperipheral circuit region 8. A second contact plug 52 a is formed in thememory cell region 7. The second contact plug 52 a is connected to thefirst contact plug 51 a. Furthermore, the semiconductor device A includes third contact plugs 53 a, which are connected to the first contact plugs 51 b and 51 c, respectively, in thememory cell region 7. The semiconductor device A includes athird contact plug 53 b connected to thesecond contact plug 52 c in theperipheral circuit region 8. The semiconductor device A further includes a third contact plug 53 c connected to thesecond contact plug 52 e in theperipheral circuit region 8. - Also, the semiconductor device A includes the
first level interconnection 10 including thebit line 10A in thememory cell region 7 and the firstintermediate interconnection layer 10B in theperipheral circuit region 8. Thebit line 10A is separated from the firstintermediate interconnection layer 10B. Thebit line 10A is connected to the memorycell diffusion layer 72 via a stack structure of the first and second contact plugs 51 a and 52 a. The firstintermediate interconnection layer 10B is connected via thesecond contact plug 52 b to the peripheral circuit diffusion layers (second and third source and drain regions) 82. Also, the firstintermediate interconnection layer 10B is connected via thesecond contact plug 52 d to the gate electrode (second and third gate electrodes) 42. Further, the semiconductor device A includes thesecond level interconnection 20 including thecapacitor pad 20A in thememory cell region 7 and the secondintermediate interconnection layer 20B in theperipheral circuit region 8. Thecapacitor pad 20A is separated from the secondintermediate interconnection layer 20B. Thecapacitance pad 20A for the capacitor is connected to the memorycell diffusion layer 72 via a stack structure of the first contact plugs 51 b and 51 c and the third contact plug 53 a. The secondintermediate interconnection layer 20B is connected to theperipheral diffusion layer 82 via a stack structure of thesecond contact plug 52 b and thethird contact plug 53 b. The secondintermediate interconnection layer 20B is connected to thegate electrode 42 via a stack structure of thesecond contact plug 52 e and the third contact plug 53 c. - As shown in
FIGS. 1A , 1B, 1C, and 1D, the semiconductor device A according to the present embodiment, which has the DRAM device structure, may include a plurality ofmemory cell regions 7. A plurality ofmemory cells 71 are disposed in thememory cell region 7 according to predetermined rules.FIG. 10 is a fragmentary and horizontally cross-sectional view showing some elements such as word lines W and sidewall insulatinglayers 47 in each of thememory cells 71. In addition, a capacitor 9 is not shown inFIG. 10 but shown inFIG. 1 andFIGS. 8A , 8B, 9A, and 9B, which are fragmentary cross-sectional elevation views for illustrating processes of the semiconductor device A. - Also, each of the
memory cells 71 has aMOS transistor 3 and a capacitor 9 connected to theMOS transistor 3 via a plurality of contact plugs (refer to 51 b and 53 a ofFIG. 1A ). Furthermore, thefirst level interconnection 10 including thebit line 10A is connected to the memory cell diffusion layers 72 corresponding to source and drain regions of theMOS transistor 3, which are not connected to the capacitor 9, via a plurality of contact plugs (refer to 51 b and 52 a ofFIG. 1A ). - As described above, a portion of the
semiconductor substrate 1 is doped with an impurity, thereby forming the memorycell diffusion layer 72 in thememory cell region 7 and forming the peripheralcircuit diffusion layer 82 in theperipheral circuit region 8. Also, a plurality of regions whereMOS transistors element isolation portion 2 which isolates active regions K from each other in thesemiconductor substrate 1. - For example, a P-type silicon substrate may be used as the
semiconductor substrate 1. However, the present embodiment is not limited thereto and a germanium (Ge)-containing semiconductor substrate may be used as thesemiconductor substrate 1. - The memory
cell diffusion layer 72 is an impurity diffusion region doped with N-type impurity ions, which is provided in a predetermined position on a surface 1 a of thesemiconductor substrate 1 as shown inFIG. 1A . - For example, phosphorus (P) or arsenic (As) ions are implanted at a predetermined concentration into the memory
cell diffusion layer 72 of the present embodiment. - Like the memory
cell diffusion layer 72, the peripheral circuit diffusion layers 82 (82A, 82B, 82C, and 82D) are impurity diffusion regions doped with N-type impurity ions, which are provided in predetermined positions on the surface 1 a of thesemiconductor substrate 1 as shown inFIG. 1B . - Like the memory
cell diffusion layer 72, for example, N-type impurity ions, such as P or As ions, may be implanted at a predetermined concentration into the peripheralcircuit diffusion layer 82A of the present embodiment. - In the present embodiment, as in the planar structure of
FIG. 10 , in thememory cell region 7, a plurality of elongated strip-shaped active regions K are prepared in the surface of thesemiconductor substrate 1 at predetermined intervals. Each elongated strip-shaped active region K extends in a direction inclined to a direction along which the word lines W extend. The active regions K are defined by theelement isolation portions 2 surrounding the outer circumferences of the active regions K. - Although
FIG. 10 shows a memory-cell layout known as 6F2, the layout of the active regions K according to the present embodiment is not limited thereto. For instance, another layout of active regions applied to typical memory cells (e.g., a layout known as 8F2) may be selected and applied. - Diffusion regions are formed in both end portions and a central portion of each of the active regions K. In the diffusion regions, N-type impurities are introduced. The diffusion regions may be the memory
cell diffusion region 72 and the peripheralcircuit diffusion layer 82 ofFIGS. 1A and 1B . Each of the diffusion regions functions as a source or drain region of thefirst MOS transistor 3 as described above. Also, the first contact plugs 51 are disposed directly on the diffusion regions functioning as the source and drain regions of thefirst MOS transistor 3. The first contact plugs 51 may be first contact plugs 51 a, 51 b, and 51 c illustrated with dotted-and-broken lines inFIG. 10 . - With reference back to
FIGS. 1A and 1B , the gate electrodes 4 (41 and 42) are provided on the active region K of thesemiconductor substrate 1. Thefirst gate electrode 41 is provided in thememory cell region 7 and forms a portion of the word line W. Also, the gate electrodes (second and third gate electrodes) 42 are provided in theperipheral circuit region 8 and intersect the active region K. Thegate electrodes - Also, a
gate insulating layer 45 formed of a silicon oxide (SiO2) layer is formed between each of thegate electrodes FIGS. 1A and 1B and thesemiconductor substrate 1. A gatemask insulating layer 46 formed of a silicon nitride (Si3N4) layer is stacked on the surface of each of thegate electrodes sidewall insulating layer 47 formed of a silicon nitride layer is formed on a side surface of each of stack structures obtained by sequentially stacking thegate insulating layer 45, thegate electrodes mask insulating layer 46. - Referring to
FIG. 10 , a plurality of wavy-shaped (or curved) bit lines (or first level interconnections) 10A extend in an X direction and are spaced apart from one another at predetermined intervals in a Y direction. Also, straight-line-shaped word lines W are disposed to extend in the Y direction ofFIG. 10 . A plurality of word lines W are disposed at predetermined intervals in the X direction ofFIG. 10 . Each of the plurality of word lines W extends across the active regions K as shown inFIG. 10 . Each of the plurality of word lines W has crossing points that cross over the active regions K. The crossing point of the word line W performs as agate electrode 41 of theMOS transistor 3. Although the present embodiment describes an example where thegate electrode 41 of theMOS transistor 3 is a planar gate electrode, thegate electrode 41 may be modified to a grooved gate electrode. - A plurality of second and
third MOS transistors peripheral circuit region 8 to perform predetermined circuit operations.FIG. 11 shows a plan view of the second andthird MOS transistors peripheral circuit region 8. The present embodiment describes a case where the second andthird MOS transistors - Furthermore, in the
peripheral circuit region 8, active regions K are provided. - The
gate electrode 42 is disposed in thesecond MOS transistor 31 to intersect the active region K defined on thesemiconductor substrate 1 by theelement isolation portion 2. In the present embodiment, thegate electrode 42 of thesecond MOS transistor 31 are independent in its extending direction from the word line W of thememory cell region 7. Also, an N-type impurity is introduced into a region of the active region K that is not covered with thegate electrode 42, thereby forming peripheralcircuit diffusion layers 82A and 82C functioning as a source or drain region. Also, like thesecond MOS transistor 31, thegate electrode 42 extends across the active region K and peripheral circuit diffusion layers 82B and 82D are formed in thethird MOS transistor 32. - The semiconductor device A according to the present embodiment includes first contact plugs 51 a, 51 b, 51 c, 51 d, and 51 e second contact plugs 52 b, 52 c, 52 d, and 52 e and third contact plugs 53 a, 53 b, and 53 c. Also, an example of the semiconductor device A of
FIGS. 1A , 1B, 1C, and 1D further includes fourth contact plugs 54 a, 54 b, 54 c, and 54 d. - Each of the first contact plugs 51 a, 51 b, and 51 c is provided on the memory
cell diffusion layer 72. The second contact plug 52 a, which will be described later, is stacked over the first contact plug 51. Also, the third contact plugs 53 a, which will be described later, are stacked over each of the first contact plugs 51 b and 51 c. Furthermore, each of the first contact plugs 51 b and 51 c has an upper portion that has an upper side surface contacting a firstinterlayer insulating film 11. The remaining portion other than the upper portion of each of the first contact plugs 51 b and 51 c has a side surface that is covered by the sidewall insulating layer 47 a. - The second contact plug 52 a is provided over the
first contact plug 51 a in thememory cell region 7. The first level interconnection 10 (thebit line 10A) is disposed on the second contact plug 52 a and connected to the second contact plug 52 a. Also, the second contact plugs 52 b and 52 c are provided over the peripheral circuit diffusion layers 82 (82A and 82B) of theperipheral circuit region 8. The second contact plugs 52 d and 52 e are provided over thegate electrode 42 of theperipheral circuit region 8. Thesecond MOS transistor 31 includes the firstintermediate interconnection layer 10B which is disposed on thesecond contact plug 52 b and connected to thesecond contact plug 52 b. Thethird MOS transistor 32 includes thethird contact plug 53 b which is stacked over thesecond contact plug 52 c. Also, each of the second contact plugs 52 a, 52 b, 52 c, 52 d, and 52 e has an upper portion that has an upper side surface contacting the firstinterlayer insulating film 11. The remaining portion other than the upper portion of each of the second contact plugs 52 a, 52 b, 52 c, 52 d, and 52 e has a side surface that is covered by a secondinterlayer insulating film 12. - The third contact plug 53 a is formed over the first contact plugs 51 b and 51 c in the
memory cell region 7. A second level interconnection 20 (acapacitance pad 20A) is disposed on the third contact plug 53 a and connected to the third contact plug 53 a. Also, thethird MOS transistor 32 includes thethird contact plug 53 b which is disposed over thesecond contact plug 52 c in theperipheral circuit region 8. Thethird MOS transistor 32 includes the third contact plug 53 c which is disposed over thesecond contact plug 52 e in theperipheral circuit region 8. The secondintermediate interconnection layer 20B is disposed on thethird contact plug 53 b and connected to thethird contact plug 53 b. Further, the secondintermediate interconnection layer 20B is disposed on the third contact plug 53 c and connected to the third contact plug 53 c. Furthermore, the third contact plug 53 a has an upper portion that has an upper side surface contacting a thirdinterlayer insulating film 13. The remaining portion other than the upper portion of the third contact plug 53 a has a side surface that is covered by the firstinterlayer insulating film 11, the secondinterlayer insulating film 12. - The
second MOS transistor 31 of theperipheral circuit region 8 includes the fourth contact plugs 54 a and 54 c provided on the firstintermediate interconnection layer 10B. Athird level interconnection 30 is disposed on the fourth contact plugs 54 a and connected to the fourth contact plug 54 a. Athird level interconnection 30 is disposed on the fourth contact plugs 54 c and connected to thefourth contact plug 54 c. Also, thethird MOS transistor 32 of theperipheral circuit region 8 includes thefourth contact plug intermediate interconnection layer 20B. Thethird level interconnection 30 is disposed on thefourth contact plug 54 b and connected to thefourth contact plug 54 b as the fourth contact plug 54 a. Thethird level interconnection 30 is disposed on thefourth contact plug 54 d and connected to thefourth contact plug 54 d. Furthermore, a side surface of the fourth contact plugs 54 a and 54 c contacts thethird interlayer 13, afourth interlayer 14, and afifth interlayer 15. A side surface of thefourth contact plug interlayer insulating films - The first through fourth contact plugs 51, 52, 53, and 54 may be formed of materials including, but not limited to, the following materials.
- To begin with, the first contact plug 51 may include, for example, polycrystalline silicon (poly-Si) containing impurities, such as P.
- Also, the second contact plug 52 may be formed by sequentially stacking, for example, a titanium (Ti) layer, a titanium nitride (TiN) layer, and a tungsten (W) layer.
- Furthermore, like the second contact plug 52, the third contact plug 53 may be formed by sequentially stacking a Ti layer, a TiN layer, and a W layer. In addition, the third contact plug 53 may include a metal material having a high melting point or a poly-Si layer containing impurities.
- In addition, the fourth contact plug 54 may also be formed by sequentially stacking a Ti layer, a TiN layer, and a W layer.
- Also, the above-described first through
fifth interlayers 11 through 15 may be formed using known materials and structures with no limitations. For example, each of the first throughfifth interlayers 11 through 15 may be formed of a silicon oxide layer. - As described above, the first level interconnection 10 (10A) is formed in the
memory cell region 7 while the first level interconnection 10 (10B) is formed in theperipheral circuit region 8. In addition, as thefirst level interconnection 10, the bit wiring 10A is provided to be connected to memorycell diffusion layer 72 via a stack structure including the first and second contact plugs 51 a and 52 a in thememory cell region 7. In theperipheral circuit region 8, as thefirst level interconnection 10, the firstintermediate interconnection layer 10B is provided to be connected to the peripheralcircuit diffusion layer 82 via thesecond contact plug 52 b. The firstintermediate interconnection layer 10B is provided to be connected to thegate electrode 42 via thesecond contact plug 52 d. - Although the
first level interconnection 10 may be formed by sequentially stacking, for example, a tungsten nitride (tungsten nitride) layer and a W layer, the present embodiment is not limited thereto. Thefirst level interconnection 10 may be formed of another metal layer having a high melting point or a metal silicide layer. - Like the
first level interconnection 10, the second level interconnection 20 (20A) is formed in thememory cell region 7 while the second level interconnection 20 (20B) is formed in theperipheral circuit region 8. As thesecond level interconnection 20, thecapacitor pad 20A is provided to be connected to the memorycell diffusion layer 72 via a stack structure including the first and third contact plugs 51 and 53 in thememory cell region 7. Also, as thesecond level interconnection 20, the secondintermediate interconnection layer 20B is provided to be connected to the peripheralcircuit diffusion layer 82 42 via a stack structure including the second and third contact plugs 52 b and 53 b in theperipheral circuit region 8. The secondintermediate interconnection layer 20B is provided to be connected to the gate electrode via a stack structure including the second and third contact plugs 52 e and 53 c in theperipheral circuit region 8. - The
second level interconnection 20 may be formed using the same material and structure as the above-describedfirst level interconnection 10. - Here, the
second MOS transistor 31 includes the peripheralcircuit diffusion layer 82 connected to the first level interconnection 10 (10B), which is an upper intermediate interconnection layer (a local interconnection layer), via thesecond contact plug 52 b. Also, inFIG. 11 , thethird MOS transistor 32 includes the peripheralcircuit diffusion layer 82B connected to the second level interconnection 20 (a secondintermediate interconnection layer 20B), which is an upper intermediate interconnection layer (a local interconnection layer), via the second and third contact plugs 52 c and 53 b. Furthermore, each of the intermediate interconnection layers (the first andsecond level interconnections 10 and 20) is connected to thethird level interconnection 30 disposed thereon via the fourth contact plugs 54 a and 54 b (the third level interconnection is not shown inFIG. 11 ). - The capacitor 9 is provided over the
capacitor pad 20A, which forms a portion of thesecond level interconnection 20. The capacitor 9 may be formed using known materials and structures used for conventional capacitors with no limitation. The material and structure of the capacitor 9 may be adopted in consideration of general characteristics of a semiconductor device. - In the example of
FIGS. 1A and 1B , the capacitor 9 includes afirst capacitor electrode 91 having aninside surface 91 a, acapacitance insulating layer 92, and asecond capacitor electrode 93. The capacitance insulating layer is provided to cover theinside surface 91 a of thefirst capacitor electrode 91. Thesecond capacitor electrode 93 is provided to cover thecapacitance insulating layer 92 and inside surface 91 a. - As in the above-described construction, the semiconductor device A according to the present embodiment includes the
first level interconnection 10 including thebit line 10A and the firstintermediate interconnection layer 10B which are disposed in thememory cell region 7 and theperipheral circuit region 8, respectively. As thefirst level interconnection 10, thebit line 10A is disposed in thememory cell region 7. As thefirst level interconnection 10, the firstintermediate interconnection layer 10B is disposed in theperipheral circuit region 8. The firstintermediate interconnection layer 10B is connected via thesecond contact plug 52 b to the peripheralcircuit diffusion layer 82 of thesecond MOS transistor 31. The firstintermediate interconnection layer 10B is connected via thesecond contact plug 52 d to thegate electrode 42 of thesecond MOS transistor 31. Furthermore, in thememory cell region 7, thefirst level interconnection 10 forming thebit line 10A is connected to the memorycell diffusion layer 72 of thefirst MOS transistor 3 via the second contact plug 52. In addition, thesecond level interconnection 20 includes thecapacitance pad 20A and the secondlevel interconnection layer 20B which are disposed in thememory cell region 7 and theperipheral circuit region 8, respectively. The secondintermediate interconnection layer 20B is connected to the peripheralcircuit diffusion layer 82 of thethird MOS transistor 32 via a stack structure of the second and third contact plugs 52 b and 53 b. The secondintermediate interconnection layer 20B is connected to thegate electrode 42 of thethird MOS transistor 32 via a stack structure of the second and third contact plugs 52 e and 53 c. - The above-described structure allows reducing the circuit area in the
peripheral circuit region 8 in the semiconductor device A, such as a DRAM device. Shrinkage of the semiconductor device A can be obtained. Horizontal dimensions of the semiconductor device A can be reduced. - <Method of Fabricating Semiconductor Device>
- Hereinafter, a method of fabricating the semiconductor device A according to the present embodiment will be described with reference to
FIGS. 2A through 9A and 2B through 9B (andFIGS. 1A , 1B, 10, and 11). -
FIGS. 2A , 3A, 4A, 5A, 6A, 7A, 8A and 9A are cross-sectional views taken along line D-D′ of thememory cell region 7 shown in the plan view ofFIG. 10 . FIGS. 2B, 3B, 4B, 5B, 6B, 7B, 8B, and 9B are cross-sectional views taken along line B-B′ of theperipheral circuit region 8 shown in the plan view ofFIG. 11 . In addition, unless defined otherwise, it is assumed that thememory cell region 7 and theperipheral circuit region 8 are processed at the same time. - Initially, the method of fabricating the semiconductor device A according to the present embodiment includes the following semiconductor-substrate forming process (1). The
element isolation portion 2 is formed to isolate the active regions K from each other over thesemiconductor substrate 1. Thegate electrode 4 formed over the corresponding active region K using a patterning process. The impurity is doped into a portion of thesemiconductor substrate 1 in a self-aligned manner using thecorresponding gate electrode 4 as a mask. During the semiconductor-substrate forming process (1), according to the above-described order, the memory cell diffusion layer (first source and drain regions) 72 forming thememory cell region 7 and the peripheral circuit diffusion layer (second and third source and drain regions) 82 forming theperipheral circuit region 8 are formed. Accordingly, a plurality of regions constituting the first through third metal-oxide-semiconductor (MOS)transistors cell diffusion layer 72 and theperipheral circuit region 8 may be separately doped with an impurity. - Next, in the present embodiment, an electrode-forming process (2) is performed as follows. A first
interlayer insulating film 11 is formed by embedding an insulating layer between gate electrodes 4 (41 and 42). Afirst contact hole 11 a is formed in the firstinterlayer insulating film 11 to expose a top surface of the memorycell diffusion layer 72 in thememory cell region 7. First contact plugs 51 a, 51 b, and 51 c are formed over the memorycell diffusion layer 72 to fill thefirst contact hole 11 a. In the electrode-forming process (2), a secondinterlayer insulating film 12 is formed to cover the surfaces of the first contact plugs 51 a, 51 b, and 51 c formed in the above-described order and the firstinterlayer insulating film 11. Further, asecond contact 12 a is formed through the secondinterlayer insulating film 12 to expose a surface of thefirst contact plug 51 a. Second contact holes 12 b are formed in the secondinterlayer insulating film 12 and the firstinterlayer insulating film 11 to expose surfaces of the peripheralcircuit diffusion layers circuit diffusion layer 82B to fill the second contact hole 12 b in theperipheral circuit region 8. A second contact plug 52 a is formed over thefirst contact plug 51 a to fill thesecond contact hole 12 a in thememory cell region 7. - Next, in the present embodiment, a first-interconnection forming process (3) is performed as follows. The
first level interconnection 10 is formed as thebit line 10A connected to the second contact plug 52 a in thememory cell region 7 by stacking a first level interconnection material to cover the secondinterlayer insulating film 12 and the second contact plugs 52 a, 52 b, and 52 c. Then, the first level interconnection material is patterned. Also, in the first-interconnection forming process (3), thefirst level interconnection 10 is formed in thememory cell region 7 while thefirst level interconnection 10 in theperipheral circuit region 8 is formed. - Next, in the present embodiment, a second-electrode forming process (4) is performed as follows. The third
interlayer insulating film 13 is formed over thefirst level interconnection 10. Third contact holes 13 a is formed in thethird interlayer 13 and the secondinterlayer insulating film 12 in thememory cell region 7 to expose surfaces of the first contact plugs 51 b and 51 c. Athird contact hole 13 b is formed in thethird interlayer 13 in theperipheral circuit region 8 to expose a surface of thesecond contact plug 52 b. Also, in the second-electrode forming process (4), third contact plugs 53 a and 53 b are formed over the first contact plugs 51 b and 51 c of thememory cell region 7, respectively. The second contact plugs 52 c of theperipheral circuit region 8 are formed to fill the third contact holes 13 a and 13 b, respectively, which are formed in the above-described order. - The method of fabricating the semiconductor device A according to the present embodiment includes the following second-interconnection forming process (5). As the
second level interconnection 20, thecapacitor pad 20A is formed to be connected to the third contact plug 53 a in thememory cell region 7 by stacking an interconnection material to cover thethird interlayer 13 and then patterning the interconnection material. Also, during the second-interconnection forming process 5, thesecond level interconnection 20 is formed in thememory cell region 7 while thesecond level interconnection 20 in theperipheral circuit region 8 is formed. - The method of fabricating the semiconductor device A according to the present embodiment includes the respective processes (1) through (5) in at least the above-described order. Also, in the present embodiment, an example will now be described of a method of fabricating the semiconductor device A. The process (5) is followed by a capacitor forming process (6) and a third-interconnection forming process (7) subsequently.
- Hereinafter, each of the processes (1) through (7) will be described in detail. Each of the processes (1) through (7) may optionally be included in the method of fabricating the semiconductor device A according to the present embodiment.
- <Semiconductor-
Substrate Forming Process 1> - The semiconductor-substrate forming process includes the following processes. The
element isolation portion 2 is formed over thesemiconductor substrate 1 to isolate the active regions K from each other. The gate electrode 4 (41 and 42) is formed over the corresponding active region K using a patterning process. The impurity is doped into a portion of thesemiconductor substrate 1 in a self-aligned manner using thegate electrode 4 as a mask. Thus, the memorycell diffusion layer 72 forming amemory cell region 7 and the peripheralcircuit diffusion layer 82 forming aperipheral circuit region 8 are formed. A plurality of regions for first throughthird MOS transistors - Specifically, as shown in
FIGS. 2A and 2B , first, theelement isolation portion 2 is formed over thesemiconductor substrate 1 to isolate the active regions K from each other using a shallow-trench-isolation (STI) technique (refer toFIG. 10 ). Although a P-type silicon substrate is used as thesemiconductor substrate 1, the present embodiment is not limited thereto. For example, a Ge-containing semiconductor substrate may be used as thesemiconductor substrate 1. - Thereafter, although not specifically shown, a
gate insulating layer 45 including a silicon oxide (SiO2) layer, agate electrode 4 including a conductive layer, and a gatemask insulating layer 46 including a silicon nitride (Si3N4) layer are sequentially formed over the active regions K. Subsequently, the stack structure is patterned, thereby forming the stacked structure having thegate insulating layer 45, the gate electrode 4 (41 and 42), and the gatemask insulating layer 46 stacked in this order. In this case, for example, thegate insulating layer 45 with a thickness of about 5 nm may be formed. Thegate electrode 4 with a thickness of about 150 nm may be formed. The gate mask insulatinglayer 46 with a thickness of about 100 nm may be formed. In addition, when a groove-type gate electrode is formed in thememory cell region 7, processes of forming the gate electrodes are separately performed in thememory cell region 7 and theperipheral circuit region 8. - Thereafter, an N-type impurity, such as P ion, is introduced into the
semiconductor substrate 1 in a self-aligned manner using thegate electrode 4 as a mask. The memorycell diffusion layer 72 is formed in thememory cell region 7. The peripheralcircuit diffusion layer 82 is formed in theperipheral circuit region 8. Here, each of the peripheral circuit diffusion layers 82 (82A and 82B) functions as the source or drain region (second and third source and drain regions) of the first andsecond MOS transistors peripheral circuit region 8, respectively. - In this case, one of the
memory cell region 7 and theperipheral circuit region 8 may be covered with a mask using a photoresist layer. An impurity may be introduced using several ion implantation processes such that the impurity concentration of the memorycell diffusion layer 72 is different from that of the peripheralcircuit diffusion layer 82. - Thereafter, a
sidewall insulating layer 47 including a silicon nitride layer is formed on side surfaces of thegate electrodes sidewall insulating layer 47 has a thickness of, for example, about 50 nm. Also, after forming thesidewall insulating layer 47, an N-type impurity, such as As ions, may be introduced into the active regions K, thereby forming LDD regions. - The word line W extends in the X direction of
FIG. 10 . The word line W has crossing points that cross over the active regions K. The crossing point of the word line W performs as thegate electrode 41 of theMOS transistor 3 in thememory cell region 7. The word line W has been formed during the foregoing semiconductor-substrate forming process, - Also, the second and
third MOS transistors element isolation portion 2 interposed therebetween in theperipheral circuit region 8. In the present embodiment, inFIG. 2B , thesecond MOS transistor 31 has the peripheralcircuit diffusion layer 82A as second source or drain region, and thethird MOS transistor 32 has the peripheralcircuit diffusion layer 82B as third source and drain regions. Furthermore, an element isolation width R1 may be, for example, about 60 nm in theperipheral circuit area 8. - <First-
Electrode Forming Process 2> - Next, in the first-electrode forming process, an insulating layer is buried between the gate electrodes 4 (41 and 42) to form the first
interlayer insulating film 11. Thefirst contact hole 11 a is formed in the firstinterlayer insulating film 11 in thememory cell region 7 to expose a top surface of the memorycell diffusion layer 72. Then, the first contact plugs 51 a, 51 b, and 51 c are formed over the memorycell diffusion layer 72 to fill the first contact hole ha. Next, the secondinterlayer insulating film 12 is formed to cover the surfaces of the first contact plugs 51 a, 51 b, and 51 c and the firstinterlayer insulating film 11. Thesecond contact hole 12 a is formed in the secondinterlayer insulating film 12 to expose a top surface of thefirst contact plug 51 a. The second contact hole 12 b is formed in the secondinterlayer insulating film 12 and the firstinterlayer insulating film 11 to expose a top surface of the peripheralcircuit diffusion layer 82. Also, second contact plugs 52 b and 52 c are formed over the peripheralcircuit diffusion layer peripheral circuit region 8 to fill the second contact hole 12 b while a second contact plug 52 a is formed over thefirst contact plug 51 a in thememory cell region 7 to fill thesecond contact hole 12 a. - Specifically, as shown in
FIGS. 3A and 3B , an insulating layer, such as a silicon oxide layer, is initially buried between thegate electrodes interlayer insulating film 11. Thereafter, the firstinterlayer insulating film 11 is planarized using a chemical mechanical polishing (CMP) technique. In this case, the firstinterlayer insulating film 11 is formed to a height (or thickness) of, for example, about 500 nm, from a surface 1 a of thesemiconductor substrate 1. - Next, the first contact plugs 51 a, 51 b, and 51 c connected to the memory
cell diffusion layer 72 through the firstinterlayer insulating film 11 are formed of, for example, poly-Si containing impurities, in thememory cell region 7. In this case, positions of the first contact plugs 51 a, 51 b, and 51 c correspond to referencenumerals FIG. 10 . - A
bit line 10A (the first level interconnection 10) is connected to thefirst contact plug 51 a disposed in the center of the active region K during the first-interconnection forming process that will be described later. Also, a capacitor 9 formed by a capacitor-device forming process is connected to the first contact plugs 51 b and 51 c via a third contact plug 53 a and acapacitance pad 20A (a second level interconnection 20), which will be described later. The first contact plugs 51 b and 51 c are disposed on both sides of the active region K. In addition, the formation of the first contact plugs 51 a, 51 b, and 51 c may be performed by a self-alignment-contact (SAC) technique using a difference in etch rate between the gate mask insulating layers 45 a and 45 b and the sidewall insulating layers 47 a and 47 b, and the firstinterlayer insulating film 11. - Afterwards, as shown in
FIGS. 4A and 4B , the secondinterlayer insulating film 12 includes a silicon oxide layer is formed to cover the surfaces of the first contact plugs 51 a, 51 b, and 51 c and the firstinterlayer insulating film 11. In this case, the secondinterlayer insulating film 12 with a thickness of, for example, about 100 nm may be formed. - Thereafter, the
second contact hole 12 a is formed in the secondinterlayer insulating film 12 in thememory cell region 7 to expose a top surface of thefirst contact plug 51 a. Subsequently, a second contact hole 12 b is formed in the secondinterlayer insulating film 12 and the firstinterlayer insulating film 11 to expose top surfaces of the peripheralcircuit diffusion layers peripheral circuit region 8. In this case, thesecond contact hole 12 a of thememory cell region 7 is formed to a small depth of about 100 nm so as not to reach thegate electrode 41 or thesemiconductor substrate 1, while the second contact hole 12 b of theperipheral circuit region 8 is formed to a great depth of about 600 nm, which is different from the depth of thesecond contact hole 12 a of thememory cell region 7. To do this, it is preferable for the second contact holes 12 a and 12 b to be formed by separately performing a photolithography process and a dry etching process on thememory cell region 7 and theperipheral circuit region 8. - Next, a Ti layer, a TiN layer, and a W layer are sequentially formed to fill the second contact holes 12 a and 12 b and cover the second
interlayer insulating film 12. Next, the W layer, the TiN layer, and the Ti layer formed over the secondinterlayer insulating film 12 are removed using a CMP technique, thereby forming a second contact plug 52 a in thememory cell region 7 and forming second contact plugs 52 b and 52 c in theperipheral circuit region 8. In addition, materials of the second contact plugs 52 a, 52 b, and 52 c are not limited thereto and may be formed of another metal material having a high melting point or a poly-Si layer containing impurities. Also, the formation of the second contact plugs 52 a and 52 b may be performed using an etch-back technique instead of the CMP technique. In theperipheral circuit region 8, the second contact plug connected to the peripheralcircuit diffusion layer 82A is indicated byreference numeral 52 b. The second contact plug connected to the peripheralcircuit diffusion layer 82B is indicated byreference numeral 52 c. When the first level interconnection is connected to thegate electrode 42 of theperipheral circuit region 8, the second contact plug is prepared on thegate electrode 42 as well. - The second contact plugs 52 b and 52 c are disposed to have a diameter and interval equal to the width R1 of the
element isolation portion 2 to minimize a contact pitch. Namely, a distance between the peripheralcircuit diffusion layers element isolation portion 2 contacts with the peripheralcircuit diffusion layers interlayer insulating film 11 and the secondinterlayer insulating film 12 between the second contact plugs 52 b and 52 c are aligned to theelement isolation portion 2. Thus, a pitch between adjacent second contact plugs 52 b and 52 c is given by 2×R1=120 nm so that the second contact plugs 52 b and 52 c can be densely disposed in a lateral direction ofFIG. 4B . In addition, the second contact plugs 52 b and 52 c arranged in rows in a vertical direction in the plan view ofFIG. 11 are connected to the same peripheral circuit diffusion layer. Hence, it is more preferable for the second contact plugs 52 b and 52 c arranged in rows in a vertical direction in the plan view ofFIG. 11 to be disposed at such a pitch as to satisfy contact resistance of contact plugs in a circuit operation. - <First-
Interconnection Forming Process 3> - Next, the first-interconnection forming process will be explained. First, the
first level interconnection 10 is formed as abit line 10A connected to the second contact plug 52 a in thememory cell region 7. The first level interconnection material is stacked to cover the secondinterlayer insulating film 12 and the second contact plugs 52 a and 52 b and then patterning the first level interconnection material. Further, thefirst level interconnection 10 is formed as a firstintermediate interconnection layer 10B connected to any one of thesecond contact plug 52 b and thegate electrode 42 in theperipheral circuit region 8. Thefirst level interconnection 10 is provided in thememory cell region 7 as thebit line 10A and in theperipheral circuit region 8 as the firstintermediate interconnection layer 10B. - Specifically, as shown in
FIGS. 5A and 5B , first, an interconnection material is formed (refer to the first level interconnection 10). In this case, although the interconnection material may be formed by sequentially depositing a WN layer and a W layer, the interconnection material is not limited thereto. For example, the interconnection material may be another metal layer having a high melting point or a metal silicon layer. Also, the interconnection material with a thickness of, for example, about 100 nm may be formed. - Thereafter, the interconnection material is patterned using photolithography and dry etching techniques, thereby forming the
first level interconnection 10. In this case, thefirst level interconnection 10 includes thebit line 10A connected to the surface of the second contact plug 52 a in thememory cell region 7. Also, thefirst level interconnection 10 includes the firstintermediate interconnection layer 10B connected to the surface of thesecond contact plug 52 b in theperipheral circuit region 8. Furthermore, the patterning process is performed not to form the first level interconnection 10 (the firstintermediate interconnection layer 10B) on thesecond contact plug 52 c. - Here, the patterning of the
first level interconnection 10, that is, thebit line 10A and the firstintermediate interconnection layer 10B, may be simultaneously performed using one photomask in both thememory cell region 7 and theperipheral circuit region 8. - As described above, the first level interconnection 10 (the
bit line 10A) formed in thememory cell region 7 functions as a bit line and has a pattern that extends in zigzag in the X direction from the plan view ofFIG. 10 . - Also, the first level interconnection 10 (the first
intermediate interconnection layer 10B) formed in theperipheral circuit region 8 functions as an intermediate interconnection layer electrically connected to the peripheral circuit diffusion layer 82(82A). The firstintermediate interconnection layer 10B has a strip-shaped pattern that extends in a vertical direction from the plan view ofFIG. 11 . - Also, the interconnection material formed on the surface of the
second contact plug 52 c is removed by etching process to expose the surface of thesecond contact plug 52 c. Here, when thefirst level interconnection 10 is formed of the same material as the second contact plug 52, the surface of thesecond contact plug 52 c is over-etched during the patterning of thefirst level interconnection 10. The surface of thesecond contact plug 52 c may be recessed. In this case, the etching process of thefirst level interconnection 10 is performed by adjusting an over-etched amount such that a recessed amount is generally 200 nm or less. - A width w11 of the first
intermediate interconnection layer 10B ensures a one-side margin δ11 to prevent thefourth contact plug 54 b formed over the firstintermediate interconnection layer 10B from deviating from the firstintermediate interconnection layer 10B during a subsequent third-interconnection forming process. Namely, the firstintermediate interconnection layer 10B partly overlaps theelement isolation portion 2 in plan view. For instance, when thefourth contact plug 54 b is formed to have a diameter equal to the width R1 of the above-describedelement isolation portion 2, the width w11 is given by an equation {w11−R1+2×δ11}. The margin δ11 may be determined in consideration of first, second, and third maximum values. The first maximum value is a maximum value of a position adjustment deviation amount between fourth contact holes 14 a and 14 b (refer toFIG. 9B ), which will be described later, and thefirst level interconnection 10. The second maximum value is a maximum value of a dimension difference of the fourth contact holes 14 a and 14 b. The third maximum value is a maximum value of a dimension difference of thefirst level interconnections 10. Also, it is experimentally preferable for the margin δ11 to have a minimum value equivalent to about ⅓ the width R1 of theelement isolation portion 2. In this case, the margin δ11 is given by (5/3)×R1 or more. The margin δ11 is given about 20 nm or more when the width R1 is 60 nm. - Furthermore, although a margin δ12 is ensured between the first
intermediate interconnection layer 10B and thesecond contact plug 52 c to prevent the occurrence of an electrical short circuit, the margin δ12 is preferably set at a minimum value of 20 nm or more like the margin δ11. In the present embodiment, the second contact plugs 52 b and 52 c are formed at an interval equal to the width R1 (=60 nm). Thus, each of the margins δ11 and δ12 may preferably be set to a minimum value equal to the width R1. For example, the margin δ11 may be set to a minimum value of about 25 nm, and the margin δ12 may be set to a minimum value of about 35 nm. Accordingly, each of the margins δ11 and δ12 may preferably be set at a minimum value of about 20 nm or more. - As described above, even if adjacent second contact plugs 52 a and 52 c are disposed at an interval equal to the width R1 of the
element isolation portion 2, it is acceptable for the firstintermediate interconnection layer 10B to partially overlap theelement isolation portion 2 in view of avoiding the firstintermediate interconnection layer 10B to contact the secondintermediate interconnection layer 20B which will be formed later. - <Second-
Electrode Forming Process 4> - Next, in the second-electrode forming process, first, the
third interlayer 13 is formed over thefirst level interconnection 10. The third contact holes 13 a and 13 b are formed in thememory cell region 7 and theperipheral circuit region 8, respectively. Thethird contact hole 13 a is formed in thethird interlayer 13 and the secondinterlayer insulating film 12 to expose top surfaces of the first contact plugs 51 b and 51 c in thememory cell region 7. Thethird contact hole 13 b is formed in thethird interlayer 13 to expose a top surface of thesecond contact plug 52 b in theperipheral circuit region 8. Subsequently, the third contact plugs 53 a and 53 b are formed in thememory cell region 7 and theperipheral circuit region 8, respectively. The third contact plug 53 a is formed on the first contact plugs 51 b and 51 c to fill thethird contact hole 13 a, and thethird contact plug 53 b is formed over thesecond contact plug 52 b to fill thethird contact hole 13 b. - Specifically, as shown in
FIGS. 6A and 6B , a material forming thethird interlayer 13, such as a silicon oxide layer, is initially deposited over thefirst level interconnection 10. Thereafter, the material forming thethird interlayer 13 is polished using a CMP method and planarized. Thethird interlayer 13 with a thickness of about 400 nm is formed on the secondinterlayer insulating film 12. - Thereafter, third contact holes 13 a are formed in the
third interlayer 13 and the secondinterlayer insulating film 12 in thememory cell region 7 to expose the insides of the first contact plugs 52 b and 51 c while athird contact hole 13 b is formed in thethird interlayer 13 in theperipheral circuit region 8 to expose the inside of thesecond contact plug 52 c. In this case, no contact hole is formed over thesecond contact plug 52 b. Since there is only a small difference in depth between the third contact holes 13 a and 13 b formed in thememory cell region 7 and theperipheral circuit region 8 during the present process, the third contact holes 13 a and 13 b may be simultaneously formed in thememory cell region 7 and theperipheral circuit region 8. - Afterwards, a Ti layer, a TiN layer, and a W layer are sequentially formed to fill the third contact holes 13 a and 13 b and simultaneously cover the second
interlayer insulating film 12. In this case, the present embodiment is not limited to the above-described materials and a metal material having a high melting point or a doped silicon layer may be employed. - The W layer, the TiN layer, and the Ti layer formed over the
third interlayer 13 are removed using a CMP technique, thereby forming third contact plugs 53 a and 53 b in thememory cell region 7 and theperipheral circuit region 8, respectively. Also, the formation of the third contact plugs 53 a and 53 b may be performed using an etch-back process. Furthermore, thethird contact plug 53 b is stacked directly on thesecond contact plug 52 c not to contact the adjacent firstintermediate interconnection layer 10B in theperipheral circuit region 8. In addition, thethird contact plug 53 b may be formed to have an outer diameter equal to or less than the outer diameter of thesecond contact plug 52 c to prevent the occurrence of an electrical short circuit between thethird contact plug 53 b and the firstintermediate interconnection layer 10B. - In the present embodiment, when the third contact plugs 53 a and 53 b are formed on the first and second contact plugs, the third contact plugs 53 a and 53 b are directly on the first and second contact plugs without forming connection pads on the first and second contact plugs. When the
third interlayer 13 has a thickness of about 400 nm, even if thethird interlayer 13 is over-etched by 50% of the thickness of thethird interlayer 13 during the etching process for forming the third contact holes 13 a and 13 b, an over-etched amount of thethird interlayer 13 corresponds to about 200 nm. Accordingly, even if the third contact holes 13 a and 13 b are deviated from the surfaces of the underlying contact plugs due to a position difference, the third contact plugs 13 a and 13 b do not reach the surface 1 a of thesemiconductor substrate 1. Furthermore, since the top and side surfaces of thegate electrodes gate electrodes - <Second-Interconnection Forming Process 5>
- Next, in the second-interconnection forming process, a
second level interconnection 20 is formed as acapacitance pad 20A for a capacitor connected to the third contact plug 53 a in thememory cell region 7. Thesecond level interconnection 20 is formed as follows. An interconnection material is stacked to cover thethird interlayer 13. Then, the interconnection material is patterned. Further, thesecond level interconnection 20 is formed as a secondintermediate interconnection layer 20B connected to any one of thethird contact plug 53 b and thegate electrode 42 in theperipheral circuit region 8. Also, when thesecond level interconnection 20 is connected to thegate electrode 42 of theperipheral circuit region 8, each contact plug is disposed to be connected to thegate electrode 42 via thethird contact plug 53 b and thesecond contact plug 52 b. - Specifically, as shown in
FIGS. 7A and 7B , an interconnection material (refer to thesecond level interconnection 20 inFIGS. 7A and 7B ) is formed over thethird interlayer 13. In this case, like thefirst level interconnection 10, the interconnection material is formed by sequentially depositing a TiN layer and a W layer. Also, as thefirst level interconnection 10, the interconnection material is not limited to the above-described materials and may be, for example, another metal layer having a high melting point or a metal silicide layer. Also, the interconnection material with a thickness of, for example, about 100 nm may be formed. - Next, the interconnection material is patterned using photolithography and dry etching techniques, thereby forming the
second level interconnection 20. In this case, thecapacitance pad 20A, which is a portion of thesecond level interconnection 20, is formed in thememory cell region 7 and contacts the surface of the third contact plug 53 a. Also, the secondintermediate interconnection layer 20B, which is another portion of thesecond level interconnection 20, is formed in theperipheral circuit region 8 and contacts the surface of thethird contact plug 53 b. Furthermore, the patterning of thecapacitance pad 20A and the firstintermediate interconnection layer 20B that form thesecond level interconnection 20 may be simultaneously performed using one photomask both in thememory cell region 7 and theperipheral circuit region 8. - The second level interconnection 20 (the
capacitance pad 20A) formed in thememory cell region 7 functions as a capacitance pad configured to connect the third contact plug 53 a with a capacitor 9 that will be described later. By preparing thecapacitance pad 20A for the capacitor, the capacitor 9 having a bottom size greater than the diameter of the surface of the third contact plug 53 a may be disposed. Also, it becomes easy to control positions of adjacent capacitors 9 and equalize intervals between the adjacent capacitors 9 in order to optimize the positions where the capacitors 9 are disposed. - In addition, the second level interconnection 20 (the second
intermediate interconnection layer 20B) formed in the peripheral circuit region functions as an intermediate interconnection layer electrically connected to the peripheralcircuit diffusion layer 82B. As can be seen from the plan view ofFIG. 11 , the secondintermediate interconnection layer 20B in theperipheral circuit region 8 is formed as a strip-shaped pattern extending in the vertical direction. Also, a width w21 of the secondintermediate interconnection layer 20B is preferably set in consideration of the margin δ21 between the secondintermediate interconnection layer 20B and thethird contact plug 53 b. For example, the width w21 of the secondintermediate interconnection layer 20B may be set to be equal to the width w11 of the firstintermediate interconnection layer 10B. Here, the secondintermediate interconnection layer 20B is formed to partially overlap theelement isolation portion 2. - <Capacitor-Device Forming Process 6>
- Next, during the capacitor-device forming process, the capacitor 9 is formed over the second level interconnection 20 (the
capacitance pad 20A for the capacitor) formed over the third contact plug 53 a in thememory cell region 7 using the second-interconnection forming process (5). - Furthermore, in the present embodiment, a
fourth interlayer 14 is stacked over thesecond level interconnection 20 and thethird interlayer 13. Acapacitor contact hole 14 a is formed in thefourth interlayer 14 to expose a top surface of thecapacitance pad 20A in thememory cell region 7. Afterwards, afirst capacitor electrode 91 is formed to cover thecapacitance pad 20A, which is exposed by the sidewalls and inside of thecapacitor contact hole 14 a. Thefirst capacitor electrode 91 is cylindrical shaped. Next, thecapacitance insulating layer 92 is formed to cover theinside surface 91 a of thefirst capacitor electrode 91 and thefourth interlayer 14. Asecond capacitor electrode 93 is formed to cover thecapacitance insulating layer 92 and fill the inside of thecapacitor contact hole 14 a. An example of the above-described processes will now be described. - Specifically, as shown in
FIGS. 8A and 8B , thefourth interlayer 14 is formed of a silicon oxide layer over thethird interlayer 13 and the second level interconnection 20 (thecapacitance pad 20A for the capacitor and the secondintermediate layer 20B). In this case, thefourth interlayer 14 is preferably formed to a great thickness to ensure a sufficient capacitance of the capacitor 9 disposed in thememory cell region 7. For example, thefourth interlayer 14 with a thickness of, for example, about 2 μm is preferably formed. - Next, a
capacitor contact hole 14 a is formed in thefourth interlayer 14 in thememory cell region 7 to expose the inside of thecapacitance pad 20A. - A first capacitor electrode material (refer to the
first capacitor electrode 91 inFIG. 8A ) is formed to cover thecapacitance pad 20A exposed by the side surface and inside of thecapacitor contact hole 14 a and thefourth interlayer 14. In this case, although the first capacitor electrode material may be formed of for example, a TN layer, the present embodiment is not limited thereto. The first capacitor electrode material may be another metal layer having a high melting point. - Thereafter, the first capacitor electrode material formed over the
fourth interlayer 14 is removed using a CMP method, thereby forming a first capacitor electrode (a lower electrode) 91 to cover thecapacitance pad 20A exposed by the side surface and inside of thecapacitor contact hole 14 a. - Next, the
capacitance insulating layer 92 is formed to cover the surface of theinside surface 91 a of thefirst capacitor electrode 91 and thefourth interlayer 14. Thecapacitance insulating layer 92 may be formed of a high-dielectric (high-k) layer, such as a zirconium oxide (ZrO2) layer, a hafnium oxide (HIO2) layer, and an aluminum oxide (Al2O5) layer, or a stack layer thereof. - A second capacitor electrode material (refer to a
second capacitor electrode 93 ofFIG. 8A ) is formed to cover the surface of thecapacitance insulating layer 92 and theinside surface 91 a of thefirst capacitor electrode 91 within thecapacitor contact hole 14 a. In this case, the second capacitor electrode material may be, for example, a TiN layer. Alternatively, the formation of the second capacitor electrode material may include forming a TiN layer to such a thickness so as not to cover theinside surface 91 a of thefirst capacitor electrode 91 and stacking another material, for example, poly-Si or W over theinside surface 91 a of thefirst capacitor electrode 91. - In addition, although the present embodiment describes the cylindrical capacitor as an example of the capacitor 9, the present embodiment is not limited thereto. For example, the
first capacitor electrode 91 may be modified to a crown or pillar shape. - Thereafter, the second capacitor electrode material is patterned using photolithography and etching techniques, thereby forming the second capacitor electrode (a lower electrode) 93. As a result, the capacitor 9 including the
first capacitor electrode 91, thecapacitance insulating layer 92, and thesecond capacitor electrode 93 is formed in thememory cell region 7. Also, thesecond capacitor electrode 93 is formed to cover thememory cell region 7 and functions as a plate electrode configured to apply a predetermined electric potential to the capacitor 9. Also, thefirst capacitor electrode 91 is in contact with thecapacitance pad 20A, which forms a portion of thesecond level interconnection 20, so that the capacitor 9 can be connected to afirst MOS transistor 3. - Moreover, the second capacitor electrode material and the capacitance insulating layer are removed from the
peripheral circuit region 8. - <Third-
Interconnection Forming Process 7> - Next, in the third-interconnection forming process, first, the fourth contact holes 14 b and 14 c are formed in the
fourth interlayer 14 to expose a top surface of the firstintermediate interconnection layer 10B or the secondintermediate interconnection layer 20B in theperipheral circuit region 8. The fourth contact plugs 54 a and 54 b are formed over the first and second intermediate interconnection layers 10B and 20B to fill the fourth contact holes 14 b and 14 c. Afterwards, an interconnection material is stacked to cover thefourth interlayer 14 and the fourth contact plugs 54 a and 54 b and patterned. Thethird level interconnection 30 connected to the firstintermediate interconnection layer 10B (the first level interconnection 10) or the secondintermediate interconnection layer 20B (the second level interconnection 20) via the fourth contact plugs 54 a and 54 b can be formed. - Specifically, as shown in
FIGS. 9A and 9B , first, the fifthinterlayer insulating film 15 is formed of a silicon oxide layer to cover thesecond capacitor electrode 93. In this case, the surface of the fifthinterlayer insulating film 15 is planarized using a CMP method so that the fifthinterlayer insulating film 15 with a thickness of, for example, about 400 nm can be formed. - Next, in the
peripheral circuit region 8, the fourth contact holes 14 b and 14 c are formed in the fifthinterlayer insulating film 15, the fourthinterlayer insulating film 14, and the thirdinterlayer insulating film 13 to expose the firstintermediate interconnection layer 10B and the secondintermediate interconnection layer 20B, respectively. The firstintermediate interconnection layer 10B forms a portion of thefirst level interconnection 10. The secondintermediate interconnection layer 20B forms a portion of thesecond level interconnection 20. Here, an etching process for forming the fourth contact holes 14 b and 14 c is preferably performed in consideration of a difference in interlayer thickness and a difference in etch rate. As for the conditions of the etching process, it is preferable that about 30% of the total thickness of the interlayer insulatingfilms intermediate interconnection layer 10B. In this case, the secondintermediate interconnection layer 20B is over-etched during the formation of thefourth contact hole 14 c penetrating the fourthinterlayer insulating film 14 since the secondintermediate interconnection layer 20B is disposed at a higher level than the firstintermediate interconnection layer 10B. In the present embodiment, for example, a conductive material forming the secondintermediate interconnection layer 20B (the second level interconnection 20) is selected under such a condition as to selectively etch an insulating layer (a silicon oxide layer) forming thefourth interlayer 14. Thus, the fourth contact holes 14 b and 14 c may be formed without causing problems. - Also, since the first
intermediate interconnection layer 10B ensures the margin δ11 and the secondintermediate interconnection layer 20B ensures the margin δ21, even if differences in positions where the fourth contact holes 14 b and 14 c are formed occur, deviation of the first and second intermediate interconnection layers 10B and 20B may be prevented or reduced. - Also, as shown in
FIGS. 1A and 1B , the method of fabricating the semiconductor device according to the present embodiment includes filling the fourth contact holes 14 b and 14 c with a conductive material, thereby forming the fourth contact plugs 54 a and 54 b connected to the first and second intermediate interconnection layers 10B and 20B, respectively. In this case, a Ti layer, a TiN layer, and a W layer are sequentially deposited as the conductive material and processed using a CMP technique so that the conductive material left within the fourth contact holes 14 b and 14 c can serve as the fourth contact plugs 54 a and 54 b. - Subsequently, according to the present process, as shown in
FIGS. 1A and 1B , thethird level interconnection 30 connected to the fourth contact plugs 54 a and 54 b is formed of, for example, aluminum (Al) or copper (Cu). In this case, the formation of thethird level interconnection 30 may be performed using a known conventional method with no limitations. Also, thethird level interconnection 30 may be formed by a conventional known method with no limitations. Furthermore, thethird level interconnection 30 is not limited to the above-described materials and may be appropriately formed of a conventional contact material. - Also, a surface protection layer (not shown) is formed of, for example, a silicon oxynitride (SiON) layer on the surface of the stack structure shown in
FIGS. 1A and 1B , thereby completing the fabrication of a DRAM device as the semiconductor device A. - In addition, in the present embodiment, another metal interconnection layer may be further disposed over the
third level interconnection 30 if required. -
FIGS. 14A and 14B are cross-sectional views of a semiconductor device 100 according to a comparative example of the semiconductor device A of the present embodiment. Hereinafter, the comparison of the semiconductor device 100 with the semiconductor device A will be described with reference toFIGS. 14A and 14B . - In the semiconductor device 100 of
FIGS. 14A and 14B according to the comparative example, only a bit line (a first level interconnection) 110A of amemory cell region 107 is disposed as an intermediate interconnection layer in aperipheral circuit region 108. - The semiconductor device 100 has the
memory cell region 107 in common with the semiconductor device A according to the first embodiment of the present invention. Also, in theperipheral circuit region 108, peripheralcircuit diffusion layers 182A and 182B functioning as second and third source or drain regions of second andthird MOS transistors 131 and 132 are connected to a third level interconnection 130 by a fourth contact plug 154 a via afirst level interconnection 110B. - An interval R3 between adjacent
first level interconnections 110B is determined by the resolution of an applied photolithography technique. In an advanced DRAM device, when a device miniaturized to approximately the resolution limit of the photolithography technique is processed, a width R1 of anelement isolation portion 102 and an interval R3 between thefirst level interconnections 110B is about the same minimum value equivalent to the resolution limit. Consequently, further reducing the width R1 and the interval R3 is difficult. Meanwhile, to prevent the formation of an electrical short circuit between the fourth contact plug 154 a and thesemiconductor substrate 101 due to a position deviation of the fourth contact plug 154 a, it is necessary to prepare the margin δ11 in asecond contact plug 152 b. Thus, an interval R2 between the second contact plugs 152 b is given by an equation {R2=R3+2×δ11}. Accordingly, even if the width R1 of theelement isolation portion 102 is set to the minimum value and the interval R3 between thefirst level interconnections 110B is equalized to the width R1 of theelement isolation portion 102, the second contact plugs 152 b should be disposed at an interval that is increased by as much as a value of 2×δ11 as compared with the semiconductor device A according to the first embodiment of the present invention. This hinders disposing MOS transistors at a high density in the semiconductor device 100 according to the comparative example, thereby precluding the fabrication of downscaled or high-density semiconductor devices. - In addition, in the semiconductor device A according to the present embodiment, as shown in the plan view of
FIG. 11 (refer toFIGS. 1A and 1B ), a peripheral circuit diffusion layer 82C functioning as the source or drain region is preferably formed as follows. Theperipheral circuit region 8 of thesecond MOS transistor 31 of the peripheral circuit diffusion layer 82C may be formed to have the same structure as a peripheralcircuit diffusion layer 82B of thethird MOS transistor 32. - Also, in
FIG. 11 , the peripheral circuit diffusion layer 82D functioning as the source or drain region, which of thethird MOS transistor 32 of theperipheral circuit region 8, is preferably formed to have the same structure as a peripheralcircuit diffusion layer 82A of thesecond MOS transistor 31. -
FIG. 12 is a cross-sectional view of a semiconductor device A including the peripheral circuit diffusion layers 82C and 82D. - Here, an example of the semiconductor device A shown in
FIG. 11 includes two transistors. However, when at least three transistors are disposed in parallel according to the present invention, as shown inFIG. 12 , it is preferable for a first intermediate interconnection layers 10B and a second intermediate interconnection layers 20B to be alternately and repetitively connected to the peripheral circuit diffusion layers 82A, 82B, 82C, and 82D. Thus, a distance between adjacent transistors may be shortened, thereby reducing the area occupied by theperipheral circuit region 8. - Also, a
gate electrode 42 may be prepared to be connected to a more suitable one of the first and second intermediate interconnection layers 10B and 20B as an intermediate interconnection according to a position of a contact plug connected to thegate electrode 42. When the firstintermediate interconnection layer 10B is connected to thegate electrode 42, the firstintermediate interconnection layer 10B and thegate electrode 42 are connected to each other via asecond contact plug 52 d prepared on thegate electrode 42. Also, when the secondintermediate interconnection layer 20B is connected to thegate electrode 42, the secondintermediate interconnection layer 20B and thegate electrode 42 are connected to each other via a stack structure of second and third contact plugs 52 e and 53 c prepared on thegate electrode 42. - Furthermore, the
MOS transistors peripheral circuit region 8 may have p-type conductivity. When theMOS transistors MOS transistors - Also, both n-type and p-type transistors may be disposed to prepare CMOS transistors.
- In addition, first and second contact plugs may not be directly in contact with a semiconductor substrate but may be connected to the semiconductor substrate via a selectively epitaxially grown silicon layer.
- The semiconductor device related with the present embodiment may be very effectively applied to formation of an intermediate interconnection layer of a peripheral circuit region (a connection portion) disposed adjacent to a memory cell region, such as a sense amplifier circuit or a word line driver circuit. Also, the semiconductor device related with the present embodiment may be applied to other peripheral circuit regions.
- The above-described method of fabricating the semiconductor device A according to the present embodiment may involve the respective processes, thereby enabling efficient fabrication of a DRAM device having a small chip size as the semiconductor device A with a high throughput.
- Hereinafter, a semiconductor device B according to a second embodiment of the present invention will be described with reference to
FIG. 13 . -
FIG. 13 is a schematic plan view of the semiconductor device B according to the second embodiment of the present invention, which illustrates the structure of a MOS transistor disposed in a peripheral circuit region. - In the present embodiment, the same reference numerals are used to denote the same components as the semiconductor device A of the first embodiment, and a detailed description thereof will be omitted.
- As shown in
FIG. 13 , the semiconductor device B according to the present embodiment differs from the semiconductor device A according to the first embodiment in the following constitution. The semiconductor device B is mainly disposed in the peripheral circuit region and an upper interconnection connected to any one of afirst level interconnection 10B and asecond level interconnection 20B is not prepared. - The semiconductor device B includes a plurality of ring-shaped
gate electrodes 42 disposed in a rectangular active region K. For example,FIG. 13 illustrates fourgate electrodes 42 disposed in the active region K. Referring toFIG. 13 , asecond contact plug 52 b is connected to a central peripheral circuit diffusion layer (source or drain regions) 82E surrounded by the ring-shapedgate electrodes 42. Also, second contact plugs 52 b are provided to be connected to thegate electrodes 42. - As shown in
FIG. 13 , fivefirst level interconnections 10B extend in a lateral direction in the peripheral circuit region of the semiconductor device B. InFIG. 13 , for brevity, reference numerals (a) through (e) are respectively assigned to the fivefirst level interconnections 10B from above. - The
first level interconnection 10B(a) connects thegate electrode 42 and the peripheralcircuit diffusion layer 82E of a transistor disposed adjacent thereto and simultaneously extends in a lateral direction ofFIG. 13 to be connected to another circuit (not shown). Each of thefirst level interconnections 10B(b), 10B(d), and 10B(e) is configured in the same manner as thefirst level interconnection 10B(a). - Also, the
first level interconnection 10B(c) disposed in the center in a vertical direction ofFIG. 13 is not connected to transistors shown inFIG. 13 . However, thefirst level interconnection 10B(c) is disposed in the center to be connected to another transistor (not shown). - A stack plug obtained by directly stacking the
second contact plug 52 b and athird contact plug 53 b is connected to a peripheral circuit diffusion layer (source or drain region) 82F disposed outside the ring-shaped gate electrode 42 (FIG. 13 shows only the position of thethird contact plug 53 b). - The second contact plugs 52 b connected respectively to the peripheral circuit diffusion layers 82 E and 82 F and the
gate electrode 42 may be simultaneously formed using one photomask. - Also, in the semiconductor device B, a
second level interconnection 20B is provided on and connected to thethird contact plug 53 b. Thesecond level interconnection 20B is electrically connected to the peripheralcircuit diffusion layer 82F via thethird contact plug 53 b and thesecond contact plug 52 b. - In addition, a
fourth contact plug 54 b is connected to thesecond level interconnection 20B and connected to an upper interconnection layer (not shown). - Here, since the
second level interconnection 20B connected to the peripheralcircuit diffusion layer 82F may be disposed on thefirst level interconnection 10B to intersect the first level interconnection 10 t from plan view, thefirst level interconnection 10B and a transistor may be disposed at high density. -
FIG. 15 is a plan view of a semiconductor device 200 using only afirst level interconnection 10B according to a comparative example of the semiconductor device B of the present embodiment. Hereinafter, the comparison of the semiconductor device 200 with the semiconductor device B will be described with reference toFIG. 15 . - In the semiconductor device 200 of
FIG. 15 according to the comparative example, afirst level interconnection 110B(f) is connected to a peripheralcircuit diffusion layer 182F. Here, it is necessary to determine a space R2 within the resolution limit of a photolithography process between thefirst level interconnection 110B(f) and a first level interconnection 110 disposed adjacent thereto. For this reason, since afirst level interconnection 110B(c) is disposed away from thefirst level interconnection 110B(f), a dimension required to dispose thefirst level interconnections 110B(c) and 110B(f) is enlarged in a vertical direction ofFIG. 15 , thereby precluding the miniaturization of the semiconductor device 200. - As a result, in the semiconductor device B according to the embodiment of the present invention, as shown in the plan view of
FIG. 13 , thesecond contact plug 52 b and thethird contact plug 53 b are disposed not to cause an electrical short circuit between the second and third contact plugs 52 b and 53 b. Thefirst level interconnection 10B, thefirst level interconnection 10B and a transistor may be disposed at a higher density than the comparative example. - Accordingly, in the peripheral circuit region, when a plurality of transistors are repetitively disposed in a connection portion (a region disposed adjacent to the memory cell region) where a sense amplifier circuit or a word line driver circuit is disposed, the area occupied by the sense amplifier circuit or the word line driver circuit may be reduced effectively.
- Like the semiconductor device A of the first embodiment, the semiconductor device B of the second embodiment may reduce the area occupied by a circuit disposed in the peripheral circuit region, thereby obtaining the semiconductor device B with a small chip size.
- As used herein, the following directional terms “forward, rearward, above, downward, vertical, horizontal, below, and transverse” as well as any other similar directional terms refer to those directions of an apparatus equipped with the present invention. Accordingly, these terms, as utilized to describe the present invention should be interpreted relative to an apparatus equipped with the present invention.
- Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
- The terms of degree such as “substantially,” “about,” and “approximately” as used herein mean a reasonable amount of deviation of the modified term such that the end result is not significantly changed. For example, these terms can be construed as including a deviation of at least ±5 percents of the modified term if this deviation would not negate the meaning of the word it modifies.
- It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.
Claims (1)
1. A semiconductor device comprising:
a semiconductor substrate;
first and second diffusion regions in the semiconductor substrate;
an element isolation portion separating the first and second diffusion regions from each other;
a first insulating film over the element isolation portion and the first and second diffusion regions;
first and second contact plugs over the first and second diffusion regions, respectively, the first and second contact plugs penetrating the first insulating film;
a first conductive layer over the first insulating film;
a second insulating film over the first conductive layer;
a third contact plug penetrating the second insulating film, the third contact plug being connected to the first contact plug; and
a second conductive layer over the second insulating film, the second conductive layer contacting the third contact plug,
wherein the first and second conductive layers partly overlap the element isolation portion.
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US10355002B2 (en) | 2016-08-31 | 2019-07-16 | Micron Technology, Inc. | Memory cells, methods of forming an array of two transistor-one capacitor memory cells, and methods used in fabricating integrated circuitry |
US10157926B2 (en) | 2016-08-31 | 2018-12-18 | Micron Technology, Inc. | Memory cells and memory arrays |
US10535399B2 (en) | 2016-08-31 | 2020-01-14 | Micron Technology, Inc. | Memory arrays |
US10339985B2 (en) | 2016-08-31 | 2019-07-02 | Micron Technology, Inc. | Sense amplifier constructions |
US10622363B2 (en) * | 2016-08-31 | 2020-04-14 | Micron Technology, Inc. | Memory cells, methods of forming an array of two transistor-one capacitor memory cells, and methods used in fabricating integrated circuitry |
US10847516B2 (en) | 2016-08-31 | 2020-11-24 | Micron Technology, Inc. | Memory cells and memory arrays |
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Also Published As
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JP2011142256A (en) | 2011-07-21 |
US9209192B2 (en) | 2015-12-08 |
US20110169062A1 (en) | 2011-07-14 |
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