US20160035736A1 - High Endurance Non-Volatile Memory Cell - Google Patents
High Endurance Non-Volatile Memory Cell Download PDFInfo
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- US20160035736A1 US20160035736A1 US14/445,697 US201414445697A US2016035736A1 US 20160035736 A1 US20160035736 A1 US 20160035736A1 US 201414445697 A US201414445697 A US 201414445697A US 2016035736 A1 US2016035736 A1 US 2016035736A1
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Definitions
- Flash memory is an electronic non-volatile computer storage medium that can be electrically erased and reprogrammed.
- flash memory includes an addressable array of memory cells; each of which includes a transistor with a floating gate disposed over a substrate separated therefrom by an insulating dielectric layer.
- defects disposed in the insulating dielectric layer may trap charges and unavoidably degrade the insulating effect.
- Other types of damage may also reduce the effectiveness of the insulating dielectric layer, reducing ability of the floating gate to hold a charge for an extended period of time.
- Each flash memory can sustain a finite amount of degradation before it becomes unreliable, meaning it may still function but not consistently.
- FIG. 1A illustrates a top view of some embodiments of a non-volatile memory cell.
- FIG. 1B illustrates a cross-sectional view of some embodiments of the non-volatile memory cell of FIG. 1A along line A-A′.
- FIG. 1C illustrates an enlarged regional view of FIG. 1B .
- FIG. 1D illustrates a cross-sectional view of some embodiments of the non-volatile memory cell of FIG. 1A along line B-B′.
- FIG. 2A illustrates a top view of some embodiments of a non-volatile memory.
- FIG. 2B illustrates an equivalent circuit of some embodiments of the non-volatile memory of FIG. 2A .
- FIG. 3 illustrates a flow diagram of some embodiments of a method of forming a non-volatile memory cell.
- FIG. 4 illustrates a flow diagram of some other embodiments of a method of forming a pair of non-volatile memory cells.
- FIGS. 5A-13B illustrate a series of cross-sectional views of some embodiments of forming a non-volatile memory cell at various stages of manufacture.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- a non-volatile memory cell includes a transistor with a floating gate disposed above a channel, which is arranged between source/drain regions of the transistor.
- the floating gate is insulated by a thin insulation film so that the floating gate can store charge (electrons) for a relatively long time (e.g. years) regardless of power being on or off.
- the charge stored in the floating gate controls a threshold of the transistor depending on how much charge is stored in the floating gate.
- One approach to write a first data state e.g., a so-called “program operation” for the non-volatile memory cell is to inject electrons into the floating gate by applying a high current from a source region of the transistor to the floating gate (known as source side injection, SSI, which sets the voltage threshold value of the transistor to a first value.
- SSI source side injection
- a second data state e.g., a so-called “erase operation”
- a high voltage can be applied to the floating gate to promote electrons leaving the floating gate by tunneling (known as Fowler-Nordheim tunneling, FN tunneling).
- the non-volatile memory cell 100 a includes a first transistor 103 a and a second transistor 103 b spaced apart from one another but have their corresponding floating gates 11 and 12 connected together.
- the non-volatile memory cell 100 a is programmed and erased from the first transistor 103 a and read from the second transistor 103 b. Since the floating gates 11 and 12 of the two transistors are connected together and insulated from other ambient layers, stored charge can be controlled from the first transistor 103 a and affect a threshold of the second transistor 103 b. A gate dielectric layer of reading transistor-the second transistor 103 b disposed between the floating gate 12 and the channel 111 b is saved from degrading introduced by high voltage, high current, and charge movement during programming and erasing. Also, since the programming and erasing operations are separated from the reading operation, speed of the non-volatile memory can be improved and disturbance can be reduced.
- the non-volatile memory cell 100 a is formed by a manufacturing procedure including a slit etch followed by a planarization process.
- the non-volatile memory cell 100 a can be fabricated by forming a plurality of isolation regions 102 higher than a top surface of a semiconductor substrate first and then forming transistors within active regions 104 self-aligned by the isolation regions 102 .
- the connection component, a floating gate bridge 106 a electrically connecting the floating gates 11 and 12 can be formed by covering a portion of a conductive material directly above a central isolation region 102 a from being removed when etching the conductive material directly above peripheral isolation regions 102 b and 102 c.
- FIG. 1B shows an example cross-sectional view of the non-volatile memory cell 100 a of FIG. 1A along line A-A′.
- the isolation regions 102 can be disposed higher than a top surface of the substrate 120 to form recesses between the isolation regions 102 .
- the floating gates 11 and 12 are self-aligned and well-defined by sidewalls of the isolation regions 102 .
- the central isolation region 102 a is extended and continuous along the y direction between the active regions 104 a and 104 b compared to previous approaches.
- FIG. 1A shows a 2 ⁇ 2 memory cell array disposed over a semiconductor substrate in a first direction x and a second direction y as a non-limiting example for easy illustration.
- the first direction x and the second direction y may be perpendicular to each other.
- Each memory cell 100 a, 100 b, etc. may have a similar structure as the memory cell 100 .
- FIG. 1B shows a cross-sectional view of some embodiments of the non-volatile memory cell 100 of FIG. 1A along line A-A′ in the x direction.
- the non-volatile memory cell 100 comprises a first active region 104 a and a second active region 104 b.
- the first and second active regions 104 a and 104 b have a first conductivity type, such as p type or n type.
- the central isolation region 102 a central isolation region 102 a is disposed between innermost sides of the first active region 104 a and the second active region 104 b.
- a first peripheral isolation region 102 b is arranged about an outermost side of the first active region 104 a; and a second peripheral isolation region 102 c is arranged about an outermost side of the second active region 104 b.
- the central isolation region 102 a and the first and second peripheral isolation regions 102 b and 102 c are disposed higher than the first and second active regions 104 a and 104 b ; forming a first recess between the central isolation region 102 a and the first peripheral isolation region 102 b, and a second recess between the central isolation region 102 a and the second peripheral isolation region 102 c.
- the isolation regions are shallow trenches filled with an insulating material.
- a conductive material is filled into the first and second recesses to form a first floating gate 11 of a first transistor and a second floating gate 12 of a second transistor.
- a first dielectric layer 110 is respectively formed between the first and second floating gates 11 and 12 and the first and second active regions 104 a and 104 b as a gate dielectric.
- a floating gate bridge 106 a is disposed above the central isolation region 102 a; connecting the first floating gate 11 and the second floating gate 12 .
- the floating gate bridge 106 a can be made of same material with the first and second floating gates 11 and 12 .
- the first and second floating gates 11 and 12 are disposed in the first and second recesses so that the first floating gate 11 abuts a left sidewall of the central isolation region 102 a and a first sidewall of the first peripheral isolation region 102 b.
- the second floating gate 12 abuts a right sidewall of the central isolation region 102 a and a second sidewall of the first peripheral isolation region 102 b.
- FIG. 1C shows an enlarged regional view of a portion of FIG. 1B marked by dash-dotted rectangular of some embodiments of the non-volatile memory cell 100 .
- FIG. 1C shows some embodiments of relative positions of the first floating gate 11 , the floating gate bridge 106 a, the central isolation region 102 a, the first peripheral isolation region 102 b, and the first active region 104 a.
- the first floating gate 11 is disposed abutting the first sidewall 132 a of the first peripheral isolation region 102 b and the left sidewall 132 b of the central isolation region 102 a central isolation region 102 a.
- the first height 138 from the active region 104 a to a top surface 134 a of the first peripheral isolation region 102 b is in a range of from about 100 ⁇ to about 1000 ⁇ . In some embodiments, the first height 138 is around 350 ⁇ .
- the gate dielectric 110 is disposed between the first floating gate 11 and the first active region 104 a.
- a second dielectric layer 112 is disposed on the first floating gate 11 and the floating gate bridge 106 a under a control gate layer 108 .
- the floating gate bridge 106 is disposed above the central isolation region 102 a with a second height from a top surface 134 b of the central isolation region 102 a central isolation region 102 a. In some embodiments, the second height is about 350 ⁇ .
- the floating gate bridge 106 laterally extends over an edge of the central isolation region 102 a along the x direction.
- the non-volatile memory cell 100 comprises a first transistor corresponding to the first floating gate 11 is disposed at the first active region 104 a and a second transistor corresponding to the second floating gate 12 is disposed at the second active region 104 b.
- the first transistor comprises a first drain region 115 a and a first source region 114 a spaced apart by a first channel region 111 a in the y direction.
- a first control gate is capacitively coupled to the first floating gate 11 .
- the second transistor comprise a second drain region 115 b and a second source region 114 b spaced apart by a second channel region 111 b in the y direction.
- a second control gate is capacitively coupled to the second floating gate 12 .
- the non-volatile memory cell 100 is read from one of the transistors, for example the first transistor, and programmed and erased from the other transistor, for example the second transistor.
- the non-volatile memory cell 100 can be read by applying a first bias to the first drain region 115 a; while non-volatile memory cell 100 can be programmed by applying a second bias to the second floating gate 12 and be erased by injecting hot electrons from the second source region 114 b.
- the first source region 114 a and the second source region 114 b are electrically connected together in the substrate 120 .
- the first drain region 115 a of the first transistor can be connected with the first transistors of other memory cells by a bit line.
- the second drain region 115 b of the second transistor can be connected with the second transistors of other memory cells by a programming line.
- FIG. 2A shows an example top view of some embodiments of a non-volatile memory 200 with a plurality of non-volatile memory cells 100 .
- the non-volatile memory 200 includes 2 columns in the y direction and 2 rows in the x direction of non-volatile memory cell 100 , but it is to be understood that more or less columns and/or more or less rows are amenable.
- FIG. 1 shows an example top view of some embodiments of a non-volatile memory 200 with a plurality of non-volatile memory cells 100 .
- the non-volatile memory 200 includes 2 columns in the y direction and 2 rows in the x direction of non-volatile memory cell 100 , but it is to be understood that more or less columns and/or
- a plurality of word lines extend in the x direction, each word line connecting control gates of the memory cells along a given row.
- a first word line 322 a connects the control gates in a row n
- a second word line 322 b connects the control gates in a row n+1.
- a plurality of bit lines are extended in the y direction, each bit line connecting drain region of the first transistor of the memory cells in a given column.
- a first bit line 224 a connects the drain regions of the first transistors in a column n, i.e.
- a plurality of program lines are extended in the y direction, each program line connecting drain region of the second transistor of the memory cells in a given column.
- a first program line 222 a connects the drain regions of the second transistors in a column n, i.e. 115 b and 115 f
- a second program line 222 b connects the drain regions of the second transistor in a column n+1, i.e. 115 d and 115 h.
- the plurality of non-volatile memory cells 100 shares a common source region 114 .
- FIG. 2B shows an equivalent circuit of some embodiments of the non-volatile memory 200 of FIG. 2A .
- FIG. 2 shows as a “NOR” memory cell structure wherein a pair of the memory cells (e.g. 100 a and 100 c ) are connected in parallel sharing a common source and having drain regions connected together within a bit line.
- the memory cells 100 can be connected in series, wherein a drain region of one memory cell is shared as a source region of another memory cell; and multiple memory cells within a bit line can be connected in this way.
- This structure is known as “NAND” memory structure.
- Other applicable memory cell structures are also amenable.
- FIG. 3 shows a flow diagram of some embodiments of a method 300 of forming a non-volatile memory cell.
- the method 300 discloses a self-aligned process to form the non-volatile memory cell with two transistors having floating gates connected together by a floating gate bridge.
- the method 300 includes a slit etch act followed by a planarization act to form the floating gates and the floating gate bridge.
- a first hard mask layer is patterned over a first dielectric layer.
- the first dielectric layer is acted as a gate dielectric precursor.
- the patterned first hard mask layer includes a plurality of strips spaced apart from one another.
- a central isolation region and first and second peripheral isolation regions are formed through the dielectric layer into the substrate.
- the central isolation region is formed between innermost sides the first and second peripheral isolation regions and the central isolation region and the first and second peripheral isolation regions are spaced apart from one another by the first hard mask layer in a first direction.
- the isolation regions are used to insulate active regions disposed in the substrate under the hard mask layer from one another.
- the isolation regions are formed between the first hard mask layer strips, separating the strips from one another.
- the first hard mask layer is removed to form a first recess between the central isolation region and the first peripheral isolation region and a second recess between the central isolation region and the peripheral isolation region.
- a first conductive layer is formed to fill the first and second recesses and over the isolation regions.
- a photoresist layer is formed to cover a first portion of the first conductive layer above the central isolation region, and a second portion of the first conductive layer above the first and second peripheral isolation regions is removed, thereby exposing a top surface of the first and second peripheral isolation regions.
- removal of the second portion of the first conductive layer is performed by a dry etching process, and act 310 is referred to as a “slit etch”.
- the floating gates are formed self-aligned by the isolation regions.
- the bridge precursor connects the floating gate precursors in the different recesses.
- FIG. 4 shows a flow diagram of some embodiments of a method 400 of forming a pair of non-volatile memory cell.
- the method 400 includes a self-aligned process to form a bridge precursor connected two floating gate precursors (similar to the method 300 ) followed by forming the pair of non-volatile memory cells with gate structures of some embodiments.
- a first hard mask layer is patterned over a first dielectric layer.
- a central isolation region and first and second peripheral isolation regions are formed through the dielectric layer into the substrate.
- the first hard mask layer is removed to form a first recess between the central isolation region and the first peripheral isolation region and a second recess between the central isolation region and the peripheral isolation region.
- a first conductive layer is formed to fill the first and second recesses and over the isolation regions.
- a photoresist layer is formed to cover a first portion of the first conductive layer above the central isolation region, and a second portion of the first conductive layer above the first and second peripheral isolation regions is removed, thereby exposing a top surface of the first and second peripheral isolation regions.
- removal of the second portion of the first conductive layer is performed by a dry etching process, and act 310 is referred to as a “slit etch”.
- performing a planarization to reduce a height of the first portion of the first conductive layer to form a bridge precursor over the central isolation region and to leave the floating gate precursors in the first and second recesses, respectively.
- a second, conformal dielectric layer, a second conductive layer, and a hard mask layer are stacked over exposed surfaces of the isolation regions and the remaining first conductive layer.
- an etch is performed through the hard mask layer, the second conductive layer, the second dielectric layer and the remaining first conductive layer to form a pair of gate stacks.
- a shared source/drain region is embedded within the surface of the semiconductor substrate between the gates stacks and two individual source/drain regions are embedded within the surface of the semiconductor substrate about outermost sides the gates stacks.
- FIGS. 5-13 cross-sectional views of some embodiments of the semiconductor structure at various stages of manufacture are provided to illustrate some embodiments of forming non-volatile memory cells.
- Figures with a suffix of “A” correspond to cross-sectional views along an x direction
- figures with a suffix of “B” correspond to cross-sectional views along a y direction that is perpendicular to the x direction.
- FIGS. 5A-13B are described in relation to the method 400 , it will be appreciated that the structures disclosed in FIGS. 5A-13B are not limited to the method 400 , but instead may stand alone as structures independent of the method 400 .
- the method 400 is described in relation to FIGS. 5A-13B , it will be appreciated that the method 400 is not limited to the structures disclosed in FIGS. 5A-13B , but instead may stand alone independent of the structures disclosed in FIGS. 5A-13B .
- a first dielectric layer 610 is formed over a semiconductor substrate 620 .
- the semiconductor substrate 620 is typically planar with a uniform thickness. Further, the semiconductor substrate 620 is n- or p-type, and can, for example, be a handle wafer, such as a Si wafer or a silicon-on-insulator (SOI) substrate. If present, an SOI substrate is often made up of an active layer of high quality silicon.
- the first dielectric layer 610 can be an oxide, such as silicon dioxide.
- a mask layer 602 is formed on the first dielectric layer 610 . The mask layer 602 is formed and patterned so it covers diffusion regions (e.g.
- the mask layer 602 can be formed to leave exposed only those regions of the semiconductor substrate 620 to be employed as isolation regions.
- the mask layer 602 is typically formed of silicon nitride, but other materials are amenable.
- a first etch is performed through the first dielectric layer 610 and partially into the semiconductor substrate 620 in accordance with the mask 602 to create trenches.
- the trenches are spaced to define diffusion regions therebetween for the non-volatile memory cells.
- An insulating material is formed to fill the trenches to form isolation regions 702 a - e .
- the insulating material can be formed filling the trenches and covering the mask layer 602 first; then be planarized to exposed the mask layer 602 .
- the insulating material can be an oxide, such as silicon dioxide.
- a second etch is performed through the mask layer 602 to remove the mask layer 602 and to create recesses between the isolation regions 702 abutting sidewalls of the isolation regions 702 .
- a first conductive layer 802 is formed to fill the recesses and cover the insulating material.
- the first conductive layer 802 is typically formed of polysilicon and typically has a maximum thickness of from about 450 ⁇ to about 550 ⁇ .
- a anti-reflective coating (BARC) layer 804 with a thickness of from about 400 ⁇ to about 800 ⁇ can be formed on the first conductive layer 802 .
- a photoresist layer 902 is formed to cover a first portion of the first conductive layer 802 above a first group of isolation regions, named central isolation regions, including for example 702 b and 702 d, and a second etch is performed to a second portion of the first conductive layer 802 above the second group of isolation regions, named peripheral isolation regions, including for example, 702 a , 702 c and 702 e; thereby exposing top surfaces 934 a, 934 b and 934 c of the second group of isolation regions 702 a, 702 c and 702 e.
- the second etch process may be referred to as a “slit etch”.
- a planarization process for example, a chemical-mechanical polishing (CMP) process is performed to reduce a height to the first portion of the first conductive layer 802 to form bridge precursors 1006 a and 1006 b directly above the central isolation regions 702 b and 702 d, respectively connecting pairs of floating precursors 811 - 812 and 831 - 832 disposed in the recesses.
- CMP chemical-mechanical polishing
- the maximum thickness of the remaining first conductive layer 802 ′ is about 350 ⁇ .
- a second, conformal dielectric layer 1102 , a second conductive layer 1104 , and a hard mask layer 1106 are stacked or formed in that order over the isolation regions 702 and the remaining first conductive layer 802 ′.
- the second dielectric layer 1102 is typically an ONO dielectric and conforms to the remaining first conductive layer 802 ′ and the peripheral isolation regions 702 b, 702 c and 702 e, etc.
- the second conductive layer 1104 is typically polysilicon and typically has a planar top surface.
- the hard mask layer 1106 is typically a nitride-oxide-nitride (NON) dielectric and typically has a planar top surface.
- an etch is performed through the hard mask, second conductive, second dielectric and the remaining first conductive layers 1106 , 1104 , 1102 and 802 ′ to form a pair of gate stacks 1232 a and 1232 b.
- the gate stacks 1232 includes a pair of spaced control gates 1104 ′ a , 1104 ′ b and a pair of spaced floating gates 811 and 812 under the control gates 1104 ′.
- the formed control gates 1104 ′ are each sandwiched between an inter-gate dielectric regions 1102 ′ a , 1102 ′ b and a hard mask 1106 ′ a , 1106 ′ b , and each rest at the floating gate 811 or 821 .
- the inter-gate dielectric region 1102 ′ electrically isolates the remaining first conductive layer 802 ′ from the control gates 1104 , while the hard mask 1106 ′ masks the control gates 1104 ′ during manufacture.
- spacers 1202 a, 1202 b, 1202 c and 1202 d are formed along sidewalls of each control gate 1104 ′.
- the spacers 1202 of the control gates 1104 ′ extend from the floating gates 811 and 821 , along the sidewalls of the control gate 1104 ′, to approximately even with a top surface of the hard mask 1106 ′.
- the spacers 1202 are formed by conformally forming an intermediate dielectric layer over sidewalls of the control gates 1106 ′ and the inter-gate dielectric regions 1104 ′, over the hard masks 1106 ′, and over the floating gates 811 and 821 .
- Liners 1204 a, 1204 b, 1204 c and 1204 d are formed along opposing sidewalls of each floating gates 811 and 812 and along corresponding sidewalls of the spacers 1202 .
- the liners 1204 of a floating gate 811 or 812 extend from the semiconductor substrate 620 , along the sidewalls of the floating gate 811 or 812 and the spacers 1202 , to approximately even with a top surface of the hard mask 1106 ′.
- the liners 1204 can be formed by conformally forming an intermediate dielectric layer over sidewalls of the floating gates and the spacers 1202 , over the hard masks 1106 ′, and over the semiconductor substrate 620 .
- the intermediate dielectric layer is an oxide dielectric formed by high temperature oxide (HTO) deposition.
- An etch is then performed through the intermediate dielectric layer to remove portions of the intermediate dielectric layer that line or are otherwise formed on a horizontal surface of the semiconductor substrate 620 and, in some embodiments, the hard masks 1106 ′.
- a shared source/drain region 1314 is embedded within the surface of the semiconductor substrate 620 between the gates stacks 1232 a and 1232 b.
- the embedding is performed by masking peripheral regions of the semiconductor structure (i.e., those regions outside a central region between the gate stacks 1232 a and 1232 b ) with a photoresist. Thereafter, the liners 1204 b and 1204 c disposed between the gate stacks 1232 are removed, and ions (e.g., n+ ions) are implanted into the semiconductor substrate 620 to form the shared source/drain region 1314 with a predefined thickness, such as 20 A.
- ions e.g., n+ ions
- the shared source/drain region 1314 may be of an opposite type as the semiconductor substrate 620 or of an opposite type as a well region or active region in which the non-volatile memory cells are formed.
- Second lines 1206 b and 1206 c are then formed along sidewalls of the gate stacks 1232 to protect the gate stacks 1232 .
- two individual source/drain regions 1312 a and 1312 b are embedded within the surface of the semiconductor substrate 620 about outermost sides the gates stacks 1232 a and 1232 b.
- the individual source/drain regions 1312 are embedded by masking a central region between the gates stacks 1232 with a photoresist. Thereafter, ions (e.g., n+ ions) of the same type as the shared source/drain region 1314 are implanted into the semiconductor substrate 620 to form the individual source/drain regions 1312 with a predefined thickness, such as 20 A.
- the shared and individual source/drain regions 1312 a, 1312 b are spaced apart with the shared source/drain region 1314 in the middle of the two individual source/drain regions 1312 . Further, each individual source/drain region 1312 and the shared source/drain region 1314 define a channel region 1316 a, 1316 b therebetween.
- the present disclosure provides a non-volatile memory cell that employs a floating gate bridge connecting a first floating gate of a first transistor and a second floating gate of a second transistor.
- the present disclosure provides a non-volatile memory cell disposed over a substrate.
- the non-volatile memory cell comprises a first active region and a second active region separated by a central isolation region in a first direction.
- the non-volatile memory cell further comprises first and second peripheral isolation regions disposed about outermost sides of the first and second active regions.
- the central isolation region and the first and second peripheral isolation regions have a first height above the first and second active regions forming a first recess between the central isolation region and the first peripheral isolation region, and a second recess between the central isolation region and the second peripheral isolation region.
- the non-volatile memory cell further comprises first and second floating gates disposed in the first and second recesses respectively and a floating gate bridge disposed over the central isolation region electrically connecting the first and second floating gates.
- the first floating gate is disposed abutting a first sidewall of the first peripheral isolation region and the second floating gate is disposed abutting a second sidewall of the second peripheral isolation region.
- the present disclosure provides a non-volatile memory.
- the non-volatile memory comprises a plurality of non-volatile memory cells arranged in a plurality of rows and columns in a semiconductor substrate of a first conductivity type.
- Each memory cell comprises a first transistor and a second transistor.
- the first transistor comprises a first region and a second region of a second conductivity type spaced apart from one another by a first channel region, defined in a column direction; a first floating gate disposed over the first channel region, insulated from the first channel region by a first dielectric layer; and a first control gate disposed over the first floating gate, insulated from the first floating gate by a second dielectric layer.
- the second transistor comprises a third region and a fourth region of a second conductivity type spaced apart from one another by a second channel region, defined in a column direction; a second floating gate disposed over the second channel region, insulated from the second channel region by the first dielectric layer; and a second control gate disposed over the second floating gate, insulated from the second floating gate by the second dielectric layer.
- the second transistor is spaced apart from the first transistor in a row direction substantially perpendicular to the column direction.
- the first region and the third region are aligned in the row direction and insulated from one another in the substrate by an central isolation region.
- the first floating gate is disposed abutting a sidewall of a first peripheral isolation region and the second floating gate is disposed abutting a sidewall of a second peripheral isolation region disposed about outermost sides of the first and second transistors in the row direction and electrically connected by a floating gate bridge.
- the present disclosure provides a method of forming a non-volatile memory cell over a semiconductor substrate.
- a first hard mask layer is patterned over a first dielectric layer.
- a central isolation region and first and second peripheral isolation regions are formed through the dielectric layer into the substrate.
- the central isolation region is formed between innermost sides the first and second peripheral isolation regions and the central isolation region and the first and second peripheral isolation regions are spaced apart from one another by the first hard mask layer in a first direction.
- the first hard mask layer is removed to form a first recess between the central isolation region and the first peripheral isolation region and a second recess between the central isolation region and the peripheral isolation region.
- a first conductive layer if formed filling the first and second recesses and over the isolation regions.
- a photoresist layer is formed to cover a first portion of the first conductive layer above the central isolation region, and a second portion of the first conductive layer above the first and second peripheral isolation regions is etched, thereby exposing a top surface of the first and second peripheral isolation regions.
- a planarization is performed to reduce a height of the first portion of the first conductive layer to form a bridge precursor over the central isolation region and to leave floating gate precursors in the first and second recesses, respectively.
- the bridge precursor connects the floating gate precursors in the different recesses.
Abstract
Description
- Flash memory is an electronic non-volatile computer storage medium that can be electrically erased and reprogrammed. To store information, flash memory includes an addressable array of memory cells; each of which includes a transistor with a floating gate disposed over a substrate separated therefrom by an insulating dielectric layer. When written to and erased during the normal course of use, defects disposed in the insulating dielectric layer may trap charges and unavoidably degrade the insulating effect. Other types of damage may also reduce the effectiveness of the insulating dielectric layer, reducing ability of the floating gate to hold a charge for an extended period of time. Each flash memory can sustain a finite amount of degradation before it becomes unreliable, meaning it may still function but not consistently. The number of writes operations performed (e.g., program and erase cycles) a flash memory can sustain while still maintaining a consistent, predictable output, defines its endurance.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
-
FIG. 1A illustrates a top view of some embodiments of a non-volatile memory cell. -
FIG. 1B illustrates a cross-sectional view of some embodiments of the non-volatile memory cell ofFIG. 1A along line A-A′. -
FIG. 1C illustrates an enlarged regional view ofFIG. 1B . -
FIG. 1D illustrates a cross-sectional view of some embodiments of the non-volatile memory cell ofFIG. 1A along line B-B′. -
FIG. 2A illustrates a top view of some embodiments of a non-volatile memory. -
FIG. 2B illustrates an equivalent circuit of some embodiments of the non-volatile memory ofFIG. 2A . -
FIG. 3 illustrates a flow diagram of some embodiments of a method of forming a non-volatile memory cell. -
FIG. 4 illustrates a flow diagram of some other embodiments of a method of forming a pair of non-volatile memory cells. -
FIGS. 5A-13B illustrate a series of cross-sectional views of some embodiments of forming a non-volatile memory cell at various stages of manufacture. - The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- A non-volatile memory cell includes a transistor with a floating gate disposed above a channel, which is arranged between source/drain regions of the transistor. The floating gate is insulated by a thin insulation film so that the floating gate can store charge (electrons) for a relatively long time (e.g. years) regardless of power being on or off. The charge stored in the floating gate controls a threshold of the transistor depending on how much charge is stored in the floating gate. One approach to write a first data state (e.g., a so-called “program operation”) for the non-volatile memory cell is to inject electrons into the floating gate by applying a high current from a source region of the transistor to the floating gate (known as source side injection, SSI, which sets the voltage threshold value of the transistor to a first value. Conversely, to write a second data state (e.g., a so-called “erase operation”) for the non-volatile memory cell, a high voltage can be applied to the floating gate to promote electrons leaving the floating gate by tunneling (known as Fowler-Nordheim tunneling, FN tunneling).
- During programming and erasing, some of the electrons traveling in and out the floating gate may become permanently trapped in the insulation film disposed between the floating gate and the channel. Other types of damages, such as hot carrier effects, can also damage the insulation film. Over time, these trapped charge and/or other types of damage can cause the Vt distributions of the memory cells to shift from their target values, or can reduce the speed at which memory read or write operations can take place. Thus, the reliability and/or performance of the memory cell is degraded.
- In order to improve the endurance of a floating gate memory cell, the present disclosure sets forth a non-volatile memory cell structure and manufacturing methods therefor. Referring to
FIGS. 1A-1D concurrently, non-limiting example structures of anon-volatile memory cell 100 are disclosed. Thenon-volatile memory cell 100 a includes afirst transistor 103 a and asecond transistor 103 b spaced apart from one another but have their correspondingfloating gates - During operation, the
non-volatile memory cell 100 a is programmed and erased from thefirst transistor 103 a and read from thesecond transistor 103 b. Since thefloating gates first transistor 103 a and affect a threshold of thesecond transistor 103 b. A gate dielectric layer of reading transistor-thesecond transistor 103 b disposed between thefloating gate 12 and thechannel 111 b is saved from degrading introduced by high voltage, high current, and charge movement during programming and erasing. Also, since the programming and erasing operations are separated from the reading operation, speed of the non-volatile memory can be improved and disturbance can be reduced. - In many embodiments of the present disclosure, the
non-volatile memory cell 100 a is formed by a manufacturing procedure including a slit etch followed by a planarization process. Thenon-volatile memory cell 100 a can be fabricated by forming a plurality ofisolation regions 102 higher than a top surface of a semiconductor substrate first and then forming transistors within active regions 104 self-aligned by theisolation regions 102. The connection component, afloating gate bridge 106 a electrically connecting thefloating gates central isolation region 102 a from being removed when etching the conductive material directly aboveperipheral isolation regions -
FIG. 1B shows an example cross-sectional view of thenon-volatile memory cell 100 a ofFIG. 1A along line A-A′. As mentioned above, theisolation regions 102 can be disposed higher than a top surface of thesubstrate 120 to form recesses between theisolation regions 102. The floatinggates isolation regions 102. Notably, since the floatinggate bridge 106 a is kept while a portion of a firstconductive layer 202 directly above theperipheral isolation regions central isolation region 102 a is extended and continuous along the y direction between theactive regions central isolation region 102 a to be introduced compared to a case without the floating gate bridge (e.g. a non-volatile memory cell with single transistor). The size of the non-volatile memory cell is minimized. - In greater detail,
FIG. 1A shows a 2×2 memory cell array disposed over a semiconductor substrate in a first direction x and a second direction y as a non-limiting example for easy illustration. The first direction x and the second direction y may be perpendicular to each other. Eachmemory cell memory cell 100.FIG. 1B shows a cross-sectional view of some embodiments of thenon-volatile memory cell 100 ofFIG. 1A along line A-A′ in the x direction. Thenon-volatile memory cell 100 comprises a firstactive region 104 a and a secondactive region 104 b. The first and secondactive regions active region 104 a and the secondactive region 104 b are separated by acentral isolation region 102 a. Thecentral isolation region 102 acentral isolation region 102 a is disposed between innermost sides of the firstactive region 104 a and the secondactive region 104 b. A firstperipheral isolation region 102 b is arranged about an outermost side of the firstactive region 104 a; and a secondperipheral isolation region 102 c is arranged about an outermost side of the secondactive region 104 b. Thecentral isolation region 102 a and the first and secondperipheral isolation regions active regions central isolation region 102 a and the firstperipheral isolation region 102 b, and a second recess between thecentral isolation region 102 a and the secondperipheral isolation region 102 c. In some embodiments, the isolation regions are shallow trenches filled with an insulating material. A conductive material is filled into the first and second recesses to form a first floatinggate 11 of a first transistor and a second floatinggate 12 of a second transistor. Afirst dielectric layer 110 is respectively formed between the first and second floatinggates active regions gate bridge 106 a is disposed above thecentral isolation region 102 a; connecting the first floatinggate 11 and the second floatinggate 12. The floatinggate bridge 106 a can be made of same material with the first and second floatinggates gates gate 11 abuts a left sidewall of thecentral isolation region 102 a and a first sidewall of the firstperipheral isolation region 102 b. Symmetrically, the second floatinggate 12 abuts a right sidewall of thecentral isolation region 102 a and a second sidewall of the firstperipheral isolation region 102 b. -
FIG. 1C shows an enlarged regional view of a portion ofFIG. 1B marked by dash-dotted rectangular of some embodiments of thenon-volatile memory cell 100.FIG. 1C shows some embodiments of relative positions of the first floatinggate 11, the floatinggate bridge 106 a, thecentral isolation region 102 a, the firstperipheral isolation region 102 b, and the firstactive region 104 a. In the embodiments, the first floatinggate 11 is disposed abutting thefirst sidewall 132 a of the firstperipheral isolation region 102 b and theleft sidewall 132 b of thecentral isolation region 102 acentral isolation region 102 a. Thefirst height 138 from theactive region 104 a to atop surface 134 a of the firstperipheral isolation region 102 b is in a range of from about 100 Å to about 1000 Å. In some embodiments, thefirst height 138 is around 350 Å. Thegate dielectric 110 is disposed between the first floatinggate 11 and the firstactive region 104 a. Asecond dielectric layer 112 is disposed on the first floatinggate 11 and the floatinggate bridge 106 a under acontrol gate layer 108. The floating gate bridge 106 is disposed above thecentral isolation region 102 a with a second height from a top surface 134 b of thecentral isolation region 102 acentral isolation region 102 a. In some embodiments, the second height is about 350 Å. The floating gate bridge 106 laterally extends over an edge of thecentral isolation region 102 a along the x direction. - Referring back to
FIG. 1A , thenon-volatile memory cell 100 comprises a first transistor corresponding to the first floatinggate 11 is disposed at the firstactive region 104 a and a second transistor corresponding to the second floatinggate 12 is disposed at the secondactive region 104 b. The first transistor comprises afirst drain region 115 a and afirst source region 114 a spaced apart by afirst channel region 111 a in the y direction. A first control gate is capacitively coupled to the first floatinggate 11. The second transistor comprise asecond drain region 115 b and asecond source region 114 b spaced apart by asecond channel region 111 b in the y direction. A second control gate is capacitively coupled to the second floatinggate 12. Thenon-volatile memory cell 100 is read from one of the transistors, for example the first transistor, and programmed and erased from the other transistor, for example the second transistor. As an example, thenon-volatile memory cell 100 can be read by applying a first bias to thefirst drain region 115 a; whilenon-volatile memory cell 100 can be programmed by applying a second bias to the second floatinggate 12 and be erased by injecting hot electrons from thesecond source region 114 b. In some embodiments, thefirst source region 114 a and thesecond source region 114 b are electrically connected together in thesubstrate 120. - In some embodiments, the
first drain region 115 a of the first transistor can be connected with the first transistors of other memory cells by a bit line. Thesecond drain region 115 b of the second transistor can be connected with the second transistors of other memory cells by a programming line.FIG. 2A shows an example top view of some embodiments of anon-volatile memory 200 with a plurality ofnon-volatile memory cells 100. For illustrative purposes, thenon-volatile memory 200 includes 2 columns in the y direction and 2 rows in the x direction ofnon-volatile memory cell 100, but it is to be understood that more or less columns and/or more or less rows are amenable. In FIG. 2A's example, a plurality of word lines extend in the x direction, each word line connecting control gates of the memory cells along a given row. For example, afirst word line 322 a connects the control gates in a row n, and a second word line 322 b connects the control gates in arow n+ 1. A plurality of bit lines are extended in the y direction, each bit line connecting drain region of the first transistor of the memory cells in a given column. For example, afirst bit line 224 a connects the drain regions of the first transistors in a column n, i.e. 115 a and 115 e, and asecond bit line 224 b connects the drain regions of the first transistor in a column n+1, i.e. 115 c and 115 g. A plurality of program lines are extended in the y direction, each program line connecting drain region of the second transistor of the memory cells in a given column. For example, afirst program line 222 a connects the drain regions of the second transistors in a column n, i.e. 115 b and 115 f, and asecond program line 222 b connects the drain regions of the second transistor in a column n+1, i.e. 115 d and 115 h. The plurality ofnon-volatile memory cells 100 shares acommon source region 114. -
FIG. 2B shows an equivalent circuit of some embodiments of thenon-volatile memory 200 ofFIG. 2A .FIG. 2 shows as a “NOR” memory cell structure wherein a pair of the memory cells (e.g. 100 a and 100 c) are connected in parallel sharing a common source and having drain regions connected together within a bit line. In some other embodiments, thememory cells 100 can be connected in series, wherein a drain region of one memory cell is shared as a source region of another memory cell; and multiple memory cells within a bit line can be connected in this way. This structure is known as “NAND” memory structure. Other applicable memory cell structures are also amenable. -
FIG. 3 shows a flow diagram of some embodiments of amethod 300 of forming a non-volatile memory cell. Themethod 300 discloses a self-aligned process to form the non-volatile memory cell with two transistors having floating gates connected together by a floating gate bridge. Themethod 300 includes a slit etch act followed by a planarization act to form the floating gates and the floating gate bridge. - At 302, a first hard mask layer is patterned over a first dielectric layer. The first dielectric layer is acted as a gate dielectric precursor. The patterned first hard mask layer includes a plurality of strips spaced apart from one another.
- At 304, a central isolation region and first and second peripheral isolation regions are formed through the dielectric layer into the substrate. The central isolation region is formed between innermost sides the first and second peripheral isolation regions and the central isolation region and the first and second peripheral isolation regions are spaced apart from one another by the first hard mask layer in a first direction. The isolation regions are used to insulate active regions disposed in the substrate under the hard mask layer from one another. The isolation regions are formed between the first hard mask layer strips, separating the strips from one another.
- At 306, the first hard mask layer is removed to form a first recess between the central isolation region and the first peripheral isolation region and a second recess between the central isolation region and the peripheral isolation region.
- At 308, a first conductive layer is formed to fill the first and second recesses and over the isolation regions.
- At 310, a photoresist layer is formed to cover a first portion of the first conductive layer above the central isolation region, and a second portion of the first conductive layer above the first and second peripheral isolation regions is removed, thereby exposing a top surface of the first and second peripheral isolation regions. In some embodiments, removal of the second portion of the first conductive layer is performed by a dry etching process, and act 310 is referred to as a “slit etch”.
- At 312, performing a planarization to reduce a height of the first portion of the first conductive layer to form a bridge precursor over the central isolation region and to leave the floating gate precursors in the first and second recesses, respectively. Thereby the floating gates are formed self-aligned by the isolation regions. The bridge precursor connects the floating gate precursors in the different recesses.
- In some embodiments, followed by
act 312, two transistor of each of non-volatile memory cells are formed by a series of subsequent acts.FIG. 4 shows a flow diagram of some embodiments of amethod 400 of forming a pair of non-volatile memory cell. Themethod 400 includes a self-aligned process to form a bridge precursor connected two floating gate precursors (similar to the method 300) followed by forming the pair of non-volatile memory cells with gate structures of some embodiments. - While disclosed methods (e.g.,
methods 300 and 400) are illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. - At 402, similar to at 302, a first hard mask layer is patterned over a first dielectric layer.
- At 404, similar to at 304, a central isolation region and first and second peripheral isolation regions are formed through the dielectric layer into the substrate.
- At 406, similar to at 306, the first hard mask layer is removed to form a first recess between the central isolation region and the first peripheral isolation region and a second recess between the central isolation region and the peripheral isolation region.
- At 408, similar to at 308, a first conductive layer is formed to fill the first and second recesses and over the isolation regions.
- At 410, similar to at 310, a photoresist layer is formed to cover a first portion of the first conductive layer above the central isolation region, and a second portion of the first conductive layer above the first and second peripheral isolation regions is removed, thereby exposing a top surface of the first and second peripheral isolation regions. In some embodiments, removal of the second portion of the first conductive layer is performed by a dry etching process, and act 310 is referred to as a “slit etch”.
- At 412, similar to at 312, performing a planarization to reduce a height of the first portion of the first conductive layer to form a bridge precursor over the central isolation region and to leave the floating gate precursors in the first and second recesses, respectively.
- At 414, a second, conformal dielectric layer, a second conductive layer, and a hard mask layer are stacked over exposed surfaces of the isolation regions and the remaining first conductive layer.
- At 416, an etch is performed through the hard mask layer, the second conductive layer, the second dielectric layer and the remaining first conductive layer to form a pair of gate stacks.
- At 418, a shared source/drain region is embedded within the surface of the semiconductor substrate between the gates stacks and two individual source/drain regions are embedded within the surface of the semiconductor substrate about outermost sides the gates stacks.
- With reference to
FIGS. 5-13 , cross-sectional views of some embodiments of the semiconductor structure at various stages of manufacture are provided to illustrate some embodiments of forming non-volatile memory cells. Figures with a suffix of “A” correspond to cross-sectional views along an x direction, and figures with a suffix of “B” correspond to cross-sectional views along a y direction that is perpendicular to the x direction. AlthoughFIGS. 5A-13B are described in relation to themethod 400, it will be appreciated that the structures disclosed inFIGS. 5A-13B are not limited to themethod 400, but instead may stand alone as structures independent of themethod 400. Similarly, although themethod 400 is described in relation toFIGS. 5A-13B , it will be appreciated that themethod 400 is not limited to the structures disclosed inFIGS. 5A-13B , but instead may stand alone independent of the structures disclosed inFIGS. 5A-13B . - As shown by
FIGS. 5A & B, a firstdielectric layer 610 is formed over asemiconductor substrate 620. Thesemiconductor substrate 620 is typically planar with a uniform thickness. Further, thesemiconductor substrate 620 is n- or p-type, and can, for example, be a handle wafer, such as a Si wafer or a silicon-on-insulator (SOI) substrate. If present, an SOI substrate is often made up of an active layer of high quality silicon. Thefirst dielectric layer 610 can be an oxide, such as silicon dioxide. Amask layer 602 is formed on thefirst dielectric layer 610. Themask layer 602 is formed and patterned so it covers diffusion regions (e.g. 602 a, 602 b, 602 c and 602 d) of thesemiconductor substrate 620. For example, themask layer 602 can be formed to leave exposed only those regions of thesemiconductor substrate 620 to be employed as isolation regions. Themask layer 602 is typically formed of silicon nitride, but other materials are amenable. - As shown by
FIGS. 6A & B, a first etch is performed through thefirst dielectric layer 610 and partially into thesemiconductor substrate 620 in accordance with themask 602 to create trenches. The trenches are spaced to define diffusion regions therebetween for the non-volatile memory cells. An insulating material is formed to fill the trenches to formisolation regions 702 a-e. The insulating material can be formed filling the trenches and covering themask layer 602 first; then be planarized to exposed themask layer 602. The insulating material can be an oxide, such as silicon dioxide. - As shown by
FIGS. 7A & B, a second etch is performed through themask layer 602 to remove themask layer 602 and to create recesses between theisolation regions 702 abutting sidewalls of theisolation regions 702. - As shown by
FIGS. 8A & B, a firstconductive layer 802 is formed to fill the recesses and cover the insulating material. The firstconductive layer 802 is typically formed of polysilicon and typically has a maximum thickness of from about 450 Å to about 550 Å. A anti-reflective coating (BARC)layer 804 with a thickness of from about 400 Å to about 800 Å can be formed on the firstconductive layer 802. - As shown by
FIGS. 9A & B, a photoresist layer 902 is formed to cover a first portion of the firstconductive layer 802 above a first group of isolation regions, named central isolation regions, including for example 702 b and 702 d, and a second etch is performed to a second portion of the firstconductive layer 802 above the second group of isolation regions, named peripheral isolation regions, including for example, 702 a, 702 c and 702 e; thereby exposingtop surfaces - As shown by
FIGS. 10A & B, a planarization process, for example, a chemical-mechanical polishing (CMP) process is performed to reduce a height to the first portion of the firstconductive layer 802 to formbridge precursors central isolation regions conductive layer 802′ is about 350Å. - As shown by
FIGS. 11A & B, a second,conformal dielectric layer 1102, a secondconductive layer 1104, and ahard mask layer 1106 are stacked or formed in that order over theisolation regions 702 and the remaining firstconductive layer 802′. Thesecond dielectric layer 1102 is typically an ONO dielectric and conforms to the remaining firstconductive layer 802′ and theperipheral isolation regions 702 b, 702 c and 702 e, etc. The secondconductive layer 1104 is typically polysilicon and typically has a planar top surface. Thehard mask layer 1106 is typically a nitride-oxide-nitride (NON) dielectric and typically has a planar top surface. - As shown by
FIGS. 12A & B, an etch is performed through the hard mask, second conductive, second dielectric and the remaining firstconductive layers gate stacks control gates 1104′a, 1104′b and a pair of spaced floatinggates control gates 1104′. The formedcontrol gates 1104′ are each sandwiched between an inter-gatedielectric regions 1102′a, 1102′b and ahard mask 1106′a, 1106′b, and each rest at the floatinggate dielectric region 1102′ electrically isolates the remaining firstconductive layer 802′ from thecontrol gates 1104, while thehard mask 1106′ masks thecontrol gates 1104′ during manufacture. In some embodiments,spacers control gate 1104′. The spacers 1202 of thecontrol gates 1104′ extend from the floatinggates control gate 1104′, to approximately even with a top surface of thehard mask 1106′. In some embodiments, the spacers 1202 are formed by conformally forming an intermediate dielectric layer over sidewalls of thecontrol gates 1106′ and the inter-gatedielectric regions 1104′, over thehard masks 1106′, and over the floatinggates Liners gates gate semiconductor substrate 620, along the sidewalls of the floatinggate hard mask 1106′. In some embodiments, the liners 1204 can be formed by conformally forming an intermediate dielectric layer over sidewalls of the floating gates and the spacers 1202, over thehard masks 1106′, and over thesemiconductor substrate 620. Typically, the intermediate dielectric layer is an oxide dielectric formed by high temperature oxide (HTO) deposition. An etch is then performed through the intermediate dielectric layer to remove portions of the intermediate dielectric layer that line or are otherwise formed on a horizontal surface of thesemiconductor substrate 620 and, in some embodiments, thehard masks 1106′. - As shown by
FIGS. 13A & B, a shared source/drain region 1314 is embedded within the surface of thesemiconductor substrate 620 between the gates stacks 1232 a and 1232 b. In some embodiments, the embedding is performed by masking peripheral regions of the semiconductor structure (i.e., those regions outside a central region between the gate stacks 1232 a and 1232 b) with a photoresist. Thereafter, theliners semiconductor substrate 620 to form the shared source/drain region 1314 with a predefined thickness, such as 20 A. With the shared source/drain region 1314 embedded, the photoresist is removed. The shared source/drain region 1314 may be of an opposite type as thesemiconductor substrate 620 or of an opposite type as a well region or active region in which the non-volatile memory cells are formed.Second lines - Still shown by
FIGS. 13A & B, two individual source/drain regions semiconductor substrate 620 about outermost sides the gates stacks 1232 a and 1232 b. In some embodiments, the individual source/drain regions 1312 are embedded by masking a central region between the gates stacks 1232 with a photoresist. Thereafter, ions (e.g., n+ ions) of the same type as the shared source/drain region 1314 are implanted into thesemiconductor substrate 620 to form the individual source/drain regions 1312 with a predefined thickness, such as 20 A. The shared and individual source/drain regions drain region 1314 in the middle of the two individual source/drain regions 1312. Further, each individual source/drain region 1312 and the shared source/drain region 1314 define achannel region - Thus, as can be appreciated from above, the present disclosure provides a non-volatile memory cell that employs a floating gate bridge connecting a first floating gate of a first transistor and a second floating gate of a second transistor.
- In some embodiments, the present disclosure provides a non-volatile memory cell disposed over a substrate. The non-volatile memory cell comprises a first active region and a second active region separated by a central isolation region in a first direction. The non-volatile memory cell further comprises first and second peripheral isolation regions disposed about outermost sides of the first and second active regions. The central isolation region and the first and second peripheral isolation regions have a first height above the first and second active regions forming a first recess between the central isolation region and the first peripheral isolation region, and a second recess between the central isolation region and the second peripheral isolation region. The non-volatile memory cell further comprises first and second floating gates disposed in the first and second recesses respectively and a floating gate bridge disposed over the central isolation region electrically connecting the first and second floating gates. The first floating gate is disposed abutting a first sidewall of the first peripheral isolation region and the second floating gate is disposed abutting a second sidewall of the second peripheral isolation region.
- In other embodiments, the present disclosure provides a non-volatile memory. The non-volatile memory comprises a plurality of non-volatile memory cells arranged in a plurality of rows and columns in a semiconductor substrate of a first conductivity type. Each memory cell comprises a first transistor and a second transistor. The first transistor comprises a first region and a second region of a second conductivity type spaced apart from one another by a first channel region, defined in a column direction; a first floating gate disposed over the first channel region, insulated from the first channel region by a first dielectric layer; and a first control gate disposed over the first floating gate, insulated from the first floating gate by a second dielectric layer. The second transistor comprises a third region and a fourth region of a second conductivity type spaced apart from one another by a second channel region, defined in a column direction; a second floating gate disposed over the second channel region, insulated from the second channel region by the first dielectric layer; and a second control gate disposed over the second floating gate, insulated from the second floating gate by the second dielectric layer. The second transistor is spaced apart from the first transistor in a row direction substantially perpendicular to the column direction. The first region and the third region are aligned in the row direction and insulated from one another in the substrate by an central isolation region. The first floating gate is disposed abutting a sidewall of a first peripheral isolation region and the second floating gate is disposed abutting a sidewall of a second peripheral isolation region disposed about outermost sides of the first and second transistors in the row direction and electrically connected by a floating gate bridge.
- In yet other embodiments, the present disclosure provides a method of forming a non-volatile memory cell over a semiconductor substrate. In the method, a first hard mask layer is patterned over a first dielectric layer. Then a central isolation region and first and second peripheral isolation regions are formed through the dielectric layer into the substrate. The central isolation region is formed between innermost sides the first and second peripheral isolation regions and the central isolation region and the first and second peripheral isolation regions are spaced apart from one another by the first hard mask layer in a first direction. Then the first hard mask layer is removed to form a first recess between the central isolation region and the first peripheral isolation region and a second recess between the central isolation region and the peripheral isolation region. Then a first conductive layer if formed filling the first and second recesses and over the isolation regions. Then a photoresist layer is formed to cover a first portion of the first conductive layer above the central isolation region, and a second portion of the first conductive layer above the first and second peripheral isolation regions is etched, thereby exposing a top surface of the first and second peripheral isolation regions. Then a planarization is performed to reduce a height of the first portion of the first conductive layer to form a bridge precursor over the central isolation region and to leave floating gate precursors in the first and second recesses, respectively. The bridge precursor connects the floating gate precursors in the different recesses.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein.
- Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (21)
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TWI622133B (en) * | 2017-05-17 | 2018-04-21 | Powerchip Technology Corporation | Memory structure and manufacturing method thereof |
US10170488B1 (en) * | 2017-11-24 | 2019-01-01 | Taiwan Semiconductor Manfacturing Co., Ltd. | Non-volatile memory of semiconductor device and method for manufacturing the same |
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US4794565A (en) | 1986-09-15 | 1988-12-27 | The Regents Of The University Of California | Electrically programmable memory device employing source side injection |
US6140182A (en) | 1999-02-23 | 2000-10-31 | Actrans System Inc. | Nonvolatile memory with self-aligned floating gate and fabrication process |
US6103573A (en) | 1999-06-30 | 2000-08-15 | Sandisk Corporation | Processing techniques for making a dual floating gate EEPROM cell array |
US20060145192A1 (en) | 2002-05-31 | 2006-07-06 | Van Duuren Michiel J | Denise array structure for non-volatile semiconductor memories |
US6747310B2 (en) | 2002-10-07 | 2004-06-08 | Actrans System Inc. | Flash memory cells with separated self-aligned select and erase gates, and process of fabrication |
US7358134B2 (en) | 2003-09-15 | 2008-04-15 | Powerchip Semiconductor Corp. | Split gate flash memory cell and manufacturing method thereof |
KR100511598B1 (en) * | 2003-09-24 | 2005-08-31 | 동부아남반도체 주식회사 | Method of fabricating a flash memory |
US7075140B2 (en) | 2003-11-26 | 2006-07-11 | Gregorio Spadea | Low voltage EEPROM memory arrays |
US7046552B2 (en) | 2004-03-17 | 2006-05-16 | Actrans System Incorporation, Usa | Flash memory with enhanced program and erase coupling and process of fabricating the same |
KR100564628B1 (en) | 2004-06-16 | 2006-03-28 | 삼성전자주식회사 | Split gate type flash mwmory device and method of manufacturing the same |
US7483332B2 (en) | 2005-08-11 | 2009-01-27 | Texas Instruments Incorporated | SRAM cell using separate read and write circuitry |
KR100720481B1 (en) * | 2005-11-28 | 2007-05-22 | 동부일렉트로닉스 주식회사 | Method for manufacturing semiconductor device |
US7355236B2 (en) * | 2005-12-22 | 2008-04-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Non-volatile floating gate memory cells with polysilicon storage dots and fabrication methods thereof |
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US7598561B2 (en) | 2006-05-05 | 2009-10-06 | Silicon Storage Technolgy, Inc. | NOR flash memory |
US7514740B2 (en) * | 2006-07-10 | 2009-04-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Logic compatible storage device |
US20090039410A1 (en) | 2007-08-06 | 2009-02-12 | Xian Liu | Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing |
US7906805B2 (en) | 2008-08-22 | 2011-03-15 | Actel Corporation | Reduced-edge radiation-tolerant non-volatile transistor memory cells |
US8384147B2 (en) | 2011-04-29 | 2013-02-26 | Silicon Storage Technology, Inc. | High endurance non-volatile memory cell and array |
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