JP2013110265A - Nonvolatile semiconductor storage device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device having high controllability, and provide a manufacturing method of the nonvolatile semiconductor storage device.SOLUTION: A nonvolatile semiconductor storage device comprises: a first memory cell array layer; a first insulation layer formed on the first memory cell array layer; a second memory cell array layer formed on the first insulation layer; a control gate formed via an inter-gate insulation layer, on both lateral faces in a first direction of first and second floating gates vertically positioned via a first insulation layer, and extending in a second direction orthogonal to the first direction; and an auxiliary gate formed via the inter-gate insulation layer, on both lateral faces in the first direction of the first and second floating gates vertically positioned via the first insulation layer, and extending in the second direction, and forming an auxiliary transistor together with first and second semiconductor layers and first and second gate insulation layers.

Description

  The technology described in this specification relates to a nonvolatile semiconductor memory device and a manufacturing method thereof.

  A NAND flash memory is known as a nonvolatile semiconductor memory device that can be electrically rewritten and can be highly integrated. A memory transistor of a conventional NAND flash memory has a stack gate structure in which a charge storage layer (floating gate) and a control gate are stacked via an insulating film. A plurality of memory transistors are connected in series in the column direction so that adjacent ones share a source or drain, and select gate transistors are arranged at both ends to constitute a NAND cell unit. One end of the NAND cell unit is connected to the bit line, and the other end is connected to the source line. A memory cell array is configured by arranging NAND cell units in a matrix. A NAND cell unit arranged in the row direction is called a NAND cell block. The gates of the select gate transistors arranged in the same row are connected to the same select gate line, and the control gates of the memory transistors arranged in the same row are connected to the same word line. When N memory transistors are connected in series in the NAND cell unit, the number of word lines included in one NAND cell block is N.

  In such a NAND flash memory, various problems described below have arisen due to the reduction in gate length accompanying the miniaturization and the reduction in the distance between adjacent transistors. For example, (a) an increase in parasitic capacitance between adjacent gates, a decrease in drain current controllability due to a control gate electric field due to a short channel effect (SCE), etc., (b) an increase in interference effect between adjacent gates, (c ) Increase in leakage between adjacent electrodes, (d) Pattern misalignment and collapse during gate processing due to high aspect ratio of gate electrode, (e) Significant decrease in number of electrons (number of electrons per bit) that can be accumulated in charge storage layer This is a problem such as deterioration of data retention characteristics caused by the problem. For this reason, in the conventional NAND flash memory, the write / erase window of the memory cell is drastically lowered and the physical limit of miniaturization is being reached.

  As a technique for future high integration, there is a “three-dimensional stacked type” memory in which memory cell transistors are stacked three-dimensionally. Specifically, many structures for stacking nitride trap type (SONOS, MONOS) cells have been proposed in papers and the like, but the nitride trap type cell structure has the advantage of being easy to process (stack). However, there is a big problem that the erasing characteristic and the data retention characteristic are worse than those of the floating gate type cell due to the characteristic of trapping electrons in the nitride film.

  On the other hand, in the conventional floating gate type memory cell structure in which charges are accumulated in the floating gate electrode, the control gate electrode and the IPD film (interpoly insulating film or inter-gate insulating film) are not only on the upper surface of the floating gate electrode but also on the side surface. In addition, since it has an EB (etch back) structure that ensures the driving force (coupling ratio) of the control gate electrode by turning along, the processing difficulty is high and stacking is difficult. In order to widen the write / erase window of the memory cell, when the coupling ratio is set higher, it is necessary to increase the thickness of the floating gate electrode as one method. In this EB structure, the floating gate electrode Since the IPD film and the control gate electrode are stacked on top of each other, as a result, the word line itself becomes higher and the aspect ratio is increased, so that the problem (d) becomes obvious and the coupling ratio is not easily improved. Absent.

  Therefore, as one of the cell structures that ensure the coupling ratio without extremely increasing the processing difficulty, control is performed via the inter-gate insulating film between the floating gates in the word line direction instead of the stacked gate structure. There has been proposed a structure in which a coupling ratio is ensured by embedding a gate electrode and raising the potential of a cell to be written with control gate electrodes on both sides.

  However, in these memory cells, since simple stacking results in a simple increase in the number of processes, it is difficult to secure an increase in cell capacity commensurate with an increase in cost and reduce the bit cost. In simple stacking, the bit cost shrink ratio = 1 / the number of stacked stages is effective only by dividing the number of stages, and when the number of stacked layers is increased, the shrink ratio is small and the bit cost is likely to be high. For this reason, in the cell structure aiming at shrinking by stacking, it is a practical problem to keep the number of processes and cost low.

JP 2007-266143 A JP 2004-319948 A JP 2005-100501 A

  An object of the present invention is to provide a nonvolatile semiconductor memory device with high controllability and a method for manufacturing the same.

  The nonvolatile semiconductor memory device according to the embodiment includes a plurality of first memory cells connected in series in a first direction, and a first source line connected between the plurality of first memory cells and the source line. A first NAND cell unit including a side select gate transistor and a first bit line side select gate transistor connected between the plurality of first memory cells and the bit line, wherein the first memory cell includes: A first semiconductor layer, a first gate insulating layer formed on the first semiconductor layer, and a first floating gate formed on the first gate insulating layer, A first source line side select gate transistor and a first bit line side select gate transistor formed on a first semiconductor layer, a first gate insulating layer, and a first gate insulating layer; A first memory cell array having a select gate; A first insulating layer formed on the first memory cell array layer, and a plurality of second memory cells formed on the first insulating layer and connected in series in the first direction. A second source line side select gate transistor connected between the plurality of second memory cells and the source line, and a second bit line connected between the plurality of second memory cells and the bit line A second NAND cell unit comprising a side select gate transistor, the second memory cell comprising: a second floating gate; a second gate insulating layer formed on the second floating gate; A second semiconductor layer formed on the second gate insulating layer, wherein the second source line side select gate transistor and the second bit line side select gate transistor include the second semiconductor layer, A second gate insulating layer and a second gate insulating layer; Insulation between the gates on both side surfaces in the first direction of the formed second memory cell array layer having the second selection gate and the first and second floating gates located above and below via the first insulating layer A control gate formed through the layer and extending in a second direction orthogonal to the first direction, and first and second select gates positioned above and below the first insulating layer in the first direction An auxiliary gate is formed on both side surfaces via an inter-gate insulating layer, extends in the second direction, and forms an auxiliary transistor together with the first and second semiconductor layers and the first and second gate insulating layers.

1 is a block diagram showing an overall configuration of a nonvolatile semiconductor memory device according to a first embodiment. It is a perspective view which shows the memory cell array structure of the non-volatile semiconductor memory device. It is sectional drawing of the GC direction which shows the structure of the memory cell array. FIG. 3 is a cross-sectional view taken along lines AA ′, BB ′, and CC ′ of FIG. 2. It is an equivalent circuit diagram of the same memory cell array. 4 is a schematic view showing a write operation of the nonvolatile semiconductor memory device. FIG. 4 is a schematic view showing a read operation of the nonvolatile semiconductor memory device. FIG. 3 is a schematic view showing an erase operation of the nonvolatile semiconductor memory device. FIG. It is sectional drawing which shows the manufacturing process of the memory cell array. It is sectional drawing which shows the manufacturing process of the memory cell array. It is sectional drawing which shows the manufacturing process of the memory cell array. It is sectional drawing which shows the manufacturing process of the memory cell array. It is sectional drawing which shows the manufacturing process of the memory cell array. It is sectional drawing which shows the manufacturing process of the memory cell array. It is sectional drawing which shows the manufacturing process of the memory cell array. It is sectional drawing which shows the manufacturing process of the memory cell array. It is sectional drawing which shows the manufacturing process of the memory cell array. It is sectional drawing which shows the manufacturing process of the memory cell array. It is sectional drawing which shows the manufacturing process of the memory cell array. It is sectional drawing which shows the manufacturing process of the memory cell array. It is sectional drawing which shows the manufacturing process of the memory cell array. It is sectional drawing which shows the manufacturing process of the memory cell array. It is sectional drawing which shows the manufacturing process of the memory cell array. It is sectional drawing which shows the manufacturing process of the memory cell array. It is sectional drawing which shows the manufacturing process of the memory cell array. It is sectional drawing which shows the manufacturing process of the memory cell array. It is sectional drawing which shows the manufacturing process of the memory cell array. FIG. 6 is a schematic diagram showing an erase operation of a nonvolatile semiconductor memory device according to a second embodiment. It is a figure which shows the structure of the memory cell array of the NAND type flash memory of a comparative example. FIG. 6 is an equivalent circuit diagram of a memory cell array of a NAND flash memory of a comparative example.

  Embodiments will be described below with reference to the accompanying drawings.

[Basic memory cell array structure]
First, prior to the description of the first embodiment, a memory cell structure of a NAND flash memory that is the basis of the nonvolatile semiconductor memory device according to the present embodiment will be described.

  In this embodiment, a cell structure that secures coupling between the floating gate and the control gate is not a stack gate structure, but the control gate is embedded on both sides of the floating gate so that the floating gate and the control gate on both sides thereof are connected. A gate structure to be coupled is included.

  FIG. 29 is a diagram showing a structure of a memory cell array 1 of a NAND flash memory of a comparative example adopting this structure, and FIG. 30 is an equivalent circuit diagram of the memory cell array 1.

The memory cell array 50 includes a NAND string in which _M non-volatile memory cells MC _{0 to} MC _M−1 that can be electrically rewritten are connected in series, and select gate transistors S1 and S2 connected to both ends of the NAND string. A plurality of NAND cell units NU are arranged. One end (selection gate transistor S1 side) of the NAND cell unit NU is connected to the bit line BL, and the other end (selection gate transistor S2 side) is connected to the common source line CELSRC. The gate electrodes of the select gate transistors S1 and S2 are connected to select gate lines SGD and SGS. Control gate electrodes arranged on both sides of the memory cells MC _{0 to} MC _M-1 are connected to word lines WL _{0 to} WL _M , respectively. The bit lines BL are connected to the sense amplifier circuit 60, the word line _WL 0 to WL _M and the select gate lines SGD, SGS are connected to the row decoder circuit 70.

  In the p-type well 51 formed on the substrate, an n-type diffusion layer 52 that functions as a source and drain of a MOSFET constituting the memory cell MC is formed. A floating gate (FG) 54 is formed on the well 51 via a gate insulating film 53 functioning as a tunnel insulating film, and both sides of the floating gate 54 are interposed via an inter-gate insulating layer (IPD) 55. A control gate (CG) 56 is formed. The control gate 56 constitutes a word line WL. Further, the selection gate transistors S 1 and S 2 have a selection gate 57 on the well 51 through a gate insulating layer 53. The selection gate 57 constitutes selection gate lines SGS and SGD. Memory cell MC and select gate transistors S1, S2 are NAND-connected in such a manner that adjacent ones share a drain and a source.

  In the case of 1 bit / cell in which 1 bit of data is stored in one memory cell MC, 1 page of data is stored in the memory cell MC formed along the word line WL intersecting the NAND cell unit NU. In the case of 2 bits / cell in which 2-bit data is stored in one memory cell MC, two pages (upper page UPPER, lower page LOWER) of data are stored in the memory cell MC formed along the word line WL. Is memorized.

  One block BLK includes a plurality of NAND cell units NU sharing the word line WL. One block BLK forms one unit of data erasing operation. In one memory cell array 1, the number of word lines WL in one block BLK is M + 1, and the number of pages in one block is M × 2 = 128 pages in the case of 2 bits / cell.

  When writing data to the memory cell MC to be written, the voltage of the control gate 56 on both sides of the floating gate 54 is raised to a predetermined write voltage, and the control gates 56 from both sides to both ends are alternately switched to a low voltage and a high voltage. By sequentially lowering the voltage value so as to become, it is possible to prevent erroneous writing from occurring in unselected memory cells.

[First Embodiment]
[overall structure]
FIG. 1 is a block diagram of a nonvolatile semiconductor memory device according to the first embodiment of the present invention.

  This nonvolatile semiconductor memory device includes a memory cell array 1 including a plurality of NAND strings in which a plurality of memory cells MC are NAND-connected.

  Column control for controlling the bit line BL of the memory cell array 1 at a position adjacent to the bit line BL direction of the memory cell array 1 to perform data erasure of the memory cell, data writing to the memory cell, and data reading from the memory cell. A circuit 2 is provided.

  In addition, the word line WL of the memory cell array 1 is selected at a position adjacent to the word line WL direction of the memory cell array 1 and is necessary for erasing data in the memory cell, writing data to the memory cell, and reading data from the memory cell. A row control circuit 3 is provided for applying an appropriate voltage.

  The data input / output buffer 4 is connected to an external host 9 via an I / O line, and receives write data, receives an erase command, outputs read data, and receives address data and command data. The data input / output buffer 4 sends the received write data to the column control circuit 2, receives the data read from the column control circuit 2, and outputs it to the outside. An address supplied from the outside to the data input / output buffer 4 is sent to the column control circuit 2 and the row control circuit 3 via the address register 5.

  The command supplied from the host 9 to the data input / output buffer 4 is sent to the command interface 6. The command interface 6 receives an external control signal from the host 9, determines whether the data input to the data input / output buffer 4 is write data, a command, or an address, and if it is a command, receives it as a received command signal to the state machine 7. Forward.

  The state machine 7 manages the entire nonvolatile memory. The state machine 7 receives commands from the host 9 via the command interface 6 and performs read, write, erase, data input / output management, and the like.

  The external host 9 can also receive status information managed by the state machine 7 and determine the operation result. This status information is also used for control of writing and erasing.

  Further, the voltage generator 10 is controlled by the state machine 7. By this control, the voltage generation circuit 10 can output a pulse having an arbitrary voltage and arbitrary timing.

  Here, the formed pulse can be transferred to an arbitrary wiring selected by the column control circuit 2 and the row control circuit 3.

[Memory cell array structure]
Next, the memory cell array structure according to the first embodiment will be described.

  2 is a perspective view of the memory cell array structure according to the first embodiment, FIG. 3 is a cross-sectional view seen from the GC (gate) direction of FIG. 1, and FIG. 4 is AA ′, BB ′ of FIG. FIG. 3 is a cross-sectional view taken along line AA (active area) in FIG. In order to make the internal structure visible, a part of the structure is omitted.

  In this memory cell array structure, the memory cell array structure shown in FIGS. 29 and 30 is vertically inverted and stacked, and the control gate is shared by the upper and lower memory cell array layers.

  That is, as shown in FIG. 2, a first semiconductor layer 11 and a second semiconductor layer 21 which are bodies forming a channel are arranged on the top and bottom of an insulating base 30, and the first gate is interposed therebetween. A first floating gate 13 facing the upper surface of the first semiconductor layer 11 via the insulating layer 12 and a second floating gate facing the lower surface of the second semiconductor layer 21 via the second gate insulating layer 22 23 are stacked one above the other through the first insulating layer 31. These semiconductor layers 11, 21, gate insulating layers 12, 22 and floating gates 13, 23 are layers extending in the AA direction (first direction), as is clear from the AA ′ cross section of FIG. The insulating layers 15 and 25 are insulated from each other in the GC direction (second direction).

  A plurality of stacked structures of floating gates 13 and 23 are formed at predetermined intervals in the AA direction along the semiconductor layers 11 and 21 so as to form a NAND array. Control gates 33 extending in the GC direction are formed on both sides of the stack of floating gates 13 and 23 in the AA direction via an inter-gate insulating layer (IPD: interpoly insulating layer) 32. The control gate 33 is provided in common to the floating gates 13 and 23 so as to be coupled to the upper and lower floating gates 13 and 23 from the side surface. A mask material 33 m is provided between the control gate 33 and the second gate insulating layer 22. The lower first semiconductor layer 11, the first gate insulating layer 12, the first floating gate 13, the inter-gate insulating layer 32, and the control gate 33 are included in the configuration of the lower first memory cell MC1. included. The upper second semiconductor layer 21, the second gate insulating layer 22, the second floating gate 23, the intergate insulating layer 32, and the control gate 33 are included in the configuration of the upper second memory cell MC2. .

  The first selection gate 16 and the first selection gate 16 forming the selection gate transistors S11, S12, S21, and S22 (FIG. 3) are positioned adjacent to the control gates 33 at both ends in the arrangement direction of the stacked structure of the floating gates 13 and 23. Two select gates 26 are arranged. The select gates 16 and 26 are stacked one above the other through the first insulating layer 31 and face the semiconductor layers 11 and 21 through the gate insulating layers 12 and 22, respectively. A first selection gate line 17 extending in the GC direction is embedded in the first selection gate 16, and a second selection gate line 27 extending in the GC direction and a mask material 27m are embedded in the second selection gate 26. ing. These select gate lines 17 and 27 are insulated from each other through an interlayer insulating layer 34.

  The lower first NAND cell unit NU1 includes a lower NAND-connected memory cell MC1 and select gate transistors S11 and S21. The first memory cell array layer 10 includes a first element isolation insulating layer 15. Through a plurality of NAND cell units NU1 arranged in the GC direction. The upper second NAND cell unit NU2 includes an upper NAND-connected memory cell MC2 and select gate transistors S12 and S22, and the second memory cell array layer 20 includes a plurality of NANDs arranged in the GC direction. Cell unit NU2 is included.

  According to the above configuration, as shown in an equivalent circuit in FIG. 5, the floating gates 13 and 23 of the memory cells MC1 and MC2 corresponding to the upper and lower NAND cell units NU1 and NU2 are connected to the word lines WL on both sides. They are simultaneously driven by coupling and connected to a common bit line BL. On the other hand, the selection gate transistors S11 to S22 are provided independently for the upper and lower bit lines BL, and either one is selectively activated to selectively activate the NAND cell units NU1 and NU2. Can be.

[Auxiliary transistor]
As shown in FIG. 3, the nonvolatile semiconductor memory device according to this embodiment includes a first auxiliary gate 91e between the source line contact 36 and the source line side select gate transistors S21 and S22. A first lower auxiliary transistor 91 a is formed between the first semiconductor layer 11 and the first upper auxiliary transistor 91 b between the second semiconductor layer 21 and the second semiconductor layer 21. Similarly, a second auxiliary gate 92e is provided between the source line side selection gate transistors S21 and S22 and the first and second floating gates 13 and 23, and the first and second floating gates 13 and 23 and the bit are connected. A third auxiliary gate 93e is provided between the line side select gate transistors S11 and S12, and a fourth auxiliary gate 94e is provided between the bit line side select gate transistors S11 and S12 and the bit line contact 35. . Between the first semiconductor layer 11 and the second semiconductor layer 21, a second lower auxiliary transistor 92a and a second upper auxiliary transistor 92b, a third lower auxiliary transistor 93a and a third upper auxiliary transistor 93b, and A fourth lower auxiliary transistor 94a and a fourth upper auxiliary transistor 94b are formed.

[contact]
In the semiconductor layers 11 and 21 at one end of the NAND cell units NU1 and NU2, a bit line contact 35 extending in common up and down to the bit line BL (not shown) is formed. Further, in the semiconductor layers 11 and 21 at the other ends of the NAND cell units NU1 and NU2, a source line contact 36 is formed which extends vertically in common to these and connects to a source line (not shown). Further, a word line contact 37 (FIG. 2) is formed at the end of the control gate 33, and a select gate line contact 38 (FIG. 2) is connected to the ends of the select gate lines 17 and 27.

  The bit line contact 35 includes a lower contact 35a and an upper contact 35b. The lower contact 35 a is connected to the first semiconductor layer 11 through a first groove 81 provided in the first gate insulating layer 12. The lower contact 35a in the present embodiment is formed simultaneously with the first floating gate 13 as described later. Therefore, the widths of the lower contact 35a and the first semiconductor layer 11 in the GC direction are substantially the same. The lower contact 35a is formed of the same material as that of the first floating gate 13, and is formed in the same straight line at the same interval as the first semiconductor layer 11 through the first element isolation insulating layer 15. ing. The upper contact 35b is the same as the second floating gate 23 formed on the lower contact 35a via the second semiconductor layer 21, the second gate insulating layer 22, and the first insulating layer 31. It is buried through a via hole provided so as to penetrate the upper contact layer, the first insulating layer 31 and the lower contact 35a formed of a material.

[Operation method]
Next, an operation method of the nonvolatile semiconductor memory device according to this embodiment is described. Among electrodes such as a channel (body), a floating gate, a bit line and a source line, a certain electrode (first electrode) is different from the first potential, and another electrode (second electrode) is different from the first potential. If the potential difference generated between the first electrode and the second electrode exceeds a certain value when the potential is 2, a malfunction such as GIDL (Gate Induced Drain Leadage) or SCE may occur. Such a problem becomes conspicuous as the insulating film provided between the electrodes becomes thinner.

  The nonvolatile semiconductor memory device according to this embodiment includes the first to fourth auxiliary gates 91e to 94e adjacent to the first electrode and the second electrode via an insulating layer (third electrode). A third voltage is applied to relax the potential difference generated between the first electrode and the second electrode. By applying the third voltage, malfunctions such as GIDL and SCE can be suppressed. Note that the third voltage may be set to a value between the first voltage value and the second voltage value.

[Write operation]
FIG. 6 is a schematic diagram for explaining the write operation of the nonvolatile semiconductor memory device according to this embodiment. Hereinafter, the selected NAND cell unit including the selected memory cell MCselect to be subjected to the write operation is NU12, the unselected NAND cell unit connected to the NAND cell unit NU12 via the first insulating layer 31 is NU11, and the NAND cell unit NU11. The unselected NAND cell units connected to the same source line SL and adjacent to the GC direction via the NU12 and the element isolation insulating films 15 and 25 (FIG. 4) are referred to as NU21 and NU22, respectively.

In the write operation, first, selecting a NAND cell unit NU12 connected to the selected bit line BL1 are selected bit line voltage _{V BL_select} (e.g. 0V), the unselected bit line voltage _{V BL_inhibit} to the unselected bit line BL2 (e.g. Vdd ) Is applied. A source line voltage V _{SL_write} (for example, 0 V) is applied to the source line SL.

Further, the fourth upper auxiliary transistor 94b, the bit line side select gate transistor S12, and the third upper auxiliary transistor 93b are turned on, and the source line side select gate transistor S22 is cut off. As a result, the selected bit line voltage _{VBL_select} is transferred to the second semiconductor layer 21 that operates as a channel (body) of the selected NAND cell unit. Further, the write voltage Vpgm is applied to the pair of control gates 33 adjacent to the second floating gate 23 of the selected memory cell MCselect from both sides in the AA direction to increase the potential of the floating gate 23 of the selected memory cell MCselect, and the floating gate The writing operation is performed by the potential difference between the second semiconductor layer 21 and the second semiconductor layer 21.

In the above write operation, the channel (body) potentials of the unselected NAND cell units NU11, NU21 and NU22 capacitively coupled to the control gate and the gates of the source line side select gate transistors S21 and S22 (selection gate lines 17 and 27) When the difference from the voltage V _{SG — OFF — pgm} applied to the _input voltage exceeds a predetermined voltage value, GIDL occurs in the channel (body) of the source line side select gate transistors of the unselected NAND cell units NU11, NU21, and NU22, causing malfunctions. There are things. Therefore, in the present embodiment, further to the second auxiliary gate 92e, and applies the voltage _{V Gate_2} between the voltage _{V SG_ON_pgm} and the voltage _{V SG_OFF_pgm} applied to selected NAND cell unit to the gate of the selection gate transistors NU12 As a result, the potential difference from the body potential voltage V _{SG_OFF_pgm} of the unselected NAND cell units NU11, NU21 and NU22 is alleviated, and the above problem is avoided.

  In the present embodiment, the fourth upper auxiliary transistor 94b ′ and the source line contact of the NAND cell unit adjacent to the selected NAND cell unit NU12 from the AA direction via the first upper auxiliary transistor 91b and the bit line contact 35. The potential for setting the first upper auxiliary transistor 91b ′ of the NAND cell unit adjacent to the selected NAND cell unit NU12 in the AA direction to the cut-off state via 36 is supplied to the auxiliary gates 91e, 94e ′ and 91 ′. The occurrence of SCE is prevented.

[Read operation]
FIG. 7 is a schematic diagram for explaining the read operation of the nonvolatile semiconductor memory device according to this embodiment. In FIG. 7, an example in which a read operation is performed on the NAND cell units NU12 and NU22 will be described.

In the read operation, first, the read voltage _{V BL_read} applied to the selected bit lines BL1 and BL2, applying a source line voltage _{V SL_read} to the source line SL. Further, the fourth upper auxiliary transistor 94b, the bit line side select gate transistor S12, the third upper auxiliary transistor 93b, the second upper auxiliary transistor 92b, the source line side select gate transistor S22 and the first upper auxiliary transistor 91b are provided. Make it conductive. Further, the read voltage Vread is applied to the pair of control gates 33 adjacent to the floating gate 23 from both sides in the AA direction, and the read operation is performed by applying the voltage Vpass that makes the memory cell MC conductive to the other control gates.

In the read operation, the read voltage _{VBL_read} applied to the bit lines BL1 and BL2 and the bit line side selected source line 27 of the NAND cell unit adjacent to the selected NAND cell unit NU12 from the AA direction via the bit line contact 35. When the difference from the voltage V _{SG_OFF_read} applied to 'exceeds a predetermined voltage value, GIDL occurs in the bit line side select gate transistor S12', which may cause malfunction. Therefore, in the present embodiment, the voltage V _{Gate — 1} ′ between the read voltage V _{BL_read} and the voltage V _{SG_OFF_read} is further applied to the fourth auxiliary gate 94′e, whereby the read voltage V _{BL_read} and the voltage V _{SG_OFF_read} are The potential difference is alleviated and the above problem is avoided.

  In the present embodiment, the first upper auxiliary transistor 91b ′ is cut off to prevent the occurrence of SCE.

[Erase operation]
FIG. 8 is a schematic diagram for explaining the erase operation of the nonvolatile semiconductor memory device according to this embodiment. In FIG. 8, an example in which an erase operation is performed on the NAND cell units NU12 and NU22 will be described.

In the erase operation, first, an erase voltage V _erase is applied to a p-type semiconductor layer provided on a silicon substrate (not shown). Since the bit line contact 35 and the source line contact 36 are configured using an n-type semiconductor in the same manner as the floating gates 13 and 23, the open bit lines BL1 and BL2 are charged to the voltage _{VBL_erase} . Further, the voltage V _WL is applied to the word line (control gate line 33), and the second bit line side select gate line 27 is brought into a floating state.

Further, the fourth auxiliary gate 94e low potential _{V Gate_4} than the erase voltage _{V BL_erase} to apply to generate GIDL and raises the potential of the second semiconductor layer 21 by a hole (holes) h + generated by the GIDL . When the potential of the semiconductor layer 21 rises above a certain level, electrons are extracted from each floating gate 23 capacitively coupled to each control gate line 33, and the erase operation is completed.

In the erasing operation, the potential of the second bit line side select gate line 27 is lowered by capacitive coupling with the fourth auxiliary gate 94e, but when the potential difference with the second semiconductor layer 21 exceeds a predetermined value. There is a risk that dielectric breakdown may occur between the first bit line side select gate line 17 and the second semiconductor layer 21. Therefore, in this embodiment relaxes the potential difference between the second semiconductor layer 21 by pulling the potential of the second bit line side select gate lines 27 by applying a potential V _{Gate_3} the third upper auxiliary gate 93e , To avoid the above problems.

[Method for Manufacturing Memory Cell Array Structure]
Next, a method for manufacturing the memory cell array structure of this embodiment will be described.

  First, the peripheral circuit region can be formed in several variations. When the peripheral circuit region is formed on a bulk silicon substrate, it is necessary to form the peripheral circuit first. At this time, the memory cell array of this embodiment may be simultaneously formed on a bulk silicon substrate. In the present embodiment, since NAND cell units NU1 and NU2 are three-dimensionally provided, an example in which NAND cell units NU1 and NU2 are formed on a silicon substrate will be described. The method for forming the peripheral circuit transistor is the same as a general method. That is, first, a channel is formed on a silicon substrate, a gate oxide film (both low voltage oxide film and high voltage oxide film) is formed, a gate electrode and an AA (active area) processing mask material are stacked, and then an STI groove is formed. To do. Next, after embedding the STI trench, a GC (gate) processing mask material is stacked, GC electrode processing, and sidewall insulating film formation are performed, then a source / drain diffusion layer is formed, an inter-GC insulating film is embedded, Flatten.

  After the peripheral circuit is formed, the memory cell array of this embodiment is formed on this upper layer. 9 to 27 are views showing a method of forming a memory cell array according to the present embodiment.

First, as shown in FIG. 9, an insulating layer 30A using SiO ₂ is formed on a silicon substrate (not shown), and a first semiconductor layer 11A using polysilicon is formed thereon, and a first semiconductor layer 11A using SiO ₂ is formed. A gate insulating layer 12A and a first gate formation layer 13aA using polysilicon are sequentially stacked. The first semiconductor layer 11A serving as a channel (body) is basically formed using polysilicon, but single crystal silicon may also be used. In this embodiment, polysilicon is used for the channel (body) and the SOI structure is used, so that it is not necessary to form STI on the silicon substrate, and a cell structure suitable for stacking can be obtained. Since the gate insulating layer 12A is formed on the semiconductor layer 11A using polysilicon, a CVD (Chemical Vapor Deposition) or ALD (atomic layer deposition) oxide film is used instead of a thermal oxide film. The first semiconductor layer 11A is formed by film formation as described above, but a silicon substrate may be used as it is.

  Next, as shown in FIG. 10, a first groove 81 extending in the GC direction is provided on the surfaces of the first gate forming layer 13aA, the first gate insulating layer 12A, and the first semiconductor layer 11A. Next, as shown in FIG. 11, the second gate formation layer 13bA is formed on the first floating gate formation layer 13aA and the surface of the first semiconductor layer 11A in the portion exposed by the first trench 81.

After the formation up to the second gate formation layer 13bA, as shown in FIG. 12, mask materials 41 and 42 using, for example, SiN or SiO ₂ for AA pattern processing are formed thereon. Next, as shown in FIG. 13, the stacked body is selectively etched down to the bottom of the insulating layer 30A by RIE (Reactive Ion Etching) using mask materials 41 and 42 to provide a second groove, and the AA pattern is processed. To do. Thereby, the floating gate forming layer 13B, the first gate insulating layer 12, the first semiconductor layer 11, and the insulating layer 30 are formed.

Next, as shown in FIG. 14, the first element isolation insulating layer 15 using SiO ₂ is buried in the groove formed by AA pattern processing, and the polysilicon forming the first gate forming layer 13B is used as a stopper. Planarization is performed by CMP (Chemical Mechanical Polishing), and the upper surface of the first element isolation insulating layer 15 is retreated by etch back. Next, as shown in FIG. 15, a first insulating layer 31 for separating the upper layer and the lower layer is formed on the first element isolation insulating layer 15 and the first gate forming layer 13B, and a polycrystal is formed on the first insulating layer 31. A third gate forming layer 23A using silicon is formed.

Subsequently, as shown in FIG. 16, mask materials 43 and 44 using, for example, SiN or SiO ₂ for GC pattern processing are formed on the third gate formation layer 23A. Then, as shown in FIG. 17, the stacked body is selectively etched up to the top of the gate insulating layer 12 by RIE using mask materials 43 and 44 to form a third groove, thereby forming a GC pattern. Thereby, the first floating gate 13, the third gate formation layer 23B, the first selection gate formation layer 16A, the second selection gate formation layer 26A, and the lower contacts 35a and 36a are formed. The GC pattern processing is preferably performed by etching having a high selectivity with the lower gate insulating layer 12 so that the lower semiconductor layer 11 is not etched.

Subsequently, as shown in FIG. 18, an inter-gate insulating layer (IPD) 32 using SiO ₂ is formed, and then a control gate forming layer 33A is embedded between the GC patterns. As the control gate formation layer 33A, polysilicon, metal (such as W), or metal silicide (such as WSi) can be used.

  Next, as shown in FIG. 19, the control gate 33 and the auxiliary gates 91e to 94e are formed by etching back the control gate formation layer 33A by RIE. Further, as shown in FIG. 20, a mask material 33m using a CVD oxide film or a coating oxide film is buried, and the upper surface is flattened by CMP using a mask 43 using SiN as a stopper. After that, in order to form select gate forming layers 16A and 26A and transistors of a row decoder section (not shown), select gate groove processing corresponding to an EI (Etching Inter Poly) groove is performed by RIE or the like, as shown in FIG. A fourth groove 17A reaching the second selection gate formation layer 26B, the first insulating layer 31, and the first selection gate 16 is formed.

  Next, in order to form independent selection gate transistors S11 to S22 in each of the upper layer cell and the lower layer cell, as shown in FIG. 22, the first selection gate line 17, the interlayer insulating layer 34, The second selection gate line 27 is sequentially formed while repeating filling and etching back. As the selection gate lines 17 and 27, polysilicon, metal (W or the like), or metal silicide (WSi or the like) can be used similarly to the control gate 33 and the auxiliary gates 91e to 94e. A cap insulating layer 27m is buried in the etched back portion on the second selection gate line 27, and the upper surface thereof is planarized by CMP using the mask material 43 as a stopper. FIGS. 23A, 23B, and 23C are an AA ′ cross section, a BB ′ cross section, and a CC ′ cross section, respectively, in FIG.

Next, as shown in FIG. 24, planarization by CMP is performed using the third gate formation layer 23B as a stopper, and a second gate insulating layer 22A using SiO ₂ is formed on the third gate formation layer 23B, and polysilicon is used. Two semiconductor layers 21A are sequentially formed. Note that CMP may be performed using the control gate 33 as a stopper. FIGS. 25A, 25B, and 25C are an AA ′ section, a BB ′ section, and a CC ′ section, respectively, in FIG.

  Subsequently, as shown in FIG. 26, AA pattern processing is performed on the second semiconductor layer 21A, the second gate insulating layer 22A, the third gate formation layer 23B, and the second selection gate formation layer 26B. For this purpose, a mask material 45 using SiN for AA pattern processing is formed on the second semiconductor layer 21A, and AA pattern processing is performed by RIE. FIGS. 27A, 27B, and 27C are an AA ′ cross section, a BB ′ cross section, and a CC ′ cross section of FIG. 26, respectively. Through the above steps, the second floating gate 23 is formed, and the second gate insulating layer 22 and the second semiconductor layer 21 are formed in a self-aligned manner with respect to the second floating gate 23.

  Next, the second element isolation insulating layer 25 (FIGS. 1 and 3) is embedded in the upper AA pattern groove. Finally, via holes are formed in the second semiconductor layer, the second gate insulating layer, the upper contact layer, the first insulating layer, and the lower contact, and the upper contact is embedded in the formed via hole. When forming the via contact, the via hole is provided so as to penetrate the first insulating layer and expose the upper surface of the lower contact.

  As in the present embodiment, the auxiliary gates 91e and 94e can be formed using a process common to the process of forming the control gate line 33, and the number of manufacturing processes can be reduced.

[Second Embodiment]
Next, the erase operation of the nonvolatile semiconductor memory device according to the second embodiment will be described. FIG. 28 is a schematic diagram for explaining an erasing operation of the nonvolatile semiconductor memory device according to the present embodiment. The erase operation of the nonvolatile semiconductor memory device according to this embodiment is basically the same as that of the first embodiment, but differs in the following points. That is, in the present embodiment, the fourth upper auxiliary transistor 94b is turned on, and the voltage V _{SG_erase} lower than the erase voltage V _{BL_erase} is applied to the second bit line side select gate line 27 to generate GIDL. The potential of the second semiconductor layer 21 is increased by holes (holes) h + generated by GIDL. The voltage V _{SG_erase} is set to a value that does not cause dielectric breakdown between the second selection gate line 27 and the second semiconductor layer 21 and between the second selection gate line 27 and the first selection gate line 17. .
[Other Embodiments]
As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... 1st memory cell array layer, 11 ... 1st semiconductor layer, 12 ... 1st gate insulating layer, 13 ... 1st floating gate, 15 ... 1st element isolation insulating layer, 16 ... 1st selection Gate, 17 ... first selection gate line, 20 ... second memory cell array layer, 21 ... second semiconductor layer, 22 ... second gate insulating layer, 23 ... second floating gate, 25 ... second Element isolation insulating layer, 26 ... second selection gate, 27 ... second selection gate line, 31 ... first insulating layer, 32 ... inter-gate insulating layer, 33 ... control gate, 34 ... second insulating layer, 35 ... bit line contact, 36 ... source line contact, 37 ... word line contact, 38 ... selection gate line contact, 91e ... first auxiliary gate, 92e ... second auxiliary gate, 93e ... third auxiliary gate, 94e ... the fourth auxiliary gate, 91a ... Lower auxiliary transistor, 92a, second lower auxiliary transistor, 93a, third lower auxiliary transistor, 94a, fourth lower auxiliary transistor, 91b, first upper auxiliary transistor, 92b, second upper auxiliary transistor, 93b: third upper auxiliary transistor, 94b: fourth upper auxiliary transistor.

Claims (6)

A plurality of first memory cells connected in series in a first direction, a first source line side select gate transistor connected between the plurality of first memory cells and a source line, and the plurality of first A first NAND cell unit comprising a first bit line side select gate transistor connected between the memory cell and the bit line, the first memory cell comprising: a first semiconductor layer; A first gate insulating layer formed on the first semiconductor layer; and a first floating gate formed on the first gate insulating layer, the first source line side A selection gate transistor and a first bit line side selection gate transistor are formed on the first semiconductor layer, the first gate insulating layer, and the first gate insulating layer. First memory cell array having And,
A first insulating layer formed on the first memory cell array layer;
A plurality of second memory cells formed on the first insulating layer and connected in series in the first direction; a second memory cell connected between the plurality of second memory cells and a source line; A second NAND cell unit comprising a source line side select gate transistor and a second bit line side select gate transistor connected between the plurality of second memory cells and a bit line, Two memory cells, a second floating gate, a second gate insulating layer formed on the second floating gate, and a second semiconductor formed on the second gate insulating layer And the second source line side select gate transistor and the second bit line side select gate transistor include a second select gate, the second gate insulating layer, and the second gate. The second layer formed on the insulating layer; A second memory cell array layer having a semiconductor layer,
The first and second floating gates positioned above and below the first insulating layer are formed on both side surfaces in the first direction via an inter-gate insulating layer and orthogonal to the first direction. A control gate extending in a second direction to
The first and second select gates positioned above and below the first insulating layer are formed on both side surfaces in the first direction via the inter-gate insulating layer and extend in the second direction. And an auxiliary gate that forms an auxiliary transistor together with the first and second semiconductor layers and the first and second gate insulating layers,
The auxiliary gate is
An inter-gate insulating layer is formed between the source line and the first and second selection gates on the source line side, extends in the second direction, and serves as a gate of the first auxiliary transistor. 1 auxiliary gate,
An inter-gate insulating layer is formed between the first and second selection gates on the source line side and the plurality of first and second memory cells, and extends in the second direction. A second auxiliary gate serving as the gate of the auxiliary transistor;
An inter-gate insulating layer is formed between the plurality of first and second memory cells and the first and second select gates on the bit line side, and extends in the second direction. A third auxiliary gate serving as the gate of the auxiliary transistor;
A first gate is formed between the first and second selection gates on the bit line side and the bit line through an inter-gate insulating layer, extends in the second direction, and serves as the gate of the fourth auxiliary transistor. With 4 auxiliary gates,
During a write operation, a first voltage for turning off the first auxiliary transistor is applied to the first auxiliary gate, and the third and fourth auxiliary transistors are turned on to the third and fourth auxiliary gates. Applying a second voltage, applying an intermediate voltage between the first voltage and the second voltage to the second auxiliary gate;
In a read operation or a write operation, the first auxiliary transistor of the NAND cell unit adjacent to the NAND cell unit that is the target of the read operation or the write operation is turned off through the source line. Nonvolatile semiconductor memory device. A plurality of first memory cells connected in series in a first direction, a first source line side select gate transistor connected between the plurality of first memory cells and a source line, and the plurality of first A first NAND cell unit comprising a first bit line side select gate transistor connected between the memory cell and the bit line, the first memory cell comprising: a first semiconductor layer; A first gate insulating layer formed on the first semiconductor layer; and a first floating gate formed on the first gate insulating layer, the first source line side A selection gate transistor and a first bit line side selection gate transistor are formed on the first semiconductor layer, the first gate insulating layer, and the first gate insulating layer. First memory cell array having And,
A first insulating layer formed on the first memory cell array layer;
A plurality of second memory cells formed on the first insulating layer and connected in series in the first direction; a second memory cell connected between the plurality of second memory cells and a source line; A second NAND cell unit comprising a source line side select gate transistor and a second bit line side select gate transistor connected between the plurality of second memory cells and a bit line, Two memory cells, a second floating gate, a second gate insulating layer formed on the second floating gate, and a second semiconductor formed on the second gate insulating layer And the second source line side select gate transistor and the second bit line side select gate transistor include a second select gate, the second gate insulating layer, and the second gate. The second layer formed on the insulating layer; A second memory cell array layer having a semiconductor layer,
The first and second floating gates positioned above and below the first insulating layer are formed on both side surfaces in the first direction via an inter-gate insulating layer and orthogonal to the first direction. A control gate extending in a second direction to
The first and second select gates positioned above and below the first insulating layer are formed on both side surfaces in the first direction via the inter-gate insulating layer and extend in the second direction. A nonvolatile semiconductor memory device comprising: an auxiliary gate that forms an auxiliary transistor together with the first and second semiconductor layers and the first and second gate insulating layers. The auxiliary gate is
An inter-gate insulating layer is formed between the source line and the first and second selection gates on the source line side, extends in the second direction, and serves as a gate of the first auxiliary transistor. 1 auxiliary gate,
An inter-gate insulating layer is formed between the first and second selection gates on the source line side and the plurality of first and second memory cells, and extends in the second direction. A second auxiliary gate serving as the gate of the auxiliary transistor;
An inter-gate insulating layer is formed between the plurality of first and second memory cells and the first and second select gates on the bit line side, and extends in the second direction. A third auxiliary gate serving as the gate of the auxiliary transistor;
A first gate is formed between the first and second selection gates on the bit line side and the bit line through an inter-gate insulating layer, extends in the second direction, and serves as the gate of the fourth auxiliary transistor. The nonvolatile semiconductor memory device according to claim 2, further comprising: 4 auxiliary gates. During a write operation, a first voltage for turning off the first auxiliary transistor is applied to the first auxiliary gate, and the third and fourth auxiliary transistors are turned on to the third and fourth auxiliary gates. 4. The nonvolatile semiconductor memory device according to claim 2, wherein a second voltage is applied, and a voltage intermediate between the first voltage and the second voltage is applied to the second auxiliary gate. 5. . In a read operation or a write operation, the first auxiliary transistor of the NAND cell unit adjacent to the NAND cell unit that is the target of the read operation or the write operation is turned off through the source line. The nonvolatile semiconductor memory device according to claim 3. Forming a first gate insulating layer and a floating gate formation layer on the first semiconductor layer;
Grooves extending in the first direction at predetermined intervals in the second direction perpendicular to the first direction are formed in the floating gate formation layer, the first gate insulating layer, and the first semiconductor layer. 1 element isolation insulating layer is embedded,
Forming a first insulating layer on the floating gate forming layer and the first element isolation insulating layer;
Forming a floating gate forming layer on the first insulating layer;
Forming a plurality of grooves extending in the second direction in the floating gate forming layer formed via the first insulating layer and the first insulating layer, and covering with a gate insulating layer;
A method for manufacturing a nonvolatile semiconductor device, comprising embedding a control gate and an auxiliary gate in the intergate insulating layer.

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