US20150325647A1 - INTEGRATED CIRCUIT (IC) CHIP HAVING BOTH METAL AND SILICON GATE FIELD EFFECT TRANSISTORs (FETs) AND METHOD OF MANUFACTURE - Google Patents
INTEGRATED CIRCUIT (IC) CHIP HAVING BOTH METAL AND SILICON GATE FIELD EFFECT TRANSISTORs (FETs) AND METHOD OF MANUFACTURE Download PDFInfo
- Publication number
- US20150325647A1 US20150325647A1 US14/663,256 US201514663256A US2015325647A1 US 20150325647 A1 US20150325647 A1 US 20150325647A1 US 201514663256 A US201514663256 A US 201514663256A US 2015325647 A1 US2015325647 A1 US 2015325647A1
- Authority
- US
- United States
- Prior art keywords
- gate
- silicon
- layer
- fet
- fets
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 87
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 87
- 239000010703 silicon Substances 0.000 title claims abstract description 87
- 230000005669 field effect Effects 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 title abstract description 15
- 238000004519 manufacturing process Methods 0.000 title description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 88
- 229920005591 polysilicon Polymers 0.000 claims abstract description 88
- 229910052751 metal Inorganic materials 0.000 claims abstract description 54
- 239000002184 metal Substances 0.000 claims abstract description 54
- 239000012212 insulator Substances 0.000 claims abstract description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 42
- 229910021332 silicide Inorganic materials 0.000 claims description 33
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 18
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 10
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 10
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 10
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 5
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 claims description 5
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 5
- 239000010941 cobalt Substances 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical group [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims 8
- 229910052721 tungsten Inorganic materials 0.000 claims 8
- 239000010937 tungsten Substances 0.000 claims 8
- 229910021334 nickel silicide Inorganic materials 0.000 claims 4
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 claims 4
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 claims 4
- 239000004065 semiconductor Substances 0.000 abstract description 10
- 239000010410 layer Substances 0.000 description 43
- 150000004767 nitrides Chemical class 0.000 description 26
- 230000015572 biosynthetic process Effects 0.000 description 10
- 230000000694 effects Effects 0.000 description 10
- 239000007943 implant Substances 0.000 description 10
- 230000009969 flowable effect Effects 0.000 description 9
- 239000002344 surface layer Substances 0.000 description 9
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 8
- 239000003989 dielectric material Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- -1 Aluminum (Al) Chemical class 0.000 description 3
- 230000001419 dependent effect Effects 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 2
- 230000000593 degrading effect Effects 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 125000001475 halogen functional group Chemical group 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention generally relates to Integrated Circuit (IC) manufacture and more particularly to reducing costs in semiconductor chip manufacture of integrated circuits with short channel Field Effect Transistors (FETs).
- IC Integrated Circuit
- FETs Field Effect Transistors
- CMOS complementary insulated gate FET
- SOI silicon on insulator
- CMOS devices are formed in a thin uniform silicon surface layer.
- typical CMOS circuit includes paired complementary devices, i.e., an n-type FET (NFET) paired with a corresponding p-type FET (PFET), usually gated by the same signal.
- NFET n-type FET
- PFET p-type FET
- the pair of devices in an ideal inverter have operating characteristics that are, essentially, opposite each other, when one device (e.g., the NFET) is on and conducting (modeled simply as a closed switch), the other device (the PFET) is off, not conducting (ideally modeled as an open switch) and, vice versa.
- one device e.g., the NFET
- the PFET the PFET
- reducing RMGFET lengths has degraded device transconductances (Gm/Gds) in addition to increasing subthreshold current.
- subthreshold current increases exponentially with the magnitude of the device's drain to source voltage (V ds ) and reduces exponentially with the magnitude of the device's V T .
- Subthreshold current is especially troublesome in achieving what is known as low V T devices, where the V T may be less than 100 millivolts (100 mV). Since these and other effects become more pronounced as the devices become shorter, they are commonly known collectively as short channel effects (SCEs).
- SCEs short channel effects
- FETs Field Effect Transistors
- IC Integrated Circuit
- FET locations are defined on a layered semiconductor wafer, preferably a Silicon On Insulator (SOI) wafer.
- SOI Silicon On Insulator
- One or more FET locations are defined as silicon gate locations and remaining as Replacement Metal Gate (RMG) FET locations with at least one of each on the IC.
- RMG Replacement Metal Gate
- Polysilicon gates are formed in all FET locations. Gates in silicon gate locations are tailored, e.g., doped and silicided. Remaining polysilicon gates are replaced with metal in RMG FET locations. FETs are connected together into circuits with RMG FETs being connected to silicon gate FETs.
- FIGS. 1A-B show examples of steps forming semiconductor devices, polysilicon gate Field Effect Transistors (FETs), especially P-type devices, in a Replacement Metal Gate (RMG) FET manufacturing process according to a preferred embodiment of the present invention
- FIGS. 2A-B show a cross sectional example of a layered wafer, e.g., a Silicon On Insulator (SOI) wafer and device locations defined thereon according to a preferred embodiment of the present invention
- SOI Silicon On Insulator
- FIGS. 3A-D show an example of device formation through polysilicon device gate completion for preferred devices
- FIGS. 4A-D show a variation, wherein chip NFETs and PFETs both include RMG and polysilicon gate devices;
- FIGS. 5A-D show an example of RMG device formation after polysilicon device gate formation
- FIG. 6 shows an example of normal chip wiring in preferred chips
- FIG. 7 shows an optional fabrication variation suitable for analog applications
- FIGS. 8A-8C show forming fuses or resistors with the polysilicon gate and RMG devices
- FIG. 9 shows an example of normal chip wiring to fuses and devices in preferred chips
- FIG. 10 shows an example of a wafer with chips manufactured according to a preferred embodiment of the present invention.
- FIG. 1A shows a first example of steps in a method 100 for forming semiconductor devices, polysilicon gate Field Effect Transistors (FETs), especially P-type devices, in a Replacement Metal Gate (RMG) FET manufacturing process according to a preferred embodiment of the present invention.
- FETs polysilicon gate Field Effect Transistors
- RMG Replacement Metal Gate
- the PFET metal work function is targeted, best case, at about 100 millivolt (100 mV) from the band edge.
- the same preferred polysilicon gate PFET may be a Super Low V T (SLVT).
- SLVT Super Low V T
- These preferred SLVT devices have threshold voltage that may on the order of 100 mv lower than the V T of RMGPFETs on the same chip and/or in the same circuit. While normally gate leakage is not a major concern for these preferred SLVT devices, gate oxide thickness may be tailored to trade gate leakage against V T and to offer devices suitable for analog applications.
- IC fabrication begins 102 with a layered wafer and defining 104 device locations on the wafer. Locations may be defined by forming islands in the surface layer of the wafer. Some of the device locations are identified 106 for silicon gate devices. Silicon gates are formed with gate dielectric 108 , wherein the silicon gates are the gates of the silicon gate devices and dummy gates for RMG devices. Silicon gate are tailored 110 electrically, e.g., doped and silicided. Dummy gates are replaced 112 with metal. Wiring is formed 114 connecting devices together into circuits and circuits together on chips. Finally, BEOL fabrication continues 116 , completing chips.
- FIG. 1B shows another example of forming polysilicon gate FETs and RMGFETs as in FIG. 1A in more detail.
- the surface layer of the layered wafer is segmented into islands, e.g., using shallow trench isolation (STI), each island identifying a location of one or more devices.
- STI shallow trench isolation
- an Extra gate Dielectric (ED oxide) layer is formed 1062 normally.
- the ED oxide is removed 1064 from the SLVT poly gate locations, e.g., using a suitable mask and etch.
- a gate oxide layer is formed 1080 on the wafer and a polysilicon layer is formed on the gate oxide layer.
- the polysilicon is patterned normally 1082 , the wafer is implanted with a halo and extension implant and annealed, e.g., using a rapid thermal anneal (RTA). Spacers are formed along the patterned polysilicon sidewalls and source/drain regions are formed 1084 .
- the polysilicon is exposed and implanted 1100 in silicon gate device locations.
- the polysilicon gates are silicided.
- the exposed silicided gates are covered 1102 with a dielectric, e.g., a flowable oxide. Remaining undoped poly is removed and replaced with metal 112 ′.
- FIG. 2A-B shows a cross sectional example of a layered wafer 120 , e.g., a SOI wafer (provided in 102 of FIG. 1A ) and device locations defined 104 according to a preferred embodiment of the present invention.
- the layered wafer 120 includes a Silicon (Si) substrate 122 , an insulator layer 124 , e.g., Buried OXide (BOX), on the Si substrate 122 , and a Si surface layer 126 on the BOX layer 124 .
- the thicknesses of these layers 122 , 124 , 126 is process dependent and may be any thickness necessary for the selected SOI process.
- Device formation begins (and 104 ′ in FIG. 1B ) by segmenting the surface layer 126 , to define islands 128 , 130 in FIG. 2B .
- the islands 128 , 130 are defined using a well-known STI technique, e.g., patterning and etching the layer 124 and filling between the islands with STI oxide 132 .
- STI oxide 132 is shown in the Figures as being distinct from BOX layer 124 , this is for example only.
- the STI oxide merges with and is indistinguishable from the BOX layer 124 .
- the segmented surface layer 126 which may have been previously body doped, is channel doped normally N or P-type, depending on the type of devices being formed, 106 , 1060 . Alternately body doping may be done prior to STI formation. In this example, both Islands are doped N-type for PFETs.
- an optional ED oxide layer (not shown) may be formed 1062 on the wafer 120 .
- the ED oxide if formed, is masked 1064 and removed from islands 128 , 130 in exposed areas where thick oxide devices are not being formed.
- the mask is removed with the exposed oxide in an integrated oxide and resist removal.
- a thin gate dielectric layer is formed 108 , 1080 on the surface, e.g., a thermal oxide followed by nitridation. This gate dielectric acts as a dummy interfacial layer for RMG devices, e.g., formed on islands 128 , and gate dielectric for preferred polysilicon gate devices on islands 130 .
- the gate dielectric is less than 1.5 nanometers (1.5 nm) thick, preferably 1.0 nm thick, and chosen such that Tiny for the polysilicon devices, 1.3-1.5 nm, is matched to the RMG devices.
- FIGS. 3A-D show an example of device formation through polysilicon device gate completion for P-type devices.
- the polysilicon layer and gate dielectric layer are patterned 1082 , e.g., using a typical state of the art mask and etch technique, which defines polysilicon gates 134 , 136 on dielectric 138 , 140 in RMG device locations 142 and in preferred polysilicon gate device locations 144 .
- the polysilicon gates 134 are, essentially sacrificial polysilicon gates and polysilicon gates 136 are gates of the preferred poly gate devices.
- the islands 128 , 130 are implanted with a suitable halo and extension implant for the particular selected device type, P-type or N-type.
- a spacer dielectric (e.g., nitride) layer is conformally formed and patterned, e.g., using a suitable mask an etch techniques, leaving dielectric segments 146 , 148 as gate sidewalls and covering the polysilicon gates 134 , 136 to surface layer islands 128 , 130 .
- the exposed portions of the surface layer islands 128 , 130 are recessed 1084 and filled with a doped semiconductor, e.g., Silicon Germanium (SiGe), to form source/drain regions 150 .
- a conformable stress layer 152 is formed on the wafer, e.g., a conformable nitride layer is deposited.
- the wafer 120 is covered with a flowable dielectric layer 154 , e.g., flowable oxide.
- the wafer is masked 156 to protect areas where silicon gate devices are not being tailored, e.g., RMG FET islands 128 .
- the exposed silicon gate areas are etched 110 , 1100 with a timed etch, e.g., using an anisotropic Reactive Ion Etch (RIE).
- RIE anisotropic Reactive Ion Etch
- the RIE removes the flowable oxide 154 to expose the nitride segment 148 on the polysilicon gate 136 .
- a nitride RIE removes exposed horizontal portions of nitride segment 148 and exposes the gate 136 with only gate sidewalls 148 ′ remaining along the polysilicon gates 136 .
- the exposed polysilicon gates 136 are implanted, e.g., for a P-type FET with a P + implant.
- the mask is removed in FIG. 3D and the wafer 120 is annealed in a doping anneal.
- the wafer 120 is cleaned with a typical silicide pre-clean.
- silicide 158 is formed on the polysilicon gate 136 .
- the silicide 158 is preferably, Cobalt Silicide (CoSi), selected to withstand thermal requirements of subsequent RMG formation.
- FIGS. 4A-D show a variation on the current example of FIGS. 3B and C, wherein chip NFETs and PFETs both include RMG and polysilicon gate devices with like features labeled identically, except P-type structure features are differentiated further by -p and N-type structure features are differentiated by -n. Further, while these figures show PFETs being treated first, followed by NFETs, this is for example only and not intended as a limitation. Devices may be treated together or NFETs may be treated first, as desired at the time of manufacture.
- FIG. 4A as in FIG. 3B , the wafer is masked and only the polysilicon PFET gates 136 - p are uncovered.
- a RIE removes the flowable oxide over the exposed flowable nitride layer 152 and exposes upper portions of segment 148 on the polysilicon gate 136 - p .
- a nitride RIE removes exposed portions of segment 148 to expose the gate 136 - p , which is implanted with a P + implant.
- FIG. 4C as in FIGS. 4A and 3B , the wafer is masked and only the oxide above polysilicon NFET gates 136 - n is uncovered.
- FIG. 4C as in FIGS. 4A and 3B
- a RIE removes the flowable oxide 154 to expose the flowable nitride layer 152 above segment 148 ′′ on the polysilicon gate 136 - n .
- a nitride RIE removes the upper portion of the flowable nitride layer 152 and horizontal portions of segment 148 ′′ to expose the gate 136 - n between sidewalls 148 ′′′, for implant with a N + implant.
- FIGS. 5A-D show an example of RMG device formation after polysilicon device gate 136 (or 136 - n and - p ) formation.
- the wafer 120 is re-covered 1102 with a flowable dielectric layer 154 ′, e.g., flowable oxide.
- a flowable dielectric layer 154 ′ e.g., flowable oxide.
- FIG. 5B the upper portions of the flowable dielectric layer, the flowable nitride layer 152 ′ and the nitride segments 146 are removed 112 , 112 ′, preferably using a typical chemical-mechanical (chem-mech) polishing (CMP) technique to expose the sacrificial polysilicon gates 134 .
- CMP chemical-mechanical
- the CMP is highly selective to dielectric materials and stops on the silicide 158 . Since CMP is only used to expose the sacrificial gates 134 , the silicon gate devices 144 are relatively immune to CMP induced variations. Thus, longer channel silicon gate devices, e.g., lengths several times longer than the typical device design length, are available for analog applications.
- a partial void 160 forms in FIG. 5C .
- the dielectric 138 is removed to complete the void 160 .
- a high-k dielectric layer preferably, 2 nm thick, is formed in the RMG gate location and lining the void 160 .
- the high-k dielectric is removed from the surface, e.g. using CMP, to leave the voids lined with high-k dielectric layer 162 .
- the high-k dielectric may be any suitable high-k dielectric material, conformally deposited, and removed using CMP.
- the high-k dielectric material is Zirconium Oxide (ZrO 5 ) or hafnium dioxide (HfO 2 ).
- RMG gate formation is completed in FIG. 5D by filling the lined 162 RMG gate location with metal 164 .
- the lined RMG gate location may be filled, for example, by forming a layer of work function metals, and preferably, a combination of metals such as Aluminum (Al), Titanium Nitride (TiNi), and/or Titanium Aluminum (TiAl).
- the work function metal layer is formed on the wafer surface using any suitable technique, followed by CMP. Alternately, the metal may be formed on the high-k dielectric layer 162 and a single CMP may be used to remove excess metal and high-k dielectric.
- silicide 166 is formed on device semiconductor surfaces, e.g., on SiGe source/drain regions 150 .
- Contact pads 168 are formed through the remnant of dielectric 154 ′ to the silicide 166 .
- dielectric layer 154 ′′ is re-formed on the wafer over the contact pads 168 .
- Contacts 170 are formed through the dielectric layer 154 ′′ to underlying metal, e.g., metal gates 164 , polysilicon gates 136 and contact pads 168 .
- a metal wiring 172 layer is formed on the wafer.
- the metal wires 172 and contacts 170 may be formed in a single step, e.g., using a typical dual damascene step.
- Wafer/chip fabrication continues 116 normally though typical BEOL steps.
- the resulting ICs have both RMG and polysilicon gate devices on the same chip and even in the same circuits or functional logic blocks (e.g., Inverters. NAND gates and NOR gates).
- the polysilicon gate PFETs may have lower V TS than, and T inv matched to, any corresponding RMG PFETs.
- FIG. 7 shows an optional fabrication variation corresponding to FIG. 3B with identical features labeled identically, that may be suitable for analog applications or where low V T devices with thicker oxide are needed.
- thicker gate dielectric devices 180 may be formed on the same chips with relatively minor fabrication adjustments, depositing ED oxide 182 and selectively removing it.
- the polysilicon 184 in the thicker gate dielectric (ED) devices, or EDPFETs 180 is processed substantially identically to the polysilicon gates 136 , as shown in FIGS. 3C and D, 5 A-D and 6 . This allows for longer channel polysilicon devices, that could not otherwise be included in RMGFET circuits. Moreover, these EDPFETs are relatively more immune to CMP variations.
- fuses 190 also may be formed on STI 192 with the polysilicon gates 136 , beginning as shown in FIGS. 8A-8C , which correspond to FIGS. 3B and 3 C with identical features labeled identically.
- the wafer is masked 194 and the polysilicon segment(s) 190 is(are) uncovered with polysilicon PFET gates 136 .
- a RIE removes the flowable oxide 154 and flowable nitride 146 over, and exposes the horizontal surfaces of, nitride segments 148 and 196 .
- a nitride RIE removes the exposed horizontal surfaces of nitride segments 148 and 196 in FIG. 8B . Removing horizontal surfaces of nitride segments 148 and 196 exposes the gates 136 and polysilicon segment(s) 190 .
- the mask 194 e.g., a photoresist, is removed normally.
- the polysilicon PFET gates 136 are implanted in FIG. 8C , substantially as in FIG. 3B . So prior to implant, the wafer is masked 198 again and only the polysilicon PFET gates 136 are left unmasked. A RIE removes the flowable oxide 152 over the polysilicon gate 136 to expose flowable nitride layer 150 above nitride segment 146 . A nitride RIE removes horizontal portions of nitride layers 150 , 146 and exposes the gate 136 , which is implanted with a P + implant.
- the mask 198 is removed in FIG. 8C and the wafer 120 is annealed in a doping anneal.
- the wafer 120 is cleaned with a typical silicide pre-clean.
- silicide 158 , 200 is formed on the polysilicon gates 136 and fuse segments 190 .
- the silicide 158 , 200 is CoSi.
- silicide 158 is formed on device semiconductor surfaces, e.g., on SiGe source/drain regions 150 .
- Contact pads 168 are formed through the remnant of dielectric 154 ′ to the silicide 166 .
- dielectric layer 154 ′′ is re-formed on the wafer over the contact pads 168 .
- Contacts 170 , 202 are formed through the dielectric layer 154 ′′ to underlying metal, e.g., metal gates 164 , polysilicon gates 136 and contact pads 168 and fuses 190 .
- Metal wiring 172 layer is formed on the wafer.
- the metal wires 172 and contacts 170 , 202 again may be formed in a single, e.g., a dual damascene step. Wafer/chip fabrication continues normally though typical back end of the line (BEOL) steps.
- BEOL back end of the line
- FIG. 10 shows an example of a wafer 210 with chips 212 manufactured according to a preferred embodiment of the present invention.
- the chips include connected circuits 214 , one or more of which includes preferred FETs.
- silicon gate PFETs may be mixed selectively with metal gate devices on RMGFET ICs to provide low V T PFETs without compromising short channel effects and without adding significant manufacturing costs.
- Manufacturing costs increase only slightly because the present invention uses what was previously disposable, sacrificial polysilicon shapes in a process that adds only low critical manufacturing steps, i.e., mask and etch steps to remove dielectric layers and an implant and silicide to tailor the polysilicon gates.
- this may be extended to form thicker gate dielectric PFETs by selectively forming thick oxide, and to NFETs as well with the addition of a single implant mask.
- These thicker dielectric, low V T devices have analog applications and are very useful for achieving high dynamic ranges for analog/radio frequency (RF) circuits.
- RF radio frequency
- preferred low V T devices are produced without degrading device transconductances (Gm/Gds), otherwise apparent in a low V T devices realized using lower channel doping or compensation doping. Neither do preferred low V T devices suffer from body resistance (R body ) penalties which is also advantageous for high frequency analog devices.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
- The present invention is a continuation of U.S. patent application Ser. No. 13/108,213 (Attorney Docket No. FIS920110047US1), “INTEGRATED CIRCUIT (IC) CHIP HAVING BOTH METAL AND SILICON GATE FIELD EFFECT TRANSISTORs (FETs) AND METHOD OF MANUFACTURE” to Narasimhulu Kanike, filed May 16, 2011, assigned to the assignee of the present invention and incorporated herein by reference.
- 1. Field of the Invention
- The present invention generally relates to Integrated Circuit (IC) manufacture and more particularly to reducing costs in semiconductor chip manufacture of integrated circuits with short channel Field Effect Transistors (FETs).
- 2. Background Description
- Semiconductor technology and chip manufacturing advances have resulted in a steady decrease of chip feature size to increase on-chip circuit switching frequency (circuit performance) and the number of transistors (circuit density). Shrinking/reducing device or field effect transistor (FET) feature sizes and, correspondingly, device minimum dimensions including horizontal dimensions (e.g., minimum channel length) and vertical dimensions (e.g., channel layer depth, gate dielectric thickness, junction depths and etc.) shrinks device size for increased device density and device performance, as well as reduces device operating conditions, i.e., chip and correspondingly, device supply voltages and voltage swings.
- Generally, all other factors being constant, the active power consumed by a given unit increases linearly with switching frequency, i.e., performance. Thus, notwithstanding the decrease of chip supply voltage, chip power consumption has increased as well. Both at the chip and system levels, cooling and packaging costs have escalated as a natural result of this increase in chip power. Especially for low end systems (e.g., handhelds, portable and mobile systems), where battery life is crucial, reducing net power consumption is important. However, such a power reduction must come without degrading chip/circuit performance below acceptable levels.
- To minimize semiconductor circuit power consumption, most Integrated Circuits (ICs) are made in the well-known complementary insulated gate FET technology known as CMOS. Moreover, state of the art CMOS chips are frequently made in a silicon on insulator (SOI) technology, where CMOS devices are formed in a thin uniform silicon surface layer. Whether on a bulk wafer or in SOI, typical CMOS circuit includes paired complementary devices, i.e., an n-type FET (NFET) paired with a corresponding p-type FET (PFET), usually gated by the same signal.
- In an ideal NFET, for example, current only flows when the gate to source voltage (Vgs) exceeds the device threshold voltage (VT) and is determined in part by the amount which it exceeds VT, i.e., by Vgs−VT. PFETs operate analogously. FET drain to source current (Ids, which is considered DC current and so, DC power (IdsVsupply) consumed) is dependent upon circuit conditions, device characteristics (e.g., width, length, channel mobility and threshold voltage) and device voltages.
- Since the pair of devices in an ideal inverter have operating characteristics that are, essentially, opposite each other, when one device (e.g., the NFET) is on and conducting (modeled simply as a closed switch), the other device (the PFET) is off, not conducting (ideally modeled as an open switch) and, vice versa. Thus, ideally, there is no static or DC current path in a typical CMOS circuit and ideal CMOS circuits use no static or DC power and only consume transient power from charging and discharging capacitive loads.
- In practice, however, typical FETs are much more complex than switches. So, transient power for circuit loads (from switching currents) accounts for only a portion of CMOS chip power. Especially since device VT is directly proportional to gate dielectric thickness and also dependent on channel length, as FET features (including gate dielectric and channel length and thickness) shrink, current may continue to flow through off FETs causing what is known as subthreshold current. Subthreshold current is current conduction at gate biases below FET threshold and is directly proportional to gate width. Also, gate oxide leakage also became a major source static power loss. By replacing gate oxide with high-k dielectrics most of this gate oxide leakage has been eliminated.
- However, polysilicon cannot be used with high-k dielectrics. Also, parasitic circuit resistances reduce performance and complicate design. A source of parasitic circuit resistances has been in the polysilicon used to form FET gates. Consequently, polysilicon is being replaced with wok function metal and aluminum in what is known as Replacement Metal Gate (RMG) FET technologies.
- Further, reducing RMGFET lengths has degraded device transconductances (Gm/Gds) in addition to increasing subthreshold current. For a particular device, subthreshold current increases exponentially with the magnitude of the device's drain to source voltage (Vds) and reduces exponentially with the magnitude of the device's VT.
- Subthreshold current is especially troublesome in achieving what is known as low VT devices, where the VT may be less than 100 millivolts (100 mV). Since these and other effects become more pronounced as the devices become shorter, they are commonly known collectively as short channel effects (SCEs). Metal gates in RMGFETS, even with high work function metals, have a lower work function than polysilicon. RMGFETs require lower channel doping levels or counter doping for low VT devices than equivalent polysilicon gate devices. So, low VT RMGFETs are much more susceptible to short channel effects than equivalent polysilicon gate devices and RMGPFETs are worse than RMGNFETs.
- Consequently, especially for complex chips and arrays with a large number of devices, short channel effects can be overwhelming. When multiplied by the millions and even billions of devices on a state of the art IC, even 100 picoAmps (100 pA) of leakage in each of a million circuits, for example, results in chip leakage on the order of 100 milliAmps (100 mA).
- Further, these short channel effects are much worse at operating conditions beyond nominal, e.g., higher supply voltages. However, frequently ICs require some devices to operate at higher voltages, e.g., in analog applications and in Input/Output (I/O) building blocks. For these applications devices with process normal (low VT) but thicker than nominal gate dielectric are essential. Typically, to achieve low VTS channel doping is selectively reduced or channels are selectively counter doped, either of which degrades device performance.
- Thus, there exists a need in Integrated Circuits (ICs) for higher performance PFETs with reduced short channel effects; and more particularly, to reduce PFET VTS and channel lengths in ICs without reduced/counter doping channels even while minimizing PFET short channel effects.
- It is an aspect of the invention to reduce short channel effects in Integrated Circuits (ICs) without impairing performance;
- It is another aspect of the invention to reduce PFET VTS and channel lengths with minimal increase in PFET short channel effects;
- It is yet another aspect of the invention to reduce short channel effects in low VT, short channel IC PFETs while improving IC performance.
- The present invention relates to Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs on ICs. FET locations are defined on a layered semiconductor wafer, preferably a Silicon On Insulator (SOI) wafer. One or more FET locations are defined as silicon gate locations and remaining as Replacement Metal Gate (RMG) FET locations with at least one of each on the IC. Polysilicon gates are formed in all FET locations. Gates in silicon gate locations are tailored, e.g., doped and silicided. Remaining polysilicon gates are replaced with metal in RMG FET locations. FETs are connected together into circuits with RMG FETs being connected to silicon gate FETs.
- The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:
-
FIGS. 1A-B show examples of steps forming semiconductor devices, polysilicon gate Field Effect Transistors (FETs), especially P-type devices, in a Replacement Metal Gate (RMG) FET manufacturing process according to a preferred embodiment of the present invention; -
FIGS. 2A-B show a cross sectional example of a layered wafer, e.g., a Silicon On Insulator (SOI) wafer and device locations defined thereon according to a preferred embodiment of the present invention; -
FIGS. 3A-D show an example of device formation through polysilicon device gate completion for preferred devices; -
FIGS. 4A-D show a variation, wherein chip NFETs and PFETs both include RMG and polysilicon gate devices; -
FIGS. 5A-D show an example of RMG device formation after polysilicon device gate formation; -
FIG. 6 shows an example of normal chip wiring in preferred chips; -
FIG. 7 shows an optional fabrication variation suitable for analog applications; -
FIGS. 8A-8C show forming fuses or resistors with the polysilicon gate and RMG devices; -
FIG. 9 shows an example of normal chip wiring to fuses and devices in preferred chips; -
FIG. 10 shows an example of a wafer with chips manufactured according to a preferred embodiment of the present invention. - Turning now to the drawings and, more particularly,
FIG. 1A shows a first example of steps in amethod 100 for forming semiconductor devices, polysilicon gate Field Effect Transistors (FETs), especially P-type devices, in a Replacement Metal Gate (RMG) FET manufacturing process according to a preferred embodiment of the present invention. Since in RMG nominal PFET devices are not band edged for the gate work function, for certain doping levels, RMGPFETs typically have higher threshold voltages (i.e., the magnitude of the VTS) compared to corresponding polysilicon gate devices with the same doping profile and with the inversion layer thickness (Tinv) matched. - For a typical state of the art Silicon On Insulator (SOI) process, the PFET metal work function is targeted, best case, at about 100 millivolt (100 mV) from the band edge. Thus, by selectively using a polysilicon gate instead of metal, the same preferred polysilicon gate PFET may be a Super Low VT (SLVT). These preferred SLVT devices have threshold voltage that may on the order of 100 mv lower than the VT of RMGPFETs on the same chip and/or in the same circuit. While normally gate leakage is not a major concern for these preferred SLVT devices, gate oxide thickness may be tailored to trade gate leakage against VT and to offer devices suitable for analog applications.
- IC fabrication begins 102 with a layered wafer and defining 104 device locations on the wafer. Locations may be defined by forming islands in the surface layer of the wafer. Some of the device locations are identified 106 for silicon gate devices. Silicon gates are formed with
gate dielectric 108, wherein the silicon gates are the gates of the silicon gate devices and dummy gates for RMG devices. Silicon gate are tailored 110 electrically, e.g., doped and silicided. Dummy gates are replaced 112 with metal. Wiring is formed 114 connecting devices together into circuits and circuits together on chips. Finally, BEOL fabrication continues 116, completing chips. -
FIG. 1B shows another example of forming polysilicon gate FETs and RMGFETs as inFIG. 1A in more detail. First in 104′, the surface layer of the layered wafer is segmented into islands, e.g., using shallow trench isolation (STI), each island identifying a location of one or more devices. If the IC is to include RMGPFETs or thicker oxide polysilicon gate FETs, an Extra gate Dielectric (ED oxide) layer is formed 1062 normally. The ED oxide is removed 1064 from the SLVT poly gate locations, e.g., using a suitable mask and etch. A gate oxide layer is formed 1080 on the wafer and a polysilicon layer is formed on the gate oxide layer. The polysilicon is patterned normally 1082, the wafer is implanted with a halo and extension implant and annealed, e.g., using a rapid thermal anneal (RTA). Spacers are formed along the patterned polysilicon sidewalls and source/drain regions are formed 1084. The polysilicon is exposed and implanted 1100 in silicon gate device locations. The polysilicon gates are silicided. The exposed silicided gates are covered 1102 with a dielectric, e.g., a flowable oxide. Remaining undoped poly is removed and replaced withmetal 112′. -
FIG. 2A-B shows a cross sectional example of alayered wafer 120, e.g., a SOI wafer (provided in 102 ofFIG. 1A ) and device locations defined 104 according to a preferred embodiment of the present invention. In this example, thelayered wafer 120 includes a Silicon (Si)substrate 122, aninsulator layer 124, e.g., Buried OXide (BOX), on theSi substrate 122, and aSi surface layer 126 on theBOX layer 124. The thicknesses of theselayers - Device formation begins (and 104′ in
FIG. 1B ) by segmenting thesurface layer 126, to defineislands FIG. 2B . Preferably, theislands layer 124 and filling between the islands withSTI oxide 132. AlthoughSTI oxide 132 is shown in the Figures as being distinct fromBOX layer 124, this is for example only. Typically, below thesurface layer 126, the STI oxide merges with and is indistinguishable from theBOX layer 124. Thesegmented surface layer 126, which may have been previously body doped, is channel doped normally N or P-type, depending on the type of devices being formed, 106, 1060. Alternately body doping may be done prior to STI formation. In this example, both Islands are doped N-type for PFETs. - Next, an optional ED oxide layer (not shown) may be formed 1062 on the
wafer 120. The ED oxide, if formed, is masked 1064 and removed fromislands islands 128, and gate dielectric for preferred polysilicon gate devices onislands 130. Preferably, the gate dielectric is less than 1.5 nanometers (1.5 nm) thick, preferably 1.0 nm thick, and chosen such that Tiny for the polysilicon devices, 1.3-1.5 nm, is matched to the RMG devices. A polysilicon layer less than 50 nm thick, preferably 25 nm thick, is deposited on the gate dielectric layer. -
FIGS. 3A-D show an example of device formation through polysilicon device gate completion for P-type devices. First, the polysilicon layer and gate dielectric layer are patterned 1082, e.g., using a typical state of the art mask and etch technique, which definespolysilicon gates dielectric RMG device locations 142 and in preferred polysilicongate device locations 144. Thepolysilicon gates 134 are, essentially sacrificial polysilicon gates andpolysilicon gates 136 are gates of the preferred poly gate devices. Theislands - Next, a spacer dielectric (e.g., nitride) layer is conformally formed and patterned, e.g., using a suitable mask an etch techniques, leaving
dielectric segments polysilicon gates surface layer islands surface layer islands drain regions 150. Aconformable stress layer 152 is formed on the wafer, e.g., a conformable nitride layer is deposited. Then, thewafer 120 is covered with aflowable dielectric layer 154, e.g., flowable oxide. - In
FIG. 3B the wafer is masked 156 to protect areas where silicon gate devices are not being tailored, e.g.,RMG FET islands 128. Then, inFIG. 3C the exposed silicon gate areas are etched 110, 1100 with a timed etch, e.g., using an anisotropic Reactive Ion Etch (RIE). The RIE removes theflowable oxide 154 to expose thenitride segment 148 on thepolysilicon gate 136. A nitride RIE removes exposed horizontal portions ofnitride segment 148 and exposes thegate 136 withonly gate sidewalls 148′ remaining along thepolysilicon gates 136. The exposedpolysilicon gates 136 are implanted, e.g., for a P-type FET with a P+ implant. - The mask is removed in
FIG. 3D and thewafer 120 is annealed in a doping anneal. Thewafer 120 is cleaned with a typical silicide pre-clean. Then, silicide 158 is formed on thepolysilicon gate 136. Thesilicide 158 is preferably, Cobalt Silicide (CoSi), selected to withstand thermal requirements of subsequent RMG formation. -
FIGS. 4A-D show a variation on the current example ofFIGS. 3B and C, wherein chip NFETs and PFETs both include RMG and polysilicon gate devices with like features labeled identically, except P-type structure features are differentiated further by -p and N-type structure features are differentiated by -n. Further, while these figures show PFETs being treated first, followed by NFETs, this is for example only and not intended as a limitation. Devices may be treated together or NFETs may be treated first, as desired at the time of manufacture. - So, first in
FIG. 4A as inFIG. 3B , the wafer is masked and only the polysilicon PFET gates 136-p are uncovered. As inFIG. 3C inFIG. 4B , a RIE removes the flowable oxide over the exposedflowable nitride layer 152 and exposes upper portions ofsegment 148 on the polysilicon gate 136-p. A nitride RIE removes exposed portions ofsegment 148 to expose the gate 136-p, which is implanted with a P+ implant. InFIG. 4C as inFIGS. 4A and 3B , the wafer is masked and only the oxide above polysilicon NFET gates 136-n is uncovered. InFIG. 4D , a RIE removes theflowable oxide 154 to expose theflowable nitride layer 152 abovesegment 148″ on the polysilicon gate 136-n. A nitride RIE removes the upper portion of theflowable nitride layer 152 and horizontal portions ofsegment 148″ to expose the gate 136-n betweensidewalls 148′″, for implant with a N+ implant. - Whether only PFET fabrication or both include polysilicon gates, fabrication continues in
FIGS. 5A-D , which show an example of RMG device formation after polysilicon device gate 136 (or 136-n and -p) formation. First, thewafer 120 is re-covered 1102 with aflowable dielectric layer 154′, e.g., flowable oxide. Then inFIG. 5B , the upper portions of the flowable dielectric layer, theflowable nitride layer 152′ and thenitride segments 146 are removed 112, 112′, preferably using a typical chemical-mechanical (chem-mech) polishing (CMP) technique to expose thesacrificial polysilicon gates 134. Preferably, the CMP is highly selective to dielectric materials and stops on thesilicide 158. Since CMP is only used to expose thesacrificial gates 134, thesilicon gate devices 144 are relatively immune to CMP induced variations. Thus, longer channel silicon gate devices, e.g., lengths several times longer than the typical device design length, are available for analog applications. - After removing the
sacrificial polysilicon gates 128, preferably, using a selective wet etch, apartial void 160 forms inFIG. 5C . Then, the dielectric 138 is removed to complete thevoid 160. A high-k dielectric layer, preferably, 2 nm thick, is formed in the RMG gate location and lining thevoid 160. The high-k dielectric is removed from the surface, e.g. using CMP, to leave the voids lined with high-k dielectric layer 162. The high-k dielectric may be any suitable high-k dielectric material, conformally deposited, and removed using CMP. Preferably, the high-k dielectric material is Zirconium Oxide (ZrO5) or hafnium dioxide (HfO2). - RMG gate formation is completed in
FIG. 5D by filling the lined 162 RMG gate location withmetal 164. The lined RMG gate location may be filled, for example, by forming a layer of work function metals, and preferably, a combination of metals such as Aluminum (Al), Titanium Nitride (TiNi), and/or Titanium Aluminum (TiAl). The work function metal layer is formed on the wafer surface using any suitable technique, followed by CMP. Alternately, the metal may be formed on the high-k dielectric layer 162 and a single CMP may be used to remove excess metal and high-k dielectric. - Thereafter, as shown in
FIG. 6 , processing continues normally 114. So, for example,silicide 166 is formed on device semiconductor surfaces, e.g., on SiGe source/drain regions 150. Contactpads 168 are formed through the remnant of dielectric 154′ to thesilicide 166. Then,dielectric layer 154″ is re-formed on the wafer over thecontact pads 168.Contacts 170 are formed through thedielectric layer 154″ to underlying metal, e.g.,metal gates 164,polysilicon gates 136 andcontact pads 168. Ametal wiring 172 layer is formed on the wafer. Optionally, themetal wires 172 andcontacts 170 may be formed in a single step, e.g., using a typical dual damascene step. Wafer/chip fabrication continues 116 normally though typical BEOL steps. - Thus, the resulting ICs have both RMG and polysilicon gate devices on the same chip and even in the same circuits or functional logic blocks (e.g., Inverters. NAND gates and NOR gates). Moreover, the polysilicon gate PFETs may have lower VTS than, and Tinv matched to, any corresponding RMG PFETs.
-
FIG. 7 shows an optional fabrication variation corresponding toFIG. 3B with identical features labeled identically, that may be suitable for analog applications or where low VT devices with thicker oxide are needed. In this optional embodiment, thicker gatedielectric devices 180 may be formed on the same chips with relatively minor fabrication adjustments, depositingED oxide 182 and selectively removing it. Thepolysilicon 184 in the thicker gate dielectric (ED) devices, orEDPFETs 180, is processed substantially identically to thepolysilicon gates 136, as shown inFIGS. 3C and D, 5A-D and 6. This allows for longer channel polysilicon devices, that could not otherwise be included in RMGFET circuits. Moreover, these EDPFETs are relatively more immune to CMP variations. - Optionally, fuses 190 also may be formed on
STI 192 with thepolysilicon gates 136, beginning as shown inFIGS. 8A-8C , which correspond toFIGS. 3B and 3C with identical features labeled identically. First inFIG. 8A as inFIG. 3B , the wafer is masked 194 and the polysilicon segment(s) 190 is(are) uncovered withpolysilicon PFET gates 136. A RIE removes theflowable oxide 154 andflowable nitride 146 over, and exposes the horizontal surfaces of,nitride segments nitride segments FIG. 8B . Removing horizontal surfaces ofnitride segments gates 136 and polysilicon segment(s) 190. Then, themask 194, e.g., a photoresist, is removed normally. - Next, the
polysilicon PFET gates 136 are implanted inFIG. 8C , substantially as inFIG. 3B . So prior to implant, the wafer is masked 198 again and only thepolysilicon PFET gates 136 are left unmasked. A RIE removes theflowable oxide 152 over thepolysilicon gate 136 to exposeflowable nitride layer 150 abovenitride segment 146. A nitride RIE removes horizontal portions ofnitride layers gate 136, which is implanted with a P+ implant. - The
mask 198 is removed inFIG. 8C and thewafer 120 is annealed in a doping anneal. Thewafer 120 is cleaned with a typical silicide pre-clean. Then,silicide polysilicon gates 136 and fusesegments 190. Preferably, thesilicide - Thereafter, as shown in
FIG. 9 , processing continues normally, substantially as described forFIG. 6 . So again,silicide 158 is formed on device semiconductor surfaces, e.g., on SiGe source/drain regions 150. Contactpads 168 are formed through the remnant of dielectric 154′ to thesilicide 166. Then,dielectric layer 154″ is re-formed on the wafer over thecontact pads 168.Contacts dielectric layer 154″ to underlying metal, e.g.,metal gates 164,polysilicon gates 136 andcontact pads 168 and fuses 190.Metal wiring 172 layer is formed on the wafer. Optionally, themetal wires 172 andcontacts -
FIG. 10 shows an example of awafer 210 with chips 212 manufactured according to a preferred embodiment of the present invention. The chips includeconnected circuits 214, one or more of which includes preferred FETs. - Thus advantageously, silicon gate PFETs (and silicon eFuses) may be mixed selectively with metal gate devices on RMGFET ICs to provide low VT PFETs without compromising short channel effects and without adding significant manufacturing costs. Manufacturing costs increase only slightly because the present invention uses what was previously disposable, sacrificial polysilicon shapes in a process that adds only low critical manufacturing steps, i.e., mask and etch steps to remove dielectric layers and an implant and silicide to tailor the polysilicon gates. Moreover, this may be extended to form thicker gate dielectric PFETs by selectively forming thick oxide, and to NFETs as well with the addition of a single implant mask. These thicker dielectric, low VT devices have analog applications and are very useful for achieving high dynamic ranges for analog/radio frequency (RF) circuits.
- In addition, preferred low VT devices are produced without degrading device transconductances (Gm/Gds), otherwise apparent in a low VT devices realized using lower channel doping or compensation doping. Neither do preferred low VT devices suffer from body resistance (Rbody) penalties which is also advantageous for high frequency analog devices.
- While the invention has been described in terms of preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims. It is intended that all such variations and modifications fall within the scope of the appended claims. Examples and drawings are, accordingly, to be regarded as illustrative rather than restrictive.
Claims (19)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/663,256 US20150325647A1 (en) | 2011-05-16 | 2015-03-19 | INTEGRATED CIRCUIT (IC) CHIP HAVING BOTH METAL AND SILICON GATE FIELD EFFECT TRANSISTORs (FETs) AND METHOD OF MANUFACTURE |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/108,213 US9012283B2 (en) | 2011-05-16 | 2011-05-16 | Integrated circuit (IC) chip having both metal and silicon gate field effect transistors (FETs) and method of manufacture |
US14/663,256 US20150325647A1 (en) | 2011-05-16 | 2015-03-19 | INTEGRATED CIRCUIT (IC) CHIP HAVING BOTH METAL AND SILICON GATE FIELD EFFECT TRANSISTORs (FETs) AND METHOD OF MANUFACTURE |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/108,213 Division US9012283B2 (en) | 2011-05-16 | 2011-05-16 | Integrated circuit (IC) chip having both metal and silicon gate field effect transistors (FETs) and method of manufacture |
Publications (1)
Publication Number | Publication Date |
---|---|
US20150325647A1 true US20150325647A1 (en) | 2015-11-12 |
Family
ID=47174292
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/108,213 Expired - Fee Related US9012283B2 (en) | 2011-05-16 | 2011-05-16 | Integrated circuit (IC) chip having both metal and silicon gate field effect transistors (FETs) and method of manufacture |
US14/663,256 Abandoned US20150325647A1 (en) | 2011-05-16 | 2015-03-19 | INTEGRATED CIRCUIT (IC) CHIP HAVING BOTH METAL AND SILICON GATE FIELD EFFECT TRANSISTORs (FETs) AND METHOD OF MANUFACTURE |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/108,213 Expired - Fee Related US9012283B2 (en) | 2011-05-16 | 2011-05-16 | Integrated circuit (IC) chip having both metal and silicon gate field effect transistors (FETs) and method of manufacture |
Country Status (1)
Country | Link |
---|---|
US (2) | US9012283B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9929091B2 (en) | 2016-08-25 | 2018-03-27 | International Business Machines Corporation | Vertical fuse structures |
US10304685B2 (en) | 2017-08-14 | 2019-05-28 | United Microelectronics Corp. | Manufacturing method of integrated circuit |
Families Citing this family (149)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9324576B2 (en) | 2010-05-27 | 2016-04-26 | Applied Materials, Inc. | Selective etch for silicon films |
US10283321B2 (en) | 2011-01-18 | 2019-05-07 | Applied Materials, Inc. | Semiconductor processing system and methods using capacitively coupled plasma |
US8999856B2 (en) | 2011-03-14 | 2015-04-07 | Applied Materials, Inc. | Methods for etch of sin films |
US9064815B2 (en) | 2011-03-14 | 2015-06-23 | Applied Materials, Inc. | Methods for etch of metal and metal-oxide films |
US8771536B2 (en) | 2011-08-01 | 2014-07-08 | Applied Materials, Inc. | Dry-etch for silicon-and-carbon-containing films |
US20130260564A1 (en) * | 2011-09-26 | 2013-10-03 | Applied Materials, Inc. | Insensitive dry removal process for semiconductor integration |
US8927390B2 (en) | 2011-09-26 | 2015-01-06 | Applied Materials, Inc. | Intrench profile |
US8808563B2 (en) | 2011-10-07 | 2014-08-19 | Applied Materials, Inc. | Selective etch of silicon by way of metastable hydrogen termination |
US9267739B2 (en) | 2012-07-18 | 2016-02-23 | Applied Materials, Inc. | Pedestal with multi-zone temperature control and multiple purge capabilities |
US9373517B2 (en) | 2012-08-02 | 2016-06-21 | Applied Materials, Inc. | Semiconductor processing with DC assisted RF power for improved control |
US9034770B2 (en) | 2012-09-17 | 2015-05-19 | Applied Materials, Inc. | Differential silicon oxide etch |
US9023734B2 (en) | 2012-09-18 | 2015-05-05 | Applied Materials, Inc. | Radical-component oxide etch |
US9390937B2 (en) | 2012-09-20 | 2016-07-12 | Applied Materials, Inc. | Silicon-carbon-nitride selective etch |
US9132436B2 (en) | 2012-09-21 | 2015-09-15 | Applied Materials, Inc. | Chemical control features in wafer process equipment |
US8969212B2 (en) | 2012-11-20 | 2015-03-03 | Applied Materials, Inc. | Dry-etch selectivity |
US8980763B2 (en) | 2012-11-30 | 2015-03-17 | Applied Materials, Inc. | Dry-etch for selective tungsten removal |
US9064816B2 (en) | 2012-11-30 | 2015-06-23 | Applied Materials, Inc. | Dry-etch for selective oxidation removal |
US9111877B2 (en) | 2012-12-18 | 2015-08-18 | Applied Materials, Inc. | Non-local plasma oxide etch |
US8921234B2 (en) | 2012-12-21 | 2014-12-30 | Applied Materials, Inc. | Selective titanium nitride etching |
US10256079B2 (en) | 2013-02-08 | 2019-04-09 | Applied Materials, Inc. | Semiconductor processing systems having multiple plasma configurations |
US9362130B2 (en) | 2013-03-01 | 2016-06-07 | Applied Materials, Inc. | Enhanced etching processes using remote plasma sources |
US9040422B2 (en) | 2013-03-05 | 2015-05-26 | Applied Materials, Inc. | Selective titanium nitride removal |
US20140252491A1 (en) * | 2013-03-05 | 2014-09-11 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method of the same |
US8801952B1 (en) | 2013-03-07 | 2014-08-12 | Applied Materials, Inc. | Conformal oxide dry etch |
US10170282B2 (en) | 2013-03-08 | 2019-01-01 | Applied Materials, Inc. | Insulated semiconductor faceplate designs |
US9287313B2 (en) * | 2013-03-12 | 2016-03-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Active pixel sensor having a raised source/drain |
US9978650B2 (en) | 2013-03-13 | 2018-05-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistor channel |
US20140271097A1 (en) | 2013-03-15 | 2014-09-18 | Applied Materials, Inc. | Processing systems and methods for halide scavenging |
US8895449B1 (en) | 2013-05-16 | 2014-11-25 | Applied Materials, Inc. | Delicate dry clean |
US9114438B2 (en) | 2013-05-21 | 2015-08-25 | Applied Materials, Inc. | Copper residue chamber clean |
US9493879B2 (en) | 2013-07-12 | 2016-11-15 | Applied Materials, Inc. | Selective sputtering for pattern transfer |
US9773648B2 (en) | 2013-08-30 | 2017-09-26 | Applied Materials, Inc. | Dual discharge modes operation for remote plasma |
US8956980B1 (en) | 2013-09-16 | 2015-02-17 | Applied Materials, Inc. | Selective etch of silicon nitride |
US8951429B1 (en) | 2013-10-29 | 2015-02-10 | Applied Materials, Inc. | Tungsten oxide processing |
US9576809B2 (en) | 2013-11-04 | 2017-02-21 | Applied Materials, Inc. | Etch suppression with germanium |
US9236265B2 (en) | 2013-11-04 | 2016-01-12 | Applied Materials, Inc. | Silicon germanium processing |
US9520303B2 (en) | 2013-11-12 | 2016-12-13 | Applied Materials, Inc. | Aluminum selective etch |
US9245762B2 (en) | 2013-12-02 | 2016-01-26 | Applied Materials, Inc. | Procedure for etch rate consistency |
US9117855B2 (en) | 2013-12-04 | 2015-08-25 | Applied Materials, Inc. | Polarity control for remote plasma |
US9263278B2 (en) | 2013-12-17 | 2016-02-16 | Applied Materials, Inc. | Dopant etch selectivity control |
US9287095B2 (en) | 2013-12-17 | 2016-03-15 | Applied Materials, Inc. | Semiconductor system assemblies and methods of operation |
US9190293B2 (en) | 2013-12-18 | 2015-11-17 | Applied Materials, Inc. | Even tungsten etch for high aspect ratio trenches |
US9287134B2 (en) | 2014-01-17 | 2016-03-15 | Applied Materials, Inc. | Titanium oxide etch |
US9396989B2 (en) | 2014-01-27 | 2016-07-19 | Applied Materials, Inc. | Air gaps between copper lines |
US9293568B2 (en) | 2014-01-27 | 2016-03-22 | Applied Materials, Inc. | Method of fin patterning |
US9385028B2 (en) | 2014-02-03 | 2016-07-05 | Applied Materials, Inc. | Air gap process |
US9499898B2 (en) | 2014-03-03 | 2016-11-22 | Applied Materials, Inc. | Layered thin film heater and method of fabrication |
US9299575B2 (en) | 2014-03-17 | 2016-03-29 | Applied Materials, Inc. | Gas-phase tungsten etch |
US9299538B2 (en) | 2014-03-20 | 2016-03-29 | Applied Materials, Inc. | Radial waveguide systems and methods for post-match control of microwaves |
US9299537B2 (en) | 2014-03-20 | 2016-03-29 | Applied Materials, Inc. | Radial waveguide systems and methods for post-match control of microwaves |
US9136273B1 (en) | 2014-03-21 | 2015-09-15 | Applied Materials, Inc. | Flash gate air gap |
US9903020B2 (en) | 2014-03-31 | 2018-02-27 | Applied Materials, Inc. | Generation of compact alumina passivation layers on aluminum plasma equipment components |
US9269590B2 (en) | 2014-04-07 | 2016-02-23 | Applied Materials, Inc. | Spacer formation |
US9309598B2 (en) | 2014-05-28 | 2016-04-12 | Applied Materials, Inc. | Oxide and metal removal |
US9847289B2 (en) | 2014-05-30 | 2017-12-19 | Applied Materials, Inc. | Protective via cap for improved interconnect performance |
US9406523B2 (en) | 2014-06-19 | 2016-08-02 | Applied Materials, Inc. | Highly selective doped oxide removal method |
US9378969B2 (en) | 2014-06-19 | 2016-06-28 | Applied Materials, Inc. | Low temperature gas-phase carbon removal |
US9425058B2 (en) | 2014-07-24 | 2016-08-23 | Applied Materials, Inc. | Simplified litho-etch-litho-etch process |
US9159606B1 (en) | 2014-07-31 | 2015-10-13 | Applied Materials, Inc. | Metal air gap |
US9496167B2 (en) | 2014-07-31 | 2016-11-15 | Applied Materials, Inc. | Integrated bit-line airgap formation and gate stack post clean |
US9378978B2 (en) | 2014-07-31 | 2016-06-28 | Applied Materials, Inc. | Integrated oxide recess and floating gate fin trimming |
US9165786B1 (en) | 2014-08-05 | 2015-10-20 | Applied Materials, Inc. | Integrated oxide and nitride recess for better channel contact in 3D architectures |
US9659753B2 (en) | 2014-08-07 | 2017-05-23 | Applied Materials, Inc. | Grooved insulator to reduce leakage current |
US9553102B2 (en) | 2014-08-19 | 2017-01-24 | Applied Materials, Inc. | Tungsten separation |
US9355856B2 (en) | 2014-09-12 | 2016-05-31 | Applied Materials, Inc. | V trench dry etch |
US9355862B2 (en) | 2014-09-24 | 2016-05-31 | Applied Materials, Inc. | Fluorine-based hardmask removal |
US9368364B2 (en) | 2014-09-24 | 2016-06-14 | Applied Materials, Inc. | Silicon etch process with tunable selectivity to SiO2 and other materials |
US9613822B2 (en) | 2014-09-25 | 2017-04-04 | Applied Materials, Inc. | Oxide etch selectivity enhancement |
US9966240B2 (en) | 2014-10-14 | 2018-05-08 | Applied Materials, Inc. | Systems and methods for internal surface conditioning assessment in plasma processing equipment |
US9355922B2 (en) | 2014-10-14 | 2016-05-31 | Applied Materials, Inc. | Systems and methods for internal surface conditioning in plasma processing equipment |
US11637002B2 (en) | 2014-11-26 | 2023-04-25 | Applied Materials, Inc. | Methods and systems to enhance process uniformity |
US9299583B1 (en) | 2014-12-05 | 2016-03-29 | Applied Materials, Inc. | Aluminum oxide selective etch |
US10573496B2 (en) | 2014-12-09 | 2020-02-25 | Applied Materials, Inc. | Direct outlet toroidal plasma source |
US10224210B2 (en) | 2014-12-09 | 2019-03-05 | Applied Materials, Inc. | Plasma processing system with direct outlet toroidal plasma source |
US9502258B2 (en) | 2014-12-23 | 2016-11-22 | Applied Materials, Inc. | Anisotropic gap etch |
US9343272B1 (en) | 2015-01-08 | 2016-05-17 | Applied Materials, Inc. | Self-aligned process |
US11257693B2 (en) | 2015-01-09 | 2022-02-22 | Applied Materials, Inc. | Methods and systems to improve pedestal temperature control |
US9373522B1 (en) | 2015-01-22 | 2016-06-21 | Applied Mateials, Inc. | Titanium nitride removal |
US9449846B2 (en) | 2015-01-28 | 2016-09-20 | Applied Materials, Inc. | Vertical gate separation |
US20160225652A1 (en) | 2015-02-03 | 2016-08-04 | Applied Materials, Inc. | Low temperature chuck for plasma processing systems |
US9728437B2 (en) | 2015-02-03 | 2017-08-08 | Applied Materials, Inc. | High temperature chuck for plasma processing systems |
US9881805B2 (en) | 2015-03-02 | 2018-01-30 | Applied Materials, Inc. | Silicon selective removal |
US9741593B2 (en) | 2015-08-06 | 2017-08-22 | Applied Materials, Inc. | Thermal management systems and methods for wafer processing systems |
US9691645B2 (en) | 2015-08-06 | 2017-06-27 | Applied Materials, Inc. | Bolted wafer chuck thermal management systems and methods for wafer processing systems |
US9349605B1 (en) | 2015-08-07 | 2016-05-24 | Applied Materials, Inc. | Oxide etch selectivity systems and methods |
US10504700B2 (en) | 2015-08-27 | 2019-12-10 | Applied Materials, Inc. | Plasma etching systems and methods with secondary plasma injection |
US10504754B2 (en) | 2016-05-19 | 2019-12-10 | Applied Materials, Inc. | Systems and methods for improved semiconductor etching and component protection |
US10522371B2 (en) | 2016-05-19 | 2019-12-31 | Applied Materials, Inc. | Systems and methods for improved semiconductor etching and component protection |
US9865484B1 (en) | 2016-06-29 | 2018-01-09 | Applied Materials, Inc. | Selective etch using material modification and RF pulsing |
US10629473B2 (en) | 2016-09-09 | 2020-04-21 | Applied Materials, Inc. | Footing removal for nitride spacer |
US10062575B2 (en) | 2016-09-09 | 2018-08-28 | Applied Materials, Inc. | Poly directional etch by oxidation |
US9721789B1 (en) | 2016-10-04 | 2017-08-01 | Applied Materials, Inc. | Saving ion-damaged spacers |
US9934942B1 (en) | 2016-10-04 | 2018-04-03 | Applied Materials, Inc. | Chamber with flow-through source |
US10546729B2 (en) | 2016-10-04 | 2020-01-28 | Applied Materials, Inc. | Dual-channel showerhead with improved profile |
US10062585B2 (en) | 2016-10-04 | 2018-08-28 | Applied Materials, Inc. | Oxygen compatible plasma source |
US10062579B2 (en) | 2016-10-07 | 2018-08-28 | Applied Materials, Inc. | Selective SiN lateral recess |
US9947549B1 (en) | 2016-10-10 | 2018-04-17 | Applied Materials, Inc. | Cobalt-containing material removal |
US10163696B2 (en) | 2016-11-11 | 2018-12-25 | Applied Materials, Inc. | Selective cobalt removal for bottom up gapfill |
US9768034B1 (en) | 2016-11-11 | 2017-09-19 | Applied Materials, Inc. | Removal methods for high aspect ratio structures |
US10026621B2 (en) | 2016-11-14 | 2018-07-17 | Applied Materials, Inc. | SiN spacer profile patterning |
US10242908B2 (en) | 2016-11-14 | 2019-03-26 | Applied Materials, Inc. | Airgap formation with damage-free copper |
US10566206B2 (en) | 2016-12-27 | 2020-02-18 | Applied Materials, Inc. | Systems and methods for anisotropic material breakthrough |
US10403507B2 (en) | 2017-02-03 | 2019-09-03 | Applied Materials, Inc. | Shaped etch profile with oxidation |
US10431429B2 (en) | 2017-02-03 | 2019-10-01 | Applied Materials, Inc. | Systems and methods for radial and azimuthal control of plasma uniformity |
US10043684B1 (en) | 2017-02-06 | 2018-08-07 | Applied Materials, Inc. | Self-limiting atomic thermal etching systems and methods |
US10319739B2 (en) | 2017-02-08 | 2019-06-11 | Applied Materials, Inc. | Accommodating imperfectly aligned memory holes |
US10943834B2 (en) | 2017-03-13 | 2021-03-09 | Applied Materials, Inc. | Replacement contact process |
US10319649B2 (en) | 2017-04-11 | 2019-06-11 | Applied Materials, Inc. | Optical emission spectroscopy (OES) for remote plasma monitoring |
US11276559B2 (en) | 2017-05-17 | 2022-03-15 | Applied Materials, Inc. | Semiconductor processing chamber for multiple precursor flow |
US11276590B2 (en) | 2017-05-17 | 2022-03-15 | Applied Materials, Inc. | Multi-zone semiconductor substrate supports |
US10049891B1 (en) | 2017-05-31 | 2018-08-14 | Applied Materials, Inc. | Selective in situ cobalt residue removal |
US10497579B2 (en) | 2017-05-31 | 2019-12-03 | Applied Materials, Inc. | Water-free etching methods |
US10920320B2 (en) | 2017-06-16 | 2021-02-16 | Applied Materials, Inc. | Plasma health determination in semiconductor substrate processing reactors |
US10541246B2 (en) | 2017-06-26 | 2020-01-21 | Applied Materials, Inc. | 3D flash memory cells which discourage cross-cell electrical tunneling |
US10727080B2 (en) | 2017-07-07 | 2020-07-28 | Applied Materials, Inc. | Tantalum-containing material removal |
US10541184B2 (en) | 2017-07-11 | 2020-01-21 | Applied Materials, Inc. | Optical emission spectroscopic techniques for monitoring etching |
US10354889B2 (en) | 2017-07-17 | 2019-07-16 | Applied Materials, Inc. | Non-halogen etching of silicon-containing materials |
US10170336B1 (en) | 2017-08-04 | 2019-01-01 | Applied Materials, Inc. | Methods for anisotropic control of selective silicon removal |
US10043674B1 (en) | 2017-08-04 | 2018-08-07 | Applied Materials, Inc. | Germanium etching systems and methods |
US10297458B2 (en) | 2017-08-07 | 2019-05-21 | Applied Materials, Inc. | Process window widening using coated parts in plasma etch processes |
US10283324B1 (en) | 2017-10-24 | 2019-05-07 | Applied Materials, Inc. | Oxygen treatment for nitride etching |
US10128086B1 (en) | 2017-10-24 | 2018-11-13 | Applied Materials, Inc. | Silicon pretreatment for nitride removal |
US10256112B1 (en) | 2017-12-08 | 2019-04-09 | Applied Materials, Inc. | Selective tungsten removal |
US10903054B2 (en) | 2017-12-19 | 2021-01-26 | Applied Materials, Inc. | Multi-zone gas distribution systems and methods |
US11328909B2 (en) | 2017-12-22 | 2022-05-10 | Applied Materials, Inc. | Chamber conditioning and removal processes |
US10854426B2 (en) | 2018-01-08 | 2020-12-01 | Applied Materials, Inc. | Metal recess for semiconductor structures |
US10679870B2 (en) | 2018-02-15 | 2020-06-09 | Applied Materials, Inc. | Semiconductor processing chamber multistage mixing apparatus |
US10964512B2 (en) | 2018-02-15 | 2021-03-30 | Applied Materials, Inc. | Semiconductor processing chamber multistage mixing apparatus and methods |
TWI716818B (en) | 2018-02-28 | 2021-01-21 | 美商應用材料股份有限公司 | Systems and methods to form airgaps |
US10593560B2 (en) | 2018-03-01 | 2020-03-17 | Applied Materials, Inc. | Magnetic induction plasma source for semiconductor processes and equipment |
US10319600B1 (en) | 2018-03-12 | 2019-06-11 | Applied Materials, Inc. | Thermal silicon etch |
US10497573B2 (en) | 2018-03-13 | 2019-12-03 | Applied Materials, Inc. | Selective atomic layer etching of semiconductor materials |
US10573527B2 (en) | 2018-04-06 | 2020-02-25 | Applied Materials, Inc. | Gas-phase selective etching systems and methods |
US10490406B2 (en) | 2018-04-10 | 2019-11-26 | Appled Materials, Inc. | Systems and methods for material breakthrough |
US10699879B2 (en) | 2018-04-17 | 2020-06-30 | Applied Materials, Inc. | Two piece electrode assembly with gap for plasma control |
US10886137B2 (en) | 2018-04-30 | 2021-01-05 | Applied Materials, Inc. | Selective nitride removal |
US10755941B2 (en) | 2018-07-06 | 2020-08-25 | Applied Materials, Inc. | Self-limiting selective etching systems and methods |
US10872778B2 (en) | 2018-07-06 | 2020-12-22 | Applied Materials, Inc. | Systems and methods utilizing solid-phase etchants |
US10672642B2 (en) | 2018-07-24 | 2020-06-02 | Applied Materials, Inc. | Systems and methods for pedestal configuration |
US10892198B2 (en) | 2018-09-14 | 2021-01-12 | Applied Materials, Inc. | Systems and methods for improved performance in semiconductor processing |
US11049755B2 (en) | 2018-09-14 | 2021-06-29 | Applied Materials, Inc. | Semiconductor substrate supports with embedded RF shield |
US11062887B2 (en) | 2018-09-17 | 2021-07-13 | Applied Materials, Inc. | High temperature RF heater pedestals |
US11417534B2 (en) | 2018-09-21 | 2022-08-16 | Applied Materials, Inc. | Selective material removal |
US11682560B2 (en) | 2018-10-11 | 2023-06-20 | Applied Materials, Inc. | Systems and methods for hafnium-containing film removal |
US11121002B2 (en) | 2018-10-24 | 2021-09-14 | Applied Materials, Inc. | Systems and methods for etching metals and metal derivatives |
US11437242B2 (en) | 2018-11-27 | 2022-09-06 | Applied Materials, Inc. | Selective removal of silicon-containing materials |
US11721527B2 (en) | 2019-01-07 | 2023-08-08 | Applied Materials, Inc. | Processing chamber mixing systems |
US10920319B2 (en) | 2019-01-11 | 2021-02-16 | Applied Materials, Inc. | Ceramic showerheads with conductive electrodes |
JP2021093397A (en) * | 2019-12-06 | 2021-06-17 | キヤノン株式会社 | Semiconductor device and apparatus |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6207510B1 (en) * | 1999-01-12 | 2001-03-27 | Lucent Technologies Inc. | Method for making an integrated circuit including high and low voltage transistors |
US6297139B1 (en) * | 2000-01-10 | 2001-10-02 | United Microelectronics Corp. | Method of forming a contact hole in a semiconductor wafer |
US20060267137A1 (en) * | 2005-05-24 | 2006-11-30 | International Business Machines Corporation | Method and structure to prevent circuit network charging during fabrication of integrated circuits |
US20110045665A1 (en) * | 2007-12-31 | 2011-02-24 | Globalfoundries Inc. | Reducing the creation of charge traps at gate dielectrics in mos transistors by performing a hydrogen treatment |
US8901537B2 (en) * | 2010-12-21 | 2014-12-02 | Intel Corporation | Transistors with high concentration of boron doped germanium |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5650340A (en) | 1994-08-18 | 1997-07-22 | Sun Microsystems, Inc. | Method of making asymmetric low power MOS devices |
US5856225A (en) * | 1997-11-24 | 1999-01-05 | Chartered Semiconductor Manufacturing Ltd | Creation of a self-aligned, ion implanted channel region, after source and drain formation |
US6096611A (en) | 1998-03-13 | 2000-08-01 | Texas Instruments - Acer Incorporated | Method to fabricate dual threshold CMOS circuits |
US6265293B1 (en) * | 1999-08-27 | 2001-07-24 | Advanced Micro Devices, Inc. | CMOS transistors fabricated in optimized RTA scheme |
US6369606B1 (en) | 2000-09-27 | 2002-04-09 | International Business Machines Corporation | Mixed threshold voltage CMOS logic device and method of manufacture therefor |
US6849492B2 (en) | 2002-07-08 | 2005-02-01 | Micron Technology, Inc. | Method for forming standard voltage threshold and low voltage threshold MOSFET devices |
US7091118B1 (en) | 2004-11-16 | 2006-08-15 | Advanced Micro Devices, Inc. | Replacement metal gate transistor with metal-rich silicon layer and method for making the same |
US8188551B2 (en) * | 2005-09-30 | 2012-05-29 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
US8648403B2 (en) * | 2006-04-21 | 2014-02-11 | International Business Machines Corporation | Dynamic memory cell structures |
US7625791B2 (en) | 2007-10-29 | 2009-12-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | High-k dielectric metal gate device structure and method for forming the same |
-
2011
- 2011-05-16 US US13/108,213 patent/US9012283B2/en not_active Expired - Fee Related
-
2015
- 2015-03-19 US US14/663,256 patent/US20150325647A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6207510B1 (en) * | 1999-01-12 | 2001-03-27 | Lucent Technologies Inc. | Method for making an integrated circuit including high and low voltage transistors |
US6297139B1 (en) * | 2000-01-10 | 2001-10-02 | United Microelectronics Corp. | Method of forming a contact hole in a semiconductor wafer |
US20060267137A1 (en) * | 2005-05-24 | 2006-11-30 | International Business Machines Corporation | Method and structure to prevent circuit network charging during fabrication of integrated circuits |
US20110045665A1 (en) * | 2007-12-31 | 2011-02-24 | Globalfoundries Inc. | Reducing the creation of charge traps at gate dielectrics in mos transistors by performing a hydrogen treatment |
US8901537B2 (en) * | 2010-12-21 | 2014-12-02 | Intel Corporation | Transistors with high concentration of boron doped germanium |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9929091B2 (en) | 2016-08-25 | 2018-03-27 | International Business Machines Corporation | Vertical fuse structures |
US10032717B2 (en) | 2016-08-25 | 2018-07-24 | International Business Machines Corporation | Vertical fuse structures |
US10043747B2 (en) | 2016-08-25 | 2018-08-07 | International Business Machines Corporation | Vertical fuse structures |
US10304685B2 (en) | 2017-08-14 | 2019-05-28 | United Microelectronics Corp. | Manufacturing method of integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
US20120292664A1 (en) | 2012-11-22 |
US9012283B2 (en) | 2015-04-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9012283B2 (en) | Integrated circuit (IC) chip having both metal and silicon gate field effect transistors (FETs) and method of manufacture | |
US6864540B1 (en) | High performance FET with elevated source/drain region | |
US6580137B2 (en) | Damascene double gated transistors and related manufacturing methods | |
TWI412106B (en) | Integrated circuit | |
US6696333B1 (en) | Method of making integrated circuit with MOSFETs having bi-layer metal gate electrodes | |
EP2319077B1 (en) | Body contact for sram cell comprising double-channel transistors | |
TWI608571B (en) | Cointegration of bulk and soi semiconductor devices | |
EP2381470B1 (en) | Semiconductor device comprising a field-effect transistor in a silicon-on-insulator structure | |
US9385047B2 (en) | Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same | |
US11031301B2 (en) | Gate formation scheme for n-type and p-type transistors having separately tuned threshold voltages | |
US9231045B2 (en) | Methods for fabricating integrated circuits with polycrystalline silicon resistor structures using a replacment gate process flow, and the integrated circuits fabricated thereby | |
US10510750B2 (en) | High voltage integration for HKMG technology | |
US20170338343A1 (en) | High-voltage transistor device | |
US7824989B2 (en) | Method for reducing overlap capacitance in field effect transistors | |
US11393819B2 (en) | Semiconductor device implemented with buried rails | |
US8846476B2 (en) | Methods of forming multiple N-type semiconductor devices with different threshold voltages on a semiconductor substrate | |
Thomas et al. | 32nm and beyond Multi-V T Ultra-Thin Body and BOX FDSOI: From device to circuit | |
EP1506579A2 (en) | Schottky barrier cmos device and method | |
US9899319B2 (en) | Raised e-fuse | |
JP2008211155A (en) | Semiconductor integrated circuit and manufacturing method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KANIKE, NARASIMHULU;REEL/FRAME:035618/0550 Effective date: 20150406 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001 Effective date: 20150629 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001 Effective date: 20150910 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., NEW YORK Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:056987/0001 Effective date: 20201117 |