JP2008211155A - Semiconductor integrated circuit and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit having protection performance necessary for electrostatic damage and easy to be manufactured, and to provide a method for manufacturing the semiconductor integrated circuit. <P>SOLUTION: The semiconductor integrated circuit includes a plurality of MOSFETs each of which includes a part of an SOI layer formed on a buried oxide film, and at least one of the plurality of MOSFETs acts as an ESD protection transistor. The ESD protection transistor comprises a gate area formed on the SOI layer, a first conductive type area having a first conductive type and formed between the gate area out of the SOI layer and the buried oxide film, and two second conductive type areas each having a second conductive type and opposed to each other through the first conductive type area out of the SOI layer. The first conductive type area has an area having higher first conductive type density on a position closer to the buried oxide film than the intermediate position of the first conductive type area in the depth direction. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit composed of an SOI-CMOS device using an SOI (Silicon on Insulator) substrate, and in particular, protection for protecting the CMOS device from ESD (Electro-Static Damage), that is, electrostatic breakdown. The present invention relates to a semiconductor integrated circuit including a circuit.

  The patent disclosed in Patent Document 1 is that an electrode is also formed in the input protection circuit region when forming a gate electrode of a CMOS transistor, and an impurity is diffused using the electrode as a mask when forming a source / drain of the CMOS transistor. The semiconductor integrated circuit including the input protection circuit portion can be formed without increasing the number of steps by forming a diode in the input protection circuit portion.

  Japanese Patent Application Laid-Open No. 2004-228561 describes a technique for making the thickness of the SOI layer in which the input protection circuit is formed larger than the thickness of the SOI layer that is completely depleted in a circuit portion that requires high-speed operation. Patent Document 3 describes a technique for making a PN junction portion of a protection element amorphous. Furthermore, the content disclosed in Patent Document 4 describes a technique for forming an ESD protection element on a support substrate.

By the way, in a bulk CMOS device, P / N type MOS transistors are separated by a well layer. On the other hand, the SOI-CMOS device is separated by a silicon support substrate and a buried oxide film (BOX), and each element is completely separated by a LOCOS (Local Oxidation of Silicon) oxide film. The operating element region (referred to as an SOI layer) is completely separated by an insulator. Also, the SOI layer is thin (usually <50 nm) and the body region under the channel is all depleted (FD: Fully Depleted) SOI, the SOI layer is thick (usually> 100 nm), and the bottom of the body region A region having a region that is not depleted is called PD (Partially Depleted) SOI. The FD-SOI has the advantage that the substrate floating effect is less likely to occur than the PD-SOI because the majority carriers generated during the device operation are not easily accumulated in the body portion, and the operation with low voltage and low current consumption can be obtained. .
Japanese Patent No. 3415401 JP-A-6-318702 JP-A-8-125030 JP 2002-313924 A

  However, when the internal circuit is configured with FD-SOI, the protection circuit for protecting the internal circuit from the electrostatic breakdown phenomenon has an FD structure similar to the internal circuit due to the difficulty in the manufacturing process and the restrictions on the process. Usually, it is formed. Thus, there are manufacturing restrictions in realizing the protection circuit necessary to obtain the necessary protection characteristics.

  For example, a protection transistor used in a protection circuit is required to prevent an inflow into an internal circuit by promptly flowing an assumed maximum surge current when it occurs. For this reason, the performance of the protection transistor requires current drive characteristics and response characteristics that allow the assumed maximum surge current to flow, and the gate width is also required to be a size corresponding to such characteristics.

  If the gate width is increased to allow a sufficient surge current to flow, the back channel formed parasitically in the protection transistor may not be formed uniformly, and a large surge can only be generated through the locally formed back channel. There is a concern that the protection transistor itself may be destroyed as a result of the current flowing. A structure that appropriately prevents or equalizes the formation of the back channel of the protection transistor is desired.

  The present invention has been devised in view of such problems, and an object of the present invention is to provide a semiconductor integrated circuit and a manufacturing method that have a protection performance necessary for electrostatic breakdown and are easy to manufacture.

  The semiconductor integrated circuit according to claim 1 includes a plurality of MOSFETs each including a part of an SOI layer formed on the buried oxide film, and at least one of the plurality of MOSFETs operates as an ESD protection transistor. The ESD protection transistor is an integrated circuit and has a gate region formed on the SOI layer and a first conductivity type and is formed between the gate region and the buried oxide film in the SOI layer. A first conductivity type region, and two second conductivity type regions having a second conductivity type and facing each other across the first conductivity type region in the SOI layer, the first conductivity type The mold region has a region having a high first conductivity type concentration closer to the buried oxide film than an intermediate position in the depth direction.

  According to a fourth aspect of the present invention, there is provided a manufacturing method for manufacturing the semiconductor integrated circuit according to the first aspect, wherein a resist film having an opening corresponding to a body region of the ESD protection transistor is formed on the SOI layer. A resist film forming step, and a concentration adjusting step of adjusting the concentration of the first conductivity type by changing the energy intensity while implanting impurity ions corresponding to the first conductivity type through the opening. It is characterized by including.

  A semiconductor integrated circuit according to claim 6 is a semiconductor including a plurality of MOSFETs on an SOI wafer including a support substrate, and a functional circuit and an ESD protection circuit that are respectively connected to an external signal terminal, a power supply terminal, and a ground terminal. An ESD protection circuit comprising: a first protection MOSFET comprising a gate connected to the ground terminal; a drain connected to the external signal terminal; and a source connected to the ground terminal; A second protection MOSFET having the same conductivity type as the protection MOSFET and comprising a gate connected to the ground terminal, a drain connected to the power supply terminal, and a source connected to the external signal terminal; And a substrate line connecting the support substrate.

A manufacturing method according to claim 9 is a manufacturing method for manufacturing the protection MOSFET according to claim 6, wherein a gate region forming step of forming a gate region on an SOI wafer;
An opening forming step for forming an opening reaching the support substrate in a field region around the gate region, and an ion implantation process are performed to simultaneously form a drain region and a source region below the gate region. A region forming step for forming a high concentration region on the support substrate exposed through the substrate, an ion activation step for simultaneously performing ion activation treatment on each formed region, and each of the formed regions reach And a substrate line forming step of forming a substrate line composed of a plurality of contacts and a metal wiring connecting the contacts.

  According to the semiconductor integrated circuit and the manufacturing method of the present invention, there is provided a configuration in which the generation of a depletion layer that should occur in substantially the entire body region of the protection transistor is suppressed in the vicinity of the buried oxide film. This provides the necessary protection against electrostatic breakdown and facilitates manufacture.

Embodiments of the present invention will be described in detail with reference to the accompanying drawings.
<First embodiment>
FIG. 1 shows a first embodiment of the present invention and shows a cross section of a semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit 10 includes at least one protection circuit 20 and at least one internal circuit 30.

  The semiconductor integrated circuit 10 has an SOI (Silicon On Insulator) structure, and is a source for an active silicon layer (SOI layer) further formed on a buried oxide film (BOX layer) 12 formed on a silicon substrate 11. Regions and drain regions are formed. With this structure, the parasitic capacitance between the source and drain regions and the substrate is reduced, and high speed and low power operation is possible. Further, since each element is completely separated by the BOX layer, latch-up does not occur, and a high-density layout is possible. On the other hand, in the SOI structure, since there is an insulating layer under the semiconductor thin film layer, when a high voltage is induced in the semiconductor thin film layer due to static electricity or the like, ESD (Electro-Static Damage) is likely to occur.

  The protection circuit 20 is a circuit that protects the internal circuit 30 from such electrostatic breakdown. The internal circuit 30 includes a plurality of transistors having at least a CMOS configuration and has a circuit configuration corresponding to an arbitrary desired function.

  When the internal circuit 30 is viewed in detail, the source region 31 and the drain region 33 formed by ion implantation into the SOI layer previously formed on the buried oxide film 12 and the source region 31 and the drain region 33 are sandwiched. As described above, one MOS type field effect is formed of a body region 35 formed in the SOI layer and a gate region 32 made of a polysilicon film disposed on the gate oxide film 34 stacked on the body region 35. A transistor is formed. The configuration may be a pMOS type or an nMOS type. The thickness D1 of the SOI layer is, for example, 0.05 μm. On both sides of the source region 31 and the drain region 33, an element isolation layer 13b is formed by subjecting a previously formed SOI layer to an oxidation heat treatment. The source region 31, the gate region 32, and the drain region 33 are connected to an external current path through a member such as an appropriate contact metal.

  When the protection circuit 20 is viewed in detail, the source region 21 and the drain region 23 formed by ion implantation into the SOI layer previously formed on the buried oxide film 12 and the source region 21 and the drain region 23 are sandwiched. Thus, one MOS type field effect is made up of a body region 25 formed in the SOI layer and a gate region 22 made of a polysilicon film disposed on the gate oxide film 24 stacked on the body region 25. A transistor is formed. The configuration may be a pMOS type or an nMOS type. For example, when the field effect transistor is an nMOS type, the source region 21 and the drain region 23 have the n type as the second conductivity type, and the body region 22 has the p type as the first conductivity type.

  The thickness D1 of the SOI layer is substantially the same across the protection circuit 20 and the internal circuit 30, and is, for example, 0.05 μm. On both sides of the source region 21 and the drain region 23, an element isolation layer 13a is formed by subjecting a previously formed SOI layer to an oxidation heat treatment. The source region 21, the gate region 22, and the drain region 23 are connected to the ground terminal GND or the power supply terminal VDD through a member such as an appropriate contact metal (see FIG. 2).

  As one feature of the present invention, a high concentration region 251 having a high concentration is formed in the body region 25. Thus, the internal circuit 30 is formed of FD-SOI, while the transistor of the protection circuit 20 is formed of PD-SOI. That is, the channel concentration is set higher at the bottom of the body region (SOI layer) of the transistor of the protection circuit 20, that is, closer to the buried oxide film (BOX layer) 12 when viewed from the intermediate position in the depth direction. Since the depletion layer in the body region is difficult to extend, a PD type transistor is formed.

  The MOS field effect transistor included in the protection circuit 20 and / or the internal circuit 30 of the semiconductor memory device according to the present invention may include an LDD (Lightly Doped Drain) region for suppressing the short channel effect. In this case, extension regions serving as LDD regions are provided in the SOI layer of each transistor in the vicinity of the source region and the drain region that are separated from the gate region by the gate region. With the structure including the LDD region, the current driving capability of the protection circuit 20 when a surge current is applied can be further increased.

  FIG. 2 shows an equivalent circuit of the semiconductor integrated circuit 10 shown in FIG. Here, the internal circuit 30 is connected to the ground terminal GND and the power supply terminal VDD, and the input voltage Vin input from the input terminal PAD is input via the protective resistor 40, and is usually included in the CMOS included in the internal circuit 30. Commonly connected to the gates of both transistors of the configuration. The protection circuit 20 includes two gate-grounded NMOS transistors 20a and 20b. The source of the NMOS transistor 20a is connected to the power supply terminal VDD, and the drain thereof is connected to the source of the NMOS transistor 20b. The drain of the NMOS transistor 20b is connected to the ground terminal GND.

  A connection point between the drain of the NMOS transistor 20a and the source of the NMOS transistor 20b is connected to the input terminal PAD and one end of the protective resistor 40, and is connected to the internal circuit 30 via the protective resistor 40. For example, when a negative surge current flows from the GND side, the NMOS transistors 20a and 20b included in the protection circuit 20 are turned on, and the surge current flows to the power supply terminal VDD side, thereby causing the surge current to the internal circuit 30. It is intended to prevent inflow. In this case, since the surge current is required to flow promptly, the NMOS transistors 20a and 20b are required to have a current driving capability and a current resistance characteristic sufficient to flow the assumed maximum surge current.

  3A to 3D show a manufacturing process of the semiconductor integrated circuit shown in FIG. Here, the buried oxide film 12 is formed on the silicon substrate 11 and the SOI layer 14 having a film thickness D1 of about 0.05 μm is formed on the silicon substrate 11 by a normal method for manufacturing a semiconductor integrated circuit having an SOI structure. Assume that an SOI wafer is prepared.

  As shown in FIG. 3A, the SOI wafer is subjected to a LOCOS (LOCal Oxidation of Silicon) process in which a silicon nitride film patterned by a photolithography process is formed and subjected to a heat treatment in an oxygen atmosphere. The regions of the protection circuit 20 and the internal circuit 30 separated by the regions 13a and 13b are formed. Furthermore, a gate oxide film 15 is formed on the SOI layer 14 through a process of thermal oxidation, and low concentration impurity ions are further implanted into the SOI layer 14 through the gate oxide film 15 to thereby form the body region. Is formed.

As shown in FIG. 3B, a resist having an opening 17 in which a portion corresponding to the source region, the body region, and the drain region of the protection circuit 20 is opened by a photolithography process on the SOI wafer on which the body region is formed. A film 16 is formed. Next, as shown in FIG. 3C, high-concentration impurity ions 18 are implanted through the gate oxide film 15. At this time, ion implantation is performed with high energy (for example, 40 kV), so that the average implantation distance Rp of ion implantation is set to come to the bottom of the SOI layer 14. As a result, the channel concentration at the bottom of the SOI layer 14 can be increased. The impurity ions 18 are n-type impurity ions if the transistor of the protection circuit 20 is a p-type MOS field effect transistor, and boron (B) or boron fluoride (for example) if the transistor is an n-type MOS field effect transistor. P-type impurity ions such as BF ₂ ). As a result, a high concentration region 251 is formed under the SOI layer 14 facing the opening 17.

  Next, a gate length of about 0.15 μm is obtained by depositing a polysilicon film on the gate oxide film 15 through a process such as a low-pressure CVD (Chemical Vapor Deposition) method by a normal method for manufacturing a semiconductor integrated circuit having an SOI structure. Then, using the gate electrode 22 and the resist film as a mask, impurity ions having a conductivity type opposite to that of the impurity ions 18 are implanted to form a source region and a drain region in a self-aligned manner. As a result, the structure shown in FIG. 3D is obtained.

  As described above, by adding the steps of photolithography and ion implantation to the process of forming the internal circuit 30 with a normal FD transistor, it is possible to easily convert only the transistor of the protection circuit 20 into a PD. The ion implantation into the bottom of the SOI layer 14 may be performed before the gate oxide film 15 is formed.

FIG. 4 shows the result of device simulation of the semiconductor integrated circuit of the present invention. In this simulation, when forming a body region by implanting BF ₂ as a channel impurity into an N-channel transistor constituting the protection circuit, the body region is formed as a normal channel with an ion implantation energy of 15 keV. This is a comparison with the case where the body region is formed as a high-concentration channel region by adjusting the energy in the range of 15 keV to 40 keV.

  As is apparent from this figure, it is understood that by increasing the channel concentration at the bottom of the SOI, the S value of the subthreshold is deteriorated, and the transistor performs PD operation. Here, the S value is expressed by S = Vg / log (Ids), and means the gate voltage Vg necessary for changing the drain current Ids by one digit. For example, if S = 60 mV / dec, it means that Ids is increased by one digit by increasing Vg by 60 mV.

  In the first embodiment described above, in the configuration of the protection circuit described above, holes are present in a region that is not a depletion layer because a high concentration region is formed at the bottom of the body region. For this reason, even if a surge current enters the support substrate, the parasitic transistor is not turned on unless holes in the body region are discharged to the source side (see FIG. 7). It is known that it takes about several milliseconds to discharge holes to the body region, and during this time, proper operation is obtained by the surface channel of the protection transistor, and there is no local operation of the back channel. Protection circuit characteristics can be obtained.

  In addition, the semiconductor integrated circuit of the present invention does not need to form two kinds of transistors constituting the internal circuit and the protection circuit from completely different processes, and can be manufactured only by adding a photolithography process and an ion implantation process. As a result, the number of steps is not significantly increased without increasing the difficulty in the process.

Since the protection transistor operates only when the surge current is released, the operation of the entire device is not affected even if the protection transistor is a PD type.
<Second embodiment>
FIG. 5 shows a second embodiment and shows a cross section of a semiconductor integrated circuit according to the present invention. Here, the internal circuit 30 similar to that in the first embodiment is formed by FD-SOI, while the thickness of the SOI layer of the protection circuit 20 is thicker than that of the internal circuit 30.

  The semiconductor integrated circuit 10 includes at least one protection circuit 20 and at least one internal circuit 30. The semiconductor integrated circuit 10 has an SOI (Silicon On Insulator) structure, and is a source for an active silicon layer (SOI layer) further formed on a buried oxide film (BOX layer) 12 formed on a silicon substrate 11. Regions and drain regions are formed. The protection circuit 20 is a circuit that protects the internal circuit 30 from electrostatic breakdown. The internal circuit 30 includes a plurality of transistors having at least a CMOS configuration and has a circuit configuration corresponding to an arbitrary desired function.

  The internal circuit 30 includes a source region 31 and a drain region 33 on the buried oxide film 12, a body region 35 formed in an SOI layer having a film thickness D1 so as to be sandwiched between the source region 31 and the drain region 33, and a body region The gate region 32 made of a polysilicon film disposed on the gate oxide film 34 stacked on the layer 35 constitutes one MOS field effect transistor. The protection circuit 20 includes a source region 21 and a drain region 23 on the buried oxide film 12, a body region 25 formed in an SOI layer having a film thickness D2 so as to be sandwiched between the source region 21 and the drain region 23, and a body region The gate region 22 made of a polysilicon film disposed on the gate oxide film 24 stacked on the gate electrode 25 constitutes one MOS field effect transistor.

  As another feature of the present invention, as shown in the figure, the film thickness D2 of the SOI layer of the transistor of the protection circuit 20 is thicker than the film thickness D1 of the SOI layer of the transistor of the internal circuit 30. . If the film thickness D1 is, for example, 0.05 μm, it is assumed that the film thickness D2 is 0.1 μm or more. With this structure, since the depletion layer of the transistor in the protection circuit 20 does not completely extend to the bottom of the SOI layer, the transistor performs a PD type operation.

  As a method for manufacturing a semiconductor integrated circuit in the second embodiment, a stacked film 19 of a silicon oxide film and a silicon nitride film is formed as an antioxidant film on an SOI wafer in the initial stage of manufacture. By performing photolithography and an etching process, the area other than the protection circuit 20 is etched to expose the SOI layer 14. Further, SOI layer adjustment oxidation is performed in which a sacrificial oxide film 141 is formed and etched on the exposed SOI layer 14. Thereafter, the silicon nitride film and the silicon oxide film are all removed by wet etching, so that the SOI layer other than the protection circuit unit 20 is formed thin and the SOI layer of the protection circuit 20 only is formed thick. Thereafter, the normal CMOS formation process of element isolation, gate oxidation, gate electrode formation, and LDD and source region and drain region formation is performed, thereby manufacturing the semiconductor integrated circuit 10 shown in FIG.

  In the second embodiment described above, in the configuration of the protection circuit described above, the region that is not a depletion layer remains because the body region is formed thick, and holes exist. For this reason, even if a surge current enters the support substrate, the parasitic transistor is not turned on unless holes in the body region are discharged to the source side (see FIG. 7). It is known that it takes about several milliseconds to discharge holes to the body region, and during this time, proper operation is obtained by the surface channel of the protection transistor, and there is no local operation of the back channel. Protection circuit characteristics can be obtained.

  Since the protection transistor operates only when the surge current is released, even if only the transistor of the protection circuit is a PD type, the operation of the entire semiconductor integrated circuit is not affected.

In the semiconductor integrated circuit in the above embodiment, the internal circuit of the CMOS device is formed by a fully depleted type (FD), while a protection transistor for protecting the internal circuit from an electrostatic breakdown phenomenon is a partially depleted type (PD). It is characterized by being formed by SOI. Therefore, the functions of the internal circuits constituting the semiconductor integrated circuit are not limited to those that fulfill a specific function, and may be various functions for general-purpose CPUs and mobile devices.
<Third embodiment>
FIG. 8 shows a third embodiment and shows a circuit configuration of a semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit 10 has an SOI (Silicon On Insulator) structure, and includes at least one protection circuit 20 and at least one internal circuit 30 as a functional circuit having a predetermined function.

  The internal circuit 30 is connected to the ground terminal GND and the power supply terminal VDD, and the input voltage Vin input from the input terminal PAD which is an external signal terminal is input via the protective resistor 40, and is usually included in the internal circuit 30. Commonly connected to the gates of both transistors of a CMOS configuration.

  The protection circuit 20 includes two gate-grounded NMOS transistors 20a and 20b. The source of the NMOS transistor 20a is connected to the power supply terminal VDD, and the drain thereof is connected to the source of the NMOS transistor 20b. The drain of the NMOS transistor 20b is connected to the ground terminal GND. A connection point between the drain of the NMOS transistor 20a and the source of the NMOS transistor 20b is connected to the input terminal PAD and one end of the protective resistor 40, and is connected to the internal circuit 30 via the protective resistor 40. For example, when a negative surge current flows from the GND side, the NMOS transistors 20a and 20b included in the protection circuit 20 are turned on, and the surge current flows to the power supply terminal VDD side, thereby causing the surge current to the internal circuit 30. It is intended to prevent inflow.

  Further, the semiconductor integrated circuit 10 includes a substrate line SUB electrically connected to a silicon substrate in the SOI wafer, and the substrate line SUB is electrically connected to the ground terminal GND. The ground terminal GND is connected to the gate and source of the protection transistor 20b and to the gate of the protection transistor 20a. The electrical connection between the silicon substrate and the substrate line SUB can be easily created by performing metal wiring through a substrate contact penetrating the buried oxide film.

  The NMOS transistors 20a and 20b are both NMOS type MOSFETs, but may be both PMOS transistors instead.

  FIG. 9 illustrates the operation in the circuit configuration shown in FIG. Referring to (a) of the figure, the protection transistor is floating with respect to the support substrate, that is, has a capacity C. In this case, when a reverse surge voltage is generated at the ground terminal GND for the protection operation of the protection transistor, the potential of the support substrate corresponding to the gate of the parasitic transistor on the back surface of the SOI structure is not the same as the source potential. The channel is turned on. On the other hand, referring to (b) of the figure, a state is shown in which the support substrate and the protection transistor are connected via the substrate line. In this case, even if a surge current is applied to the support substrate, the source of the protection transistor and the support substrate are at the same potential. Therefore, the parasitic transistor on the back surface of the SOI structure is not turned on, and the protection transistor is statically operated by the parasitic transistor operation. The electric breakdown phenomenon can be suppressed.

  10A to 10E show a method for manufacturing the protection transistor shown in FIG. The manufacturing method is characterized in that when an internal circuit of a semiconductor integrated circuit is formed on an SOI wafer, it is connected to a support substrate via a contact.

  The first step (see FIG. 10A) forms the protection transistor 20 on the SOI wafer using a known CMOS process. This figure shows a state where the side walls are formed. That is, the protection transistor 20 includes a body region 25 on the silicon substrate 11 and the buried oxide film 12 as a support substrate, and a gate region 22 disposed on the gate oxide film 24 stacked on the body region 25. LDD regions 41 and 42 arranged in a self-aligned manner with respect to the gate region 22 are formed.

  In the second step (see FIG. 10B), an opening 50 that penetrates the buried oxide film 12 is formed in a field region (see FIG. 10A) adjacent to the body region 25 by photolithography and etching techniques. Thereafter, a high concentration implant process for the opening 50, the source region 23, and the drain region 21 is performed using an appropriate resist mask. Thereby, the high concentration region 51 is also formed on the silicon substrate 11 in the opening 50 simultaneously with the formation of the source region 23 and the drain region 21. As the implanted ions in the implant process, for example, when the protection transistor 20 is a pMOS type, a p-type impurity is implanted at a high concentration.

  In the third step (see FIG. 10C), after activation annealing of impurities by RTA (Rapid Thermal Anneal) treatment, a silicide layer is formed on the surface of the gate region 22 of the protection transistor 20 using a known silicide formation technique. 45, a silicide layer 44 is formed on the surface of the source region, and a silicide layer 43 is formed on the surface of the drain region 21, respectively. At this time, if necessary, the silicide layer 52 is also formed on the surface of the high concentration region 51. The silicide layers 43, 44, 45 and 52 are made of a low resistance material.

  In the fourth step (see FIG. 10D), an intermediate insulating film 67 is deposited on the entire protection transistor 20, and planarization is performed using a CMP (Chemical Mechanical Polishing) technique or the like.

  In the fifth step (see FIG. 1E), contact formation and metal wiring are finally performed. That is, the silicide layer 43 of the protection transistor 20 is connected to the metal wiring 65 through the contact 61. The silicide layer 45 is connected to the metal wiring 66 through the contact 64, the silicide layer 44 is connected to the metal wiring 66 through the contact 62, and the silicide layer 52 is connected to the metal wiring 66 through the contact 63. Thereby, the circuit configuration shown in FIG. 8 is realized.

  In the third embodiment described above, it becomes possible to connect the source of the protection transistor of the SOI structure and the supporting substrate without adding an additional heat treatment for the substrate contact to the normal CMOS process. Since there is no additional heat treatment step, the transistor characteristics are not affected at all, and desired protection operation characteristics can be obtained in which only the back channel is not turned on.

1 is a block diagram showing a cross section of a semiconductor integrated circuit according to the present invention according to a first embodiment. FIG. FIG. 2 is a circuit diagram showing an equivalent circuit of the semiconductor integrated circuit shown in FIG. 1. FIG. 2 is a diagram showing a manufacturing process of the semiconductor integrated circuit shown in FIG. 1. FIG. 2 is a diagram showing a manufacturing process of the semiconductor integrated circuit shown in FIG. 1. FIG. 2 is a diagram showing a manufacturing process of the semiconductor integrated circuit shown in FIG. 1. FIG. 2 is a diagram showing a manufacturing process of the semiconductor integrated circuit shown in FIG. 1. It is a figure which shows the result of having performed device simulation about the semiconductor integrated circuit of this invention. It is a block diagram which shows the 2nd Example and shows the cross section of the semiconductor integrated circuit by this invention. FIG. 6 is a diagram showing a manufacturing process of the semiconductor integrated circuit shown in FIG. 5. It is explanatory drawing explaining the mode of the surface channel and back surface channel which are formed. It is a block diagram which shows the 3rd Example and shows the equivalent circuit of the semiconductor integrated circuit by this invention. It is explanatory drawing explaining the operation | movement in the circuit structure shown by FIG. FIG. 9 is a diagram showing a manufacturing process of the semiconductor integrated circuit shown in FIG. 8. FIG. 9 is a diagram showing a manufacturing process of the semiconductor integrated circuit shown in FIG. 8. FIG. 9 is a diagram showing a manufacturing process of the semiconductor integrated circuit shown in FIG. 8. FIG. 9 is a diagram showing a manufacturing process of the semiconductor integrated circuit shown in FIG. 8. FIG. 9 is a diagram showing a manufacturing process of the semiconductor integrated circuit shown in FIG. 8.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor integrated circuit 11 Silicon substrate 12 Embedded oxide film 13a, 13b Element isolation layer 14 SOI layer 15, 24, 34, Gate oxide film 16 Resist film 17 Opening 18 Implanted ion 19 Stacked film 20 Protection circuit 20a, 20b NMOS transistor 21 , 31 Source region 22, 32 Gate region 23, 33 Drain region 24, 34 Gate oxide film 25, 35 Body region 30 Internal circuit 40 Protection resistance 43-45, 52 Silicide layer 50 Opening 51 High concentration region 61-64 Contact 65 , 66 Metal wiring 67 Intermediate insulating film 251 High concentration region D1, D2 Film thickness GND Ground terminal PAD Input terminal VDD Power supply terminal

Claims (9)

A semiconductor integrated circuit including a plurality of MOSFETs each including a part of an SOI layer formed on a buried oxide film, wherein at least one of the plurality of MOSFETs operates as an ESD protection transistor;
The ESD protection transistor is:
A gate region formed on the SOI layer;
A first conductivity type region having a first conductivity type and formed between the gate region and the buried oxide film in the SOI layer;
Two second conductivity type regions having a second conductivity type and facing each other across the first conductivity type region in the SOI layer,
The semiconductor integrated circuit according to claim 1, wherein the first conductivity type region has a region having a high first conductivity type concentration closer to the buried oxide film than an intermediate position in the depth direction.   Instead of adjusting the distribution of the first conductivity type concentration, the film thickness of the SOI layer in the ESD protection transistor is larger than the film thickness of the SOI layer in other transistors. The semiconductor integrated circuit according to claim 1.   3. The semiconductor integrated circuit according to claim 1, wherein the SOI layer of the ESD protection transistor has an LDD region in contact with the first conductivity type region and the second conductivity type region. A manufacturing method for manufacturing the semiconductor integrated circuit according to claim 1,
Forming a resist film having an opening corresponding to at least a body region of the ESD protection transistor on the SOI layer;
A concentration adjusting step of adjusting the concentration of the first conductivity type by changing the energy intensity while implanting impurity ions corresponding to the first conductivity type through the opening;
The manufacturing method characterized by including. A manufacturing method for manufacturing the semiconductor integrated circuit according to claim 2,
Forming an antioxidant film having an opening corresponding to other transistors except the ESD protection transistor on the SOI layer; and
A film thickness adjusting step of adjusting the film thickness of the SOI layer in the ESD protection transistor by performing oxidation and etching treatment on the SOI layer exposed by the opening;
The manufacturing method characterized by including. A semiconductor integrated circuit comprising a plurality of MOSFETs on an SOI wafer including a support substrate, and including a functional circuit and an ESD protection circuit, each of which is connected to an external signal terminal, a power supply terminal, and a ground terminal;
The ESD protection circuit is
A first protection MOSFET comprising a gate connected to the ground terminal, a drain connected to the external signal terminal, and a source connected to the ground terminal;
A second protection MOSFET having the same conductivity type as the first protection MOSFET and comprising a gate connected to the ground terminal, a drain connected to the power supply terminal, and a source connected to the external signal terminal;
A substrate wire connecting the ground terminal and the support substrate;
A semiconductor integrated circuit comprising:   The substrate line is connected to the ground terminal and is connected to the metal substrate formed on the surface of the SOI wafer and to the metal substrate, and is extended to the inside of the SOI wafer and connected to the support substrate. The semiconductor integrated circuit according to claim 6, further comprising a contact.   8. The semiconductor integrated circuit according to claim 7, wherein the contact is connected to the support substrate through a high concentration region formed between the support substrate and the support substrate. A manufacturing method for manufacturing the protection MOSFET according to claim 6,
A gate region forming step of forming a gate region on the SOI wafer;
An opening forming step of forming an opening reaching the support substrate in a field region around the gate region;
A region forming step of forming a high concentration region on the support substrate exposed through the opening while performing drain implantation and source region under the gate region by performing ion implantation processing;
An ion activation step of simultaneously performing ion activation treatment on each formed region;
A substrate line forming step for forming a substrate line comprising a plurality of contacts each reaching each formed region and a metal wiring connecting the contacts;
The manufacturing method characterized by including.

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