US20150079774A1 - Self-Alignment for using Two or More Layers and Methods of Forming Same - Google Patents
Self-Alignment for using Two or More Layers and Methods of Forming Same Download PDFInfo
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- US20150079774A1 US20150079774A1 US14/030,601 US201314030601A US2015079774A1 US 20150079774 A1 US20150079774 A1 US 20150079774A1 US 201314030601 A US201314030601 A US 201314030601A US 2015079774 A1 US2015079774 A1 US 2015079774A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
Definitions
- Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.
- the semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area.
- various electronic components e.g., transistors, diodes, resistors, capacitors, etc.
- conductive features connecting to layers above and below may become shorted if the conductive feature is misaligned. Generally, this occurs when the etching process through the layer is misaligned such that the conductive feature exposes portions of an adjacent conductive feature on the layer below.
- FIGS. 1A through 1N illustrate cross-sectional views of intermediate stages in the manufacturing of a semiconductor device in accordance with an embodiment
- FIGS. 2A through 2G illustrate cross-sectional views of intermediate stages in the manufacturing of a semiconductor device in accordance with an embodiment
- FIGS. 3A through 3L illustrate cross-sectional views of intermediate stages in the manufacturing of a semiconductor device in accordance with an embodiment
- FIGS. 4A through 4N illustrate cross-sectional views of intermediate stages in the manufacturing of a semiconductor device in accordance with an embodiment
- FIGS. 5A through 5T illustrate cross-sectional views of intermediate stages in the manufacturing of a semiconductor device in accordance with an embodiment
- FIGS. 6A through 6X illustrate cross-sectional views of intermediate stages in the manufacturing of a semiconductor device in accordance with an embodiment.
- Embodiments will be described with respect to a specific context, namely a self-alignment scheme between two layers. Other embodiments may also be applied, however, to align three or more layers.
- FIGS. 1A through 1N illustrate cross-sectional views of intermediate stages in the manufacturing of a semiconductor device in accordance with an embodiment.
- FIG. 1A illustrates a semiconductor device includes a substrate 102 , gates 104 , hard masks 106 on the gates 104 , gate spacers 108 on the sidewalls of the gates 104 , and an inter-layer dielectric (ILD) 110 over the gates 104 , the hard masks 106 , and the gate spacers 108 .
- the substrate 102 may be made of a semiconductor material such as silicon, germanium, diamond, or the like.
- the substrate 102 may be a silicon-on-insulator (SOI) substrate.
- SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof.
- the substrate 102 may include active and passive devices (not shown in FIG. 1A ). As one of ordinary skill in the art will recognize, a wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the semiconductor device. The devices may be formed using any suitable methods. Only a portion of the substrate 102 is illustrated in the figures, as this is sufficient to fully describe the illustrative embodiments.
- the substrate 102 may also include metallization layers (not shown).
- the metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry.
- the metallization layers may be formed of alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) and may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like).
- the gates 104 are formed over the substrate 102 .
- the gates 104 may include a gate dielectric layer (not shown), a hard mask 106 , and gate spacers 108 .
- the gate dielectric layer may be formed by thermal oxidation, chemical vapor deposition (CVD), sputtering, or any other methods known and used in the art for forming a gate dielectric.
- the gate dielectric layer includes dielectric materials having a high dielectric constant (k value), for example, greater than 3.9.
- the gate dielectric materials include silicon nitrides, oxynitrides, metal oxides such as HfO 2 , HfZrO x , HfSiO x , HfTiO x , HfAlO x , the like, or combinations and multi-layers thereof.
- the gate electrode layer (not shown) may be formed over the gate dielectric layer.
- the gate electrode layer may comprise a conductive material and may be selected from a group comprising polycrystalline-silicon (poly-Si), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals.
- amorphous silicon is deposited and recrystallized to create polycrystalline silicon (poly-silicon).
- the gate electrode layer may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques known and used in the art for depositing conductive materials.
- the top surface of the gate electrode layer usually has a non-planar top surface, and may be planarized prior to patterning of the gate electrode layer or gate etch. Ions may or may not be introduced into the gate electrode layer at this point. Ions may be introduced, for example, by ion implantation techniques.
- a hard mask layer (not shown) is formed over the gate electrode layer.
- the hard mask layer may be made of SiN, SiON, SiO 2 the like, or a combination thereof.
- the hard mask layer is then patterned.
- the patterning of the hard mask layer may be accomplished by depositing mask material (not shown) such as photoresist over the hard mask layer.
- the mask material is then patterned and the hard mask layer is etched in accordance with the pattern to form hard masks 106 .
- the gate electrode layer and the gate dielectric layer may be patterned to form the gates 104 .
- the gate patterning process may be accomplished by using the hard mask 106 as a pattern and etching the gate electrode layer and the gate dielectric layer to form the gates 104 .
- the gate spacers 108 are formed on opposite sides of the gates 104 .
- the gate spacers 108 are formed by blanket depositing a spacer layer (not shown) on the previously formed gates 104 and hard masks 106 .
- the gate spacers 108 include a spacer liner (not shown).
- the spacer liner may be made of SiN, SiC, SiGe, oxynitride, oxide, the like, or a combination thereof.
- the spacer layer may comprise SiN, oxynitride, SiC, SiON, oxide, combinations thereof, or the like and may be formed by methods utilized to form such a layer, such as CVD, plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), atomic layer deposition (ALD), sputter, the like, or a combination thereof.
- the gate spacers 108 are then patterned, for example, by an anisotropic etch to remove the spacer layer from top surfaces 106 A of the hard masks 106 .
- the structure 104 is not limited to a gate.
- the structure 104 is a conductive line 104 that is to be aligned and coupled with another conductive feature by the subsequently formed conductive feature 126 (see FIG. 1N ).
- the ILD 110 is formed over these structures and the substrate 102 .
- the ILD 110 may be formed of oxides such as silicon oxide, borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer such as polyimide, the like, or a combination thereof.
- the low-k dielectric materials may have k values lower than 3.9.
- the ILD 110 may be deposited by CVD, PVD, ALD, a spin-on-dielectric (SOD) process, the like, or a combination thereof.
- the ILD 24 is formed directly on a top surface 102 A of the substrate 102 .
- the ILD 110 is formed on intermediate layers and/or structures (not shown) which are on substrate 102 .
- the ILD 110 is planarized by a chemical mechanical polish (CMP) process or an etching process to form a substantially planar top surface 110 A.
- CMP chemical mechanical polish
- FIG. 1B illustrates the formation of alignment structures 112 and alignment spacers 114 on the top surface 110 A of the ILD 110 .
- the alignment structures 112 and the spacers 114 may be formed of similar materials and by similar processes as the gates 104 and the spacers 108 , respectively, and the descriptions will not be repeated herein, although the materials and processes need not be the same.
- each of the alignment structures 112 is aligned with a gate 104 in the layer below the respective alignment structure 112 .
- the alignment spacers 114 are formed to have a width W 1 in a range from about 10% to about 40% of a minimum space between adjacent alignment structures 112 .
- FIG. 1C illustrates the formation of an ILD 116 and a patterning layer 118 over the ILD 110 .
- the ILD 116 is formed over the alignment structures 112 and the alignment spacers 114 and on the ILD 110 .
- the ILD 116 may be formed of similar materials and by similar processes as the ILD 110 and the description will not be repeated herein, although the ILD 116 and the ILD 110 need not be the same.
- the patterning layer 118 is formed and patterned over the ILD 116 .
- the patterning layer 118 is formed of a photoresist material, such as a deep ultraviolet (DUV) photoresist, an extreme ultraviolet (EUV) photoresist, an electron beam direct write (EBDW) photoresist, or the like, and is deposited on the surface of the ILD 116 by using a spin-on process to place the patterning layer 118 .
- DUV deep ultraviolet
- EUV extreme ultraviolet
- EBDW electron beam direct write
- any other suitable material or method of forming or placing a photoresist material may alternatively be utilized.
- the patterning layer 118 is exposed to energy, e.g.
- the patterning layer 118 is then developed, and portions of the patterning layer 118 are removed forming openings 120 A, 120 B, and 120 C, exposing a top surface 116 A of the ILD 116 through the openings 120 A, 120 B, and 120 C.
- the patterning layer 118 is a hard mask.
- the patterning layer 118 is formed of and by similar processes as the hard masks 106 , and the details will not be repeated herein, although the patterning layer 118 and the hard masks 106 need not be the same.
- FIG. 1D illustrates the formation of the openings 120 A, 120 B, and 120 C through the ILD 116 and partially through the ILD 110 .
- a portion of the opening 120 A extends over a top surface 112 A of the alignment structure 112 , the alignment structure 112 and the alignment spacers 114 self-align the opening 120 between a pair of the adjacent gates 104 .
- the opening 120 B is self-aligned by another spacer 114 to be between a pair of adjacent gates 104 .
- the opening 120 C does not require an alignment by an alignment structure 112 or alignment spacer 114 .
- the openings 120 A, 120 B, and 120 C may be formed by using acceptable etching techniques. In an embodiment, the openings 120 A, 120 B, and 120 C are formed by an anisotropic dry etch.
- FIG. 1E illustrates the removal of the patterning layer 118 to expose the top surface 116 A of the ILD 116 .
- the patterning layer 118 may be removed by a CMP process, an etch process, the like, or a combination thereof.
- FIG. 1F illustrates forming the openings 120 A, 120 B, and 120 C through the remaining portion of the ILD 110 to expose portions of the top surface 102 A of the substrate 102 .
- the opening 120 A is formed between a pair of alignment structures 112 with their respective alignment spacers 114 and a pair of gates 104 with their gate spacers 108 .
- the opening 120 B is formed between an alignment structure 112 with its respective alignment spacer 114 and a patterned portion of ILD 116 and between a pair of gates 104 with their respective gate spacers 108 .
- the opening 120 C is formed between patterned portions of ILD 116 and between a gate 104 with its respective gate spacer 108 and a portion of patterned ILD 110 .
- the openings 120 A, 120 B, and 120 C are extended through ILD 110 by using an anisotropic dry etch.
- FIG. 1G illustrates the formation of a conductive layer 122 in the openings 120 A, 120 B, and 120 C contacting the top surface 102 A of the substrate 102 and along top surfaces 116 A of the ILD 116 , top surfaces 112 A of the alignment structures 112 , and alignment spacers 114 .
- the conductive layer 122 includes a barrier layer (not shown). The barrier layer helps to block diffusion of the subsequently formed conductive layer 122 into adjacent dielectric materials such as ILD 110 .
- the barrier layer may be made of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, cobalt, cobalt oxide, cobalt nitride, nickel, nickel oxide, nickel nitride, silicon carbide, oxygen doped silicon carbide, nitrogen doped silicon carbide, silicon nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, a polymer such as polyimide, polybenzoxazole (PBO) the like, or a combination thereof.
- the barrier layer may be formed by CVD, PVD, plasma enhanced CVD (PECVD), ALD, SOD, the like, or a combination thereof. In some embodiments, the barrier layer is omitted.
- the conductive layer 122 may be made of tungsten, copper, aluminum, the like, or a combination thereof.
- the conductive layer 122 may be formed through a deposition process such as electrochemical plating, PVD, CVD, the like, or a combination thereof. In some embodiments, the conductive layer 122 is formed on a copper seed layer.
- FIG. 1H illustrates the recessing of the conductive layer 122 to form conductive features 122 A, 122 B, and 122 C in the openings 120 A, 120 B, and 120 C, respectively.
- the top surfaces 122 A 1 , 122 B 1 , and 122 C 1 of the conductive features 122 A, 122 B, and 122 C, respectively is below the top surface 112 A of the alignment structure 112 and the top surface 116 A of the ILD 116 after the recessing.
- the recessing is performed by a dry etch process with a plasma source and an etchant gas such as CF 4 , SF 6 , the like, or a combination thereof.
- FIG. 1I illustrates the formation of openings 124 by removing the alignment structures 112 from between the alignment spacers 114 to expose the top surface 110 A of the ILD 110 .
- the alignment structures 112 may be removed by an etch process, such as a wet etch process, that is selective to the alignment structures 112 .
- FIG. 1J illustrates extending the openings 124 through the ILD 110 to expose the top surfaces 106 A of the hard masks 106 .
- the openings 124 may be extended through the ILD 110 by using acceptable etching techniques such as, for example, an anisotropic dry etch.
- FIG. 1K illustrates extending the openings 124 through the hard masks 106 to expose top surfaces 104 A of the gates 104 .
- the openings 124 may be extended through the hard masks 106 by using acceptable etching techniques such as, for example, an anisotropic dry etch.
- FIG. 1L illustrates the formation of a conductive layer 126 in the openings 124 contacting the top surface 104 A of the gates 104 and over the conductive features 122 A, 122 B, and 122 C.
- the conductive layer 126 may be formed of similar materials and by similar processes as the conductive layer 122 discussed above and the description will not be repeated herein, although the conductive layers 122 and 126 need not be the same.
- FIG. 1M illustrates the recessing of the conductive layer 126 to form conductive features 126 A and 126 B in the openings 124 and the recessing of the conductive features 122 A, 122 B, and 122 C.
- the top surfaces 126 A 1 and 126 B 1 of the conductive features 126 A and 126 B, respectively, and the top surfaces 122 A 1 , 122 B 1 , and 122 C 1 of the conductive features 122 A, 122 B, and 122 C, respectively are substantially coplanar after the recessing.
- the recessing is performed by a dry etch process that etches conductive layer 126 conductive features 122 A, 122 B, and 122 C with a plasma source and an etchant gas such as CF 4 , SF 6 , the like, or a combination thereof.
- FIG. 1N illustrates the removal of the alignment spacers 114 and the remaining portions of ILD 116 and the planarization of the ILD 110 , conductive features 126 A, 126 B, 122 A, 122 B, and 122 C.
- the planarization process may be a CMP process, an etch process, the like, or a combination thereof.
- the top surfaces 126 A 1 and 126 B 1 of the conductive features 126 A and 126 B, respectively, the top surfaces 122 A 1 , 122 B 1 , and 122 C 1 of the conductive features 122 A, 122 B, and 122 C, respectively, and the top surface 110 A of the ILD 110 are substantially coplanar after the planarization process.
- the conductive features 126 are formed to have a width W 2 in a range from about 50% to about 150% of a width of the gate 104 below the respective conductive feature 126 .
- the conductive features 122 are formed to have a width W 3 in a range from about 50% to about 150% of a width between adjacent gates 104 .
- the conductive features 126 A and 126 B are used as contacts to couple the gates 104 to layers above the ILD 110 and the conductive features 122 A, 122 B, and 122 C are used as contacts to couple the substrate 102 and devices and layers (e.g.
- the conductive features 126 and 126 B are used to couple the conductive line 104 to another conductive feature above the ILD 110 and the conductive features 122 A, 122 B, and 122 C are used as contacts to couple the substrate 102 and devices and metallization layers formed therein to layers above ILD 110 .
- the ILD layer is able to be kept clean and free from residue from other spacers and/or hard masks as the alignment structures are formed in ILD layer above the ILD layer containing the gates. Further, the process described above allows line patterns (e.g. alignment structure 112 ) to self-align to another line pattern (
- FIGS. 2A through 2G illustrate cross-sectional views of intermediate stages in the manufacturing of a semiconductor device in accordance with an embodiment. Details regarding this embodiment that are similar to those for the previously described embodiment will not be repeated herein.
- FIGS. 2A and 2B are similar to FIGS. 1A and 1B , respectively, and the descriptions will not be repeated herein.
- FIG. 2C is similar to FIG. 1C except that in FIG. 2 C, the openings 120 A and 120 B do not have portion of patterning layer 118 between them.
- FIG. 2D illustrates the formation of the openings 120 A, 120 B, and 120 C through the ILD 116 and partially through the ILD 110 .
- FIG. 2E illustrates the removal of the patterning layer 118 to expose the top surface 116 A of the ILD 116 .
- the patterning layer 118 may be removed by a CMP process, an etch process, the like, or a combination thereof.
- FIG. 2F illustrates forming the openings 120 A, 120 B, and 120 C through the remaining portion of the ILD 110 to expose portions of the top surface 102 A of the substrate 102 .
- the semiconductor device in FIG. 2F is similar to the semiconductor device in FIG. 1F and the description will not be repeated herein.
- the openings 120 A and 120 B ended up the same as the embodiment illustrated in FIG. 1F because the alignment structure 112 and alignment spacer 114 separate the openings 120 A and 120 B in both embodiments.
- FIG. 2G illustrates the semiconductor device with conductive features 126 A, 126 B, 122 A, 122 B, and 122 C similar to those described above in FIG. 1N .
- the processing steps between FIGS. 2F and 2G are similar to those illustrate in FIGS. 1G through 1N and are not repeated herein.
- FIGS. 3A through 3L illustrate cross-sectional views of intermediate stages in the manufacturing of a semiconductor device in accordance with an embodiment. Details regarding this embodiment that are similar to those for the previously described embodiment will not be repeated herein.
- FIGS. 3A and 3B are similar to FIGS. 1A and 1B , respectively, and the descriptions will not be repeated herein.
- FIG. 3C is similar to FIG. 1C except that in FIG. 3C , the openings 120 B and 120 C of FIG. 1C do not have a portion of patterning layer 118 between them forming a single opening 120 D in FIG. 2C .
- FIG. 3D illustrates the formation of the openings 120 A and 120 D through the ILD 116 and partially through the ILD 110 .
- the opening 120 D includes the entire top surface 106 A of a hard mask 106 on a gate 104 as there was no portion of ILD 116 on the hard mask 106 .
- FIG. 3E illustrates the removal of the patterning layer 118 and forming the openings 120 A and 120 D through the remaining portion of the ILD 110 to expose portions of the top surface 102 A of the substrate 102 .
- the opening 120 D includes a gate 104 , hard mask 106 , and gate spacers 108 along a bottom of the opening 120 D.
- FIG. 3F illustrates the formation of a conductive layer 122 in the openings 120 A and 120 D contacting the top surface 102 A of the substrate 102 and along the top surface 106 A of a hard mask 106 , gate spacers 108 , top surfaces 116 A of the ILD 116 , top surfaces 112 A of the alignment structures 112 , and alignment spacers 114 .
- FIG. 3G illustrates the recessing of the conductive layer 122 to form conductive features 122 A and 122 D in the openings 120 A and 120 D, respectively.
- the conductive feature 122 D coupled to the substrate 102 on at least two sides of a gate 104 .
- a single gate 104 is embedded in the conductive feature 122 D.
- more than one gate 104 is embedded in the conductive feature 122 D.
- FIG. 3H illustrates the formation of openings 124 by removing the alignment structures 112 from between the alignment spacers 114 and extending the openings 124 through the ILD 110 to expose the top surfaces 106 A of the hard masks 106 .
- the top surfaces 122 A 1 and 122 D 1 are higher than the top surface 116 A of the ILD 116 .
- FIG. 3I illustrates extending the openings 124 through the hard masks 106 to expose top surfaces 104 A of the gates 104 .
- FIG. 3J illustrates the formation of the conductive layer 126 in the openings 124 contacting the top surface 104 A of the gates 104 and over the alignment spacers 114 and the conductive features 122 A and 122 D.
- the conductive layer 126 may be formed of similar materials and by similar processes as the conductive layer 122 discussed above and the description will not be repeated herein, although the conductive layers 122 and 126 need not be the same.
- FIG. 3K illustrates the recessing of the conductive layer 126 to form conductive features 126 A and 126 B in the openings 124 and the recessing of the conductive features 122 A, 122 B, and 122 C.
- the top surfaces 126 A 1 and 126 B 1 of the conductive features 126 A and 126 B, respectively, and the top surfaces 122 A 1 and 122 D 1 of the conductive features 122 A and 122 D, respectively, are substantially coplanar after the recessing.
- FIG. 3L illustrates the removal of the alignment spacers 114 and the remaining portions of ILD 116 and the planarization of the ILD 110 , conductive features 126 A, 126 B, 122 A, and 122 D.
- the planarization process may be a CMP process, an etch process, the like, or a combination thereof.
- the top surfaces 126 A 1 and 126 B 1 of the conductive features 126 A and 126 B, respectively, the top surfaces 122 A 1 and 122 D 1 of the conductive features 122 A and 122 D, respectively, and the top surface 110 A of the ILD 110 are substantially coplanar after the planarization process.
- the conductive features 126 A and 126 B may be used as contacts to couple the gates 104 to layers above the ILD 110 and the conductive features 122 A and 122 D may be used as contacts to couple the substrate 102 and devices and metallization layers formed therein to layers above ILD 110 .
- the conductive feature 122 D is used to couple devices that have higher current requirements than the devices coupled to the conductive feature 122 A.
- FIGS. 4A through 4N illustrate cross-sectional views of intermediate stages in the manufacturing of a semiconductor device in accordance with an embodiment. Details regarding this embodiment that are similar to those for the previously described embodiment will not be repeated herein.
- FIG. 4A illustrates a semiconductor device includes a substrate 302 , gates 304 , hard masks 306 on the gates 304 , gate spacers 308 on the sidewalls of the gates 304 , and an ILD 310 over the gates 304 , the hard masks 306 , and the gate spacers 308 .
- the substrate 302 , gates 304 , hard masks 306 , gate spacers 308 , and ILD 310 may be formed of similar materials and similar processes as the substrate 102 , gates 104 , hard masks 106 , gate spacers 108 , and ILD 110 described above and the descriptions will not be repeated herein. However, the materials and processes of the two embodiments of the semiconductor device need not be the same.
- FIG. 4B illustrates the formation of alignment structures 312 and alignment spacers 314 on the top surface 310 A of the ILD 310 .
- the alignment structures 312 and the alignment spacers 314 may be formed of similar materials and by similar processes as the alignment structures 112 and the alignment spacers 114 , respectively, described above and the descriptions will not be repeated herein, although the materials and processes need not be the same.
- each of the alignment structures 312 is aligned between a pair of adjacent gates 304 in the layer below the respective alignment structure 312 .
- FIG. 4C illustrates the formation of an ILD 316 and a patterning layer 318 over the ILD 310 .
- the ILD 316 is formed over the alignment structures 312 and the alignment spacers 314 and on the ILD 310 .
- the ILD 316 may be formed of similar materials and by similar processes as the ILD 116 described above and the description will not be repeated herein, although the ILD 316 and the ILD 116 need not be the same.
- the patterning layer 318 is formed and patterned over the ILD 316 .
- the patterning layer 318 may be formed of similar materials and patterned by similar processes as the patterning layer 118 described above and the description will not be repeated herein.
- the patterning layer 318 is patterned to form openings 320 exposing portions of the top surface 316 A of the ILD 316 . In some embodiments, each of the openings 320 is aligned directly over a gate 304 .
- FIG. 4D illustrates extending the openings 320 through the ILD 316 and partially through the ILD 310 to expose portions of top surfaces 306 A of the hard masks 306 .
- the openings 320 may be formed by using acceptable etching techniques such as, for example, an anisotropic dry etch.
- FIG. 4E illustrates the removal of the patterning layer 318 to expose the top surface 316 A of the ILD 316 .
- the patterning layer 318 may be removed by a CMP process, an etch process, the like, or a combination thereof.
- FIG. 4F illustrate the thinning of the ILD 316 to expose top surfaces 312 A of the alignments structures 312 .
- the thinning process may be by a CMP process, an etch process, the like, or a combination thereof.
- FIG. 4G illustrates extending the openings 320 through the hard masks 306 to expose top surfaces 304 A of the gates 304 .
- the openings 320 may be extended through the hard masks 306 by using acceptable etching techniques such as, for example, an anisotropic dry etch.
- FIG. 4H illustrates the formation of a conductive layer 322 in the openings 320 contacting the top surface 304 A of the gates 304 and along the top surfaces 312 A of the alignment structures 312 , the alignment spacers 314 , and the ILD 36 .
- the conductive layer 322 may be formed of similar materials and by similar processes as the conductive layer 122 discussed above and the description will not be repeated herein, although the conductive layers 322 and 122 need not be the same.
- FIG. 4I illustrates the recessing of the conductive layer 322 to form conductive features 322 in the openings 320 .
- the top surfaces 322 A of the conductive features 322 are lower than the top surfaces 312 A of the alignment structures 312 and the top surface 316 A of the ILD 316 .
- This recessing process may be similar to the recessing process of conductive layer 122 described above and the description will not be repeated herein, although the recessing processes need not be the same.
- FIG. 4J illustrates the formation of openings 324 by removing the alignment structures 312 from between the alignment spacers 314 to expose the top surface 310 A of the ILD 310 .
- the alignment structures 312 may be removed by a wet etch process that is selective to the alignment structures 312 .
- FIG. 4K illustrates extending the openings 324 through the ILD 310 to expose portions of the top surface 302 A of the substrate 302 .
- the openings 324 may be extended through the ILD 310 by using acceptable photolithography and etching techniques such as, for example, an anisotropic dry etch.
- FIG. 4L illustrates the formation of a conductive layer 326 in the openings 324 contacting the top surface 302 A of the substrate 302 and over the conductive features 322 .
- the conductive layer 326 may be formed of similar materials and by similar processes as the conductive layer 122 discussed above and the description will not be repeated herein.
- FIG. 4M illustrates the recessing of the conductive layer 326 to form conductive features 326 in the openings 324 .
- the top surfaces 326 A of the conductive features 326 and the top surfaces 322 A the conductive features 322 are substantially coplanar after the recessing.
- This recessing process may be similar to the recessing process of conductive layer 122 described above and the description will not be repeated herein, although the recessing processes need not be the same.
- FIG. 4N illustrates the removal of the alignment spacers 314 and the remaining portions of ILD 116 and the planarization of the ILD 310 and the conductive features 322 and 326 .
- the planarization process may be a CMP process, an etch process, the like, or a combination thereof.
- the top surfaces 326 A of the conductive features 326 , the top surfaces 322 A of the conductive features 322 , and the top surface 310 A of the ILD 310 are substantially coplanar after the planarization process.
- the conductive features 322 may be used as contacts to couple the gates 304 to layers above the ILD 310 and the conductive features 326 may be used as contacts to couple the substrate 302 and devices and metallization layers formed therein to layers above ILD 310 .
- FIGS. 5A through 5T illustrate cross-sectional views of intermediate stages in the manufacturing of a semiconductor device in accordance with an embodiment. Details regarding this embodiment that are similar to those for the previously described embodiment will not be repeated herein.
- FIG. 5A illustrates a semiconductor device includes a substrate 402 , gates 404 , hard masks 406 on the gates 404 , gate spacers 408 on the sidewalls of the gates 404 , and an ILD 410 over the gates 404 , the hard masks 406 , and the gate spacers 408 .
- the semiconductor device further includes an anti-reflective coating (ARC) layer 412 , a hardmask layer 414 , an ARC layer 416 , a dielectric layer 418 , an ARC layer 420 , a hardmask layer 422 , an ARC layer 424 , a dielectric layer 426 , a hardmask layer 428 , and a photoresist 430 .
- ARC anti-reflective coating
- the substrate 402 , gates 404 , hard masks 406 , gate spacers 408 , and ILD 410 may be formed of similar materials and similar processes as the substrate 102 , gates 104 , hard masks 106 , gate spacers 108 , and ILD 110 described above and the descriptions will not be repeated herein. However, the materials and processes of the two embodiments of the semiconductor device need not be the same.
- the ARC layer 412 is formed over the ILD 410 .
- the ARC layer 412 prevents radiation in a subsequent photolithographic process to reflect off layers below and interfering with the exposure process. Such interference can increase the critical dimension of the photolithography process.
- the ARC layer 412 may comprise SiON, a polymer, the like, or a combination thereof and may be formed by CVD, a spin-on process, the like, or a combination thereof. In an embodiment the ARC layer 412 is formed to a thickness of between about 200 ⁇ and about 400 ⁇ .
- the hardmask layer 414 is formed over the ARC layer 412 .
- the hardmask layer 414 may be a masking material such as poly-silicon, silicon nitride, the like, or a combination thereof may be formed using a process such as plasma enhanced chemical vapor deposition (PECVD).
- PECVD plasma enhanced chemical vapor deposition
- any other suitable hardmask material, such as silicon oxide, and any other process of formation, such as CVD may alternatively be utilized.
- the hardmask layer 414 is formed to a thickness of between about 200 ⁇ and about 400 ⁇ .
- the ARC layer 416 is formed over the hardmask layer 414 .
- the ARC layer 416 may be formed of similar materials and by similar processes as the ARC layer 412 described above and the description is not repeated herein, although the first and ARC layers 412 and 416 need not be the same.
- the ARC layer 416 is formed to a thickness of from about 200 ⁇ to about 400 ⁇ .
- the dielectric layer 418 is formed over the ARC layer 416 .
- the dielectric layer 418 may be formed of oxides such as silicon oxide, BPSG, USG, FSG, low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer such as polyimide, the like, or a combination thereof.
- the low-k dielectric materials may have k values lower than 3.9.
- the dielectric layer 418 may be deposited by CVD, PVD, ALD, an SOD process, the like, or a combination thereof. In an embodiment, the dielectric layer 418 is formed to a thickness of from about 300 ⁇ to about 700 ⁇ .
- the ARC layer 420 , the hardmask layer 422 , the ARC layer 424 , and the dielectric layer 426 are formed over the dielectric layer 418 .
- the ARC layer 420 , the hardmask layer 422 , the ARC layer 424 , and the dielectric layer 426 may be formed of similar materials and by similar processes as the ARC layer 412 , the hardmask layer 414 , the ARC layer 416 , and the dielectric layer 418 , respectively, described above and the descriptions are not repeated herein.
- the hardmask layer 428 is formed over the dielectric layer 426 .
- the hardmask layer may be formed of similar materials and by similar processes as the hardmask layer 414 described above and the description is not repeated herein.
- the photoresist 430 is formed over the hardmask layer 428 .
- the photoresist 430 may be formed of a conventional photoresist material, such as a deep ultra-violet (DUV) photoresist.
- the photoresist 430 may be deposited on the surface of the hardmask layer 428 , for example, by using a spin-on process to place the photoresist 430 .
- any other suitable material or method of forming or placing a photoresist material may alternatively be utilized.
- FIG. 5B illustrates the semiconductor device after undergoing a double patterning process to form openings 432 .
- the double patterning process may be process including two photolithography exposure steps and two etching steps which may be referred to as a 2P2E process.
- the openings 432 extend through the ARC layer 424 and the hardmask layer 422 and expose portions of the ARC layer 420 .
- the openings 432 may be formed by using acceptable photolithography and etching techniques such as, for example, an anisotropic dry etch.
- FIG. 5C illustrates extending the openings 432 through the ARC layer 420 and the dielectric layer 418 to expose portions of the ARC layer 416 .
- the openings 432 are extended through the ARC layer 420 and the dielectric layer 418 by using an anisotropic dry etch.
- FIG. 5D illustrates forming an alignment layer 434 on the ARC layer 420 and in the openings 432 .
- the alignment layer 434 may be formed of a polycrystalline-silicon (poly-Si), poly-crystalline silicon-germanium (poly-SiGe), oxides, nitrides, the like, or a combination thereof.
- amorphous silicon is deposited and recrystallized to create polycrystalline silicon (poly-silicon).
- the alignment layer 434 may be deposited by PVD, CVD, sputter deposition, the like, or a combination thereof.
- the top surface of the alignment layer 434 may have a non-planar top surface, and may be planarized by, for example, a CMP process.
- FIG. 5E illustrates the thinning of the alignment layer 434 and the removal of the ARC layer 420 and the dielectric layer 418 to form alignment structures 436 .
- the thinning and removal steps may include a CMP process, an etch process, the like, or a combination thereof.
- each of the alignment structures 436 is aligned with a gate 404 in layers below the respective alignment structure 436 .
- FIG. 5F illustrates the formation of alignment spacers 438 on the sidewalls of the alignment structures 436 .
- the alignment spacers 438 may be formed of similar materials and by similar processes as the alignment spacers 114 described above the description is not repeated herein.
- FIG. 5G illustrates the formation of dielectric layer 440 , hardmask layer 442 , and photoresist 444 over the alignment structures 436 with openings 446 formed in the photoresist 444 .
- the openings 446 are aligned between the alignment structures 436 .
- FIG. 5G illustrates extending the openings 446 through the hardmask layer 442 , the dielectric layer 440 , and the ARC layer 416 to portions of the top surface 414 A of the hardmask layer 414 .
- FIG. 5I illustrates the formation of dielectric layer 448 , hardmask layer 450 , and photoresist 452 over the alignment structures 436 and in the openings 446 and the formation of an opening 454 formed in the photoresist 452 .
- the opening 446 is aligned adjacent an alignment structures 436 and between gates 404 .
- FIG. 5J illustrates extending the opening 454 through the hardmask layer 450 , the dielectric layer 448 , and the ARC layer 416 to expose portions of the top surface 414 A of the hardmask layer 414 .
- FIG. 5K illustrates removing the dielectric layer 448 to expose the alignment structures 436 and the ARC layer 416 .
- FIG. 5L illustrate extending the openings 446 and 454 to form openings 456 through the hardmask layer 414 , the ARC layer 412 , and the ILD 410 to expose portions of the top surface 402 A of the substrate 402 .
- FIG. 5M illustrates forming a conductive layer 458 in the openings 456 and over the alignment structures 436 and the ARC layer 416 .
- the conductive layer 458 may be formed of similar materials and by similar processes as the conductive layer 122 described above and the description is not repeated herein.
- FIG. 5N illustrates the recessing of the conductive layer 458 and removing the alignment structures 436 to expose the top surface 416 A of the ARC layer 416 between the alignment spacers 438 .
- the alignment structures 436 may be removed by a wet etch process that is selective to the alignment structures 436 .
- FIG. 5O illustrates forming openings 460 through the ARC layer 416 , the hardmask layer 414 , the ARC layer 412 , and partially through the ILD 410 to expose the top surfaces 406 A of the hard masks 406 .
- the openings 460 may be formed by using acceptable photolithography and etching techniques such as, for example, an anisotropic dry etch.
- FIG. 5P illustrates extending the openings 460 through the hard masks 406 to expose top surfaces 404 A of the gates 104 .
- the openings 460 may be extended through the hard masks 406 by using acceptable photolithography and etching techniques such as, for example, an anisotropic dry etch.
- FIG. 5Q illustrates removing the conductive layer 458 from the openings 456 to expose the portions of the top surface 402 A of the substrate 402 in the openings 456 .
- the conductive layer 458 may be removed by a wet etch process that is selective to the conductive layer 458 .
- FIG. 5R illustrates forming a conductive layer 462 in the openings 456 and 460 .
- FIG. 5S illustrates recessing the conductive layer 462 to form conductive features 464 in the openings 460 contacting the top surfaces 404 A of the gates 404 and conductive features 466 in the openings 456 contacting the top surface 402 A of the substrate 402 .
- the recessing is performed by a dry etch process with a plasma source and an etchant gas such as H 2 , NH 3 , Ar, He, the like, or a combination thereof.
- FIG. 5T illustrates removing the alignment spacers 438 , the ARC layers 416 and 412 , and the hardmask layer 414 and the planarization of the ILD 510 and the conductive features 466 and 464 .
- the planarization process may be a CMP process, an etch process, the like, or a combination thereof.
- the top surfaces 466 A of the conductive features 466 , the top surfaces 464 A of conductive features 464 , and the top surface 410 A of the ILD 410 are substantially coplanar after the planarization process.
- the conductive features 464 may be used as contacts to couple the gates 404 to layers above the ILD 410 and the conductive features 466 may be used as contacts to couple the substrate 402 and devices and metallization layers formed therein to layers above ILD 410 .
- FIGS. 6A through 6X illustrate cross-sectional views of intermediate stages in the manufacturing of a semiconductor device in accordance with an embodiment. Details regarding this embodiment that are similar to those for the previously described embodiment will not be repeated herein.
- FIG. 6A illustrates an intermediate stage of manufacture of a semiconductor device similar to FIG. 5C described above and the description is not repeated herein.
- FIG. 6B illustrates the formation of alignment spacers 468 inside the openings 432 .
- the alignment spacers 468 may be formed similar to the alignment spacers 114 described above and the description is not repeated herein.
- the alignment spacers 468 are formed on the sidewalls of openings, whereas in the previous embodiments, the alignment spacers were formed on sidewalls of a structure (e.g. an alignment structure).
- a structure e.g. an alignment structure
- FIG. 6C illustrates forming an alignment structure 470 between the alignment spacers 468 .
- the alignment structures 470 are formed after the alignment spacers 468 and are referred to as secondary alignment structures 470 with the alignment structure 467 being a primary alignment structure 467 .
- the secondary alignment structures 470 may be formed of a polycrystalline-silicon (poly-Si), poly-crystalline silicon-germanium (poly-SiGe), oxides, nitrides, the like, or a combination thereof.
- amorphous silicon is deposited and recrystallized to create polycrystalline silicon (poly-silicon).
- the secondary alignment structures 470 may be deposited by PVD, CVD, sputter deposition, the like, or a combination thereof.
- the top surfaces 470 A of the secondary alignment structures 470 are recessed by an etching process to make the top surfaces 470 A lower than the top surface 420 A of the ARC layer 420 .
- FIG. 6D illustrates the formation of a dielectric layer 472 , a hardmask layer 474 , and a photoresist 476 over the primary alignment structure 467 , the secondary alignment structures 470 , and the ARC layer 420 .
- FIG. 6E illustrates the formation of openings 478 A and 478 B in the photoresist 476 with opening the 478 A aligned over a portion of a secondary alignment structure 470 and a portion over the primary alignment structure 467 .
- the opening 478 B is aligned adjacent one of the gates 404 .
- FIG. 6F illustrates extending the openings 478 A and 478 B through the hardmask layer 474 and the dielectric layer 472 to expose portions of the top surfaces 420 A of the ARC layer 420 , a portion of the top surface 470 A of the secondary alignment structure 470 , and a portion of an alignment spacer 468 .
- both the openings 478 A and 478 B expose a portion of the top surface 420 A of the ARC layer 420 .
- FIG. 6G illustrates extending the openings 478 A and 478 B through the ARC layer 420 to expose a top surface 467 A of the primary alignment structure 467 and a portion of the top surface 418 A of the dielectric layer 418 .
- FIG. 6H illustrates removing the hardmask layer 474 , the dielectric layer 472 , and the primary alignment structure 467 and extending the openings 478 A and 478 B through the dielectric layer 418 .
- the opening 478 A extends between a pair of alignment spacers 468 to expose a top surface 416 A of the ARC layer 416 .
- FIG. 6I illustrates extending the openings 478 A and 478 B through the ARC layer 416 to expose portions of the top surface 414 A of the hardmask layer 414 .
- FIG. 6J illustrates the formation of a dielectric layer 480 , a hardmask layer 482 , and a photoresist in the openings 478 A and 478 B and over the secondary alignment structures 470 and the dielectric layer 418 .
- An opening 486 is formed in the photoresist 484 with opening 486 aligned over a portion of a secondary alignment structure 470 .
- FIG. 6K illustrates extending the opening 486 through the hardmask layer 482 and the dielectric layer 480 to expose portions of the top surfaces 416 A of the ARC layer 416 , a portion of the top surface 470 A of a secondary alignment structure 470 , and a portion of an alignment spacer 468 .
- FIG. 6L illustrates extending the opening 486 through the ARC layer 416 to expose portions of the top surface 414 A of the hardmask layer 414 .
- FIG. 6M illustrates removing the dielectric layer 480 and the dielectric layer 418 .
- FIG. 6N illustrates extending the openings 478 A, 478 B, and 486 through the hardmask layer 414 to expose portions of the top surface 412 A of the ARC layer 412 .
- FIG. 6O illustrates extending the openings 478 A, 478 B, and 486 through the ARC layer 412 to expose portions of the top surface 410 A of the ILD 410 .
- FIG. 6P illustrates extending the openings 478 A, 478 B, and 486 through the ILD 410 to expose portions of the top surface 402 A of the substrate 402 .
- FIG. 6Q illustrates forming a conductive layer 488 in the openings 478 A, 478 B, and 486 and over the secondary alignment structures 470 and the hardmask layer 414 .
- the conductive layer 488 may be formed of similar materials and by similar processes as the conductive layer 122 described above and the description is not repeated herein.
- FIG. 6R illustrates the recessing of the conductive layer 488 to have a top surface 488 A lower than top surfaces 470 A of the secondary alignment structures 470 .
- FIG. 6S illustrates removing the secondary alignment structures 470 to form openings 490 .
- the secondary alignment structures 470 may be removed by a wet etch process that is selective to the secondary alignment structures 470 .
- FIG. 6S also illustrates extending the openings 490 through the ARC layers 416 and 412 and the hardmask layer 414 .
- FIG. 6T illustrates forming the openings 490 partially through the ILD 410 and through the hardmasks 406 to expose top surfaces 404 A of the gates 404 .
- FIG. 6U illustrates removing the conductive layer 488 from the openings 478 A, 478 B, and 486 to expose the portions of the top surface 402 A of the substrate 402 in the openings 478 A, 478 B, and 486 .
- the conductive layer 488 may be removed by a wet etch process that is selective to the conductive layer 488 .
- FIG. 6V illustrates forming a conductive layer 492 in the openings 478 A, 478 B, 486 , and 490 .
- FIG. 6W illustrates recessing the conductive layer 492 to form conductive features 492 in the openings 490 contacting the top surfaces 404 A of the gates 404 and conductive features 494 in the openings 478 A, 478 B, and 486 contacting the top surface 402 A of the substrate 402 .
- the recessing is performed by a dry etch process with a plasma source and an etchant gas such as H 2 , NH 3 , Ar, He, the like, or a combination thereof.
- FIG. 6X illustrates removing the alignment spacers 468 , the hardmask layer 414 , the ARC layer 412 , and the planarization of the ILD 410 and the conductive features 492 and 494 .
- the planarization process may be a CMP process, an etch process, the like, or a combination thereof.
- the top surfaces 492 A of the conductive features 492 , the top surfaces 494 A of conductive features 494 , and the top surface 410 A of the ILD 410 are substantially coplanar after the planarization process.
- the conductive features 492 may be used as contacts to couple the gates 404 to layers above the ILD 410 and the conductive features 494 may be used as contacts to couple the substrate 402 and devices and metallization layers formed therein to layers above ILD 410 .
- the embodiments described above provide self-alignment of conductive contacts and conductive lines between two or more layers.
- the embodiments include alignment structures and alignment spacers on opposite sides of the alignment structures in layers above the gates.
- the alignment structures and alignment spacers allow for self-alignment between the alignment spacers of a single alignment structure and for self-alignment between alignment spacers of different alignment structures.
- the ILD layer is able to be kept clean and free from residue from other spacers and/or hard masks as the alignment structures are formed in ILD layer above the ILD layer containing the gates.
- the process described above allows the conductive features landing on the gates and on the substrate to be self-aligning.
- An embodiment is a method for forming a semiconductor device, the method including forming at least two gates over a substrate, and forming at least two alignment structures over the at least two gates. The method further includes forming spacers on opposite sidewalls of the at least two alignment structures, and forming a first opening between a pair of the at least two alignment structures, a portion of the first opening exposing a top surface of at least one of the pair, the first opening extending a first distance from a top surface of the substrate.
- the method further includes filling the first opening with a first conductive material to form a first conductive feature, forming a second opening between the spacers of at least one of the at least two alignment structures, the second opening extending a second distance from the top surface of the substrate, the second distance being different than the first distance, and filling the second opening with a second conductive material to form a second conductive feature.
- Another embodiment is a method of forming a semiconductor device, the method including forming a plurality of gates over a semiconductor substrate, forming a first inter-layer dielectric (ILD) over the plurality of gates, and forming at least two alignment structures over the first ILD.
- the method further includes forming a second ILD over the at least two alignment structures, forming a first set of conductive contacts through the first and second ILDs to a top surface of the semiconductor substrate, one of the at least two alignment structures being between an adjacent pair of the first set of conductive contacts, and forming a second set of conductive contacts through the second ILD and partially through the first ILD to the plurality of gates, at least one of the second set of contacts extending through one of the alignment structures.
- ILD inter-layer dielectric
- Yet another embodiment is a method of forming a semiconductor device, the method including forming a plurality of gates on a substrate, forming an inter-layer dielectric (ILD) over the plurality of gates, and forming a first dielectric layer over the ILD.
- the method further includes forming a first and a second opening in the first dielectric layer, a portion of the first dielectric layer between the first and the second opening forming a primary alignment structure, and forming secondary alignment structures inside the first and second openings.
- the method further includes forming a first contact through the primary alignment structure and the ILD to a top surface of the substrate, and forming a second contact through one of the secondary alignment structures to a top surface of one of the plurality of gates.
Abstract
Description
- Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.
- The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area.
- In particular, as designs shrink, conductive features connecting to layers above and below may become shorted if the conductive feature is misaligned. Generally, this occurs when the etching process through the layer is misaligned such that the conductive feature exposes portions of an adjacent conductive feature on the layer below.
- For a more complete understanding of the present embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
-
FIGS. 1A through 1N illustrate cross-sectional views of intermediate stages in the manufacturing of a semiconductor device in accordance with an embodiment; -
FIGS. 2A through 2G illustrate cross-sectional views of intermediate stages in the manufacturing of a semiconductor device in accordance with an embodiment; -
FIGS. 3A through 3L illustrate cross-sectional views of intermediate stages in the manufacturing of a semiconductor device in accordance with an embodiment; -
FIGS. 4A through 4N illustrate cross-sectional views of intermediate stages in the manufacturing of a semiconductor device in accordance with an embodiment; -
FIGS. 5A through 5T illustrate cross-sectional views of intermediate stages in the manufacturing of a semiconductor device in accordance with an embodiment; and -
FIGS. 6A through 6X illustrate cross-sectional views of intermediate stages in the manufacturing of a semiconductor device in accordance with an embodiment. - Reference will now be made in detail to embodiments illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. In the drawings, the shape and thickness may be exaggerated for clarity and convenience. This description will be directed in particular to elements forming part of, or cooperating more directly with, methods and apparatus in accordance with the present disclosure. It is to be understood that elements not specifically shown or described may take various forms well known to those skilled in the art. Many alternatives and modifications will be apparent to those skilled in the art, once informed by the present disclosure.
- Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be appreciated that the following figures are not drawn to scale; rather, these figures are merely intended for illustration.
- Embodiments will be described with respect to a specific context, namely a self-alignment scheme between two layers. Other embodiments may also be applied, however, to align three or more layers.
-
FIGS. 1A through 1N illustrate cross-sectional views of intermediate stages in the manufacturing of a semiconductor device in accordance with an embodiment.FIG. 1A illustrates a semiconductor device includes asubstrate 102,gates 104,hard masks 106 on thegates 104,gate spacers 108 on the sidewalls of thegates 104, and an inter-layer dielectric (ILD) 110 over thegates 104, thehard masks 106, and thegate spacers 108. Thesubstrate 102 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may also be used. Additionally, thesubstrate 102 may be a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. - The
substrate 102 may include active and passive devices (not shown inFIG. 1A ). As one of ordinary skill in the art will recognize, a wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the semiconductor device. The devices may be formed using any suitable methods. Only a portion of thesubstrate 102 is illustrated in the figures, as this is sufficient to fully describe the illustrative embodiments. - The
substrate 102 may also include metallization layers (not shown). The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) and may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like). - The
gates 104 are formed over thesubstrate 102. Thegates 104 may include a gate dielectric layer (not shown), ahard mask 106, andgate spacers 108. The gate dielectric layer may be formed by thermal oxidation, chemical vapor deposition (CVD), sputtering, or any other methods known and used in the art for forming a gate dielectric. In some embodiments, the gate dielectric layer includes dielectric materials having a high dielectric constant (k value), for example, greater than 3.9. The gate dielectric materials include silicon nitrides, oxynitrides, metal oxides such as HfO2, HfZrOx, HfSiOx, HfTiOx, HfAlOx, the like, or combinations and multi-layers thereof. - The gate electrode layer (not shown) may be formed over the gate dielectric layer. The gate electrode layer may comprise a conductive material and may be selected from a group comprising polycrystalline-silicon (poly-Si), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. In one embodiment, amorphous silicon is deposited and recrystallized to create polycrystalline silicon (poly-silicon). The gate electrode layer may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques known and used in the art for depositing conductive materials. The top surface of the gate electrode layer usually has a non-planar top surface, and may be planarized prior to patterning of the gate electrode layer or gate etch. Ions may or may not be introduced into the gate electrode layer at this point. Ions may be introduced, for example, by ion implantation techniques.
- A hard mask layer (not shown) is formed over the gate electrode layer. The hard mask layer may be made of SiN, SiON, SiO2 the like, or a combination thereof. The hard mask layer is then patterned. The patterning of the hard mask layer may be accomplished by depositing mask material (not shown) such as photoresist over the hard mask layer. The mask material is then patterned and the hard mask layer is etched in accordance with the pattern to form hard masks 106. The gate electrode layer and the gate dielectric layer may be patterned to form the
gates 104. The gate patterning process may be accomplished by using thehard mask 106 as a pattern and etching the gate electrode layer and the gate dielectric layer to form thegates 104. - The gate spacers 108 are formed on opposite sides of the
gates 104. The gate spacers 108 are formed by blanket depositing a spacer layer (not shown) on the previously formedgates 104 andhard masks 106. In an embodiment, thegate spacers 108 include a spacer liner (not shown). The spacer liner may be made of SiN, SiC, SiGe, oxynitride, oxide, the like, or a combination thereof. The spacer layer may comprise SiN, oxynitride, SiC, SiON, oxide, combinations thereof, or the like and may be formed by methods utilized to form such a layer, such as CVD, plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), atomic layer deposition (ALD), sputter, the like, or a combination thereof. The gate spacers 108 are then patterned, for example, by an anisotropic etch to remove the spacer layer fromtop surfaces 106A of thehard masks 106. - Although the description above described the formation of a
gate 104, thestructure 104 is not limited to a gate. In some embodiments, thestructure 104 is aconductive line 104 that is to be aligned and coupled with another conductive feature by the subsequently formed conductive feature 126 (seeFIG. 1N ). - After the
gates 104,hard masks 106, andgate spacers 108 are formed, theILD 110 is formed over these structures and thesubstrate 102. TheILD 110 may be formed of oxides such as silicon oxide, borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer such as polyimide, the like, or a combination thereof. The low-k dielectric materials may have k values lower than 3.9. TheILD 110 may be deposited by CVD, PVD, ALD, a spin-on-dielectric (SOD) process, the like, or a combination thereof. In an embodiment, the ILD 24 is formed directly on atop surface 102A of thesubstrate 102. In other embodiments, theILD 110 is formed on intermediate layers and/or structures (not shown) which are onsubstrate 102. In some embodiments, theILD 110 is planarized by a chemical mechanical polish (CMP) process or an etching process to form a substantially planartop surface 110A. -
FIG. 1B illustrates the formation ofalignment structures 112 andalignment spacers 114 on thetop surface 110A of theILD 110. Thealignment structures 112 and thespacers 114 may be formed of similar materials and by similar processes as thegates 104 and thespacers 108, respectively, and the descriptions will not be repeated herein, although the materials and processes need not be the same. In an embodiment, each of thealignment structures 112 is aligned with agate 104 in the layer below therespective alignment structure 112. In some embodiments, thealignment spacers 114 are formed to have a width W1 in a range from about 10% to about 40% of a minimum space betweenadjacent alignment structures 112. -
FIG. 1C illustrates the formation of anILD 116 and apatterning layer 118 over theILD 110. TheILD 116 is formed over thealignment structures 112 and thealignment spacers 114 and on theILD 110. TheILD 116 may be formed of similar materials and by similar processes as theILD 110 and the description will not be repeated herein, although theILD 116 and theILD 110 need not be the same. - The
patterning layer 118 is formed and patterned over theILD 116. In an embodiment, thepatterning layer 118 is formed of a photoresist material, such as a deep ultraviolet (DUV) photoresist, an extreme ultraviolet (EUV) photoresist, an electron beam direct write (EBDW) photoresist, or the like, and is deposited on the surface of theILD 116 by using a spin-on process to place thepatterning layer 118. However, any other suitable material or method of forming or placing a photoresist material may alternatively be utilized. In this embodiment, once thepatterning layer 118 has been placed on theILD 116, thepatterning layer 118 is exposed to energy, e.g. light, through a patterned reticle in order to induce a reaction in those portions of thepatterning layer 118 exposed to the energy. Thepatterning layer 118 is then developed, and portions of thepatterning layer 118 are removed formingopenings top surface 116A of theILD 116 through theopenings patterning layer 118 is a hard mask. In this embodiment, thepatterning layer 118 is formed of and by similar processes as thehard masks 106, and the details will not be repeated herein, although thepatterning layer 118 and thehard masks 106 need not be the same. -
FIG. 1D illustrates the formation of theopenings ILD 116 and partially through theILD 110. Although a portion of theopening 120A extends over atop surface 112A of thealignment structure 112, thealignment structure 112 and thealignment spacers 114 self-align the opening 120 between a pair of theadjacent gates 104. Theopening 120B is self-aligned by anotherspacer 114 to be between a pair ofadjacent gates 104. Theopening 120C does not require an alignment by analignment structure 112 oralignment spacer 114. Theopenings openings -
FIG. 1E illustrates the removal of thepatterning layer 118 to expose thetop surface 116A of theILD 116. Thepatterning layer 118 may be removed by a CMP process, an etch process, the like, or a combination thereof. -
FIG. 1F illustrates forming theopenings ILD 110 to expose portions of thetop surface 102A of thesubstrate 102. Theopening 120A is formed between a pair ofalignment structures 112 with theirrespective alignment spacers 114 and a pair ofgates 104 with theirgate spacers 108. Theopening 120B is formed between analignment structure 112 with itsrespective alignment spacer 114 and a patterned portion ofILD 116 and between a pair ofgates 104 with theirrespective gate spacers 108. Theopening 120C is formed between patterned portions ofILD 116 and between agate 104 with itsrespective gate spacer 108 and a portion ofpatterned ILD 110. In an embodiment, theopenings ILD 110 by using an anisotropic dry etch. -
FIG. 1G illustrates the formation of aconductive layer 122 in theopenings top surface 102A of thesubstrate 102 and alongtop surfaces 116A of theILD 116,top surfaces 112A of thealignment structures 112, andalignment spacers 114. In some embodiments, theconductive layer 122 includes a barrier layer (not shown). The barrier layer helps to block diffusion of the subsequently formedconductive layer 122 into adjacent dielectric materials such asILD 110. The barrier layer may be made of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, cobalt, cobalt oxide, cobalt nitride, nickel, nickel oxide, nickel nitride, silicon carbide, oxygen doped silicon carbide, nitrogen doped silicon carbide, silicon nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, a polymer such as polyimide, polybenzoxazole (PBO) the like, or a combination thereof. The barrier layer may be formed by CVD, PVD, plasma enhanced CVD (PECVD), ALD, SOD, the like, or a combination thereof. In some embodiments, the barrier layer is omitted. - The
conductive layer 122 may be made of tungsten, copper, aluminum, the like, or a combination thereof. Theconductive layer 122 may be formed through a deposition process such as electrochemical plating, PVD, CVD, the like, or a combination thereof. In some embodiments, theconductive layer 122 is formed on a copper seed layer. -
FIG. 1H illustrates the recessing of theconductive layer 122 to formconductive features openings conductive features top surface 112A of thealignment structure 112 and thetop surface 116A of theILD 116 after the recessing. In an embodiment, the recessing is performed by a dry etch process with a plasma source and an etchant gas such as CF4, SF6, the like, or a combination thereof. -
FIG. 1I illustrates the formation ofopenings 124 by removing thealignment structures 112 from between thealignment spacers 114 to expose thetop surface 110A of theILD 110. Thealignment structures 112 may be removed by an etch process, such as a wet etch process, that is selective to thealignment structures 112. -
FIG. 1J illustrates extending theopenings 124 through theILD 110 to expose thetop surfaces 106A of thehard masks 106. Theopenings 124 may be extended through theILD 110 by using acceptable etching techniques such as, for example, an anisotropic dry etch. -
FIG. 1K illustrates extending theopenings 124 through thehard masks 106 to exposetop surfaces 104A of thegates 104. Theopenings 124 may be extended through thehard masks 106 by using acceptable etching techniques such as, for example, an anisotropic dry etch. -
FIG. 1L illustrates the formation of aconductive layer 126 in theopenings 124 contacting thetop surface 104A of thegates 104 and over theconductive features conductive layer 126 may be formed of similar materials and by similar processes as theconductive layer 122 discussed above and the description will not be repeated herein, although theconductive layers -
FIG. 1M illustrates the recessing of theconductive layer 126 to formconductive features openings 124 and the recessing of theconductive features conductive features conductive features conductive layer 126conductive features -
FIG. 1N illustrates the removal of thealignment spacers 114 and the remaining portions ofILD 116 and the planarization of theILD 110,conductive features conductive features conductive features top surface 110A of theILD 110 are substantially coplanar after the planarization process. In an embodiment, the conductive features 126 (126A and 126B) are formed to have a width W2 in a range from about 50% to about 150% of a width of thegate 104 below the respectiveconductive feature 126. In an embodiment, the conductive features 122 (122A, 122B, and 122C) are formed to have a width W3 in a range from about 50% to about 150% of a width betweenadjacent gates 104. In some embodiments where thegates 104 are gate electrodes, theconductive features gates 104 to layers above theILD 110 and theconductive features substrate 102 and devices and layers (e.g. source/drain features) formed therein to layers aboveILD 110. In other embodiments where thestructure 104 is aconductive line 104, theconductive features conductive line 104 to another conductive feature above theILD 110 and theconductive features substrate 102 and devices and metallization layers formed therein to layers aboveILD 110. - By having only spacers surrounding the gates in the ILD layer, the ILD layer is able to be kept clean and free from residue from other spacers and/or hard masks as the alignment structures are formed in ILD layer above the ILD layer containing the gates. Further, the process described above allows line patterns (e.g. alignment structure 112) to self-align to another line pattern (
-
FIGS. 2A through 2G illustrate cross-sectional views of intermediate stages in the manufacturing of a semiconductor device in accordance with an embodiment. Details regarding this embodiment that are similar to those for the previously described embodiment will not be repeated herein. -
FIGS. 2A and 2B are similar toFIGS. 1A and 1B , respectively, and the descriptions will not be repeated herein.FIG. 2C is similar toFIG. 1C except that in FIG. 2C, theopenings patterning layer 118 between them.FIG. 2D illustrates the formation of theopenings ILD 116 and partially through theILD 110. In this embodiment, there is no portion ofILD 116 betweenopenings ILD 116 was removed because there was no portion ofpatterning layer 118 between theopenings ILD 116 betweenopenings -
FIG. 2E illustrates the removal of thepatterning layer 118 to expose thetop surface 116A of theILD 116. Thepatterning layer 118 may be removed by a CMP process, an etch process, the like, or a combination thereof. -
FIG. 2F illustrates forming theopenings ILD 110 to expose portions of thetop surface 102A of thesubstrate 102. The semiconductor device inFIG. 2F is similar to the semiconductor device inFIG. 1F and the description will not be repeated herein. In this embodiment, even though thepatterning layer 118 did not include a portion between theopenings FIG. 2C ), theopenings FIG. 1F because thealignment structure 112 andalignment spacer 114 separate theopenings -
FIG. 2G illustrates the semiconductor device withconductive features FIG. 1N . The processing steps betweenFIGS. 2F and 2G are similar to those illustrate inFIGS. 1G through 1N and are not repeated herein. -
FIGS. 3A through 3L illustrate cross-sectional views of intermediate stages in the manufacturing of a semiconductor device in accordance with an embodiment. Details regarding this embodiment that are similar to those for the previously described embodiment will not be repeated herein. -
FIGS. 3A and 3B are similar toFIGS. 1A and 1B , respectively, and the descriptions will not be repeated herein.FIG. 3C is similar toFIG. 1C except that inFIG. 3C , theopenings FIG. 1C do not have a portion ofpatterning layer 118 between them forming asingle opening 120D inFIG. 2C . -
FIG. 3D illustrates the formation of theopenings ILD 116 and partially through theILD 110. In this embodiment, theopening 120D includes the entiretop surface 106A of ahard mask 106 on agate 104 as there was no portion ofILD 116 on thehard mask 106. -
FIG. 3E illustrates the removal of thepatterning layer 118 and forming theopenings ILD 110 to expose portions of thetop surface 102A of thesubstrate 102. In this embodiment, theopening 120D includes agate 104,hard mask 106, andgate spacers 108 along a bottom of theopening 120D. -
FIG. 3F illustrates the formation of aconductive layer 122 in theopenings top surface 102A of thesubstrate 102 and along thetop surface 106A of ahard mask 106,gate spacers 108,top surfaces 116A of theILD 116,top surfaces 112A of thealignment structures 112, andalignment spacers 114. -
FIG. 3G illustrates the recessing of theconductive layer 122 to formconductive features openings conductive feature 122D coupled to thesubstrate 102 on at least two sides of agate 104. In some embodiments, asingle gate 104 is embedded in theconductive feature 122D. In other embodiments, more than onegate 104 is embedded in theconductive feature 122D. -
FIG. 3H illustrates the formation ofopenings 124 by removing thealignment structures 112 from between thealignment spacers 114 and extending theopenings 124 through theILD 110 to expose thetop surfaces 106A of thehard masks 106. In some embodiments, after theopenings 124 are extended to thehard masks 106, the top surfaces 122A1 and 122D1 are higher than thetop surface 116A of theILD 116.FIG. 3I illustrates extending theopenings 124 through thehard masks 106 to exposetop surfaces 104A of thegates 104. -
FIG. 3J illustrates the formation of theconductive layer 126 in theopenings 124 contacting thetop surface 104A of thegates 104 and over thealignment spacers 114 and theconductive features conductive layer 126 may be formed of similar materials and by similar processes as theconductive layer 122 discussed above and the description will not be repeated herein, although theconductive layers -
FIG. 3K illustrates the recessing of theconductive layer 126 to formconductive features openings 124 and the recessing of theconductive features conductive features conductive features -
FIG. 3L illustrates the removal of thealignment spacers 114 and the remaining portions ofILD 116 and the planarization of theILD 110,conductive features conductive features conductive features top surface 110A of theILD 110 are substantially coplanar after the planarization process. The conductive features 126A and 126B may be used as contacts to couple thegates 104 to layers above theILD 110 and theconductive features substrate 102 and devices and metallization layers formed therein to layers aboveILD 110. In some embodiments, theconductive feature 122D is used to couple devices that have higher current requirements than the devices coupled to theconductive feature 122A. -
FIGS. 4A through 4N illustrate cross-sectional views of intermediate stages in the manufacturing of a semiconductor device in accordance with an embodiment. Details regarding this embodiment that are similar to those for the previously described embodiment will not be repeated herein. -
FIG. 4A illustrates a semiconductor device includes asubstrate 302,gates 304,hard masks 306 on thegates 304,gate spacers 308 on the sidewalls of thegates 304, and anILD 310 over thegates 304, thehard masks 306, and thegate spacers 308. Thesubstrate 302,gates 304,hard masks 306,gate spacers 308, andILD 310 may be formed of similar materials and similar processes as thesubstrate 102,gates 104,hard masks 106,gate spacers 108, andILD 110 described above and the descriptions will not be repeated herein. However, the materials and processes of the two embodiments of the semiconductor device need not be the same. -
FIG. 4B illustrates the formation ofalignment structures 312 andalignment spacers 314 on thetop surface 310A of theILD 310. Thealignment structures 312 and thealignment spacers 314 may be formed of similar materials and by similar processes as thealignment structures 112 and thealignment spacers 114, respectively, described above and the descriptions will not be repeated herein, although the materials and processes need not be the same. In embodiment, each of thealignment structures 312 is aligned between a pair ofadjacent gates 304 in the layer below therespective alignment structure 312. -
FIG. 4C illustrates the formation of anILD 316 and apatterning layer 318 over theILD 310. TheILD 316 is formed over thealignment structures 312 and thealignment spacers 314 and on theILD 310. TheILD 316 may be formed of similar materials and by similar processes as theILD 116 described above and the description will not be repeated herein, although theILD 316 and theILD 116 need not be the same. - The
patterning layer 318 is formed and patterned over theILD 316. Thepatterning layer 318 may be formed of similar materials and patterned by similar processes as thepatterning layer 118 described above and the description will not be repeated herein. Thepatterning layer 318 is patterned to formopenings 320 exposing portions of thetop surface 316A of theILD 316. In some embodiments, each of theopenings 320 is aligned directly over agate 304. -
FIG. 4D illustrates extending theopenings 320 through theILD 316 and partially through theILD 310 to expose portions oftop surfaces 306A of thehard masks 306. Theopenings 320 may be formed by using acceptable etching techniques such as, for example, an anisotropic dry etch. -
FIG. 4E illustrates the removal of thepatterning layer 318 to expose thetop surface 316A of theILD 316. Thepatterning layer 318 may be removed by a CMP process, an etch process, the like, or a combination thereof. -
FIG. 4F illustrate the thinning of theILD 316 to exposetop surfaces 312A of thealignments structures 312. The thinning process may be by a CMP process, an etch process, the like, or a combination thereof. -
FIG. 4G illustrates extending theopenings 320 through thehard masks 306 to exposetop surfaces 304A of thegates 304. Theopenings 320 may be extended through thehard masks 306 by using acceptable etching techniques such as, for example, an anisotropic dry etch. -
FIG. 4H illustrates the formation of aconductive layer 322 in theopenings 320 contacting thetop surface 304A of thegates 304 and along thetop surfaces 312A of thealignment structures 312, thealignment spacers 314, and the ILD 36. Theconductive layer 322 may be formed of similar materials and by similar processes as theconductive layer 122 discussed above and the description will not be repeated herein, although theconductive layers -
FIG. 4I illustrates the recessing of theconductive layer 322 to formconductive features 322 in theopenings 320. In some embodiments, thetop surfaces 322A of theconductive features 322 are lower than thetop surfaces 312A of thealignment structures 312 and thetop surface 316A of theILD 316. This recessing process may be similar to the recessing process ofconductive layer 122 described above and the description will not be repeated herein, although the recessing processes need not be the same. -
FIG. 4J illustrates the formation ofopenings 324 by removing thealignment structures 312 from between thealignment spacers 314 to expose thetop surface 310A of theILD 310. Thealignment structures 312 may be removed by a wet etch process that is selective to thealignment structures 312. -
FIG. 4K illustrates extending theopenings 324 through theILD 310 to expose portions of thetop surface 302A of thesubstrate 302. Theopenings 324 may be extended through theILD 310 by using acceptable photolithography and etching techniques such as, for example, an anisotropic dry etch. -
FIG. 4L illustrates the formation of aconductive layer 326 in theopenings 324 contacting thetop surface 302A of thesubstrate 302 and over the conductive features 322. Theconductive layer 326 may be formed of similar materials and by similar processes as theconductive layer 122 discussed above and the description will not be repeated herein. -
FIG. 4M illustrates the recessing of theconductive layer 326 to formconductive features 326 in theopenings 324. In some embodiments, thetop surfaces 326A of theconductive features 326 and thetop surfaces 322A theconductive features 322 are substantially coplanar after the recessing. This recessing process may be similar to the recessing process ofconductive layer 122 described above and the description will not be repeated herein, although the recessing processes need not be the same. -
FIG. 4N illustrates the removal of thealignment spacers 314 and the remaining portions ofILD 116 and the planarization of theILD 310 and theconductive features top surfaces 326A of theconductive features 326, thetop surfaces 322A of theconductive features 322, and thetop surface 310A of theILD 310 are substantially coplanar after the planarization process. The conductive features 322 may be used as contacts to couple thegates 304 to layers above theILD 310 and theconductive features 326 may be used as contacts to couple thesubstrate 302 and devices and metallization layers formed therein to layers aboveILD 310. -
FIGS. 5A through 5T illustrate cross-sectional views of intermediate stages in the manufacturing of a semiconductor device in accordance with an embodiment. Details regarding this embodiment that are similar to those for the previously described embodiment will not be repeated herein. -
FIG. 5A illustrates a semiconductor device includes asubstrate 402,gates 404,hard masks 406 on thegates 404,gate spacers 408 on the sidewalls of thegates 404, and anILD 410 over thegates 404, thehard masks 406, and thegate spacers 408. The semiconductor device further includes an anti-reflective coating (ARC)layer 412, ahardmask layer 414, anARC layer 416, adielectric layer 418, anARC layer 420, ahardmask layer 422, anARC layer 424, adielectric layer 426, ahardmask layer 428, and aphotoresist 430. Thesubstrate 402,gates 404,hard masks 406,gate spacers 408, andILD 410 may be formed of similar materials and similar processes as thesubstrate 102,gates 104,hard masks 106,gate spacers 108, andILD 110 described above and the descriptions will not be repeated herein. However, the materials and processes of the two embodiments of the semiconductor device need not be the same. - The
ARC layer 412 is formed over theILD 410. TheARC layer 412 prevents radiation in a subsequent photolithographic process to reflect off layers below and interfering with the exposure process. Such interference can increase the critical dimension of the photolithography process. TheARC layer 412 may comprise SiON, a polymer, the like, or a combination thereof and may be formed by CVD, a spin-on process, the like, or a combination thereof. In an embodiment theARC layer 412 is formed to a thickness of between about 200 Å and about 400 Å. - The
hardmask layer 414 is formed over theARC layer 412. Thehardmask layer 414 may be a masking material such as poly-silicon, silicon nitride, the like, or a combination thereof may be formed using a process such as plasma enhanced chemical vapor deposition (PECVD). However, any other suitable hardmask material, such as silicon oxide, and any other process of formation, such as CVD, may alternatively be utilized. In an embodiment thehardmask layer 414 is formed to a thickness of between about 200 Å and about 400 Å. - The
ARC layer 416 is formed over thehardmask layer 414. TheARC layer 416 may be formed of similar materials and by similar processes as theARC layer 412 described above and the description is not repeated herein, although the first andARC layers ARC layer 416 is formed to a thickness of from about 200 Å to about 400 Å. - The
dielectric layer 418 is formed over theARC layer 416. Thedielectric layer 418 may be formed of oxides such as silicon oxide, BPSG, USG, FSG, low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer such as polyimide, the like, or a combination thereof. The low-k dielectric materials may have k values lower than 3.9. Thedielectric layer 418 may be deposited by CVD, PVD, ALD, an SOD process, the like, or a combination thereof. In an embodiment, thedielectric layer 418 is formed to a thickness of from about 300 Å to about 700 Å. - The
ARC layer 420, thehardmask layer 422, theARC layer 424, and thedielectric layer 426 are formed over thedielectric layer 418. TheARC layer 420, thehardmask layer 422, theARC layer 424, and thedielectric layer 426 may be formed of similar materials and by similar processes as theARC layer 412, thehardmask layer 414, theARC layer 416, and thedielectric layer 418, respectively, described above and the descriptions are not repeated herein. - The
hardmask layer 428 is formed over thedielectric layer 426. The hardmask layer may be formed of similar materials and by similar processes as thehardmask layer 414 described above and the description is not repeated herein. Thephotoresist 430 is formed over thehardmask layer 428. Thephotoresist 430 may be formed of a conventional photoresist material, such as a deep ultra-violet (DUV) photoresist. Thephotoresist 430 may be deposited on the surface of thehardmask layer 428, for example, by using a spin-on process to place thephotoresist 430. However, any other suitable material or method of forming or placing a photoresist material may alternatively be utilized. -
FIG. 5B illustrates the semiconductor device after undergoing a double patterning process to formopenings 432. The double patterning process may be process including two photolithography exposure steps and two etching steps which may be referred to as a 2P2E process. Theopenings 432 extend through theARC layer 424 and thehardmask layer 422 and expose portions of theARC layer 420. Theopenings 432 may be formed by using acceptable photolithography and etching techniques such as, for example, an anisotropic dry etch. -
FIG. 5C illustrates extending theopenings 432 through theARC layer 420 and thedielectric layer 418 to expose portions of theARC layer 416. In an embodiment, theopenings 432 are extended through theARC layer 420 and thedielectric layer 418 by using an anisotropic dry etch. -
FIG. 5D illustrates forming analignment layer 434 on theARC layer 420 and in theopenings 432. Thealignment layer 434 may be formed of a polycrystalline-silicon (poly-Si), poly-crystalline silicon-germanium (poly-SiGe), oxides, nitrides, the like, or a combination thereof. In one embodiment, amorphous silicon is deposited and recrystallized to create polycrystalline silicon (poly-silicon). Thealignment layer 434 may be deposited by PVD, CVD, sputter deposition, the like, or a combination thereof. The top surface of thealignment layer 434 may have a non-planar top surface, and may be planarized by, for example, a CMP process. -
FIG. 5E illustrates the thinning of thealignment layer 434 and the removal of theARC layer 420 and thedielectric layer 418 to formalignment structures 436. The thinning and removal steps may include a CMP process, an etch process, the like, or a combination thereof. In embodiment, each of thealignment structures 436 is aligned with agate 404 in layers below therespective alignment structure 436. -
FIG. 5F illustrates the formation ofalignment spacers 438 on the sidewalls of thealignment structures 436. Thealignment spacers 438 may be formed of similar materials and by similar processes as thealignment spacers 114 described above the description is not repeated herein. -
FIG. 5G illustrates the formation ofdielectric layer 440,hardmask layer 442, andphotoresist 444 over thealignment structures 436 withopenings 446 formed in thephotoresist 444. Theopenings 446 are aligned between thealignment structures 436.FIG. 5G illustrates extending theopenings 446 through thehardmask layer 442, thedielectric layer 440, and theARC layer 416 to portions of thetop surface 414A of thehardmask layer 414. -
FIG. 5I illustrates the formation ofdielectric layer 448,hardmask layer 450, andphotoresist 452 over thealignment structures 436 and in theopenings 446 and the formation of anopening 454 formed in thephotoresist 452. Theopening 446 is aligned adjacent analignment structures 436 and betweengates 404.FIG. 5J illustrates extending theopening 454 through thehardmask layer 450, thedielectric layer 448, and theARC layer 416 to expose portions of thetop surface 414A of thehardmask layer 414. -
FIG. 5K illustrates removing thedielectric layer 448 to expose thealignment structures 436 and theARC layer 416.FIG. 5L illustrate extending theopenings openings 456 through thehardmask layer 414, theARC layer 412, and theILD 410 to expose portions of thetop surface 402A of thesubstrate 402.FIG. 5M illustrates forming aconductive layer 458 in theopenings 456 and over thealignment structures 436 and theARC layer 416. Theconductive layer 458 may be formed of similar materials and by similar processes as theconductive layer 122 described above and the description is not repeated herein. -
FIG. 5N illustrates the recessing of theconductive layer 458 and removing thealignment structures 436 to expose thetop surface 416A of theARC layer 416 between thealignment spacers 438. Thealignment structures 436 may be removed by a wet etch process that is selective to thealignment structures 436. -
FIG. 5O illustrates formingopenings 460 through theARC layer 416, thehardmask layer 414, theARC layer 412, and partially through theILD 410 to expose thetop surfaces 406A of thehard masks 406. Theopenings 460 may be formed by using acceptable photolithography and etching techniques such as, for example, an anisotropic dry etch. -
FIG. 5P illustrates extending theopenings 460 through thehard masks 406 to exposetop surfaces 404A of thegates 104. Theopenings 460 may be extended through thehard masks 406 by using acceptable photolithography and etching techniques such as, for example, an anisotropic dry etch. -
FIG. 5Q illustrates removing theconductive layer 458 from theopenings 456 to expose the portions of thetop surface 402A of thesubstrate 402 in theopenings 456. Theconductive layer 458 may be removed by a wet etch process that is selective to theconductive layer 458. -
FIG. 5R illustrates forming aconductive layer 462 in theopenings FIG. 5S illustrates recessing theconductive layer 462 to formconductive features 464 in theopenings 460 contacting thetop surfaces 404A of thegates 404 andconductive features 466 in theopenings 456 contacting thetop surface 402A of thesubstrate 402. In an embodiment, the recessing is performed by a dry etch process with a plasma source and an etchant gas such as H2, NH3, Ar, He, the like, or a combination thereof. -
FIG. 5T illustrates removing thealignment spacers 438, the ARC layers 416 and 412, and thehardmask layer 414 and the planarization of the ILD 510 and theconductive features top surfaces 466A of theconductive features 466, thetop surfaces 464A ofconductive features 464, and thetop surface 410A of theILD 410 are substantially coplanar after the planarization process. The conductive features 464 may be used as contacts to couple thegates 404 to layers above theILD 410 and theconductive features 466 may be used as contacts to couple thesubstrate 402 and devices and metallization layers formed therein to layers aboveILD 410. -
FIGS. 6A through 6X illustrate cross-sectional views of intermediate stages in the manufacturing of a semiconductor device in accordance with an embodiment. Details regarding this embodiment that are similar to those for the previously described embodiment will not be repeated herein. -
FIG. 6A illustrates an intermediate stage of manufacture of a semiconductor device similar toFIG. 5C described above and the description is not repeated herein. -
FIG. 6B illustrates the formation ofalignment spacers 468 inside theopenings 432. Thealignment spacers 468 may be formed similar to thealignment spacers 114 described above and the description is not repeated herein. In this embodiment, thealignment spacers 468 are formed on the sidewalls of openings, whereas in the previous embodiments, the alignment spacers were formed on sidewalls of a structure (e.g. an alignment structure). By forming thealignment spacers 468 in theopenings 432, a portion of thedielectric layer 418 between theopenings 432 forms analignment structure 467. -
FIG. 6C illustrates forming analignment structure 470 between thealignment spacers 468. Thealignment structures 470 are formed after thealignment spacers 468 and are referred to assecondary alignment structures 470 with thealignment structure 467 being aprimary alignment structure 467. Thesecondary alignment structures 470 may be formed of a polycrystalline-silicon (poly-Si), poly-crystalline silicon-germanium (poly-SiGe), oxides, nitrides, the like, or a combination thereof. In one embodiment, amorphous silicon is deposited and recrystallized to create polycrystalline silicon (poly-silicon). Thesecondary alignment structures 470 may be deposited by PVD, CVD, sputter deposition, the like, or a combination thereof. In an embodiment, thetop surfaces 470A of thesecondary alignment structures 470 are recessed by an etching process to make thetop surfaces 470A lower than thetop surface 420A of theARC layer 420. -
FIG. 6D illustrates the formation of adielectric layer 472, ahardmask layer 474, and aphotoresist 476 over theprimary alignment structure 467, thesecondary alignment structures 470, and theARC layer 420.FIG. 6E illustrates the formation ofopenings photoresist 476 with opening the 478A aligned over a portion of asecondary alignment structure 470 and a portion over theprimary alignment structure 467. Theopening 478B is aligned adjacent one of thegates 404. -
FIG. 6F illustrates extending theopenings hardmask layer 474 and thedielectric layer 472 to expose portions of thetop surfaces 420A of theARC layer 420, a portion of thetop surface 470A of thesecondary alignment structure 470, and a portion of analignment spacer 468. In an embodiment, both theopenings top surface 420A of theARC layer 420. -
FIG. 6G illustrates extending theopenings ARC layer 420 to expose atop surface 467A of theprimary alignment structure 467 and a portion of thetop surface 418A of thedielectric layer 418.FIG. 6H illustrates removing thehardmask layer 474, thedielectric layer 472, and theprimary alignment structure 467 and extending theopenings dielectric layer 418. In this embodiment, theopening 478A extends between a pair ofalignment spacers 468 to expose atop surface 416A of theARC layer 416. -
FIG. 6I illustrates extending theopenings ARC layer 416 to expose portions of thetop surface 414A of thehardmask layer 414.FIG. 6J illustrates the formation of adielectric layer 480, ahardmask layer 482, and a photoresist in theopenings secondary alignment structures 470 and thedielectric layer 418. Anopening 486 is formed in thephotoresist 484 with opening 486 aligned over a portion of asecondary alignment structure 470. -
FIG. 6K illustrates extending theopening 486 through thehardmask layer 482 and thedielectric layer 480 to expose portions of thetop surfaces 416A of theARC layer 416, a portion of thetop surface 470A of asecondary alignment structure 470, and a portion of analignment spacer 468.FIG. 6L illustrates extending theopening 486 through theARC layer 416 to expose portions of thetop surface 414A of thehardmask layer 414.FIG. 6M illustrates removing thedielectric layer 480 and thedielectric layer 418. -
FIG. 6N illustrates extending theopenings hardmask layer 414 to expose portions of thetop surface 412A of theARC layer 412.FIG. 6O illustrates extending theopenings ARC layer 412 to expose portions of thetop surface 410A of theILD 410. -
FIG. 6P illustrates extending theopenings ILD 410 to expose portions of thetop surface 402A of thesubstrate 402.FIG. 6Q illustrates forming aconductive layer 488 in theopenings secondary alignment structures 470 and thehardmask layer 414. Theconductive layer 488 may be formed of similar materials and by similar processes as theconductive layer 122 described above and the description is not repeated herein. -
FIG. 6R illustrates the recessing of theconductive layer 488 to have atop surface 488A lower thantop surfaces 470A of thesecondary alignment structures 470.FIG. 6S illustrates removing thesecondary alignment structures 470 to formopenings 490. Thesecondary alignment structures 470 may be removed by a wet etch process that is selective to thesecondary alignment structures 470.FIG. 6S also illustrates extending theopenings 490 through the ARC layers 416 and 412 and thehardmask layer 414. -
FIG. 6T illustrates forming theopenings 490 partially through theILD 410 and through thehardmasks 406 to exposetop surfaces 404A of thegates 404.FIG. 6U illustrates removing theconductive layer 488 from theopenings top surface 402A of thesubstrate 402 in theopenings conductive layer 488 may be removed by a wet etch process that is selective to theconductive layer 488. -
FIG. 6V illustrates forming aconductive layer 492 in theopenings FIG. 6W illustrates recessing theconductive layer 492 to formconductive features 492 in theopenings 490 contacting thetop surfaces 404A of thegates 404 andconductive features 494 in theopenings top surface 402A of thesubstrate 402. In an embodiment, the recessing is performed by a dry etch process with a plasma source and an etchant gas such as H2, NH3, Ar, He, the like, or a combination thereof. -
FIG. 6X illustrates removing thealignment spacers 468, thehardmask layer 414, theARC layer 412, and the planarization of theILD 410 and theconductive features top surfaces 492A of theconductive features 492, thetop surfaces 494A ofconductive features 494, and thetop surface 410A of theILD 410 are substantially coplanar after the planarization process. The conductive features 492 may be used as contacts to couple thegates 404 to layers above theILD 410 and theconductive features 494 may be used as contacts to couple thesubstrate 402 and devices and metallization layers formed therein to layers aboveILD 410. - The embodiments described above provide self-alignment of conductive contacts and conductive lines between two or more layers. The embodiments include alignment structures and alignment spacers on opposite sides of the alignment structures in layers above the gates. The alignment structures and alignment spacers allow for self-alignment between the alignment spacers of a single alignment structure and for self-alignment between alignment spacers of different alignment structures. Further, by having only spacers surrounding the gates in the ILD layer, the ILD layer is able to be kept clean and free from residue from other spacers and/or hard masks as the alignment structures are formed in ILD layer above the ILD layer containing the gates. Also, the process described above allows the conductive features landing on the gates and on the substrate to be self-aligning.
- An embodiment is a method for forming a semiconductor device, the method including forming at least two gates over a substrate, and forming at least two alignment structures over the at least two gates. The method further includes forming spacers on opposite sidewalls of the at least two alignment structures, and forming a first opening between a pair of the at least two alignment structures, a portion of the first opening exposing a top surface of at least one of the pair, the first opening extending a first distance from a top surface of the substrate. The method further includes filling the first opening with a first conductive material to form a first conductive feature, forming a second opening between the spacers of at least one of the at least two alignment structures, the second opening extending a second distance from the top surface of the substrate, the second distance being different than the first distance, and filling the second opening with a second conductive material to form a second conductive feature.
- Another embodiment is a method of forming a semiconductor device, the method including forming a plurality of gates over a semiconductor substrate, forming a first inter-layer dielectric (ILD) over the plurality of gates, and forming at least two alignment structures over the first ILD. The method further includes forming a second ILD over the at least two alignment structures, forming a first set of conductive contacts through the first and second ILDs to a top surface of the semiconductor substrate, one of the at least two alignment structures being between an adjacent pair of the first set of conductive contacts, and forming a second set of conductive contacts through the second ILD and partially through the first ILD to the plurality of gates, at least one of the second set of contacts extending through one of the alignment structures.
- Yet another embodiment is a method of forming a semiconductor device, the method including forming a plurality of gates on a substrate, forming an inter-layer dielectric (ILD) over the plurality of gates, and forming a first dielectric layer over the ILD. The method further includes forming a first and a second opening in the first dielectric layer, a portion of the first dielectric layer between the first and the second opening forming a primary alignment structure, and forming secondary alignment structures inside the first and second openings. The method further includes forming a first contact through the primary alignment structure and the ILD to a top surface of the substrate, and forming a second contact through one of the secondary alignment structures to a top surface of one of the plurality of gates.
- Although the present embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods, and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims (20)
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US8962464B1 (en) | 2015-02-24 |
US20150171081A1 (en) | 2015-06-18 |
US9356021B2 (en) | 2016-05-31 |
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