US20150069404A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- US20150069404A1 US20150069404A1 US14/185,322 US201414185322A US2015069404A1 US 20150069404 A1 US20150069404 A1 US 20150069404A1 US 201414185322 A US201414185322 A US 201414185322A US 2015069404 A1 US2015069404 A1 US 2015069404A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 239000010410 layer Substances 0.000 claims description 205
- 239000011229 interlayer Substances 0.000 claims description 18
- 238000002161 passivation Methods 0.000 claims description 15
- 229910002601 GaN Inorganic materials 0.000 claims description 14
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 8
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims description 7
- 239000004642 Polyimide Substances 0.000 claims description 6
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 229920001721 polyimide Polymers 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 3
- 239000004033 plastic Substances 0.000 claims description 3
- 230000005669 field effect Effects 0.000 description 8
- 230000003071 parasitic effect Effects 0.000 description 7
- 239000000758 substrate Substances 0.000 description 5
- 238000009413 insulation Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
Definitions
- the present invention relates to a semiconductor device.
- a field effect transistor which controls a current flowing through it with an electric field generated in a material layer, is a switch device widely utilized in circuits made up of semiconductor devices.
- a field effect transistor includes a gate electrode, a source electrode, a drain electrode, and an active layer.
- the source electrode and the drain electrode are located at opposite sides of the active layer.
- a field effect transistor may further include a source pad and a drain pad, which are electrically connected to the source electrode and the drain electrode respectively, to allow the field effect transistor to be electrically connected to another device.
- the source pad and the drain pad usually have large bonding areas to facilitate the bonding of external circuits. With the progress made in semiconductor processing, field effect transistors have become smaller and smaller. Therefore, it is very important to provide a field effect transistor with a well-placed source pad and drain pad so as to provide adequate bonding areas and generate less electrical interference on the field effect transistor itself.
- An aspect of the present invention provides a semiconductor device including an active layer, at least one source electrode, at least one drain electrode, at least one gate electrode, a first insulating layer, a first source pad, a first drain pad, at least one source plug, and at least one drain plug.
- the source electrode is disposed on the active layer, and an orthogonal projection of the source electrode on the active layer forms a source region.
- the drain electrode is disposed on the active layer.
- the drain electrode is separate from the source electrode, and an orthogonal projection of the drain electrode on the active layer forms a drain region.
- the gate electrode is disposed above the active layer and between the source electrode and the drain electrode.
- the first insulating layer at least covers a portion of the source electrode and a portion of the drain electrode.
- the first insulating layer has at least one source via hole and at least one drain via hole within the first insulating layer.
- the first source pad is disposed on the first insulating layer.
- An orthogonal projection of the first source pad on the active layer forms a source pad region.
- the source pad region overlaps at least a portion of the drain region.
- An area of an overlapping region between the source pad region and the drain region is smaller than or equal to 40% of an area of the drain region.
- the first drain pad is disposed on the first insulating layer.
- the source plug is filled in the source via hole and is electrically connected to the first source pad and the source electrode.
- the drain plug is filled in the drain via hole and is electrically connected to the first drain pad and the drain electrode.
- an orthogonal projection of the first drain pad on the active layer forms a drain pad region.
- the drain pad region overlaps at least a portion of the source region, and an area of an overlapping region between the drain pad region and the source region is smaller than or equal to 40% of an area of the source region.
- a resistance value of the first source pad per unit length is smaller than a resistance value of the source electrode per unit length.
- a resistance value of the first drain pad per unit length is smaller than a resistance value of the drain electrode per unit length.
- the orthogonal projection of the source electrode on the active layer, the orthogonal projection of the drain electrode on the active layer, an orthogonal projection of the gate electrode on the active layer, and a region in which current passes through the active layer together define an active area, and at least a portion of the source pad region is within the active area.
- the source pad region is completely within the active area.
- At least a portion of the drain pad region is within the active area.
- the drain pad region is completely within the active area.
- the first source pad includes a source pad body and at least one source pad branch.
- An orthogonal projection of the source pad body on the active layer overlaps at least a portion of the drain region.
- the first drain pad includes a drain pad body and at least one drain pad branch.
- the drain pad body is separate from the source pad body.
- An orthogonal projection of the drain pad body on the active layer overlaps at least a portion of the source region, and the source pad branch extends from the source pad body toward the drain pad body.
- the drain pad branch extends from the drain pad body toward the source pad body.
- the number of the source pad branches is plural.
- the number of the drain pad branches is plural.
- the source pad branches and the drain pad branches are alternately arranged between the source pad body and the drain pad body.
- the semiconductor device further includes a passivation layer covering the active layer.
- the passivation layer has at least one source opening and at least one drain opening within the passivation layer. At least a portion of the source electrode and at least a portion of the drain electrode are respectively disposed in the source opening and the drain opening to electrically electrode the active layer.
- the semiconductor device further includes a gate dielectric layer disposed at least between the gate electrode and the active layer.
- the gate dielectric layer further covers the passivation layer.
- the gate dielectric layer has at least one first inter-source via hole.
- the semiconductor device further includes an interlayer dielectric covering the gate dielectric layer.
- the interlayer dielectric has at least one second inter-source via hole.
- the source electrode further includes a lower sub-source electrode, an upper sub-source electrode, and at least one inter-source plug.
- the lower sub-source electrode is disposed in the source opening.
- the upper sub-source electrode is disposed on the interlayer dielectric.
- the inter-source plug is filled in the first inter-source via hole and the second inter-source via hole and is electrically connected to the upper sub-source electrode and the lower sub-source electrode.
- a resistance value of the upper sub-source electrode per unit length is smaller than a resistance value of the lower sub-source electrode per unit length.
- the gate dielectric layer further covers the passivation layer.
- the gate dielectric layer has at least one first inter-drain via hole.
- the semiconductor device further includes an interlayer dielectric covering the gate dielectric layer.
- the interlayer dielectric has at least one second inter-drain via hole.
- the drain electrode further includes a lower sub-drain electrode, an upper sub-drain electrode, and at least one inter-drain plug.
- the lower sub-drain electrode is disposed in the drain opening.
- the upper sub-drain electrode is disposed on the interlayer dielectric.
- the inter-drain plug is filled in the first inter-drain via hole and the second inter-drain via hole and is electrically connected to the upper sub-drain electrode and the lower sub-drain electrode.
- a resistance value of the upper sub-drain electrode per unit length is smaller than a resistance value of the lower sub-drain electrode per unit length.
- the active layer includes a gallium nitride layer and an aluminum gallium nitride layer.
- the aluminum gallium nitride layer is disposed on the gallium nitride layer.
- the semiconductor device further includes a second insulating layer, a second source pad, a second drain pad, a source pad connection portion, and a drain pad connection portion.
- the second insulating layer is disposed on the first source pad, the first drain pad, and the first insulating layer.
- the second insulating layer has a source pad opening and a drain pad opening to respectively expose a portion of the first source pad and a portion of the first drain pad, and the second insulating layer has a thickness greater than 7 ⁇ m.
- the second source pad is disposed on the second insulating layer.
- the second drain pad is separate from the second source pad and is disposed on the second insulating layer.
- the source pad connection portion is disposed in the source pad opening and is electrically connected to the first source pad and the second source pad.
- the drain pad connection portion is disposed in the drain pad opening and is electrically connected to the first drain pad and the second drain pad.
- a material of the second insulating layer includes polyimide (PI), photoresist (PR), benzo cyclo butane (BCB), spin on glass (SOG), plastic, or their combinations.
- Another aspect of the present invention provides a semiconductor device including an active layer, at least one source electrode, at least one drain electrode, at least one gate electrode, a first insulating layer, a first source pad, a first drain pad, at least one source plug, and at least one drain plug.
- the source electrode is disposed on the active layer, and an orthogonal projection of the source electrode on the active layer forms a source region.
- the drain electrode is disposed on the active layer.
- the drain electrode is separate from the source electrode, and an orthogonal projection of the drain electrode on the active layer forms a drain region.
- the gate electrode is disposed above the active layer and between the source electrode and the drain electrode.
- the first insulating layer at least covers a portion of the source electrode and a portion of the drain electrode.
- the first insulating layer has at least one source via hole and at least one drain via hole within the first insulating layer.
- the first source pad is disposed on the first insulating layer.
- the first drain pad is disposed on the first insulating layer.
- An orthogonal projection of the first drain pad on the active layer forms a drain pad region.
- the drain pad region overlaps portion of the source region, and an area of an overlapping region between the drain pad region and the source region is smaller than or equal to 40% of an area of the source region.
- the source plug is filled in the source via hole and is electrically connected to the first source pad and the source electrode.
- the drain plug is filled in the drain via hole and is electrically connected to the first drain pad and the drain electrode.
- FIG. 1 is a top view of a semiconductor device according to a first embodiment of the present invention
- FIG. 2A is a cross-sectional view taken along line 2 A- 2 A of FIG. 1 ;
- FIG. 2B is a cross-sectional view taken along line 2 B- 2 B of FIG. 1 ;
- FIG. 2C is a cross-sectional view taken along line 2 C- 2 C of FIG. 1 ;
- FIG. 3 is a top view of a semiconductor device according to a second embodiment of the present invention.
- FIG. 4 is a top view of a semiconductor device according to a third embodiment of the present invention.
- FIG. 5A is a cross-sectional view taken along line 5 A- 5 A of FIG. 4 ;
- FIG. 5B is a cross-sectional view taken along line 5 B- 5 B of FIG. 4 ;
- FIG. 5C is a cross-sectional view taken along line 5 C- 5 C of FIG. 4 ;
- FIG. 6 is a top view of a semiconductor device according to a fourth embodiment of the present invention.
- FIG. 7A is a cross-sectional view taken along line 7 A- 7 A of FIG. 6 ;
- FIG. 7B is a cross-sectional view taken along line 7 B- 7 B of FIG. 6 ;
- FIG. 7C is a cross-sectional view taken along line 7 C- 7 C of FIG. 6 ;
- FIG. 7D is a cross-sectional view taken along line 7 D- 7 D of FIG. 6 .
- FIG. 1 is a top view of a semiconductor device according to a first embodiment of the present invention.
- FIG. 2A is a cross-sectional view taken along line 2 A- 2 A of FIG. 1 .
- the semiconductor device includes an active layer 100 , at least one gate electrode 150 , at least one source electrode 200 , at least one drain electrode 250 , a gate dielectric layer 300 , a first insulating layer 350 , a first source pad 400 , a first drain pad 450 , at least one source plug 500 , and at least one drain plug 550 .
- the source electrode 200 is disposed on the active layer 100 , and an orthogonal projection of the source electrode 200 on the active layer 100 forms a source region 202 .
- the drain electrode 250 is disposed on the active layer 100 .
- the drain electrode 250 is separate from the source electrode 200 , and an orthogonal projection of the drain electrode 250 on the active layer 100 forms a drain region 252 .
- the gate electrode 150 is disposed above the active layer 100 and between the source electrode 200 and the drain electrode 250 .
- the gate dielectric layer 300 is disposed at least between the gate electrode 150 and the active layer 100 .
- the first insulating layer 350 at least covers a portion of the source electrode 200 and a portion of the drain electrode 250 . For example in FIG. 2A , the first insulating layer 350 covers the gate electrode 150 , the source electrode 200 , the drain electrode 250 , and the gate dielectric layer 300 .
- the semiconductor device further includes a gate pad (not shown), and the gate pad is electrically connected to the plurality of gate electrodes 150 .
- the first insulating layer 350 has at least one source via hole 360 .
- a shape of the source via hole 360 may be different depending on process requirements.
- the source via hole 360 may be formed in the shape of a circle, a rectangle, a polygon, an arc, or their combinations.
- the first source pad 400 is disposed on the first insulating layer 350 , and an orthogonal projection of the first source pad 400 on the active layer 100 forms a source pad region 402 .
- the source pad region 402 overlaps at least a portion of the drain region 252 , and an area of an overlapping region O1 between the source pad region 402 and the drain region 252 is smaller than or equal to 40% of an area of the drain region 252 .
- the overlapping region O1 has a length L1 and the drain electrode 250 has a length L2, and the length L1 is less than or equal to 40% of the length L2.
- the source plug 500 is filled in the source via hole 360 and electrically connected to the first source pad 400 and the source electrode 200 .
- the first insulating layer 350 further has at least one drain via hole 370 within it.
- the first drain pad 450 is disposed on the first insulating layer 350 , and an orthogonal projection of the first drain pad 450 on the active layer 100 forms a drain pad region 452 .
- the drain pad region 452 overlaps at least a portion of the source region 202 , and an area of an overlapping region O2 between the drain pad region 452 and the source region 202 is smaller than or equal to 40% of an area of the source region 202 .
- the overlapping region O2 has a length L3 and the source electrode 200 has the length L2, and the length L3 is less than or equal to 40% of the length L2.
- the drain plug 550 is filled in the drain via hole 370 and electrically connected to the first drain pad 450 and the drain electrode 250 .
- both the source plug 500 and the drain plug 550 are only depicted in the cross-sectional view and not in the top view.
- the overlapping region O1 is formed between the source pad region 402 and the drain region 252
- the overlapping region O2 is formed between the drain pad region 452 and the source region 202 .
- at least a portion of the first source pad 400 is above the drain electrode 250 and at least a portion of the first drain pad 450 is above the source electrode 200 .
- the semiconductor device size can shrink to increase the area utilization ratio of the active layer 100 .
- the term area utilization ratio refers to the ratio of the area of the active layer 100 through which on currents flowing between the source electrodes 200 and the drain electrodes 250 actually pass to the area of the active layer 100 that is available for currents to pass through in the semiconductor device according to the present embodiment.
- the area of the overlapping region O1 is smaller than or equal to 40% of the area of the drain region 252 and the area of an overlapping region O2 is smaller than or equal to 40% of the area of the source region 202 , parasitic capacitances generated between the first source pad 400 and the drain electrode 250 and between the first drain pad 450 and the source electrode 200 are effectively reduced.
- the area of the overlapping region O1 is greater than 1% of the area of the drain region 252 and smaller than 20% of the area of the drain region 252 .
- the area of the overlapping region O2 is greater than 1% of the area of the source region 202 and smaller than 20% of the area of the source region 202 .
- the first source pad 400 includes a source pad body 410 and at least one source pad branch 420 .
- a direction of the source pad body 410 is approximately perpendicular to an elongation direction of the source electrode 200
- an elongation direction of the source pad branch 420 is approximately parallel to the elongation direction of the source electrode 200 .
- An orthogonal projection of the source pad body 410 on the active layer 100 overlaps at least a portion of the drain region 252 , such as the overlapping region O1 in FIG. 1 .
- the first drain pad 450 includes a drain pad body 460 and at least one drain pad branch 470 .
- a direction of the drain pad body 460 is approximately perpendicular to an elongation direction of the drain electrode 250
- an elongation direction of the drain pad branch 470 is approximately parallel to the elongation direction of the drain electrode 250 .
- the drain pad body 460 is separate from the source pad body 410 .
- An orthogonal projection of the drain pad body 460 on the active layer 100 overlaps at least a portion of the source region 202 , such as the overlapping region O2 in FIG. 1 .
- the source pad branch 420 extends from the source pad body 410 toward the drain pad body 460 .
- the drain pad branch 470 extends from the drain pad body 460 toward the source pad body 410 .
- the source pad branch 420 in addition to being strip-shaped, may be wave-shaped, zigzag-shaped, irregularly shaped, or some combination thereof, and the source pad branch 420 extends from the source pad body 410 toward the drain pad body 460 .
- a shape of the drain pad branch 470 may be different depending on product design, and the drain pad branch 470 extends outward from the source pad body 410 or the drain pad body 460 .
- the first source pad 400 or the first drain pad 450 may be electrically connected to external circuits through other conductive devices, such as a bonding wire, a ribbon, a chip, etc., to enable the operation of circuits.
- an orthogonal projection of the source pad branch 420 on the active layer 100 overlaps at least a portion of the source electrode 200 .
- the source plugs 500 may be disposed between the source pad branch 420 and the source electrode 200 to provide an adequate electrical connection between the first source pad 400 and the source electrode 200 .
- a resistance value of the source electrode 200 itself is improved.
- a resistance value of the first source pad 400 per unit length is smaller than a resistance value of the source electrode 200 per unit length (for example in FIG. 2A , a thickness T3 of the first source pad 400 is greater than a thickness T2 of the source electrode 200 )
- the resistance value of the source electrode 200 itself is also improved.
- an orthogonal projection of the drain pad branch 470 on the active layer 100 overlaps at least a portion of the drain electrode 250 .
- the drain plugs 550 may be disposed between the drain pad branch 470 and the drain electrode 250 to provide an adequate electrical connection between the first drain pad 450 and the drain electrode 250 .
- a resistance value of the drain electrode 250 itself is improved.
- a resistance value of the first drain pad 450 per unit length is smaller than a resistance value of the drain electrode 250 per unit length (for example in FIG. 2A , a thickness T3 of the first drain pad 450 is greater than a thickness T2 of the drain electrode 250 )
- the resistance value of the drain electrode 250 itself is also improved.
- FIG. 2B is a cross-sectional view taken along line 2 B- 2 B of FIG. 1 .
- the source plugs 500 may be disposed between the source pad body 410 and the source electrode 200 to provide an adequate electrical connection between the source pad body 410 and the source electrode 200 .
- the source pad body 410 is electrically isolated from the drain electrode 250 , no plug exists between the source pad body 410 and the drain electrode 250 (that is, the portion of the first insulating layer 350 above the overlapping region O1).
- FIG. 2C is a cross-sectional view taken along line 2 C- 2 C of FIG. 1 .
- the drain plugs 550 may also be disposed between the drain pad body 460 and the drain electrode 250 to provide an adequate electrical connection between the drain pad body 460 and the drain electrode 250 .
- the drain pad body 460 is electrically isolated from the source electrode 200 , no plug exists between the drain pad body 460 and the source electrode 200 (that is, the portion of the first insulating layer 350 above the overlapping region O2).
- the first source pad 400 is electrically connected to the source electrodes 200 through the source pad branches 420 and a portion of the source pad body 410 .
- a sufficient amount of current can flow between the first source pad 400 and the source electrodes 200 to improve the resistance value of the source electrodes 200 .
- the first drain pad 450 is electrically connected to the drain electrodes 250 through the drain pad branches 470 and a portion of the drain pad body 460 . With such a configuration, a sufficient amount of current can flow between the first drain pad 450 and the drain electrodes 250 to improve the resistance value of the drain electrodes 250 .
- the source electrode 200 , the drain electrode 250 , and the gate electrode 150 together define an active area 102 .
- the active area 102 includes the source region 202 , the drain region 252 , and the region between the source region 202 and the drain region 252 in which current passes through the active layer 100 .
- the semiconductor device further includes an insulation area 600 surrounding the active area 102 , and at least a portion of the insulation area 600 is located in the active layer 100 to prevent leakage currents from being generated, and thus to increase the breakdown voltage.
- the first source pad 400 and the first drain pad 450 are completely within the active area 102 .
- the semiconductor device can be cut along the insulation area 600 according to the present embodiment.
- the vast majority of the active area 102 is put to good use and it is not necessary to add extra regions to the non-active area for accommodating source pads and drain pads.
- the size of the semiconductor device is effectively reduced, or a semiconductor device is fabricated that is able to sustain a higher breakdown voltage or a larger on current with the same device size.
- the active layer 100 includes a plurality of different nitride-based semiconductor layers to allow two-dimensional electron gas (2DEG) to be generated at the heterojunction so as to create a conducting path.
- 2DEG two-dimensional electron gas
- a stack structure made up of a gallium nitride (GaN) layer 110 and an aluminum gallium nitride (AlGaN) layer 120 may be utilized, and the aluminum gallium nitride layer 120 is disposed on the gallium nitride layer 110 .
- GaN gallium nitride
- AlGaN aluminum gallium nitride
- the active layer 100 may be selectively disposed on a substrate 50 .
- the substrate 50 may be a silicon substrate or a sapphire substrate, but the invention is not limited in this respect.
- the semiconductor device may further include a buffer layer disposed between the active layer 100 and the substrate 50 .
- the number of the source electrodes 200 and the number of the drain electrodes 250 are both plural.
- the source electrodes 200 are alternately arranged with the drain electrodes 250 to increase the amount of the on current flowing through the semiconductor device.
- the number of the source pad branches 420 may be plural, and the number of the drain pad branches 470 may also be plural.
- the source pad branches 420 and the drain pad branches 470 are alternately arranged between the source pad body 410 and the drain pad body 460 . All the source pad branches 420 are over the source electrodes 200 , and all the drain pad branches 470 are over the drain electrodes 250 .
- the first source pad 400 and the first drain pad 450 are both in the shape of a finger.
- the semiconductor device may further include a passivation layer 650 which covers the active layer 100 .
- the passivation layer 650 has at least one source opening 660 and at least one drain opening 670 within it. At least a portion of the source electrode 200 and at least a portion of the drain electrode 250 are respectively disposed in the source opening 660 and the drain opening 670 .
- the source electrode 200 and the drain electrode 250 are respectively disposed in the source opening 660 and the drain opening 670 to electrically electrode the active layer 100 .
- the gate dielectric layer 300 may selectively cover the passivation layer 650 , and the gate dielectric layer 300 has at least one first inter-source via hole 310 and at least one first inter-drain via hole 320 .
- a portion of the source plug 500 is filled in the first inter-source via hole 310 to electrically interconnect the first source pad 400 and the source electrode 200 .
- a portion of the drain plug 550 is filled in the first inter-drain via hole 320 to electrically interconnect the first drain pad 450 and the drain electrode 250 .
- the passivation layer 650 has at least one gate opening 680 within it.
- the gate electrode 150 and the gate dielectric layer 300 cover the gate opening 680 in a manner conforming to the shape of the gate opening 680 .
- the presence of the gate opening 680 can function to adjust the electrical characteristics of the gate electrode 150 .
- the passivation layer 650 may not have the gate opening 680 , and the invention is not limited in this respect.
- the amount of parasitic capacitance generated in the present invention structure is 20% of that generated in the traditional vertical circuit layout structure.
- the resistivities of the source electrode 200 , the drain electrode 250 , the first source pad 400 , and the first drain pad 450 are all p.
- the resistance values of the source electrode 200 and the drain electrode 250 per unit length are much greater than the resistance values of the first source pad 400 and the first drain pad 450 per unit length, effects contributed by the source electrode 200 and the drain electrode 250 can be negligible when calculating the total effects in areas where the first source pad 400 and the first drain pad 450 are located to thereby simplify the calculation.
- FIG. 3 is a top view of a semiconductor device according to a second embodiment of the present invention.
- the semiconductor device in the present embodiment differs from the semiconductor device in the first embodiment with respect to positions of the first source pad 400 and the first drain pad 450 .
- at least a portion of the source pad region 402 formed by the first source pad 400 on the active layer 100 is outside the active area 102
- at least a portion of the drain pad region 452 formed by the first drain pad 450 on the active layer 100 is outside the active area 102 .
- the source pad region 402 and the drain pad region 452 are both within the active area 102 .
- both a portion of the source pad region 402 and the drain pad region 252 are outside the active area 102 .
- the source pad region 402 may be within the active area 102 and a portion of the drain pad region 452 may be outside the active area 102 , and vice versa.
- FIG. 4 is a top view of a semiconductor device according to a third embodiment of the present invention.
- FIG. 5A is a cross-sectional view taken along line 5 A- 5 A of FIG. 1 .
- the present embodiment differs from the first embodiment with respect to structures of the source electrode 200 and the drain electrode 250 and the disposition of an interlayer dielectric 700 .
- the semiconductor device further includes the interlayer dielectric 700 that covers the gate dielectric layer 300 .
- the interlayer dielectric 700 has at least one second inter-source via hole 710 .
- the source electrode 200 includes a lower sub-source electrode 210 , an upper sub-source electrode 200 , and at least one inter-source plug 230 .
- the lower sub-source electrode 210 is disposed in the source opening 660
- the upper sub-source electrode 220 is disposed on the interlayer dielectric 700 .
- the inter-source plug 230 is filled in the first inter-source via hole 310 and the second inter-source via hole 710 , and electrically connected to the upper sub-source electrode 220 and the lower sub-source electrode 210 .
- the interlayer dielectric 700 has at least one second inter-drain via hole 720 .
- the drain electrode 250 includes a lower sub-drain electrode 260 , an upper sub-drain electrode 270 , and at least one inter-drain plug 280 .
- the lower sub-drain electrode 260 is disposed in the drain opening 670
- the upper sub-drain electrode 270 is disposed on the interlayer dielectric 700 .
- the inter-drain plug 280 is filled in the first inter-drain via hole 320 and the second inter-drain via hole 720 and electrically connected to the upper sub-drain electrode 270 and the lower sub-drain electrode 260 .
- the lower sub-source electrode 210 of the source electrode 200 directly electrodes the active layer 100 and may be an ohmic electrode having a large resistance value per unit length.
- the upper sub-source electrode 220 that has a resistance value per unit length smaller than the resistance value of the lower sub-source electrode 210 per unit length is added over the lower sub-source electrode 210 .
- the overall resistance value of the source electrode 200 is reduced by electrically connecting the upper sub-source electrode 220 to the lower sub-source electrode 210 .
- the lower sub-drain electrode 260 of the drain electrode 250 directly electrodes the active layer 100 and may be an ohmic electrode having a large resistance value per unit length.
- the upper sub-drain electrode 270 that has a resistance value per unit length smaller than the resistance value of the lower sub-drain electrode 260 per unit length is added over the lower sub-drain electrode 260 .
- the overall resistance value of the drain electrode 250 is reduced by electrically connecting the upper sub-drain electrode 270 to the lower sub-drain electrode 260 .
- FIG. 5B is a cross-sectional view taken along line 5 B- 5 B of FIG. 4 .
- the source pad body 410 is electrically connected to the upper sub-source electrode 220 through the source plugs 500 .
- the upper sub-source electrode 220 and the lower sub-source electrode 210 below the source pad body 410 are electrically connected through the inter-source plugs 230 .
- the upper sub-drain electrode 270 and the lower sub-drain electrode 260 below the source pad body 410 are electrically connected through the inter-drain plugs 280 .
- a sufficient amount of current can flow between the upper sub-drain electrode 270 and the lower sub-drain electrode 260 .
- FIG. 5C is a cross-sectional view taken along line 5 C- 5 C of FIG. 4 .
- the drain pad body 460 is electrically connected to the upper sub-drain electrode 270 through the drain plugs 550 .
- the upper sub-drain electrode 270 and the lower sub-drain electrode 260 below the drain pad body 460 are electrically connected through the inter-drain plugs 280 .
- the inter-drain plugs 280 Hence, a sufficient amount of current can flow between the drain electrode 250 and the drain pad body 460 .
- the upper sub-source electrode 220 and the lower sub-source electrode 210 below the drain pad body 460 are electrically connected through the inter-source plugs 230 .
- a sufficient amount of current can flow between the upper sub-source electrode 220 and the lower sub-source electrode 210 . Since other details of the present embodiment are the same as those in the first embodiment, a further description in this regard is not provided.
- FIG. 6 is a top view of a semiconductor device according to a fourth embodiment of the present invention.
- FIG. 7A is a cross-sectional view taken along line 7 A- 7 A of FIG. 6 .
- FIG. 7B is a cross-sectional view taken along line 7 B- 7 B of FIG. 6 .
- FIG. 7C is a cross-sectional view taken along line 7 C- 7 C of FIG. 6 .
- FIG. 7D is a cross-sectional view taken along line 7 D- 7 D of FIG. 6 .
- the present embodiment differs from the first embodiment with respect to the disposition of a second insulating layer 750 , a second source pad 800 , a second drain pad 850 , a source pad connection portion 900 , and a drain pad connection portion 950 .
- the second insulating layer 750 is disposed on the first source pad 400 and the first insulating layer 350 .
- the second insulating layer 750 has a source pad opening 760 to expose a portion of the first source pad 400 , and the second insulating layer 750 has a thickness T4 greater than 7 ⁇ m.
- the second source pad 800 is disposed on the second insulating layer 750 .
- the source pad connection portion 900 is disposed in the source pad opening 760 and is electrically connected to the first source pad 400 and the second source pad 800 . As shown in FIG.
- the second source pad 800 and the first source pad 400 are electrically connected through the source pad connection portion 900 .
- the capacitance value of the parasitic capacitance is not large because the thickness T4 of the second insulating layer 750 is greater than 7 ⁇ m.
- an area of a region 802 formed by an orthogonal projection of the second source pad 800 on the active layer 100 may be greater than an area of the region formed by the orthogonal projection of the source pad body 410 on the active layer 100 to facilitate connection with external circuits.
- the second insulating layer 750 is further disposed on the first drain pad 450 .
- the second insulating layer 750 has a drain pad opening 770 to expose a portion of the first drain pad 450 .
- the second drain pad 850 is separate from the second source pad 800 and is disposed on the second insulating layer 750 .
- the drain pad connection portion 950 is disposed in the drain pad opening 770 and is electrically connected to the first drain pad 450 and the second drain pad 850 .
- the second drain pad 850 and the first drain pad 450 are electrically connected through the drain pad connection portion 950 .
- FIG. 7B the drain pad 850 and the first drain pad 450 are electrically connected through the drain pad connection portion 950 .
- an area of a region 852 formed by an orthogonal projection of the second drain pad 850 on the active layer 100 may be greater than an area of the region formed by the orthogonal projection of the drain pad body 460 on the active layer 100 to facilitate connection with external circuits.
- a material of the second insulating layer 750 includes polyimide (PI), photoresist (PR), benzo cyclo butane (BCB), spin on glass (SOG), plastic, or their combinations.
- the second insulating layer 750 may be formed on the first source pad 400 , the first drain pad 450 , and the first insulating layer 350 by, for example, spin coating, but the invention is not limited in this respect. Since other details of the present embodiment are the same as those in the first embodiment, a further description in this regard is not provided.
- the second insulating layer 750 , the second source pad 800 , the second drain pad 850 , the source pad connection portion 900 , and the drain pad connection portion 950 are all disposed on the semiconductor device of the first embodiment.
- the second insulating layer 750 , the second source pad 800 , the second drain pad 850 , the source pad connection portion 900 , and the drain pad connection portion 950 may be disposed on the semiconductor device of the second embodiment or the third embodiment.
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Abstract
Description
- This application claims priority to Taiwan Application Serial Number 102132512, filed Sep. 10, 2013, which is herein incorporated by reference.
- 1. Field of Invention
- The present invention relates to a semiconductor device.
- 2. Description of Related Art
- A field effect transistor, which controls a current flowing through it with an electric field generated in a material layer, is a switch device widely utilized in circuits made up of semiconductor devices. In greater detail, a field effect transistor includes a gate electrode, a source electrode, a drain electrode, and an active layer. The source electrode and the drain electrode are located at opposite sides of the active layer. By controlling the voltage applied to the gate electrode, the electric field in the active layer is affected to allow current to flow from the source electrode to the drain electrode. As a result, the field effect transistor is in an on state.
- Generally speaking, a field effect transistor may further include a source pad and a drain pad, which are electrically connected to the source electrode and the drain electrode respectively, to allow the field effect transistor to be electrically connected to another device. The source pad and the drain pad usually have large bonding areas to facilitate the bonding of external circuits. With the progress made in semiconductor processing, field effect transistors have become smaller and smaller. Therefore, it is very important to provide a field effect transistor with a well-placed source pad and drain pad so as to provide adequate bonding areas and generate less electrical interference on the field effect transistor itself.
- An aspect of the present invention provides a semiconductor device including an active layer, at least one source electrode, at least one drain electrode, at least one gate electrode, a first insulating layer, a first source pad, a first drain pad, at least one source plug, and at least one drain plug. The source electrode is disposed on the active layer, and an orthogonal projection of the source electrode on the active layer forms a source region. The drain electrode is disposed on the active layer. The drain electrode is separate from the source electrode, and an orthogonal projection of the drain electrode on the active layer forms a drain region. The gate electrode is disposed above the active layer and between the source electrode and the drain electrode. The first insulating layer at least covers a portion of the source electrode and a portion of the drain electrode. The first insulating layer has at least one source via hole and at least one drain via hole within the first insulating layer. The first source pad is disposed on the first insulating layer. An orthogonal projection of the first source pad on the active layer forms a source pad region. The source pad region overlaps at least a portion of the drain region. An area of an overlapping region between the source pad region and the drain region is smaller than or equal to 40% of an area of the drain region. The first drain pad is disposed on the first insulating layer. The source plug is filled in the source via hole and is electrically connected to the first source pad and the source electrode. The drain plug is filled in the drain via hole and is electrically connected to the first drain pad and the drain electrode.
- In one or more embodiments, an orthogonal projection of the first drain pad on the active layer forms a drain pad region. The drain pad region overlaps at least a portion of the source region, and an area of an overlapping region between the drain pad region and the source region is smaller than or equal to 40% of an area of the source region.
- In one or more embodiments, a resistance value of the first source pad per unit length is smaller than a resistance value of the source electrode per unit length.
- In one or more embodiments, a resistance value of the first drain pad per unit length is smaller than a resistance value of the drain electrode per unit length.
- In one or more embodiments, the orthogonal projection of the source electrode on the active layer, the orthogonal projection of the drain electrode on the active layer, an orthogonal projection of the gate electrode on the active layer, and a region in which current passes through the active layer together define an active area, and at least a portion of the source pad region is within the active area.
- In one or more embodiments, the source pad region is completely within the active area.
- In one or more embodiments, at least a portion of the drain pad region is within the active area.
- In one or more embodiments, the drain pad region is completely within the active area.
- In one or more embodiments, the first source pad includes a source pad body and at least one source pad branch. An orthogonal projection of the source pad body on the active layer overlaps at least a portion of the drain region.
- In one or more embodiments, the first drain pad includes a drain pad body and at least one drain pad branch. The drain pad body is separate from the source pad body. An orthogonal projection of the drain pad body on the active layer overlaps at least a portion of the source region, and the source pad branch extends from the source pad body toward the drain pad body. The drain pad branch extends from the drain pad body toward the source pad body.
- In one or more embodiments, the number of the source pad branches is plural. The number of the drain pad branches is plural. The source pad branches and the drain pad branches are alternately arranged between the source pad body and the drain pad body.
- In one or more embodiments, the semiconductor device further includes a passivation layer covering the active layer. The passivation layer has at least one source opening and at least one drain opening within the passivation layer. At least a portion of the source electrode and at least a portion of the drain electrode are respectively disposed in the source opening and the drain opening to electrically electrode the active layer.
- In one or more embodiments, the semiconductor device further includes a gate dielectric layer disposed at least between the gate electrode and the active layer.
- In one or more embodiments, the gate dielectric layer further covers the passivation layer. The gate dielectric layer has at least one first inter-source via hole. The semiconductor device further includes an interlayer dielectric covering the gate dielectric layer. The interlayer dielectric has at least one second inter-source via hole. The source electrode further includes a lower sub-source electrode, an upper sub-source electrode, and at least one inter-source plug. The lower sub-source electrode is disposed in the source opening. The upper sub-source electrode is disposed on the interlayer dielectric. The inter-source plug is filled in the first inter-source via hole and the second inter-source via hole and is electrically connected to the upper sub-source electrode and the lower sub-source electrode.
- In one or more embodiments, a resistance value of the upper sub-source electrode per unit length is smaller than a resistance value of the lower sub-source electrode per unit length.
- In one or more embodiments, the gate dielectric layer further covers the passivation layer. The gate dielectric layer has at least one first inter-drain via hole. The semiconductor device further includes an interlayer dielectric covering the gate dielectric layer. The interlayer dielectric has at least one second inter-drain via hole. The drain electrode further includes a lower sub-drain electrode, an upper sub-drain electrode, and at least one inter-drain plug. The lower sub-drain electrode is disposed in the drain opening. The upper sub-drain electrode is disposed on the interlayer dielectric. The inter-drain plug is filled in the first inter-drain via hole and the second inter-drain via hole and is electrically connected to the upper sub-drain electrode and the lower sub-drain electrode.
- In one or more embodiments, a resistance value of the upper sub-drain electrode per unit length is smaller than a resistance value of the lower sub-drain electrode per unit length.
- In one or more embodiments, the active layer includes a gallium nitride layer and an aluminum gallium nitride layer. The aluminum gallium nitride layer is disposed on the gallium nitride layer.
- In one or more embodiments, the semiconductor device further includes a second insulating layer, a second source pad, a second drain pad, a source pad connection portion, and a drain pad connection portion. The second insulating layer is disposed on the first source pad, the first drain pad, and the first insulating layer. The second insulating layer has a source pad opening and a drain pad opening to respectively expose a portion of the first source pad and a portion of the first drain pad, and the second insulating layer has a thickness greater than 7 μm. The second source pad is disposed on the second insulating layer. The second drain pad is separate from the second source pad and is disposed on the second insulating layer. The source pad connection portion is disposed in the source pad opening and is electrically connected to the first source pad and the second source pad. The drain pad connection portion is disposed in the drain pad opening and is electrically connected to the first drain pad and the second drain pad.
- In one or more embodiments, a material of the second insulating layer includes polyimide (PI), photoresist (PR), benzo cyclo butane (BCB), spin on glass (SOG), plastic, or their combinations.
- Another aspect of the present invention provides a semiconductor device including an active layer, at least one source electrode, at least one drain electrode, at least one gate electrode, a first insulating layer, a first source pad, a first drain pad, at least one source plug, and at least one drain plug. The source electrode is disposed on the active layer, and an orthogonal projection of the source electrode on the active layer forms a source region. The drain electrode is disposed on the active layer. The drain electrode is separate from the source electrode, and an orthogonal projection of the drain electrode on the active layer forms a drain region. The gate electrode is disposed above the active layer and between the source electrode and the drain electrode. The first insulating layer at least covers a portion of the source electrode and a portion of the drain electrode. The first insulating layer has at least one source via hole and at least one drain via hole within the first insulating layer. The first source pad is disposed on the first insulating layer. The first drain pad is disposed on the first insulating layer. An orthogonal projection of the first drain pad on the active layer forms a drain pad region. The drain pad region overlaps portion of the source region, and an area of an overlapping region between the drain pad region and the source region is smaller than or equal to 40% of an area of the source region. The source plug is filled in the source via hole and is electrically connected to the first source pad and the source electrode. The drain plug is filled in the drain via hole and is electrically connected to the first drain pad and the drain electrode.
-
FIG. 1 is a top view of a semiconductor device according to a first embodiment of the present invention; -
FIG. 2A is a cross-sectional view taken alongline 2A-2A ofFIG. 1 ; -
FIG. 2B is a cross-sectional view taken alongline 2B-2B ofFIG. 1 ; -
FIG. 2C is a cross-sectional view taken alongline 2C-2C ofFIG. 1 ; -
FIG. 3 is a top view of a semiconductor device according to a second embodiment of the present invention; -
FIG. 4 is a top view of a semiconductor device according to a third embodiment of the present invention; -
FIG. 5A is a cross-sectional view taken alongline 5A-5A ofFIG. 4 ; -
FIG. 5B is a cross-sectional view taken alongline 5B-5B ofFIG. 4 ; -
FIG. 5C is a cross-sectional view taken alongline 5C-5C ofFIG. 4 ; -
FIG. 6 is a top view of a semiconductor device according to a fourth embodiment of the present invention; -
FIG. 7A is a cross-sectional view taken alongline 7A-7A ofFIG. 6 ; -
FIG. 7B is a cross-sectional view taken alongline 7B-7B ofFIG. 6 ; -
FIG. 7C is a cross-sectional view taken alongline 7C-7C ofFIG. 6 ; and -
FIG. 7D is a cross-sectional view taken alongline 7D-7D ofFIG. 6 . - Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. The practical details of the invention will be described below. However, it should be understood that such description is only to illustrate and not to limit the scope of the invention. That is, in some embodiments of the invention, the practical details are not necessary. In addition, for the sake of simplifying the drawings, known structures and components will be depicted schematically.
-
FIG. 1 is a top view of a semiconductor device according to a first embodiment of the present invention.FIG. 2A is a cross-sectional view taken alongline 2A-2A ofFIG. 1 . The semiconductor device includes anactive layer 100, at least onegate electrode 150, at least onesource electrode 200, at least onedrain electrode 250, agate dielectric layer 300, a first insulatinglayer 350, afirst source pad 400, afirst drain pad 450, at least onesource plug 500, and at least onedrain plug 550. Thesource electrode 200 is disposed on theactive layer 100, and an orthogonal projection of thesource electrode 200 on theactive layer 100 forms asource region 202. Thedrain electrode 250 is disposed on theactive layer 100. Thedrain electrode 250 is separate from thesource electrode 200, and an orthogonal projection of thedrain electrode 250 on theactive layer 100 forms adrain region 252. Thegate electrode 150 is disposed above theactive layer 100 and between thesource electrode 200 and thedrain electrode 250. Thegate dielectric layer 300 is disposed at least between thegate electrode 150 and theactive layer 100. The first insulatinglayer 350 at least covers a portion of thesource electrode 200 and a portion of thedrain electrode 250. For example inFIG. 2A , the first insulatinglayer 350 covers thegate electrode 150, thesource electrode 200, thedrain electrode 250, and thegate dielectric layer 300. The semiconductor device further includes a gate pad (not shown), and the gate pad is electrically connected to the plurality ofgate electrodes 150. - The first insulating
layer 350 has at least one source viahole 360. A shape of the source viahole 360 may be different depending on process requirements. For example, the source viahole 360 may be formed in the shape of a circle, a rectangle, a polygon, an arc, or their combinations. Thefirst source pad 400 is disposed on the first insulatinglayer 350, and an orthogonal projection of thefirst source pad 400 on theactive layer 100 forms asource pad region 402. Thesource pad region 402 overlaps at least a portion of thedrain region 252, and an area of an overlapping region O1 between thesource pad region 402 and thedrain region 252 is smaller than or equal to 40% of an area of thedrain region 252. For example inFIG. 1 , the overlapping region O1 has a length L1 and thedrain electrode 250 has a length L2, and the length L1 is less than or equal to 40% of the length L2. The source plug 500 is filled in the source viahole 360 and electrically connected to thefirst source pad 400 and thesource electrode 200. - The first insulating
layer 350 further has at least one drain viahole 370 within it. Thefirst drain pad 450 is disposed on the first insulatinglayer 350, and an orthogonal projection of thefirst drain pad 450 on theactive layer 100 forms adrain pad region 452. Thedrain pad region 452 overlaps at least a portion of thesource region 202, and an area of an overlapping region O2 between thedrain pad region 452 and thesource region 202 is smaller than or equal to 40% of an area of thesource region 202. For example inFIG. 1 , the overlapping region O2 has a length L3 and thesource electrode 200 has the length L2, and the length L3 is less than or equal to 40% of the length L2. Thedrain plug 550 is filled in the drain viahole 370 and electrically connected to thefirst drain pad 450 and thedrain electrode 250. For the sake of clarity, it is worth noting that both the source plug 500 and thedrain plug 550 are only depicted in the cross-sectional view and not in the top view. - As mentioned previously, the overlapping region O1 is formed between the
source pad region 402 and thedrain region 252, and the overlapping region O2 is formed between thedrain pad region 452 and thesource region 202. In other words, at least a portion of thefirst source pad 400 is above thedrain electrode 250 and at least a portion of thefirst drain pad 450 is above thesource electrode 200. With this configuration, the semiconductor device size can shrink to increase the area utilization ratio of theactive layer 100. The term area utilization ratio refers to the ratio of the area of theactive layer 100 through which on currents flowing between thesource electrodes 200 and thedrain electrodes 250 actually pass to the area of theactive layer 100 that is available for currents to pass through in the semiconductor device according to the present embodiment. Since the area of the overlapping region O1 is smaller than or equal to 40% of the area of thedrain region 252 and the area of an overlapping region O2 is smaller than or equal to 40% of the area of thesource region 202, parasitic capacitances generated between thefirst source pad 400 and thedrain electrode 250 and between thefirst drain pad 450 and thesource electrode 200 are effectively reduced. In another embodiment of the present invention, the area of the overlapping region O1 is greater than 1% of the area of thedrain region 252 and smaller than 20% of the area of thedrain region 252. The area of the overlapping region O2 is greater than 1% of the area of thesource region 202 and smaller than 20% of the area of thesource region 202. - With reference to
FIG. 1 , in greater detail, in the present embodiment thefirst source pad 400 includes asource pad body 410 and at least onesource pad branch 420. A direction of thesource pad body 410 is approximately perpendicular to an elongation direction of thesource electrode 200, and an elongation direction of thesource pad branch 420 is approximately parallel to the elongation direction of thesource electrode 200. An orthogonal projection of thesource pad body 410 on the active layer 100 (as depicted inFIG. 2A ) overlaps at least a portion of thedrain region 252, such as the overlapping region O1 inFIG. 1 . Thefirst drain pad 450 includes adrain pad body 460 and at least onedrain pad branch 470. A direction of thedrain pad body 460 is approximately perpendicular to an elongation direction of thedrain electrode 250, and an elongation direction of thedrain pad branch 470 is approximately parallel to the elongation direction of thedrain electrode 250. Thedrain pad body 460 is separate from thesource pad body 410. An orthogonal projection of thedrain pad body 460 on theactive layer 100 overlaps at least a portion of thesource region 202, such as the overlapping region O2 inFIG. 1 . Thesource pad branch 420 extends from thesource pad body 410 toward thedrain pad body 460. Thedrain pad branch 470 extends from thedrain pad body 460 toward thesource pad body 410. In another embodiment of the present invention, in addition to being strip-shaped, thesource pad branch 420 may be wave-shaped, zigzag-shaped, irregularly shaped, or some combination thereof, and thesource pad branch 420 extends from thesource pad body 410 toward thedrain pad body 460. Similarly, a shape of thedrain pad branch 470 may be different depending on product design, and thedrain pad branch 470 extends outward from thesource pad body 410 or thedrain pad body 460. In one embodiment of the present invention, thefirst source pad 400 or thefirst drain pad 450 may be electrically connected to external circuits through other conductive devices, such as a bonding wire, a ribbon, a chip, etc., to enable the operation of circuits. - With reference to
FIG. 1 andFIG. 2A , in greater detail, an orthogonal projection of thesource pad branch 420 on theactive layer 100 overlaps at least a portion of thesource electrode 200. Hence, the source plugs 500 may be disposed between thesource pad branch 420 and thesource electrode 200 to provide an adequate electrical connection between thefirst source pad 400 and thesource electrode 200. As a result, a resistance value of thesource electrode 200 itself is improved. In addition, when a resistance value of the first source pad 400 per unit length is smaller than a resistance value of the source electrode 200 per unit length (for example inFIG. 2A , a thickness T3 of thefirst source pad 400 is greater than a thickness T2 of the source electrode 200), the resistance value of thesource electrode 200 itself is also improved. - In addition, an orthogonal projection of the
drain pad branch 470 on theactive layer 100 overlaps at least a portion of thedrain electrode 250. Hence, the drain plugs 550 may be disposed between thedrain pad branch 470 and thedrain electrode 250 to provide an adequate electrical connection between thefirst drain pad 450 and thedrain electrode 250. As a result, a resistance value of thedrain electrode 250 itself is improved. In addition, when a resistance value of thefirst drain pad 450 per unit length is smaller than a resistance value of thedrain electrode 250 per unit length (for example inFIG. 2A , a thickness T3 of thefirst drain pad 450 is greater than a thickness T2 of the drain electrode 250), the resistance value of thedrain electrode 250 itself is also improved. -
FIG. 2B is a cross-sectional view taken alongline 2B-2B ofFIG. 1 . The source plugs 500 may be disposed between thesource pad body 410 and thesource electrode 200 to provide an adequate electrical connection between thesource pad body 410 and thesource electrode 200. In addition, because thesource pad body 410 is electrically isolated from thedrain electrode 250, no plug exists between thesource pad body 410 and the drain electrode 250 (that is, the portion of the first insulatinglayer 350 above the overlapping region O1). -
FIG. 2C is a cross-sectional view taken alongline 2C-2C ofFIG. 1 . The drain plugs 550 may also be disposed between thedrain pad body 460 and thedrain electrode 250 to provide an adequate electrical connection between thedrain pad body 460 and thedrain electrode 250. In addition, because thedrain pad body 460 is electrically isolated from thesource electrode 200, no plug exists between thedrain pad body 460 and the source electrode 200 (that is, the portion of the first insulatinglayer 350 above the overlapping region O2). - Referring again to
FIG. 1 , in summary, thefirst source pad 400 is electrically connected to thesource electrodes 200 through thesource pad branches 420 and a portion of thesource pad body 410. With such a configuration, a sufficient amount of current can flow between thefirst source pad 400 and thesource electrodes 200 to improve the resistance value of thesource electrodes 200. Similarly, thefirst drain pad 450 is electrically connected to thedrain electrodes 250 through thedrain pad branches 470 and a portion of thedrain pad body 460. With such a configuration, a sufficient amount of current can flow between thefirst drain pad 450 and thedrain electrodes 250 to improve the resistance value of thedrain electrodes 250. - Referring again to
FIG. 1 andFIG. 2A , in the present embodiment, thesource electrode 200, thedrain electrode 250, and thegate electrode 150 together define anactive area 102. Theactive area 102 includes thesource region 202, thedrain region 252, and the region between thesource region 202 and thedrain region 252 in which current passes through theactive layer 100. The semiconductor device further includes aninsulation area 600 surrounding theactive area 102, and at least a portion of theinsulation area 600 is located in theactive layer 100 to prevent leakage currents from being generated, and thus to increase the breakdown voltage. InFIG. 1 , thefirst source pad 400 and thefirst drain pad 450 are completely within theactive area 102. In other words, the semiconductor device can be cut along theinsulation area 600 according to the present embodiment. Hence, the vast majority of theactive area 102 is put to good use and it is not necessary to add extra regions to the non-active area for accommodating source pads and drain pads. As a result, the size of the semiconductor device is effectively reduced, or a semiconductor device is fabricated that is able to sustain a higher breakdown voltage or a larger on current with the same device size. - Referring again to
FIG. 2A , in one or more embodiments, theactive layer 100 includes a plurality of different nitride-based semiconductor layers to allow two-dimensional electron gas (2DEG) to be generated at the heterojunction so as to create a conducting path. For example, a stack structure made up of a gallium nitride (GaN)layer 110 and an aluminum gallium nitride (AlGaN)layer 120 may be utilized, and the aluminumgallium nitride layer 120 is disposed on thegallium nitride layer 110. With this structure, two-dimensional electron gas can exist at the interface of thegallium nitride layer 110 and the aluminumgallium nitride layer 120. Thus, when the semiconductor device is in the on state, the on current between thesource electrode 200 and thedrain electrode 250 is able to flow along the interface of thegallium nitride layer 110 and the aluminumgallium nitride layer 120. Theactive layer 100 may be selectively disposed on asubstrate 50. Thesubstrate 50 may be a silicon substrate or a sapphire substrate, but the invention is not limited in this respect. In one embodiment, the semiconductor device may further include a buffer layer disposed between theactive layer 100 and thesubstrate 50. - Referring again to
FIG. 1 , in the present embodiment, the number of thesource electrodes 200 and the number of thedrain electrodes 250 are both plural. Thesource electrodes 200 are alternately arranged with thedrain electrodes 250 to increase the amount of the on current flowing through the semiconductor device. In order to provide an adequate electrical connection to thesource electrodes 200 and thedrain electrodes 250, the number of thesource pad branches 420 may be plural, and the number of thedrain pad branches 470 may also be plural. Thesource pad branches 420 and thedrain pad branches 470 are alternately arranged between thesource pad body 410 and thedrain pad body 460. All thesource pad branches 420 are over thesource electrodes 200, and all thedrain pad branches 470 are over thedrain electrodes 250. Hence, thefirst source pad 400 and thefirst drain pad 450 are both in the shape of a finger. - With reference to
FIG. 2A , in the present embodiment, the semiconductor device may further include apassivation layer 650 which covers theactive layer 100. Thepassivation layer 650 has at least onesource opening 660 and at least onedrain opening 670 within it. At least a portion of thesource electrode 200 and at least a portion of thedrain electrode 250 are respectively disposed in the source opening 660 and thedrain opening 670. For example inFIG. 2A , thesource electrode 200 and thedrain electrode 250 are respectively disposed in the source opening 660 and thedrain opening 670 to electrically electrode theactive layer 100. - In one or more embodiments, the
gate dielectric layer 300 may selectively cover thepassivation layer 650, and thegate dielectric layer 300 has at least one first inter-source viahole 310 and at least one first inter-drain viahole 320. A portion of the source plug 500 is filled in the first inter-source viahole 310 to electrically interconnect thefirst source pad 400 and thesource electrode 200. A portion of thedrain plug 550 is filled in the first inter-drain viahole 320 to electrically interconnect thefirst drain pad 450 and thedrain electrode 250. - In one or more embodiments, the
passivation layer 650 has at least onegate opening 680 within it. Thegate electrode 150 and thegate dielectric layer 300 cover the gate opening 680 in a manner conforming to the shape of thegate opening 680. The presence of the gate opening 680 can function to adjust the electrical characteristics of thegate electrode 150. However, in other embodiments, thepassivation layer 650 may not have thegate opening 680, and the invention is not limited in this respect. - In the following, the electrical characteristics of the present embodiment semiconductor device are illustrated with reference to
FIG. 1 andFIG. 2A . For the sake of convenience, it is worth noting that asingle gate electrode 150, asingle source electrode 200, and asingle drain electrode 250 are utilized for the calculation of the electrical characteristics in the present embodiment. According to the present embodiment, each of thesource electrode 200 and thedrain electrode 250 has a width W=4 μm and a length L2=1000 μm, and so the area of each of thesource region 202 and the area of thedrain region 252 is L2*W=4000 μm2. In addition, the overlapping region O1 has a length L1=100 μm and the overlapping region O2 has a length L3=100 μm. Hence, the area of the overlapping region O1 is L1*W=400 μm2 and the area of the overlapping region O2 is L3*W=400 μm2. That is, the area of the overlapping region O1 is equal to 10% of the area of thedrain region 252, and the area of the overlapping region O2 is equal to 10% of the area of thesource region 202. When compared with the traditional vertical circuit layout structure, the amount of parasitic capacitance generated in the present invention structure is 20% of that generated in the traditional vertical circuit layout structure. - The
source electrode 200 and thedrain electrode 250 both have a thickness T2=0.2 μm. Thefirst source pad 400 and thefirst drain pad 450 both have a thickness T3=4 μm. A distance between thesource pad body 410 and thedrain pad branch 470 is D1=10 μm. A distance between thedrain pad body 460 and thesource pad branch 420 is D2=10 μm. Thesource pad branch 420 has a width Ws=15 μm and thedrain pad branch 470 has a width Wd=4.2 μm. In addition, the resistivities of thesource electrode 200, thedrain electrode 250, thefirst source pad 400, and thefirst drain pad 450 are all p. Since the resistance values of thesource electrode 200 and thedrain electrode 250 per unit length are much greater than the resistance values of thefirst source pad 400 and thefirst drain pad 450 per unit length, effects contributed by thesource electrode 200 and thedrain electrode 250 can be negligible when calculating the total effects in areas where thefirst source pad 400 and thefirst drain pad 450 are located to thereby simplify the calculation. Based on the above, the total resistance of thesource electrode 200 and thefirst source pad 400 is approximately calculated as Rs=ρ*(L3+D2)/(T2*W)+ρ*(L2−L3−D2−L1)/(T3*Ws)˜151*ρ (here the resistance of thesource pad body 410 is negligible). The total resistance of thedrain electrode 250 and thefirst drain pad 450 is approximately calculated as Rd=ρ*(L1+D1)/(T2*W)+p*(L2−L1−D1−L3)/(T3*Wd)˜185*ρ (here the resistance of thedrain pad body 460 is negligible). If the material of thesource electrode 200, thedrain electrode 250, thefirst source pad 400, and thefirst drain pad 450 is not changed, the Rs or Rd of the source pads or the drain pads in the traditional vertical circuit layout structure is approximately 625 ρ. It is apparent that both the resistance and parasitic capacitance generated in the semiconductor device of the present embodiment are smaller than those generated in the prior art vertical circuit layout structure. In addition, an area utilization ratio of the semiconductor device of the present embodiment is higher than that in the prior art horizontal circuit layout structure (areas required by the source pads and the drain pads are all outside the active area). -
FIG. 3 is a top view of a semiconductor device according to a second embodiment of the present invention. The semiconductor device in the present embodiment differs from the semiconductor device in the first embodiment with respect to positions of thefirst source pad 400 and thefirst drain pad 450. In the present embodiment, at least a portion of thesource pad region 402 formed by thefirst source pad 400 on the active layer 100 (as shown inFIG. 2A ) is outside theactive area 102, and at least a portion of thedrain pad region 452 formed by thefirst drain pad 450 on theactive layer 100 is outside theactive area 102. Basically, any design in which thesource pad region 402 and thedrain region 252 form the overlapping region O1 and the area of the overlapping region O1 is smaller than or equal to 40% of the area of thedrain region 252, or in which thedrain pad region 452 and thesource region 202 form the overlapping region O2 and the area of the overlapping region O2 is smaller than or equal to 40% of the area of thesource region 202 is within the scope of the invention. Since other details of the present embodiment are the same as those in the first embodiment, a further description in this regard is not provided. - Furthermore, in the first embodiment the
source pad region 402 and thedrain pad region 452 are both within theactive area 102. In the second embodiment, both a portion of thesource pad region 402 and thedrain pad region 252 are outside theactive area 102. However, in other embodiments, thesource pad region 402 may be within theactive area 102 and a portion of thedrain pad region 452 may be outside theactive area 102, and vice versa. -
FIG. 4 is a top view of a semiconductor device according to a third embodiment of the present invention.FIG. 5A is a cross-sectional view taken alongline 5A-5A ofFIG. 1 . The present embodiment differs from the first embodiment with respect to structures of thesource electrode 200 and thedrain electrode 250 and the disposition of aninterlayer dielectric 700. In the present embodiment, the semiconductor device further includes theinterlayer dielectric 700 that covers thegate dielectric layer 300. Theinterlayer dielectric 700 has at least one second inter-source via hole 710. Thesource electrode 200 includes alower sub-source electrode 210, anupper sub-source electrode 200, and at least oneinter-source plug 230. Thelower sub-source electrode 210 is disposed in the source opening 660, and theupper sub-source electrode 220 is disposed on theinterlayer dielectric 700. Theinter-source plug 230 is filled in the first inter-source viahole 310 and the second inter-source via hole 710, and electrically connected to theupper sub-source electrode 220 and thelower sub-source electrode 210. - In addition, the
interlayer dielectric 700 has at least one second inter-drain via hole 720. Thedrain electrode 250 includes alower sub-drain electrode 260, an uppersub-drain electrode 270, and at least oneinter-drain plug 280. Thelower sub-drain electrode 260 is disposed in thedrain opening 670, and the uppersub-drain electrode 270 is disposed on theinterlayer dielectric 700. Theinter-drain plug 280 is filled in the first inter-drain viahole 320 and the second inter-drain via hole 720 and electrically connected to the uppersub-drain electrode 270 and thelower sub-drain electrode 260. - In the present embodiment, the
lower sub-source electrode 210 of thesource electrode 200 directly electrodes theactive layer 100 and may be an ohmic electrode having a large resistance value per unit length. Hence, theupper sub-source electrode 220 that has a resistance value per unit length smaller than the resistance value of thelower sub-source electrode 210 per unit length is added over thelower sub-source electrode 210. As a result, the overall resistance value of thesource electrode 200 is reduced by electrically connecting theupper sub-source electrode 220 to thelower sub-source electrode 210. - Similarly, the
lower sub-drain electrode 260 of thedrain electrode 250 directly electrodes theactive layer 100 and may be an ohmic electrode having a large resistance value per unit length. Hence, the uppersub-drain electrode 270 that has a resistance value per unit length smaller than the resistance value of thelower sub-drain electrode 260 per unit length is added over thelower sub-drain electrode 260. As a result, the overall resistance value of thedrain electrode 250 is reduced by electrically connecting the uppersub-drain electrode 270 to thelower sub-drain electrode 260. -
FIG. 5B is a cross-sectional view taken alongline 5B-5B ofFIG. 4 . A detailed description of electrical connections between the various electrode layers below thesource pad body 410 will now be provided. First, thesource pad body 410 is electrically connected to theupper sub-source electrode 220 through the source plugs 500. Theupper sub-source electrode 220 and thelower sub-source electrode 210 below thesource pad body 410 are electrically connected through the inter-source plugs 230. Hence, a sufficient amount of current can flow between thesource electrode 200 and thesource pad body 410. In addition, the uppersub-drain electrode 270 and thelower sub-drain electrode 260 below thesource pad body 410 are electrically connected through the inter-drain plugs 280. Hence, a sufficient amount of current can flow between the uppersub-drain electrode 270 and thelower sub-drain electrode 260. -
FIG. 5C is a cross-sectional view taken alongline 5C-5C ofFIG. 4 . A detailed description of electrical connections between the various electrode layers below thedrain pad body 460 will now be provided. First, thedrain pad body 460 is electrically connected to the uppersub-drain electrode 270 through the drain plugs 550. The uppersub-drain electrode 270 and thelower sub-drain electrode 260 below thedrain pad body 460 are electrically connected through the inter-drain plugs 280. Hence, a sufficient amount of current can flow between thedrain electrode 250 and thedrain pad body 460. In addition, theupper sub-source electrode 220 and thelower sub-source electrode 210 below thedrain pad body 460 are electrically connected through the inter-source plugs 230. Hence, a sufficient amount of current can flow between theupper sub-source electrode 220 and thelower sub-source electrode 210. Since other details of the present embodiment are the same as those in the first embodiment, a further description in this regard is not provided. -
FIG. 6 is a top view of a semiconductor device according to a fourth embodiment of the present invention.FIG. 7A is a cross-sectional view taken alongline 7A-7A ofFIG. 6 .FIG. 7B is a cross-sectional view taken alongline 7B-7B ofFIG. 6 .FIG. 7C is a cross-sectional view taken alongline 7C-7C ofFIG. 6 .FIG. 7D is a cross-sectional view taken alongline 7D-7D ofFIG. 6 . The present embodiment differs from the first embodiment with respect to the disposition of a second insulatinglayer 750, asecond source pad 800, asecond drain pad 850, a sourcepad connection portion 900, and a drainpad connection portion 950. With reference toFIG. 6 ,FIG. 7A , andFIG. 7C , in the present embodiment, the second insulatinglayer 750 is disposed on thefirst source pad 400 and the first insulatinglayer 350. The secondinsulating layer 750 has a source pad opening 760 to expose a portion of thefirst source pad 400, and the second insulatinglayer 750 has a thickness T4 greater than 7 μm. Thesecond source pad 800 is disposed on the second insulatinglayer 750. The sourcepad connection portion 900 is disposed in thesource pad opening 760 and is electrically connected to thefirst source pad 400 and thesecond source pad 800. As shown inFIG. 7A , thesecond source pad 800 and thefirst source pad 400 are electrically connected through the sourcepad connection portion 900. As shown inFIG. 7C , despite the parasitic capacitance generated in the overlapping region formed by thesecond source pad 800 and thefirst drain pad 450, the capacitance value of the parasitic capacitance is not large because the thickness T4 of the second insulatinglayer 750 is greater than 7 μm. Hence, an area of aregion 802 formed by an orthogonal projection of thesecond source pad 800 on theactive layer 100 may be greater than an area of the region formed by the orthogonal projection of thesource pad body 410 on theactive layer 100 to facilitate connection with external circuits. - With reference to
FIG. 6 ,FIG. 7B , andFIG. 7D , the second insulatinglayer 750 is further disposed on thefirst drain pad 450. The secondinsulating layer 750 has adrain pad opening 770 to expose a portion of thefirst drain pad 450. Thesecond drain pad 850 is separate from thesecond source pad 800 and is disposed on the second insulatinglayer 750. The drainpad connection portion 950 is disposed in thedrain pad opening 770 and is electrically connected to thefirst drain pad 450 and thesecond drain pad 850. As shown inFIG. 7B , thesecond drain pad 850 and thefirst drain pad 450 are electrically connected through the drainpad connection portion 950. As shown inFIG. 7D , despite the parasitic capacitance generated in the overlapping region formed by thesecond drain pad 850 and thefirst source pad 400, the capacitance value of the parasitic capacitance is not large because the thickness T4 of the second insulatinglayer 750 is greater than 7 μm. Hence, an area of aregion 852 formed by an orthogonal projection of thesecond drain pad 850 on theactive layer 100 may be greater than an area of the region formed by the orthogonal projection of thedrain pad body 460 on theactive layer 100 to facilitate connection with external circuits. - In the present embodiment, a material of the second insulating
layer 750 includes polyimide (PI), photoresist (PR), benzo cyclo butane (BCB), spin on glass (SOG), plastic, or their combinations. The secondinsulating layer 750 may be formed on thefirst source pad 400, thefirst drain pad 450, and the first insulatinglayer 350 by, for example, spin coating, but the invention is not limited in this respect. Since other details of the present embodiment are the same as those in the first embodiment, a further description in this regard is not provided. It is worth noting that in the present embodiment, the second insulatinglayer 750, thesecond source pad 800, thesecond drain pad 850, the sourcepad connection portion 900, and the drainpad connection portion 950 are all disposed on the semiconductor device of the first embodiment. However, in other embodiments, the second insulatinglayer 750, thesecond source pad 800, thesecond drain pad 850, the sourcepad connection portion 900, and the drainpad connection portion 950 may be disposed on the semiconductor device of the second embodiment or the third embodiment. - Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims.
Claims (20)
Priority Applications (12)
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US14/333,795 US9190393B1 (en) | 2013-09-10 | 2014-07-17 | Low parasitic capacitance semiconductor device package |
US14/496,471 US9508843B2 (en) | 2013-09-10 | 2014-09-25 | Heterojunction semiconductor device for reducing parasitic capacitance |
US15/297,123 US10084076B2 (en) | 2013-09-10 | 2016-10-18 | Heterojunction semiconductor device for reducing parasitic capacitance |
US15/429,184 US10236236B2 (en) | 2013-09-10 | 2017-02-10 | Heterojunction semiconductor device for reducing parasitic capacitance |
US15/468,133 US10665709B2 (en) | 2013-09-10 | 2017-03-24 | Power semiconductor device integrated with ESD protection circuit under source pad, drain pad, and/or gate pad |
US15/678,102 US10833185B2 (en) | 2013-09-10 | 2017-08-15 | Heterojunction semiconductor device having source and drain pads with improved current crowding |
US16/041,848 US10468516B2 (en) | 2013-09-10 | 2018-07-23 | Heterojunction semiconductor device for reducing parasitic capacitance |
US16/233,115 US10950524B2 (en) | 2013-09-10 | 2018-12-27 | Heterojunction semiconductor device for reducing parasitic capacitance |
US16/550,293 US10910491B2 (en) | 2013-09-10 | 2019-08-26 | Semiconductor device having reduced capacitance between source and drain pads |
US16/581,781 US10573736B2 (en) | 2013-09-10 | 2019-09-25 | Heterojunction semiconductor device for reducing parasitic capacitance |
US17/121,706 US11817494B2 (en) | 2013-09-10 | 2020-12-14 | Semiconductor device having reduced capacitance between source and drain pads |
US18/482,025 US20240030338A1 (en) | 2013-09-10 | 2023-10-06 | Semiconductor device |
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US14/496,471 Continuation-In-Part US9508843B2 (en) | 2013-09-10 | 2014-09-25 | Heterojunction semiconductor device for reducing parasitic capacitance |
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US11101349B2 (en) | 2018-08-29 | 2021-08-24 | Efficient Power Conversion Corporation | Lateral power device with reduced on-resistance |
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US10665709B2 (en) | 2013-09-10 | 2020-05-26 | Delta Electronics, Inc. | Power semiconductor device integrated with ESD protection circuit under source pad, drain pad, and/or gate pad |
TWI577022B (en) | 2014-02-27 | 2017-04-01 | 台達電子工業股份有限公司 | Semiconductor device and semiconductor device package using the same |
US10910491B2 (en) | 2013-09-10 | 2021-02-02 | Delta Electronics, Inc. | Semiconductor device having reduced capacitance between source and drain pads |
US10833185B2 (en) | 2013-09-10 | 2020-11-10 | Delta Electronics, Inc. | Heterojunction semiconductor device having source and drain pads with improved current crowding |
US9190393B1 (en) * | 2013-09-10 | 2015-11-17 | Delta Electronics, Inc. | Low parasitic capacitance semiconductor device package |
US10236236B2 (en) | 2013-09-10 | 2019-03-19 | Delta Electronics, Inc. | Heterojunction semiconductor device for reducing parasitic capacitance |
CN109411535B (en) * | 2017-08-15 | 2022-03-18 | 台达电子工业股份有限公司 | Semiconductor device with a plurality of semiconductor chips |
US10903398B2 (en) | 2019-02-06 | 2021-01-26 | Osram Opto Semiconductors Gmbh | Dielectric film coating for full conversion ceramic platelets |
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