TWI660506B - Semiconductor device - Google Patents
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- TWI660506B TWI660506B TW107100424A TW107100424A TWI660506B TW I660506 B TWI660506 B TW I660506B TW 107100424 A TW107100424 A TW 107100424A TW 107100424 A TW107100424 A TW 107100424A TW I660506 B TWI660506 B TW I660506B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 239000006185 dispersion Substances 0.000 claims abstract description 54
- 229910052751 metal Inorganic materials 0.000 claims description 88
- 239000002184 metal Substances 0.000 claims description 88
- 230000004308 accommodation Effects 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 10
- 238000009825 accumulation Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 7
- 239000000758 substrate Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- 230000005533 two-dimensional electron gas Effects 0.000 description 5
- 229910002601 GaN Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
一種半導體裝置包含主動層、源極電極、汲極電極、閘極電極、源極墊、汲極墊與至少一源極外部連接元件。源極電極、汲極電極與閘極電極置於主動層的主動區上。源極墊電性連接至源極電極，並包含本體部、複數個分支部與至少一電流分散部。本體部至少部分置於主動區並沿著第一方向延伸。分支部沿著第二方向延伸。第二方向不同於第一方向。電流分散部連接本體部與分支部，並沿著第一方向延伸。電流分散部的寬度大於一之分支部的寬度且小於本體部的一半寬度。汲極墊電性連接至汲極電極。源極外部連接元件置於本體部上且與電流分散部分開。A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, a source pad, a drain pad, and at least one source external connection element. The source electrode, the drain electrode and the gate electrode are placed on the active region of the active layer. The source pad is electrically connected to the source electrode, and includes a body portion, a plurality of branch portions, and at least one current dispersion portion. The body portion is at least partially disposed in the active area and extends along the first direction. The branch portion extends along the second direction. The second direction is different from the first direction. The current dispersion portion connects the main body portion and the branch portion, and extends along the first direction. The width of the current dispersion portion is larger than the width of the branch portion of one and smaller than half the width of the body portion. The drain pad is electrically connected to the drain electrode. The source external connection element is placed on the body portion and separated from the current dispersion portion.
Description
本發明是有關於一種半導體裝置。The present invention relates to a semiconductor device.
氮基半導體具有高電子崩潰電場與高電子飽和速度，因此，氮基半導體被期望作為具高崩潰電壓與低開啟電阻之半導體裝置的半導體材料。許多使用氮基相關材料的半導體裝置具有異質結構(heterojunctions)。異質結構係利用二種具有不同帶隙能量的氮基半導體組成，且可於接合平面附近形成二維電子氣(two-dimensional electron gas, 2DEG)層。具有異質結構的半導體裝置可達成低開啟電阻。此類的半導體裝置稱為高電子遷移率電晶體(high electron mobility transistors, HEMT)。Nitrogen-based semiconductors have high electron collapse electric fields and high electron saturation speeds. Therefore, nitrogen-based semiconductors are expected to be used as semiconductor materials for semiconductor devices with high breakdown voltages and low on-resistance. Many semiconductor devices using nitrogen-based materials have heterojunctions. The heterostructure is composed of two nitrogen-based semiconductors with different band gap energies, and a two-dimensional electron gas (2DEG) layer can be formed near the bonding plane. Semiconductor devices with heterostructures can achieve low on-resistance. Such semiconductor devices are called high electron mobility transistors (HEMT).
本揭露提供一種半導體裝置，包含主動層、源極電極、汲極電極、閘極電極、源極墊、汲極墊與至少一源極外部連接元件。主動層具有主動區。源極電極、汲極電極與閘極電極置於主動層的主動區上。源極墊電性連接至源極電極。源極墊包含本體部、複數個分支部與至少一電流分散部。本體部至少部分置於主動層的主動區。源極墊的本體部沿著第一方向延伸。分支部沿著第二方向延伸。第二方向不同於第一方向。電流分散部連接源極墊的本體部與源極墊的分支部，並沿著第一方向延伸。源極墊的電流分散部的寬度大於源極墊的一之分支部的寬度且小於源極墊的本體部的一半寬度。汲極墊電性連接至汲極電極。源極外部連接元件置於源極墊的本體部上且與源極墊的電流分散部分開。The disclosure provides a semiconductor device including an active layer, a source electrode, a drain electrode, a gate electrode, a source pad, a drain pad, and at least one source external connection element. The active layer has an active area. The source electrode, the drain electrode and the gate electrode are placed on the active region of the active layer. The source pad is electrically connected to the source electrode. The source pad includes a body portion, a plurality of branch portions, and at least one current dispersion portion. The body portion is at least partially placed in the active area of the active layer. The body portion of the source pad extends along the first direction. The branch portion extends along the second direction. The second direction is different from the first direction. The current dispersion portion connects the body portion of the source pad and a branch portion of the source pad, and extends along the first direction. The width of the current dispersion portion of the source pad is greater than the width of one of the branch portions of the source pad and less than half the width of the body portion of the source pad. The drain pad is electrically connected to the drain electrode. The source external connection element is placed on the body portion of the source pad and separated from the current dispersion portion of the source pad.
在一或多個實施方式中，源極墊的電流分散部分開源極墊的本體部與源極墊的分支部。In one or more embodiments, the current dispersing portion of the source pad is an open source body portion and a branch portion of the source pad.
在一或多個實施方式中，源極墊的本體部與源極墊的分支部置於源極墊的電流分散部的相對兩側。In one or more embodiments, the body portion of the source pad and the branch portions of the source pad are disposed on opposite sides of the current dispersion portion of the source pad.
在一或多個實施方式中，源極外部連接元件毗鄰源極墊的電流分散部的邊緣對齊源極墊的本體部與源極墊的電流分散部之間的界面。In one or more embodiments, the edge of the source external connection element adjacent to the current distribution portion of the source pad is aligned with the interface between the body portion of the source pad and the current distribution portion of the source pad.
在一或多個實施方式中，源極墊的電流分散部與源極墊的本體部具有實質相同的長度。In one or more embodiments, the current distribution portion of the source pad and the body portion of the source pad have substantially the same length.
在一或多個實施方式中，源極墊滿足：1≦L2/((W1+W3)/2)≦3，其中W1為源極墊的電流分散部的寬度，W3為源極墊的本體部的寬度，且L2為源極墊的分支部的長度。In one or more embodiments, the source pad satisfies: 1 ≦ L2 / ((W1 + W3) / 2) ≦ 3, where W1 is the width of the current dispersion portion of the source pad, and W3 is the body of the source pad And L2 is the length of the branch portion of the source pad.
在一或多個實施方式中，源極墊的本體部重疊至少部分的源極電極。In one or more embodiments, the body portion of the source pad overlaps at least a portion of the source electrode.
在一或多個實施方式中，半導體裝置更包含至少一下源極金屬層，置於源極電極與源極墊之間。In one or more embodiments, the semiconductor device further includes at least one lower source metal layer disposed between the source electrode and the source pad.
在一或多個實施方式中，下源極金屬層的數量為複數個，且下源極金屬層互相分開。In one or more embodiments, the number of the lower source metal layers is plural, and the lower source metal layers are separated from each other.
在一或多個實施方式中，半導體裝置更包含至少一上源極金屬層，置於下源極金屬層與源極墊之間。In one or more embodiments, the semiconductor device further includes at least one upper source metal layer disposed between the lower source metal layer and the source pad.
在一或多個實施方式中，上源極金屬層的數量為複數個，且上源極金屬層互相分開。In one or more embodiments, the number of the upper source metal layers is plural, and the upper source metal layers are separated from each other.
在一或多個實施方式中，下源極金屬層的厚度小於上源極金屬層與源極墊的總厚度。In one or more embodiments, the thickness of the lower source metal layer is smaller than the total thickness of the upper source metal layer and the source pad.
在一或多個實施方式中，上源極金屬層的寬度大於源極墊的至少一之分支部的寬度。In one or more embodiments, a width of the upper source metal layer is greater than a width of at least one branch portion of the source pad.
在一或多個實施方式中，汲極墊包含本體部、複數個分支部與電流分散部。本體部至少部分置於主動層的主動區。汲極墊的本體部沿著第一方向延伸。分支部沿著第二方向延伸，且源極墊的分支部與汲極墊的分支部交替排列。電流分散部連接汲極墊的本體部與汲極墊的分支部，並沿著第一方向延伸。In one or more embodiments, the drain pad includes a body portion, a plurality of branch portions, and a current dispersion portion. The body portion is at least partially placed in the active area of the active layer. The body portion of the drain pad extends along the first direction. The branch portions extend along the second direction, and the branch portions of the source pad and the branch portions of the drain pad are alternately arranged. The current dispersion portion connects the body portion of the drain pad and the branch portion of the drain pad, and extends along the first direction.
在一或多個實施方式中，汲極墊的電流分散部的寬度大於汲極墊的一之分支部的寬度且小於汲極墊的本體部的一半寬度。In one or more embodiments, the width of the current dispersing portion of the drain pad is greater than the width of one of the branch portions of the drain pad and less than half the width of the body portion of the drain pad.
在一或多個實施方式中，半導體裝置更包含至少一下汲極金屬層，置於汲極電極與汲極墊之間。In one or more embodiments, the semiconductor device further includes at least a lower drain metal layer disposed between the drain electrode and the drain pad.
在一或多個實施方式中，下汲極金屬層的數量為複數個，且下汲極金屬層互相分開。In one or more embodiments, the number of the lower drain metal layers is plural, and the lower drain metal layers are separated from each other.
在一或多個實施方式中，半導體裝置更包含至少一上汲極金屬層，置於下汲極金屬層與汲極墊之間。In one or more embodiments, the semiconductor device further includes at least one upper drain metal layer disposed between the lower drain metal layer and the drain pad.
在一或多個實施方式中，上汲極金屬層的數量為複數個，且上汲極金屬層互相分開。In one or more embodiments, the number of the upper drain metal layers is plural, and the upper drain metal layers are separated from each other.
在一或多個實施方式中，源極墊的電流分散部與汲極墊的電流分散部之間定義一容置空間，且源極墊的分支部與汲極墊的分支部於容置空間的密度為約50%至約90%。In one or more embodiments, an accommodation space is defined between the current dispersing portion of the source pad and the current dispersing portion of the drain pad, and the branch portion of the source pad and the branch portion of the drain pad are in the accommodation space. Has a density of about 50% to about 90%.
在上述實施方式中，電流分散部可改善源極墊的電流集聚(current crowding)問題。當電流分散部的寬度大於一之分支部的寬度且小於本體部的寬度的一半時，電流集聚效應與半導體裝置的佈線面積將一併獲得改善。In the above embodiment, the current dispersing portion can improve the current crowding problem of the source pad. When the width of the current dispersion portion is greater than the width of the branch portion of one and less than half the width of the body portion, the current accumulation effect and the wiring area of the semiconductor device are improved together.
以下將以圖式揭露本發明的複數個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本發明。也就是說，在本發明部分實施方式中，這些實務上的細節是非必要的。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。In the following, a plurality of embodiments of the present invention will be disclosed graphically. For the sake of clarity, many practical details will be described in the following description. It should be understood, however, that these practical details should not be used to limit the invention. That is, in some embodiments of the present invention, these practical details are unnecessary. In addition, in order to simplify the drawings, some conventional structures and components will be shown in the drawings in a simple and schematic manner.
第1圖為本揭露一些實施方式之半導體裝置的上視圖，第2A圖為沿著第1圖的線段2A-2A的剖面圖，而第2B圖為沿著第1圖的線段2B-2B的剖面圖。請參照第1圖、第2A圖與第2B圖。半導體裝置包含主動層110、源極電極120、汲極電極130、閘極電極140、源極墊150、汲極墊160與至少一源極外部連接元件170。主動層110具有主動區112。源極電極120、汲極電極130與閘極電極140置於主動層110的主動區112上。源極墊150電性連接至源極電極120，且源極墊150包含本體部152、複數個分支部154與一電流分散部156。本體部152至少部分置於主動層110的主動區112。舉例而言，本體部152於主動層110的投影位於主動區112 中，或者與主動區112重疊。亦即，本體部152重疊至少部分的源極電極120、至少部分的汲極電極130與/或至少部分的閘極電極140。本體部152沿著第一方向D1延伸。分支部154沿著第二方向D2延伸。第二方向D2不同於第一方向D1。舉例而言，如第1圖所示，第一方向D1實質垂直於第二方向D2。電流分散部156連接本體部152與分支部154，並沿著第一方向D1延伸。電流分散部156的寬度W1大於一之分支部154的寬度W2且小於本體部152的寬度W3的一半。源極外部連接元件170置於本體部152上，接觸本體部152，且與電流分散部156分開。亦即，源極外部連接元件170非接觸電流分散部156。「實質」係用以修飾任何可些微變化的關係，但這種些微變化並不會改變其本質。FIG. 1 is a top view of a semiconductor device according to some embodiments. FIG. 2A is a cross-sectional view taken along line 2A-2A of FIG. 1, and FIG. 2B is a view taken along line 2B-2B of FIG. 1. Sectional view. Please refer to Fig. 1, Fig. 2A and Fig. 2B. The semiconductor device includes an active layer 110, a source electrode 120, a drain electrode 130, a gate electrode 140, a source pad 150, a drain pad 160, and at least one source external connection element 170. The active layer 110 has an active region 112. The source electrode 120, the drain electrode 130, and the gate electrode 140 are disposed on the active region 112 of the active layer 110. The source pad 150 is electrically connected to the source electrode 120, and the source pad 150 includes a body portion 152, a plurality of branch portions 154, and a current dispersion portion 156. The body portion 152 is at least partially disposed in the active region 112 of the active layer 110. For example, the projection of the body portion 152 on the active layer 110 is located in the active area 112 or overlaps with the active area 112. That is, the body portion 152 overlaps at least part of the source electrode 120, at least part of the drain electrode 130, and / or at least part of the gate electrode 140. The body portion 152 extends along the first direction D1. The branch portion 154 extends along the second direction D2. The second direction D2 is different from the first direction D1. For example, as shown in FIG. 1, the first direction D1 is substantially perpendicular to the second direction D2. The current dispersion portion 156 connects the main body portion 152 and the branch portion 154 and extends along the first direction D1. The width W1 of the current dispersion portion 156 is larger than the width W2 of the branch portion 154 of the one and is less than half the width W3 of the main body portion 152. The source external connection element 170 is placed on the body portion 152, contacts the body portion 152, and is separated from the current dispersion portion 156. That is, the source external connection element 170 is a non-contact current dispersion portion 156. "Essential" is used to modify any relationship that can be slightly changed, but this slight change does not change its essence.
另外，汲極墊160電性連接汲極電極130，且汲極墊160包含本體部162、複數個分支部164與一電流分散部166。本體部162至少部分置於主動層110的主動區112。舉例而言，本體部162於主動層110的投影位於主動區112 中，或者與主動區112重疊。亦即，本體部162重疊至少部分的源極電極120、至少部分的汲極電極130與/或至少部分的閘極電極140。本體部162沿著第一方向D1延伸。亦即，本體部152與162實質平行。分支部164沿著第二方向D2延伸。亦即，分支部154與164實質平行。分支部154與164沿著第一方向D1交替排列。電流分散部166連接本體部162與分支部164，並沿著第一方向D1延伸。電流分散部166的寬度W4大於一之分支部164的寬度W5且小於本體部162的寬度W6的一半。In addition, the drain pad 160 is electrically connected to the drain electrode 130, and the drain pad 160 includes a body portion 162, a plurality of branch portions 164, and a current dispersion portion 166. The body portion 162 is at least partially disposed in the active region 112 of the active layer 110. For example, the projection of the body portion 162 on the active layer 110 is located in the active area 112 or overlaps with the active area 112. That is, the body portion 162 overlaps at least part of the source electrode 120, at least part of the drain electrode 130, and / or at least part of the gate electrode 140. The body portion 162 extends along the first direction D1. That is, the body portions 152 and 162 are substantially parallel. The branch portion 164 extends along the second direction D2. That is, the branch portions 154 and 164 are substantially parallel. The branch portions 154 and 164 are alternately arranged along the first direction D1. The current dispersion portion 166 connects the main body portion 162 and the branch portion 164 and extends along the first direction D1. The width W4 of the current dispersion portion 166 is larger than the width W5 of the branch portion 164 of the one and is less than half the width W6 of the main body portion 162.
在本實施方式中，電流分散部156可改善源極墊150的電流集聚(current crowding)問題。具體而言，電流自源極外部連接元件170經由源極墊150而流至源極電極120。電流依序流經本體部152、電流分散部156與分支部154而到達源極電極120。若源極外部連接元件170太過於靠近分支部154，亦即電流分散部156的寬度W1過小，則會產生電流集聚效應而惡化半導體裝置的性能。若源極外部連接元件170太過於遠離分支部154，亦即電流分散部156的寬度W1過大，則半導體裝置的佈線面積(layout area)便會增加。因此，當電流分散部156的寬度W1大於一之分支部154的寬度W2且小於本體部152的寬度W3的一半時，電流集聚效應與半導體裝置的佈線面積將一併獲得改善。類似的，當電流分散部166的寬度W4大於一之分支部164的寬度W5且小於本體部162的寬度W6的一半時，電流集聚效應與半導體裝置的佈線面積將一併獲得改善。In this embodiment, the current dispersing portion 156 can improve the current crowding of the source pad 150. Specifically, a current flows from the source external connection element 170 to the source electrode 120 through the source pad 150. The current flows sequentially through the body portion 152, the current dispersion portion 156, and the branch portion 154 to reach the source electrode 120. If the source external connection element 170 is too close to the branch portion 154, that is, the width W1 of the current dispersion portion 156 is too small, a current accumulation effect may occur and the performance of the semiconductor device may be deteriorated. If the source external connection element 170 is too far away from the branch portion 154, that is, the width W1 of the current dispersion portion 156 is too large, the layout area of the semiconductor device will increase. Therefore, when the width W1 of the current dispersion portion 156 is larger than the width W2 of the branch portion 154 of the one and is less than half the width W3 of the body portion 152, the current accumulation effect and the wiring area of the semiconductor device will be improved together. Similarly, when the width W4 of the current dispersing portion 166 is greater than the width W5 of the branch portion 164 of the one and is less than half the width W6 of the body portion 162, the current accumulation effect and the wiring area of the semiconductor device will be improved together.
在第1圖中，對於源極墊150，電流分散部156分開本體部152與分支部154。換言之，電流分散部156置於本體部152與分支部154之間。或者，本體部152與分支部154置於電流分散部156的相對兩側。在一些實施方式中，源極墊150為一體成型。亦即，本體部152、分支部154與電流分散部156為一體成型。分支部154突出於電流分散部156，因此源極墊150為指叉形。另外，在第1圖中，電流分散部156與本體部152具有實質相同的長度。In FIG. 1, with respect to the source pad 150, the current dispersion portion 156 separates the body portion 152 and the branch portion 154. In other words, the current dispersion portion 156 is interposed between the body portion 152 and the branch portion 154. Alternatively, the body portion 152 and the branch portion 154 are disposed on opposite sides of the current dispersion portion 156. In some embodiments, the source pad 150 is integrally formed. That is, the body portion 152, the branch portion 154, and the current dispersion portion 156 are integrally formed. Since the branch portion 154 protrudes from the current dispersion portion 156, the source pad 150 has an interdigitated shape. In addition, in FIG. 1, the current dispersion portion 156 and the main body portion 152 have substantially the same length.
另外，對於汲極墊160，電流分散部166分開本體部162與分支部164。換言之，電流分散部166置於本體部162與分支部164之間。或者，本體部162與分支部164置於電流分散部166的相對兩側。在一些實施方式中，汲極墊160為一體成型。亦即，本體部162、分支部164與電流分散部166為一體成型。分支部164突出於電流分散部166，因此汲極墊160為指叉形。另外，在第1圖中，電流分散部166與本體部162具有實質相同的長度。In addition, for the drain pad 160, the current spreading portion 166 separates the body portion 162 and the branch portion 164. In other words, the current dispersion portion 166 is interposed between the body portion 162 and the branch portion 164. Alternatively, the body portion 162 and the branch portion 164 are disposed on opposite sides of the current dispersion portion 166. In some embodiments, the drain pad 160 is integrally formed. That is, the body portion 162, the branch portion 164, and the current dispersion portion 166 are integrally formed. Since the branch portion 164 protrudes from the current dispersion portion 166, the drain pad 160 has an interdigitated shape. In addition, in FIG. 1, the current dispersion portion 166 and the main body portion 162 have substantially the same length.
源極外部連接元件170毗鄰電流分散部156的邊緣172對齊本體部152與電流分散部156之間的界面Is。在一些實施方式中，源極外部連接元件170可為凸塊(bump)或者連接線(wire)以將源極墊150連接至外部元件或電路。The source external connection element 170 is aligned with the interface Is between the body portion 152 and the current dispersing portion 156 adjacent to the edge 172 of the current dispersing portion 156. In some embodiments, the source external connection element 170 may be a bump or a wire to connect the source pad 150 to an external element or circuit.
在一些實施方式中，源極墊150滿足：1≦L2/((W1+W3)/2)≦3，其中L2為分支部154的長度。電流分散部156的寬度W1與本體部152的寬度W3的總和與源極之電流分散部156和分支部154之間的交接處的電流集聚效應有關。在一些實施方式中，當寬度W1與寬度W3的總和增加時，交接處的電流密度會降低。另外，分支部154的長度L2與源極的總電阻有關。在一些實施方式中，若長度L2增加，則源極的總電阻亦增加。因此，當源極墊150滿足上式關係式時，源極的電流集聚效應與總電阻皆會被改善。In some embodiments, the source pad 150 satisfies: 1 ≦ L2 / ((W1 + W3) / 2) ≦ 3, where L2 is the length of the branch portion 154. The sum of the width W1 of the current dispersion portion 156 and the width W3 of the main body portion 152 is related to the current accumulation effect at the junction between the current dispersion portion 156 and the branch portion 154 of the source. In some embodiments, as the sum of the width W1 and the width W3 increases, the current density at the junction decreases. The length L2 of the branch portion 154 is related to the total resistance of the source. In some embodiments, if the length L2 is increased, the total resistance of the source is also increased. Therefore, when the source pad 150 satisfies the above formula, the current accumulation effect and the total resistance of the source are improved.
類似的，在一些實施方式中，汲極墊160滿足：1≦L5/((W4+W6)/2)≦3，其中L5為分支部164的長度。電流分散部166的寬度W4與本體部162的寬度W6的總和與汲極之電流分散部166和分支部164之間的交接處的電流集聚效應有關。在一些實施方式中，當寬度W4與寬度W6的總和增加時，交接處的電流密度會降低。另外，分支部164的長度L5與汲極的總電阻有關。在一些實施方式中，若長度L5增加，則汲極的總電阻亦增加。因此，當汲極墊160滿足上式關係式時，汲極的電流集聚效應與總電阻皆會被改善。Similarly, in some embodiments, the drain pad 160 satisfies: 1 ≦ L5 / ((W4 + W6) / 2) ≦ 3, where L5 is the length of the branch portion 164. The sum of the width W4 of the current dispersion portion 166 and the width W6 of the main body portion 162 is related to the current accumulation effect at the junction between the current dispersion portion 166 and the branch portion 164 of the drain. In some embodiments, as the sum of the width W4 and the width W6 increases, the current density at the junction decreases. The length L5 of the branch portion 164 is related to the total resistance of the drain. In some embodiments, if the length L5 is increased, the total resistance of the drain is also increased. Therefore, when the drain pad 160 satisfies the above-mentioned relationship, both the current accumulation effect and the total resistance of the drain will be improved.
在第1圖中，半導體裝置更包含至少一汲極外部連接元件180，置於本體部162上，接觸本體部162，且與電流分散部166分開。亦即，汲極外部連接元件180非接觸電流分散部166。汲極外部連接元件180毗鄰電流分散部166的邊緣182對齊本體部162與電流分散部166之間的界面Id。在一些實施方式中，汲極外部連接元件180可為凸塊(bump)或者連接線(wire)以將汲極墊160連接至外部元件或電路。在一些實施方式中，源極外部連接元件170與汲極外部連接元件180可為相同型式的連接元件(例如皆為凸塊或皆為連接線)。或者，源極外部連接元件170與汲極外部連接元件180可為不同型式的連接元件。例如源極外部連接元件170可為凸塊，而汲極外部連接元件180可為連接線，或者相反。In FIG. 1, the semiconductor device further includes at least one drain external connection element 180 disposed on the body portion 162, contacting the body portion 162, and separated from the current dispersion portion 166. That is, the drain external connection element 180 is a non-contact current dispersion portion 166. The drain external connection element 180 is adjacent to the edge 182 of the current dispersing portion 166 and is aligned with the interface Id between the body portion 162 and the current dispersing portion 166. In some embodiments, the drain external connection element 180 may be a bump or a wire to connect the drain pad 160 to an external element or circuit. In some embodiments, the source external connection element 170 and the drain external connection element 180 may be the same type of connection elements (for example, both bumps or connection lines). Alternatively, the source external connection element 170 and the drain external connection element 180 may be different types of connection elements. For example, the source external connection element 170 may be a bump, and the drain external connection element 180 may be a connection line, or vice versa.
請參照第2A圖與第2B圖。在一些實施方式中，主動層110包含通道層116與阻障層118，阻障層118置於通道層116上。二維電子氣(two-dimensional electron gas, 2DEG)通道117形成於通道層116與阻障層118之間且位於主動區112中。阻障層118可為於通道層116中引發二維電子氣通道117的層。二維電子氣通道117形成於通道層116中，且毗鄰於通道層116與阻障層118之間的界面。在一些實施方式中，通道層116的材質可為氮化鎵，而阻障層118的材質可為氮化鎵鋁。主動層110更包含絕緣區114，包圍主動區112。絕緣區114可利用佈植離子，如氧、氮、碳等，於主動層110中。在一些其他的實施方式中，絕緣區114可為淺溝槽絕緣(Shallow Trench Isolation, STI)。主動層110可選擇性地置於一基板105上。基板105的材質例如為矽(silicon)基板或藍寶石(sapphire)基板，本揭露不以此為限。在一實施方式中，半導體裝置可更包含一緩衝層(未繪示)，置於主動層110與基板105之間。Please refer to Figures 2A and 2B. In some embodiments, the active layer 110 includes a channel layer 116 and a barrier layer 118, and the barrier layer 118 is disposed on the channel layer 116. A two-dimensional electron gas (2DEG) channel 117 is formed between the channel layer 116 and the barrier layer 118 and is located in the active region 112. The barrier layer 118 may be a layer that induces a two-dimensional electron gas channel 117 in the channel layer 116. The two-dimensional electron gas channel 117 is formed in the channel layer 116 and is adjacent to the interface between the channel layer 116 and the barrier layer 118. In some embodiments, the material of the channel layer 116 may be gallium nitride, and the material of the barrier layer 118 may be aluminum gallium nitride. The active layer 110 further includes an insulating region 114 surrounding the active region 112. The insulating region 114 may use implanted ions, such as oxygen, nitrogen, and carbon, in the active layer 110. In some other embodiments, the insulating region 114 may be a Shallow Trench Isolation (STI). The active layer 110 can be selectively placed on a substrate 105. The material of the substrate 105 is, for example, a silicon substrate or a sapphire substrate, and the disclosure is not limited thereto. In one embodiment, the semiconductor device may further include a buffer layer (not shown) disposed between the active layer 110 and the substrate 105.
第3圖為第1圖與第2A圖中的半導體裝置的下源極金屬層210、下汲極金屬層220、源極電極120、汲極電極130、閘極電極140與主動層110的上視圖。請一併參照第2A圖、第2B圖與第3圖。半導體裝置更包含P型層145、介電層255、260、下源極金屬層210與下汲極金屬層220。為了清楚起見，介電層255與260繪示於第2A圖與第2B圖，且未繪示於第3圖。P型層145置於閘極電極140與主動層110之間。因此，半導體裝置為增強型(enhancement mode)電晶體。然而，在其他的實施方式中，半導體裝置可為空乏型(depletion mode)電晶體，本揭露不以此為限。介電層255置於主動層110上且具有複數個開口256、257與258。源極電極120置於開口256中，汲極電極130置於開口257中，且P型層145置於開口258中。FIG. 3 is an upper surface of the lower source metal layer 210, the lower drain metal layer 220, the source electrode 120, the drain electrode 130, the gate electrode 140, and the active layer 110 of the semiconductor device in FIGS. 1 and 2A. view. Please refer to FIG. 2A, FIG. 2B, and FIG. 3 together. The semiconductor device further includes a P-type layer 145, dielectric layers 255, 260, a lower source metal layer 210, and a lower drain metal layer 220. For the sake of clarity, the dielectric layers 255 and 260 are shown in FIGS. 2A and 2B, and are not shown in FIG. 3. The P-type layer 145 is interposed between the gate electrode 140 and the active layer 110. Therefore, the semiconductor device is an enhancement mode transistor. However, in other embodiments, the semiconductor device may be a depletion mode transistor, and the disclosure is not limited thereto. The dielectric layer 255 is disposed on the active layer 110 and has a plurality of openings 256, 257, and 258. The source electrode 120 is placed in the opening 256, the drain electrode 130 is placed in the opening 257, and the P-type layer 145 is placed in the opening 258.
介電層260置於介電層255上且覆蓋源極電極120、汲極電極130與閘極電極140。換言之，源極電極120、汲極電極130與閘極電極140置於介電層260與主動層110之間。在一些實施方式中，源極電極120與汲極電極130為歐姆電極。下源極金屬層210置於介電層260上且覆蓋源極電極120與閘極電極140，而下汲極金屬層220置於介電層260上且覆蓋汲極電極130。下源極金屬層210與下汲極金屬層220沿著第一方向D1延伸，且沿著第二方向D2交替排列。下汲極金屬層220，例如藉由置於介電層260中的貫穿結構215，電性連接至源極電極120，且與閘極電極140電性絕緣。下汲極金屬層220，例如藉由置於介電層260中的貫穿結構225，電性連接至汲極電極130。下源極金屬層210彼此分開，且下汲極金屬層220彼此分開。The dielectric layer 260 is disposed on the dielectric layer 255 and covers the source electrode 120, the drain electrode 130, and the gate electrode 140. In other words, the source electrode 120, the drain electrode 130, and the gate electrode 140 are interposed between the dielectric layer 260 and the active layer 110. In some embodiments, the source electrode 120 and the drain electrode 130 are ohmic electrodes. The lower source metal layer 210 is disposed on the dielectric layer 260 and covers the source electrode 120 and the gate electrode 140, and the lower drain metal layer 220 is disposed on the dielectric layer 260 and covers the drain electrode 130. The lower source metal layers 210 and the lower drain metal layers 220 extend along the first direction D1 and are alternately arranged along the second direction D2. The lower drain metal layer 220 is electrically connected to the source electrode 120 and is electrically insulated from the gate electrode 140 through a through structure 215 disposed in the dielectric layer 260, for example. The lower drain metal layer 220 is electrically connected to the drain electrode 130 through a through structure 225 disposed in the dielectric layer 260, for example. The lower source metal layers 210 are separated from each other, and the lower drain metal layers 220 are separated from each other.
第4圖為第1圖與第2A圖中的半導體裝置的下源極金屬層210、下汲極金屬層220、上源極金屬層230、上汲極金屬層240與主動層110的上視圖。請一併參照第2A圖、第2B圖與第4圖。半導體裝置更包含介電層270、上源極金屬層230與上汲極金屬層240。為了清楚起見，介電層270繪示於第2A圖與第2B圖，且未繪示於第4圖。介電層270覆蓋下源極金屬層210與下汲極金屬層220。換言之，下源極金屬層210與下汲極金屬層220置於介電層260與270之間。上源極金屬層230置於介電層270上且，例如藉由置於介電層270中的貫穿結構235，電性連接下源極金屬層210。上汲極金屬層240置於介電層270上且，例如藉由置於介電層270中的貫穿結構245，電性連接下汲極金屬層220。上源極金屬層230與上汲極金屬層240沿著第二方向D2延伸且沿著第一方向D1交替排列。亦即，上源極金屬層230與下源極金屬層210沿著不同方向延伸，且上汲極金屬層240與下汲極金屬層220沿著不同方向延伸。上源極金屬層230彼此分開，且上汲極金屬層240彼此分開。FIG. 4 is a top view of the lower source metal layer 210, the lower drain metal layer 220, the upper source metal layer 230, the upper drain metal layer 240, and the active layer 110 of the semiconductor device in FIGS. 1 and 2A. . Please refer to Figures 2A, 2B and 4 together. The semiconductor device further includes a dielectric layer 270, an upper source metal layer 230, and an upper drain metal layer 240. For the sake of clarity, the dielectric layer 270 is shown in FIGS. 2A and 2B, and is not shown in FIG. 4. The dielectric layer 270 covers the lower source metal layer 210 and the lower drain metal layer 220. In other words, the lower source metal layer 210 and the lower drain metal layer 220 are disposed between the dielectric layers 260 and 270. The upper source metal layer 230 is disposed on the dielectric layer 270 and, for example, is electrically connected to the lower source metal layer 210 by a through structure 235 disposed in the dielectric layer 270. The upper drain metal layer 240 is disposed on the dielectric layer 270 and, for example, is electrically connected to the lower drain metal layer 220 by a through structure 245 disposed in the dielectric layer 270. The upper source metal layers 230 and the upper drain metal layers 240 extend along the second direction D2 and are alternately arranged along the first direction D1. That is, the upper source metal layer 230 and the lower source metal layer 210 extend in different directions, and the upper drain metal layer 240 and the lower drain metal layer 220 extend in different directions. The upper source metal layers 230 are separated from each other, and the upper drain metal layers 240 are separated from each other.
請一併參照第1圖、第2A圖與第2B圖。半導體裝置更包含介電層280。為了清楚起見，介電層280繪示於第2A圖與第2B圖，且未繪示於第1圖。介電層280覆蓋上源極金屬層230與上汲極金屬層240。亦即，上源極金屬層230與上汲極金屬層240置於介電層270與280之間。源極墊150與汲極墊160置於介電層280上。源極墊150，例如藉由置於介電層280中的貫穿結構158，電性連接上源極金屬層230。汲極墊160，例如藉由置於介電層280中的貫穿結構168，電性連接上汲極金屬層240。Please refer to FIG. 1, FIG. 2A and FIG. 2B together. The semiconductor device further includes a dielectric layer 280. For the sake of clarity, the dielectric layer 280 is shown in FIGS. 2A and 2B, and is not shown in FIG. 1. The dielectric layer 280 covers the upper source metal layer 230 and the upper drain metal layer 240. That is, the upper source metal layer 230 and the upper drain metal layer 240 are interposed between the dielectric layers 270 and 280. The source pad 150 and the drain pad 160 are disposed on the dielectric layer 280. The source pad 150 is electrically connected to the source metal layer 230 through a through structure 158 disposed in the dielectric layer 280, for example. The drain pad 160 is electrically connected to the drain metal layer 240 by, for example, a through structure 168 disposed in the dielectric layer 280.
請一併參照第2A圖與第2B圖。下源極金屬層210的厚度T1小於上源極金屬層230的厚度T2與源極墊150的厚度T3的總和。藉由如此的結構，源極的電阻可降低。類似的，下汲極金屬層220的厚度T4小於上汲極金屬層240的厚度T5與汲極墊160的厚度T6的總和。藉由如此的結構，汲極的電阻可降低。Please refer to FIG. 2A and FIG. 2B together. The thickness T1 of the lower source metal layer 210 is smaller than the sum of the thickness T2 of the upper source metal layer 230 and the thickness T3 of the source pad 150. With such a structure, the resistance of the source can be reduced. Similarly, the thickness T4 of the lower drain metal layer 220 is smaller than the sum of the thickness T5 of the upper drain metal layer 240 and the thickness T6 of the drain pad 160. With this structure, the resistance of the drain can be reduced.
請參照第1圖。源極墊150的電流分散部156與汲極墊160的電流分散部166之間定義一容置空間A。源極墊150的分支部154與汲極墊160的分支部164於容置空間A的(佈線)密度為約50%至約90%。從另一角度來看，源極墊150與汲極墊160之間形成一間隙G。具體而言，間隙G由源極墊150的分支部154的邊緣與汲極墊160的分支部164的邊緣所定義而成。間隙G的面積佔容置空間A的約10%至約50%的面積。Please refer to Figure 1. An accommodation space A is defined between the current dispersion portion 156 of the source pad 150 and the current dispersion portion 166 of the drain pad 160. The (wiring) density of the branch portion 154 of the source pad 150 and the branch portion 164 of the drain pad 160 in the accommodation space A is about 50% to about 90%. From another perspective, a gap G is formed between the source pad 150 and the drain pad 160. Specifically, the gap G is defined by an edge of the branch portion 154 of the source pad 150 and an edge of the branch portion 164 of the drain pad 160. The area of the gap G accounts for about 10% to about 50% of the accommodation space A.
第5圖為本揭露一些實施方式之半導體裝置的上視圖。第5圖與第1圖的差異處在於源極墊150與汲極墊160的結構。在第5圖中，半導體裝置包含兩個源極墊150與一個汲極墊160。源極墊150為實質鏡像對稱，且汲極墊160置於兩個源極墊150之間。源極墊150為具有與第1圖的源極墊150為相似的結構。另外，汲極墊160包含一個本體部162、兩個電流分散部166與多個分支部164。兩個電流分散部166置於本體部162的相對兩側，且電流分散部166置於本體部162與分支部164之間。至於第5圖的半導體裝置的相關結構細節與第1圖的半導體裝置相似，因此便不再贅述。FIG. 5 is a top view of a semiconductor device according to some embodiments. The difference between FIG. 5 and FIG. 1 is the structure of the source pad 150 and the drain pad 160. In FIG. 5, the semiconductor device includes two source pads 150 and one drain pad 160. The source pad 150 is substantially mirror-symmetrical, and the drain pad 160 is placed between the two source pads 150. The source pad 150 has a structure similar to that of the source pad 150 in FIG. 1. In addition, the drain pad 160 includes a body portion 162, two current dispersion portions 166, and a plurality of branch portions 164. The two current dispersing portions 166 are disposed on opposite sides of the body portion 162, and the current dispersing portions 166 are disposed between the body portion 162 and the branch portion 164. As for the structural details of the semiconductor device of FIG. 5, the semiconductor device of FIG. 1 is similar to the semiconductor device of FIG.
另外，雖然在第5圖中，半導體裝置包含兩個源極墊150與一個汲極墊160，然而在其他的實施方式中，半導體裝置可包含一個源極墊150與兩個汲極墊160，或者包含交替排列的多個源極墊150與多個汲極墊160。In addition, although the semiconductor device in FIG. 5 includes two source pads 150 and one drain pad 160, in other embodiments, the semiconductor device may include one source pad 150 and two drain pads 160. Alternatively, it includes a plurality of source pads 150 and a plurality of drain pads 160 arranged alternately.
雖然本發明已以實施方式揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope shall be determined by the scope of the attached patent application.
105：基板 110：主動層 112：主動區 114：絕緣區 116：通道層 117：二維電子氣通道 118：阻障層 120：源極電極 130：汲極電極 140：閘極電極 145：P型層 150：源極墊 152、162：本體部 154、164：分支部 156、166：電流分散部 158、168、215、225、235、245：貫穿結構 160：汲極墊 170：源極外部連接元件 172、182：邊緣 180：汲極外部連接元件 210：下源極金屬層 220：下汲極金屬層 230：上源極金屬層 240：上汲極金屬層 255、260、270、280：介電層 256、257、258：開口 2A-2A、2B-2B：線段 A：容置空間 D1：第一方向 D2：第二方向 G：間隙 Is、Id：界面 L2、L5：長度 T1、T2、T3、T4、T5、T6：厚度 W1、W2、W3、W4、W5、W6：寬度105: substrate 110: active layer 112: active region 114: insulating region 116: channel layer 117: two-dimensional electron gas channel 118: barrier layer 120: source electrode 130: drain electrode 140: gate electrode 145: P-type Layer 150: source pads 152, 162: body portions 154, 164: branch portions 156, 166: current dispersion portions 158, 168, 215, 225, 235, 245: through structure 160: drain pad 170: source external connection Element 172, 182: Edge 180: Drain external connection element 210: Lower source metal layer 220: Lower drain metal layer 230: Upper source metal layer 240: Upper drain metal layer 255, 260, 270, 280: dielectric Electrical layers 256, 257, 258: openings 2A-2A, 2B-2B: segment A: accommodation space D1: first direction D2: second direction G: gap Is, Id: interface L2, L5: length T1, T2 T3, T4, T5, T6: Thickness W1, W2, W3, W4, W5, W6: Width
第1圖為本揭露一些實施方式之半導體裝置的上視圖。 第2A圖為沿著第1圖的線段2A-2A的剖面圖。 第2B圖為沿著第1圖的線段2B-2B的剖面圖。 第3圖為第1圖與第2A圖中的半導體裝置的下源極金屬層、下汲極金屬層、源極電極、汲極電極、閘極電極與主動層的上視圖。 第4圖為第1圖與第2A圖中的半導體裝置的下源極金屬層、下汲極金屬層、上源極金屬層、上汲極金屬層與主動層的上視圖。 第5圖為本揭露一些實施方式之半導體裝置的上視圖。FIG. 1 is a top view of a semiconductor device according to some embodiments. FIG. 2A is a cross-sectional view taken along line 2A-2A of FIG. 1. FIG. 2B is a cross-sectional view taken along line 2B-2B of FIG. 1. FIG. 3 is a top view of the lower source metal layer, the lower drain metal layer, the source electrode, the drain electrode, the gate electrode, and the active layer of the semiconductor device in FIGS. 1 and 2A. FIG. 4 is a top view of the lower source metal layer, the lower drain metal layer, the upper source metal layer, the upper drain metal layer, and the active layer of the semiconductor device in FIGS. 1 and 2A. FIG. 5 is a top view of a semiconductor device according to some embodiments.
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