US20150008443A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- US20150008443A1 US20150008443A1 US14/322,822 US201414322822A US2015008443A1 US 20150008443 A1 US20150008443 A1 US 20150008443A1 US 201414322822 A US201414322822 A US 201414322822A US 2015008443 A1 US2015008443 A1 US 2015008443A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/04—Assemblies of printed circuits
- H05K2201/042—Stacked spaced PCBs; Planar parts of folded flexible circuits having mounted components in between or spaced from each other
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10166—Transistor
Definitions
- the present disclosure relates to, for example, semiconductor devices applicable to powering, etc.
- FIG. 5 illustrates an example structure of such a conventional power semiconductor module.
- a gate terminal 128 and a source terminal 129 provided in a semiconductor module 118 inside a case 116 are electrically connected to a drive element 106 mounted on a control board 208 via a shortest path.
- a gate pad and a source pad of a semiconductor element 110 are connected to the gate terminal 128 and the source terminal 129 via wires 109 .
- control signals converted by a photocoupler 103 mounted on a control board 201 are transmitted to the drive element 106 .
- the control board 208 is electrically connected to the control board 201 by a lead 204 .
- the control board 208 is located as close as possible to the control board 201 to reduce the length of the lead 204 .
- FIG. 6A a conventional semiconductor module is considered, in which a photocoupler 103 and a drive element 106 are mounted close to one another on a same control board 218 .
- drive signals generated by a control board 211 located above the control board 218 are input to the control board 218 via a lead 214 .
- FIG. 6B illustrates example arrangement of specific components of the control board 218 .
- a photocoupler 103 is located as close as possible to a drive element 106 .
- a semiconductor device includes a semiconductor module including a high-side semiconductor element connected to a first gate terminal and a first source terminal, and a low-side semiconductor element connected to a second gate terminal and a second source terminal; a first control board located above the semiconductor module; a first drive element and a second drive element held by the first control board, the first drive element being connected to the first gate terminal and the first source terminal, and the second drive element being connected to the second gate terminal and the second source terminal; a second control board located above the first control board; and a plurality of photocouplers held by the second control board, output signals of the photocouplers being input to the first drive element or the second drive element.
- the semiconductor module includes a positive electrode terminal and a ground terminal provided at one side of the semiconductor module, and an output terminal provided at another side opposite to the one side.
- the first gate terminal and the first source terminal are located at the side of the semiconductor module provided with the positive electrode terminal and the ground terminal.
- the second gate terminal and the second source terminal are located at the side of the semiconductor module provided with the output terminal.
- the present disclosure provides a semiconductor device reducing the influence of noise and the influence of heat.
- FIG. 1A is a schematic cross-sectional view illustrating a semiconductor device according to a first embodiment of the present disclosure.
- FIG. 1B is a top view illustrating a plurality of semiconductor modules forming the semiconductor device according to the first embodiment of the present disclosure.
- FIG. 2A is a schematic top view illustrating a first control board forming the semiconductor device according to the first embodiment of the present disclosure.
- FIG. 2B is a schematic top view illustrating a second control board forming the semiconductor device according to the first embodiment of the present disclosure.
- FIG. 3 is a schematic top view illustrating a plurality of semiconductor modules forming a semiconductor device according to a second embodiment of the present disclosure.
- FIG. 4A is a schematic top view illustrating a first control board forming the semiconductor device according to the second embodiment of the present disclosure.
- FIG. 4B is a schematic top view illustrating a second control board forming the semiconductor device according to the second embodiment of the present disclosure.
- FIG. 5 is a cross-sectional view illustrating a conventional power semiconductor module.
- FIG. 6A is a cross-sectional view illustrating another conventional semiconductor module.
- FIG. 6B is a top view illustrating arrangement of components of conventional semiconductor modules on a control board.
- FIG. 1A As shown in FIG. 1A , three semiconductor modules 18 shown in FIG. 1B and a case 16 containing the modules are located under a first control board 8 .
- a semiconductor device outputs three-phase power.
- the semiconductor device includes the semiconductor modules 18 contained in the case 16 , the first control board 8 contained in the case 16 and located above the semiconductor modules 18 , a second control board 5 contained in the case 16 and located above the first control board 8 , and a third control board 1 located above the second control board 5 .
- a circuit including a plurality of drive elements 6 is formed on the first control board 8 .
- a circuit including a plurality of photocouplers 3 capable of transmitting electrical signals in an insulated state is formed on the second control board 5 .
- the first control board 8 is electrically connected to the second control board 5 by a first lead 4 .
- the second control board 5 is electrically connected to the third control board 1 by a second lead 2 .
- the case 16 is mounted on a heat sink 15 .
- the second control board 5 has a smaller area than the first control board 8 .
- the drive elements 6 are, for example, elements driving SiC-MOSFETs made of a wide bandgap material at a high speed.
- each of the semiconductor modules 18 includes a first transistor 10 b being a high-side semiconductor element, and a second transistor 10 a being a low-side semiconductor element.
- the transistor closer to a power source is called a high-side transistor
- the transistor closer to ground is called a low-side transistor.
- Each semiconductor module 18 is provided with a positive electrode terminal (i.e., a power source terminal) 25 , which is directly drawn from a first die pad 11 b holding the high-side first transistor 10 b , and a ground terminal (i.e., a negative electrode terminal) 26 , which is electrically connected to the low-side second transistor 10 a , at the lower side in the figure.
- An output terminal 27 which is directly drawn from a second die pad 11 a holing the low-side second transistor 10 a , is located at the upper side in the figure.
- the positive electrode terminal 25 and the ground terminal 26 are preferably located at the same side, and the output terminal 27 is preferably located at the side opposite to the side provided with the positive electrode terminal 25 and the ground terminal 26 .
- the low-side second transistor 10 a is metallically jointed onto the second die pad 11 a .
- a drain electrode of the second transistor 10 a is connected to the output terminal 27 .
- a source electrode of the second transistor 10 a is connected to the ground terminal 26 , for example, by a plurality of aluminum ribbons.
- the high-side first transistor 10 b is metallically jointed onto the first die pad 11 b .
- a drain electrode of the first transistor 10 b is connected to the positive electrode terminal 25 .
- a source electrode of the first transistor 10 b is connected to the output terminal 27 , for example, by a plurality of aluminum ribbons.
- a first gate terminal 28 b and a first source terminal 29 b connected to the high-side first transistor 10 b are provided at the high side at which the positive electrode terminal 25 and the ground terminal 26 are located.
- a second gate terminal 28 a and a second source terminal 29 a connected to the low-side second transistor 10 a are provided at the low side at which the output terminal 27 is located.
- a gate pad and a source pad of the second transistor 10 a are connected to the second gate terminal 28 a and the second source terminal 29 a by respective wires 9 .
- a gate pad and a source pad of the first transistor 10 b are connected to the first gate terminal 28 b and the first source terminal 29 b by respective wires 9 .
- the heat sink 15 is exposed from the opening.
- the die pads 11 a and 11 b on which the transistors 10 a and 10 b are mounted, are provided on a single heat dissipater 13 via an insulating member 12 .
- the heat dissipater 13 is fixed onto the heat sink 15 at the opening of the case 16 .
- This structure electrically insulates the die pads 11 a and 11 b from the heat dissipater 13 , and efficiently releases the heat, which is generated from the transistors 10 a and 10 b , from the heat dissipater 13 to the heat sink 15 .
- the insulating member 12 is made of a material having high voltage resistance and high thermal conductivity.
- each semiconductor module 18 the heat dissipater 13 , the insulating member 12 , the die pads 11 a and 11 b , the transistors 10 a and 10 b , and the wires 9 are integrally sealed on the heat sink 15 by sealing resin 14 .
- the positive electrode terminals 25 and the ground terminals 26 of the semiconductor modules 18 are metallically jointed to a positive electrode-side bus bar 20 a and a ground-side bus bar 20 b respectively, which are fixed to the case 16 being a support body.
- the output terminals 27 of the semiconductor modules 18 are metallically jointed to an UO terminal 21 , a VO terminal 22 , and a WO terminal 23 , which are embedded in the case 16 .
- the first control board 8 located directly above the three semiconductor modules 18 is supported by the case 16 .
- the first control board 8 is provided with a control circuit (e.g., a gate drive circuit) including the drive elements 6 , etc.
- each semiconductor module 18 for example, the first gate terminal 28 b and the first source terminal 29 b of the high-side first transistor 10 b are electrically connected to the output terminal of one of the drive elements (i.e., a first drive element) 6 mounted on the first control board 8 .
- the second gate terminal 28 a and the second source terminal 29 a of the low-side second transistor 10 a are electrically connected to the output terminal of the other one of the drive element (i.e., a second drive element) 6 mounted on the first control board 8 .
- the drive elements 6 are connected to the gate pads and the source pads of the transistors 10 a and 10 b via shortest paths.
- each semiconductor module according to this embodiment reduces the inductance between the gates and the sources to improve gate controllability.
- the second gate terminals 28 a and the second source terminals 29 a of the second transistors 10 a are all located at the low side.
- the first gate terminals 28 b and the first source terminals 29 b of the first transistors 10 b are all located at the high side.
- the first gate terminal 28 b and the first source terminal 29 b of each high-side first transistor 10 b are located close to the positive electrode terminal 25 and the ground terminal 26
- the second gate terminal 28 a and the second source terminal 29 a of the low-side second transistor 10 a are located close to the output terminal 27 .
- the first control board 8 is provided as shown in FIG. 2A .
- FIG. 2A is a top view illustrating the structure of the first control board 8 .
- broken lines represent one of the semiconductor modules 18 covered by the first control board 8 .
- the first gate terminals 28 b and the first source terminals 29 b are connected to respective through-holes 50 provided in high-side first circuit regions 51 , 52 , and 53 .
- the first circuit region 51 is a high-side W-phase control circuit region
- the first circuit region 52 is a high-side V-phase control circuit region
- the first circuit region 53 is a high-side U-phase control circuit region.
- the high-side first circuit regions 51 - 53 are provided to correspond to the three semiconductor modules 18 .
- the second gate terminals 28 a and the second source terminals 29 a are connected to respective through-holes 50 located in a low-side second circuit region 54 .
- the second circuit region 54 is, for example, a low-side control circuit region.
- the high-side first circuit regions 51 - 53 are located above the high-side U-phase, V-phase, and W-phase first transistors 10 b , respectively.
- the low-side second circuit region 54 is located above the low-side U-phase, V-phase, and W-phase second transistors 10 a .
- this structure connects the drive elements 6 to the gate pads and the source pads of the transistors 10 a and 10 b to be controlled via shortest paths, with the potential of the arm elements on the first control board 8 being independent from one another. As a result, the inductance between the gates and the sources reduces, thereby providing excellent gate controllability.
- a plurality of low-side control signal lines of the first control board 8 are connected to control signal lines located in a wiring region 75 of the second control board 5 by the connectors 56 d .
- a plurality of high-side control signal lines of the first control board 8 are connected to control signal lines located in wiring regions 72 - 74 of the second control board 5 by the connectors 56 a , 56 b , and 56 c , respectively.
- the wiring regions 72 - 75 are, for example, control signal wiring regions.
- power semiconductor elements such as SiC-MOSFETs can be operated at a high speed by setting the length of the first lead 4 , which is the distance between the first control board 8 and the second control board 5 , to 20 mm or shorter. For example, if the length of the first lead 4 is longer than 20 mm, the ground potential of the first control board 8 differs from the ground potential of the second control board 5 in high speed operation. Then, logic values of signals input from the photocouplers 3 to the drive elements 6 may not be held.
- the photocouplers 3 are mounted on the second control board 5 and the drive elements 6 are mounted on the first control board 8 located under the second control board 5 . This keeps the heat sensitive elements such as the photocouplers 3 away from the semiconductor modules 18 whose temperatures rise in operation. Therefore, a highly reliable semiconductor device is provided.
- FIG. 3 illustrates how to mount three semiconductor modules included in the semiconductor device according to this embodiment.
- each semiconductor module 18 includes a positive electrode terminal 25 , a ground terminal 26 , an output terminal 27 , a plurality of gate terminals 28 a and 28 b , and a plurality of source terminals 29 a and 29 b .
- a low-side second transistor 10 a is formed by, for example, connecting three elements in parallel and metallically jointing the elements onto a second die pad 11 a , from which the output terminal 27 is drawn.
- the source electrode of the low-side second transistor 10 a is connected to the ground terminal 26 by a plurality of aluminum ribbons.
- a high-side first transistor 10 b is formed by, for example, connecting three elements in parallel and metallically jointing the elements onto a first die pad 11 b , from which the positive electrode terminal 25 is drawn.
- the source electrode of the high-side first transistor 10 b is connected to the output terminal 27 by a plurality of aluminum ribbons.
- the gate terminals 28 a and 28 b and the source terminals 29 a and 29 b are not preferably connected to the side provided with the positive electrode terminal 25 and the ground terminal 26 , and the side provided with the output terminal 27 .
- the transistors 10 a and 10 b are difficult to be switched at the same time. As shown in FIG.
- the gate terminals 28 a and 28 b and the source terminals 29 a and 29 b are preferably located in a region not provided with the positive electrode terminal 25 , the ground terminal 26 , or the output terminal 27 such that the lengths of the wires are equal.
- This structure enables more stable parallel drive.
- the gate terminals 28 a and 28 b and the source terminals 29 a and 29 b may be provided for each chip, or may be connected inside each semiconductor module 18 except for each single pair located outside.
- FIG. 4A illustrates example arrangement of drive elements 6 and through-holes 67 and 68 on a first control board 8 .
- the through-holes 67 are, for example, gate terminal through-holes
- the through-holes 68 are, for example, source terminal through-holes.
- the gate terminals 28 a and 28 b and the source terminals 29 a and 29 b which are connected to the low-side second transistors 10 a corresponding to the U-phase, V-phase, and W-phase of the semiconductor modules 18 , are connected to the through-holes 67 and 68 provided in a second circuit region 64 .
- the gate terminals 28 a and 28 b and the source terminals 29 a and 29 b which are connected to the high-side first transistors 10 b corresponding to the U-phase, V-phase, and W-phase, are connected to the through-holes 67 and 68 provided in each of first circuit regions 61 , 62 , and 63 .
- Circuit components such as drive elements 6 are provided in the circuit regions 61 - 64 .
- An insulating region 65 not provided with the circuit components or conductive patterns is formed at the boundaries between the circuit regions 61 - 64 .
- the insulating region 65 separates the high-side circuit regions 61 - 63 from the low-side circuit region 64 in the vertical direction of the substrate (i.e., the lateral direction of FIG. 4A ) and separates at boundaries between the high-side circuit regions 61 and 62 and between the high-side circuit regions 62 and 63 .
- a second control board 5 is located directly above the first control board 8 .
- the control circuit formed above the second control board 5 insulates a drive signal generation circuit including photocouplers 3 from the semiconductor modules 18 .
- FIG. 4B illustrates example overlapping where a second control board 5 is located directly above a first control board 8 having the structure shown in FIG. 4A .
- Low-side signal lines of the first control board 8 are connected to control signal lines located in a wiring region 75 by connectors 66 d of the second control board 5 . This connects input terminals of the drive elements 6 at the low side to output terminals of the photocouplers 3 .
- high-side signal lines of the first control board 8 are connected to control signal lines located in wiring regions 72 , 73 , and 74 by connectors 66 a , 66 b , and 66 c , respectively, on the second control board 5 . This connects input terminals of the drive elements 6 at the high side to the output terminals of the photocouplers 3 .
- Signal lines 81 connecting a signal input section 80 of the second control board 5 to the photocouplers 3 are preferably located on the low-side second circuit region 64 of the first control board 8 .
- the photocouplers 3 and the drive elements 6 are mounted separately on the second control board 5 and on the first control board 8 , respectively. This keeps the heat sensitive elements such as the photocouplers 3 away from the semiconductor modules 18 whose temperatures rise in operation. Therefore, the semiconductor device according to the present disclosure secures high reliability.
- the photocouplers 3 are provided not on the third control board 1 but on the second control board 5 , thereby mounting the photocouplers 3 at a distance of 20 mm or shorter from the first control board 8 .
- the drive elements 6 are thus mounted close to the photocouplers 3 . As a result, high speed drive elements such as SiC-MOSFETs are stably operated by parallel drive under a high temperature.
- the semiconductor device according to the present disclosure provides high reliability and are useful for power semiconductor devices, etc.
Abstract
Description
- This application claims priority to Japanese Patent Application No. 2013-141476 filed on Jul. 5, 2013 and Japanese Patent Application No. 2014-097433 filed on May 9, 2014, the entire disclosures of which are incorporated by reference herein.
- The present disclosure relates to, for example, semiconductor devices applicable to powering, etc.
- Higher efficiency in power semiconductor modules for power conversion is demanded in view of low energy consumption.
- Most of heat generated in power semiconductor modules in operation is generated from semiconductor elements. In order to reduce the inductance between ground and power sources in half bridge structures to the limit, optimization in the structures of power semiconductor modules is also demanded. To achieve the objective, most suitable structures of power semiconductor modules formed by closely arranging a plurality of semiconductor chips are considered from both the heat and electrical points of view.
-
FIG. 5 illustrates an example structure of such a conventional power semiconductor module. - As shown in
FIG. 5 , in the conventional power semiconductor module, a gate terminal 128 and a source terminal 129 provided in asemiconductor module 118 inside acase 116 are electrically connected to adrive element 106 mounted on acontrol board 208 via a shortest path. Inside thesemiconductor module 118, a gate pad and a source pad of asemiconductor element 110 are connected to the gate terminal 128 and the source terminal 129 viawires 109. In the conventional power semiconductor module, control signals converted by aphotocoupler 103 mounted on acontrol board 201 are transmitted to thedrive element 106. Thecontrol board 208 is electrically connected to thecontrol board 201 by alead 204. If thelead 204 is long and fine, the ground potential of thecontrol board 208 and the ground potential of thecontrol board 201 fluctuate to easily generate noise. To address the problem, in the conventional structure, thecontrol board 208 is located as close as possible to thecontrol board 201 to reduce the length of thelead 204. - In order to reduce the influence of the
lead 204, as shown inFIG. 6A , a conventional semiconductor module is considered, in which aphotocoupler 103 and adrive element 106 are mounted close to one another on asame control board 218. In the structure ofFIG. 6A , drive signals generated by acontrol board 211 located above thecontrol board 218 are input to thecontrol board 218 via alead 214.FIG. 6B illustrates example arrangement of specific components of thecontrol board 218. As shown inFIG. 6B , in each conventional semiconductor module, aphotocoupler 103 is located as close as possible to adrive element 106. - Although each of the structures shown in
FIGS. 6A and 6B reduces the influence of noise, the temperature of thephotocoupler 103 may rise, since thephotocoupler 103 is mounted on thecontrol board 218 together with thedrive element 106. - In order to reduce the influence of heat, providing a shield between two control boards is considered (see, e.g., Japanese Unexamined Patent Publication No. 2001-237368).
- It is however necessary to increase the distance between the control boards to provide the shield between the two control boards as in the invention of Japanese Unexamined Patent Publication No. 2001-237368. If the distance between the two control boards increases, a long lead is needed to connect the two control boards. This may cause noise.
- It is an objective of the present disclosure to provide a semiconductor device which achieves the objective of reducing the influence of noise and the influence of heat.
- In order to achieve the objective, a semiconductor device according to a first aspect of the present disclosure includes a semiconductor module including a high-side semiconductor element connected to a first gate terminal and a first source terminal, and a low-side semiconductor element connected to a second gate terminal and a second source terminal; a first control board located above the semiconductor module; a first drive element and a second drive element held by the first control board, the first drive element being connected to the first gate terminal and the first source terminal, and the second drive element being connected to the second gate terminal and the second source terminal; a second control board located above the first control board; and a plurality of photocouplers held by the second control board, output signals of the photocouplers being input to the first drive element or the second drive element. The semiconductor module includes a positive electrode terminal and a ground terminal provided at one side of the semiconductor module, and an output terminal provided at another side opposite to the one side. The first gate terminal and the first source terminal are located at the side of the semiconductor module provided with the positive electrode terminal and the ground terminal. The second gate terminal and the second source terminal are located at the side of the semiconductor module provided with the output terminal.
- The present disclosure provides a semiconductor device reducing the influence of noise and the influence of heat.
-
FIG. 1A is a schematic cross-sectional view illustrating a semiconductor device according to a first embodiment of the present disclosure. -
FIG. 1B is a top view illustrating a plurality of semiconductor modules forming the semiconductor device according to the first embodiment of the present disclosure. -
FIG. 2A is a schematic top view illustrating a first control board forming the semiconductor device according to the first embodiment of the present disclosure. -
FIG. 2B is a schematic top view illustrating a second control board forming the semiconductor device according to the first embodiment of the present disclosure. -
FIG. 3 is a schematic top view illustrating a plurality of semiconductor modules forming a semiconductor device according to a second embodiment of the present disclosure. -
FIG. 4A is a schematic top view illustrating a first control board forming the semiconductor device according to the second embodiment of the present disclosure. -
FIG. 4B is a schematic top view illustrating a second control board forming the semiconductor device according to the second embodiment of the present disclosure. -
FIG. 5 is a cross-sectional view illustrating a conventional power semiconductor module. -
FIG. 6A is a cross-sectional view illustrating another conventional semiconductor module. -
FIG. 6B is a top view illustrating arrangement of components of conventional semiconductor modules on a control board. - Embodiments of the present disclosure will be described hereinafter with reference to the drawings. In the following description, the same reference characters are used to represent equivalent elements, and the explanation thereof will be omitted as appropriate.
- A power semiconductor device according to a first embodiment will be described with reference to
FIGS. 1A , 1B, 2A and 2B.FIG. 1B illustrates that three semiconductor modules forming the semiconductor device according to this embodiment are embedded in a case. - As shown in
FIG. 1A , threesemiconductor modules 18 shown inFIG. 1B and acase 16 containing the modules are located under afirst control board 8. In this embodiment, an example will be described where a semiconductor device outputs three-phase power. - As shown in
FIG. 1A , the semiconductor device according to this embodiment includes thesemiconductor modules 18 contained in thecase 16, thefirst control board 8 contained in thecase 16 and located above thesemiconductor modules 18, asecond control board 5 contained in thecase 16 and located above thefirst control board 8, and athird control board 1 located above thesecond control board 5. - A circuit including a plurality of
drive elements 6 is formed on thefirst control board 8. A circuit including a plurality ofphotocouplers 3 capable of transmitting electrical signals in an insulated state is formed on thesecond control board 5. Thefirst control board 8 is electrically connected to thesecond control board 5 by afirst lead 4. Thesecond control board 5 is electrically connected to thethird control board 1 by asecond lead 2. Thecase 16 is mounted on aheat sink 15. InFIGS. 1A-2B , as viewed in plan, thesecond control board 5 has a smaller area than thefirst control board 8. Thedrive elements 6 are, for example, elements driving SiC-MOSFETs made of a wide bandgap material at a high speed. - First, the structures of the
semiconductor modules 18 will be described. As shown inFIG. 1B , each of thesemiconductor modules 18 includes afirst transistor 10 b being a high-side semiconductor element, and asecond transistor 10 a being a low-side semiconductor element. - In general, for example, where transistors having the same polarity are connected in series to an output terminal of a great-power switching circuit to form a half-bridge circuit, the transistor closer to a power source is called a high-side transistor, and the transistor closer to ground is called a low-side transistor.
- Each
semiconductor module 18 is provided with a positive electrode terminal (i.e., a power source terminal) 25, which is directly drawn from afirst die pad 11 b holding the high-sidefirst transistor 10 b, and a ground terminal (i.e., a negative electrode terminal) 26, which is electrically connected to the low-sidesecond transistor 10 a, at the lower side in the figure. Anoutput terminal 27, which is directly drawn from asecond die pad 11 a holing the low-sidesecond transistor 10 a, is located at the upper side in the figure. As such, as a structure of eachsemiconductor module 18, thepositive electrode terminal 25 and theground terminal 26 are preferably located at the same side, and theoutput terminal 27 is preferably located at the side opposite to the side provided with thepositive electrode terminal 25 and theground terminal 26. - The low-side
second transistor 10 a is metallically jointed onto thesecond die pad 11 a. A drain electrode of thesecond transistor 10 a is connected to theoutput terminal 27. A source electrode of thesecond transistor 10 a is connected to theground terminal 26, for example, by a plurality of aluminum ribbons. The high-sidefirst transistor 10 b is metallically jointed onto thefirst die pad 11 b. A drain electrode of thefirst transistor 10 b is connected to thepositive electrode terminal 25. A source electrode of thefirst transistor 10 b is connected to theoutput terminal 27, for example, by a plurality of aluminum ribbons. - A
first gate terminal 28 b and afirst source terminal 29 b connected to the high-sidefirst transistor 10 b are provided at the high side at which thepositive electrode terminal 25 and theground terminal 26 are located. On the other hand, asecond gate terminal 28 a and a second source terminal 29 a connected to the low-sidesecond transistor 10 a are provided at the low side at which theoutput terminal 27 is located. A gate pad and a source pad of thesecond transistor 10 a are connected to thesecond gate terminal 28 a and the second source terminal 29 a byrespective wires 9. Similarly, a gate pad and a source pad of thefirst transistor 10 b are connected to thefirst gate terminal 28 b and thefirst source terminal 29 b byrespective wires 9. - An opening is formed at the bottom of the
case 16. Theheat sink 15 is exposed from the opening. On the other hand, thedie pads transistors single heat dissipater 13 via an insulatingmember 12. Theheat dissipater 13 is fixed onto theheat sink 15 at the opening of thecase 16. This structure electrically insulates thedie pads heat dissipater 13, and efficiently releases the heat, which is generated from thetransistors heat dissipater 13 to theheat sink 15. The insulatingmember 12 is made of a material having high voltage resistance and high thermal conductivity. In eachsemiconductor module 18, theheat dissipater 13, the insulatingmember 12, thedie pads transistors wires 9 are integrally sealed on theheat sink 15 by sealingresin 14. - The
positive electrode terminals 25 and theground terminals 26 of thesemiconductor modules 18 are metallically jointed to a positive electrode-side bus bar 20 a and a ground-side bus bar 20 b respectively, which are fixed to thecase 16 being a support body. Theoutput terminals 27 of thesemiconductor modules 18 are metallically jointed to anUO terminal 21, aVO terminal 22, and a WOterminal 23, which are embedded in thecase 16. - The
first control board 8 located directly above the threesemiconductor modules 18 is supported by thecase 16. Thefirst control board 8 is provided with a control circuit (e.g., a gate drive circuit) including thedrive elements 6, etc. - As shown in
FIGS. 1A and 2B , in eachsemiconductor module 18, for example, thefirst gate terminal 28 b and thefirst source terminal 29 b of the high-sidefirst transistor 10 b are electrically connected to the output terminal of one of the drive elements (i.e., a first drive element) 6 mounted on thefirst control board 8. Although not shown, thesecond gate terminal 28 a and the second source terminal 29 a of the low-sidesecond transistor 10 a are electrically connected to the output terminal of the other one of the drive element (i.e., a second drive element) 6 mounted on thefirst control board 8. With this structure, thedrive elements 6 are connected to the gate pads and the source pads of thetransistors - As shown in
FIG. 1B , where the threesemiconductor modules 18 are arranged such that the low-sidesecond transistors 10 a and the high-sidefirst transistors 10 b are aligned in the same direction, thesecond gate terminals 28 a and thesecond source terminals 29 a of thesecond transistors 10 a are all located at the low side. On the other hand, thefirst gate terminals 28 b and thefirst source terminals 29 b of thefirst transistors 10 b are all located at the high side. In this embodiment, as described above, thefirst gate terminal 28 b and thefirst source terminal 29 b of each high-sidefirst transistor 10 b are located close to thepositive electrode terminal 25 and theground terminal 26, while thesecond gate terminal 28 a and the second source terminal 29 a of the low-sidesecond transistor 10 a are located close to theoutput terminal 27. Relative to such arrangement of the terminals, thefirst control board 8 is provided as shown inFIG. 2A . -
FIG. 2A is a top view illustrating the structure of thefirst control board 8. InFIG. 2A , broken lines represent one of thesemiconductor modules 18 covered by thefirst control board 8. - As shown in
FIG. 2A , thefirst gate terminals 28 b and thefirst source terminals 29 b are connected to respective through-holes 50 provided in high-sidefirst circuit regions first circuit region 51 is a high-side W-phase control circuit region, thefirst circuit region 52 is a high-side V-phase control circuit region, and thefirst circuit region 53 is a high-side U-phase control circuit region. In this embodiment, the high-side first circuit regions 51-53 are provided to correspond to the threesemiconductor modules 18. - As shown in
FIG. 2A , thesecond gate terminals 28 a and thesecond source terminals 29 a are connected to respective through-holes 50 located in a low-sidesecond circuit region 54. Thesecond circuit region 54 is, for example, a low-side control circuit region. - As described above, in the semiconductor device according to this embodiment, the high-side first circuit regions 51-53 are located above the high-side U-phase, V-phase, and W-phase
first transistors 10 b, respectively. The low-sidesecond circuit region 54 is located above the low-side U-phase, V-phase, and W-phasesecond transistors 10 a. In this embodiment, this structure connects thedrive elements 6 to the gate pads and the source pads of thetransistors first control board 8 being independent from one another. As a result, the inductance between the gates and the sources reduces, thereby providing excellent gate controllability. - Since circuit components such as
drive elements 6 are provided in the circuit regions 51-54, the circuit components are preferably insulated from one another. In this embodiment, an insulatingregion 55 not provided with the circuit components or conductive patterns is formed to insulate and isolate the boundaries between the circuit regions 51-54. Specifically, the insulatingregion 55 insulates and isolates the boundary between the low-sidesecond circuit region 54 and the high-side first circuit regions 51-53, and insulates and isolates the boundaries between the high-sidefirst circuit regions first circuit regions - On the
first control board 8, a plurality of connectors 56 a-56 d are linearly arranged as viewed in plan in regions of the high-side first circuit regions 51-53, which face the low-sidesecond circuit region 54, and a region of thesecond circuit region 54, which faces the high-sidefirst circuit region 53, respectively. That is, the plurality of connectors 56 a-56 d are linearly arranged as viewed in plan in the vicinity of the boundary between the high-side first circuit regions 51-53 and the low-sidesecond circuit region 54. The connectors 56 a-56 d are, for example, control signal connectors. -
FIG. 2B is a top view illustrating the structure of thesecond control board 5. InFIG. 2B , broken lines represent one of thesemiconductor modules 18 covered by thesecond control board 5 and thefirst control board 8. - As shown in
FIG. 2B , a plurality of low-side control signal lines of thefirst control board 8 are connected to control signal lines located in awiring region 75 of thesecond control board 5 by theconnectors 56 d. Similarly, a plurality of high-side control signal lines of thefirst control board 8 are connected to control signal lines located in wiring regions 72-74 of thesecond control board 5 by theconnectors - A plurality of
signal lines 81 connecting asignal input section 80 of thesecond control board 5 to thephotocouplers 3 are preferably located above the low-sidesecond circuit region 54 of thefirst control board 8. In this embodiment, since thefirst control board 8 is mounted close to thesecond control board 5, a low voltage signal line (e.g., a signal line allowing a logic signal with a voltage of 5V or lower to flow) can be located not close to the high-side first circuit regions 51-53 which cause voltage fluctuations of hundreds volts but in the low-sidesecond circuit region 54, thereby reducing the influence of noise. - In this embodiment, power semiconductor elements such as SiC-MOSFETs can be operated at a high speed by setting the length of the
first lead 4, which is the distance between thefirst control board 8 and thesecond control board 5, to 20 mm or shorter. For example, if the length of thefirst lead 4 is longer than 20 mm, the ground potential of thefirst control board 8 differs from the ground potential of thesecond control board 5 in high speed operation. Then, logic values of signals input from thephotocouplers 3 to thedrive elements 6 may not be held. More specifically, assume that the minimum signal transmittance speed is (20 mm)/(70% of the speed of light), which is the ratio of the length of the lead to the signal transmittance speed in the lead, in high speed operation in which the voltage change rate of each phase output varies by 50 kV/μs. This prevents the ground potential difference of 0.48 V, which corresponds to the threshold of logic determination of a general drive element. According to the verification of the present inventors, operation at 50 kV/μs or lower is possible where thefirst lead 4 has a length of 20 mm or shorter. - A drive signal generation circuit including a microcomputer is provided on the
third control board 1 located above thesecond control board 5. Drive signals are output from thethird control board 1 via thesecond lead 2 to thesignal input section 80 of thesecond control board 5. While thethird control board 1 is preferably connected to thesecond control board 5 at a short distance, the distance between thethird control board 1 and thesecond control board 5 is not limited as long as the quality of the signals is not damaged. - As described above, in the semiconductor device according to this embodiment, the
photocouplers 3 are mounted on thesecond control board 5 and thedrive elements 6 are mounted on thefirst control board 8 located under thesecond control board 5. This keeps the heat sensitive elements such as thephotocouplers 3 away from thesemiconductor modules 18 whose temperatures rise in operation. Therefore, a highly reliable semiconductor device is provided. - As described above, the semiconductor device according to this embodiment reduces the influence of noise on logic signals caused by potential fluctuations at the low side. Therefore, the semiconductor device according to this embodiment reduces the influence of noise and the influence of heat without using a shield against the heat.
- Semiconductor modules forming a power semiconductor device according to a second embodiment will be described hereinafter with reference to
FIGS. 3 , 4A, and 4B.FIG. 3 illustrates how to mount three semiconductor modules included in the semiconductor device according to this embodiment. - As shown in
FIG. 3 , eachsemiconductor module 18 includes apositive electrode terminal 25, aground terminal 26, anoutput terminal 27, a plurality ofgate terminals source terminals second transistor 10 a is formed by, for example, connecting three elements in parallel and metallically jointing the elements onto asecond die pad 11 a, from which theoutput terminal 27 is drawn. The source electrode of the low-sidesecond transistor 10 a is connected to theground terminal 26 by a plurality of aluminum ribbons. A high-sidefirst transistor 10 b is formed by, for example, connecting three elements in parallel and metallically jointing the elements onto afirst die pad 11 b, from which thepositive electrode terminal 25 is drawn. The source electrode of the high-sidefirst transistor 10 b is connected to theoutput terminal 27 by a plurality of aluminum ribbons. - In the structure of each
semiconductor module 18, thepositive electrode terminal 25 and theground terminal 26 are preferably located at one side, and theoutput terminal 27 is preferably located at the side opposite to the one side. While the low-sidesecond transistor 10 a and the high-sidefirst transistor 10 b included in eachsemiconductor module 18 are formed by three elements, the number of the elements is not limited to three. Eachsemiconductor module 18 reduces inductance by using bus bars for wiring or other structures. In this embodiment, a plurality of chips are arranged in a line to form each of the low-sidesecond transistor 10 a and the high-sidefirst transistor 10 b to connect the chips to thegate terminals source terminals respective wires 9. - As such, in arranging the plurality of
transistors gate terminals source terminals positive electrode terminal 25 and theground terminal 26, and the side provided with theoutput terminal 27. With this structure, since the lengths of wires of thegate terminals source terminals transistors FIG. 3 , thegate terminals source terminals positive electrode terminal 25, theground terminal 26, or theoutput terminal 27 such that the lengths of the wires are equal. This structure enables more stable parallel drive. Thegate terminals source terminals semiconductor module 18 except for each single pair located outside. - In this embodiment, as shown in
FIG. 3 , for example, where threesemiconductor modules 18 are provided in the same direction, the arrangement of thegate terminals source terminals FIG. 4A illustrates example arrangement ofdrive elements 6 and through-holes first control board 8. The through-holes 67 are, for example, gate terminal through-holes, while the through-holes 68 are, for example, source terminal through-holes. - The
gate terminals source terminals second transistors 10 a corresponding to the U-phase, V-phase, and W-phase of thesemiconductor modules 18, are connected to the through-holes second circuit region 64. Similarly, thegate terminals source terminals first transistors 10 b corresponding to the U-phase, V-phase, and W-phase, are connected to the through-holes first circuit regions drive elements 6 are provided in the circuit regions 61-64. Aninsulating region 65 not provided with the circuit components or conductive patterns is formed at the boundaries between the circuit regions 61-64. In this embodiment, the insulatingregion 65 separates the high-side circuit regions 61-63 from the low-side circuit region 64 in the vertical direction of the substrate (i.e., the lateral direction ofFIG. 4A ) and separates at boundaries between the high-side circuit regions side circuit regions - In this embodiment, the low-side
second circuit region 64 is located above the U-phase, V-phase, and W-phase low-sidesecond transistors 10 a. Similarly, the high-side first circuit regions 61-63 are located above the U-phase, V-phase, and W-phase high-sidefirst transistors 10 b. This structure connects thedrive elements 6 to the gate pads and the source pads of thetransistors circuit regions - A
second control board 5 is located directly above thefirst control board 8. The control circuit formed above thesecond control board 5 insulates a drive signal generationcircuit including photocouplers 3 from thesemiconductor modules 18.FIG. 4B illustrates example overlapping where asecond control board 5 is located directly above afirst control board 8 having the structure shown inFIG. 4A . - Low-side signal lines of the
first control board 8 are connected to control signal lines located in awiring region 75 byconnectors 66 d of thesecond control board 5. This connects input terminals of thedrive elements 6 at the low side to output terminals of thephotocouplers 3. Similarly, high-side signal lines of thefirst control board 8 are connected to control signal lines located inwiring regions connectors second control board 5. This connects input terminals of thedrive elements 6 at the high side to the output terminals of thephotocouplers 3.Signal lines 81 connecting asignal input section 80 of thesecond control board 5 to thephotocouplers 3 are preferably located on the low-sidesecond circuit region 64 of thefirst control board 8. - For example, the
first control board 8 is mounted close to thesecond control board 5. The control signals are logic signals with a voltage of 5 V or lower. If formed across the high-side first circuit regions 61-63 causing voltage fluctuations of hundreds volts at a short distance, such low voltage signal lines are influenced by noise. In order to reduce the influence of noise, these low voltage signal lines are preferably located above the low-sidesecond circuit region 64. As described above in the first embodiment, power semiconductor elements such as SiC-MOSFETs can be operated at a high speed by setting the length of thefirst lead 4, which is the distance between thefirst control board 8 and thesecond control board 5, to 20 mm or shorter. - A drive signal generation circuit including a microcomputer is mounted on a
third control board 1. Drive signals are output from thethird control board 1 via asecond lead 2 to the signal input section of thesecond control board 5. - As described above, the
photocouplers 3 and thedrive elements 6 are mounted separately on thesecond control board 5 and on thefirst control board 8, respectively. This keeps the heat sensitive elements such as thephotocouplers 3 away from thesemiconductor modules 18 whose temperatures rise in operation. Therefore, the semiconductor device according to the present disclosure secures high reliability. Thephotocouplers 3 are provided not on thethird control board 1 but on thesecond control board 5, thereby mounting thephotocouplers 3 at a distance of 20 mm or shorter from thefirst control board 8. Thedrive elements 6 are thus mounted close to thephotocouplers 3. As a result, high speed drive elements such as SiC-MOSFETs are stably operated by parallel drive under a high temperature. - The semiconductor device according to the present disclosure provides high reliability and are useful for power semiconductor devices, etc.
Claims (9)
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JP2013141476 | 2013-07-05 | ||
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JP2014-097433 | 2014-05-09 | ||
JP2014097433A JP6337394B2 (en) | 2013-07-05 | 2014-05-09 | Semiconductor device |
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US10348216B2 (en) * | 2016-03-02 | 2019-07-09 | Mitsubishi Electric Corporation | Electric power converting apparatus with inner plane of control board fixed to housing |
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EP2894775B1 (en) * | 2012-09-04 | 2019-02-20 | Fuji Electric Co., Ltd. | Intelligent module |
WO2015040970A1 (en) * | 2013-09-18 | 2015-03-26 | 日立オートモティブシステムズ株式会社 | Power converter |
WO2016065485A1 (en) * | 2014-10-31 | 2016-05-06 | Algozen Corporation | A mounting apparatus, for mounting at least one heat dissipating electrical device, optionally including a heat sink body for solid, gas and fluid heat exchange, and circuit board assembly providing interface between circuits |
CN105118818B (en) * | 2015-07-20 | 2018-08-21 | 东南大学 | A kind of power module of square flat pin-free packaging structure |
CN110115115A (en) * | 2017-01-17 | 2019-08-09 | 株式会社藤仓 | Wiring body and Wiring body component |
DE212019000114U1 (en) * | 2018-10-15 | 2020-04-21 | Rohm Co., Ltd. | Control module and semiconductor device |
JP7267826B2 (en) * | 2019-04-18 | 2023-05-02 | 三菱重工サーマルシステムズ株式会社 | Automotive electric compressor |
JP2020178479A (en) * | 2019-04-19 | 2020-10-29 | 日本電産エレシス株式会社 | Inverter unit |
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JPH0645516A (en) * | 1992-07-27 | 1994-02-18 | Sanyo Electric Co Ltd | Hybrid integrated circuit device |
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DE10101086B4 (en) * | 2000-01-12 | 2007-11-08 | International Rectifier Corp., El Segundo | Power module unit |
JP4163360B2 (en) | 2000-02-21 | 2008-10-08 | 三菱電機株式会社 | Power module |
US6735968B2 (en) * | 2002-03-29 | 2004-05-18 | Hitachi, Ltd. | Refrigerating apparatus and an inverter device used therein |
JP3682550B2 (en) * | 2002-03-29 | 2005-08-10 | 株式会社日立製作所 | Refrigeration apparatus and inverter apparatus used therefor |
JP4909712B2 (en) * | 2006-11-13 | 2012-04-04 | 日立オートモティブシステムズ株式会社 | Power converter |
CN100582844C (en) * | 2006-12-15 | 2010-01-20 | 富准精密工业(深圳)有限公司 | Built-in optical focusing lens structure |
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JP5171520B2 (en) | 2008-09-30 | 2013-03-27 | 日立オートモティブシステムズ株式会社 | Power converter |
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2014
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US10348216B2 (en) * | 2016-03-02 | 2019-07-09 | Mitsubishi Electric Corporation | Electric power converting apparatus with inner plane of control board fixed to housing |
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US8916967B1 (en) | 2014-12-23 |
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JP2015029403A (en) | 2015-02-12 |
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CN104282669B (en) | 2018-11-20 |
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