US20140346598A1 - High voltage pmos (hvpmos) transistor with a composite drift region and manufacture method thereof - Google Patents

High voltage pmos (hvpmos) transistor with a composite drift region and manufacture method thereof Download PDF

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US20140346598A1
US20140346598A1 US14/277,245 US201414277245A US2014346598A1 US 20140346598 A1 US20140346598 A1 US 20140346598A1 US 201414277245 A US201414277245 A US 201414277245A US 2014346598 A1 US2014346598 A1 US 2014346598A1
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drift region
composite
oxide layer
deep
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Chenggong Han
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Hangzhou Silergy Semiconductor Technology Ltd
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Hangzhou Silergy Semiconductor Technology Ltd
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Abstract

In one embodiment, method of making a high voltage PMOS (HVPMOS) transistor, can include: (i) providing a P-type substrate; (ii) implanting N-type dopants in the P-type substrate; (iii) dispersing the implanted N-type dopants in the P-type substrate to form a deep N-type well; (iv) implanting P-type dopants of different doping concentrations in the deep N-type well along a horizontal direction of the deep N-type well; and (v) dispersing the implanted P-type dopants to form a composite drift region having an increasing doping concentration and an increasing junction depth along the horizontal direction of the deep N-type well.

Description

    RELATED APPLICATIONS
  • This application claims the benefit of Chinese Patent Application No. 201310194265.5, filed on May 22, 2013, which is incorporated herein by reference in its entirety.
    • FIELD OF THE INVENTION
  • The present invention relates to semiconductor devices, and more particularly to a high voltage PMOS (HVPMOS) transistor with a composite drift region formed by implantation, and an associated manufacturing method.
    • BACKGROUND
  • A switched-mode power supply (SMPS), or a “switching” power supply, can include a power stage circuit and a control circuit. When there is an input voltage, the control circuit can consider internal parameters and external load changes, and may regulate the on/off times of the switch system in the power stage circuit. In this way, the output voltage and/or the output current of the switching power supply can be maintained as substantially constant. Therefore, the selection and design of the particular control circuitry and approach, as well as the types of circuit components, can be important to the overall performance of the switching power supply. For example, HVPMOS transistors can be employed as switching devices in an SMPS.
    • SUMMARY
  • In one embodiment, a high voltage PMOS (HVPMOS) transistor can include: (i) a P-type substrate; (ii) a deep N-type well in the P-type substrate; and (iii) a composite drift region in the deep N-type well, where the composite drift region comprises an increasing doping concentration and an increasing junction depth along a horizontal direction of the deep N-type well.
  • In one embodiment, method of making an HVPMOS transistor, can include: (i) providing a P-type substrate; (ii) implanting N-type dopants in the P-type substrate; (iii) dispersing the implanted N-type dopants in the P-type substrate to form a deep N-type well; (iv) implanting P-type dopants of different doping concentrations in the deep N-type well along a horizontal direction of the deep N-type well; and (v) dispersing the implanted P-type dopants to form a composite drift region having an increasing doping concentration and an increasing junction depth along the horizontal direction of the deep N-type well.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a flow diagram of an example method of making an HVPMOS transistor using a BCD process.
  • FIG. 2 is a cross-section diagram of an example HVPMOS transistor formed by a BCD process.
  • FIG. 3 is a flow diagram of an example method of making an HVPMOS transistor with a composite drift region, in accordance with the embodiments of the present invention.
  • FIG. 4 is a flow diagram of an example method of making a composite drift region of an HVPMOS transistor, in accordance with embodiments of the present invention.
  • FIG. 5 is a flow diagram of an example method of making an HVPMOS transistor with a single oxide layer and a composite drift region, in accordance with embodiments of the present invention.
  • FIG. 6 is a cross-section diagram of an example HVPMOS transistor with a single oxide layer and a composite drift region based on the flow diagram of FIG. 5, and in accordance with embodiments of the present invention.
  • FIG. 7 is a flow diagram of another method of making an HVPMOS transistor with a single oxide layer and a composite drift region, in accordance with embodiments of the present invention.
  • FIG. 8 is a cross-section diagram of an example HVPMOS transistor with a single oxide layer and a composite drift region based on the flow diagram of FIG. 7, and in accordance with embodiments of the present invention.
  • FIG. 9 is a flow diagram of an example method of making an HVPMOS transistor with a composite oxide layer and a composite drift region, in accordance with the embodiments of the present invention.
  • FIG. 10 is a flow diagram of an example method of making an HVPMOS transistor with a composite oxide layer and a composite drift region, in accordance with the embodiments of the present invention.
  • FIG. 11 is a cross-section diagram of an example HVPMOS transistor with a composite oxide layer and a composite drift region based on the flow diagrams of FIGS. 9 and 10, and in accordance with embodiments of the present invention.
  • FIG. 12 is a flow diagram of an example method of making an HVPMOS transistor with a composite oxide layer and a composite drift region, in accordance with embodiments of the present invention.
  • FIG. 13 is a cross-section diagram of an example HVPMOS transistor with a composite oxide layer and a composite drift region based on the flow diagram of FIG. 12, and in accordance with embodiments of the present invention.
  • FIG. 14 is a flow diagram of an example method of making a single oxide layer and a drift region, in accordance with embodiments of the present invention.
    •  DETAILED DESCRIPTION
  • Reference may now be made in detail to particular embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention may be described in conjunction with the preferred embodiments, it may be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it may be readily apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, processes, components, structures, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention.
  • A high voltage PMOS transistor (HVPMOS) can be employed as a power device or switch in a switched-mode power supply (SMPS) or a “switching” power supply. In some cases, an HVPMOS transistor can be used in conjunction with a laterally diffused metal oxide semiconductor (LDMOS) transistor (e.g., an N-LDMOS) in a switching regulator. In one example, an HVPMOS transistor can be made by a standard BCD (Bipolar-CMOS-DMOS) process. There are typically four terminals for a HVPMOS: gate, body, source, and drain. When a voltage between the source and gate V(sg) is lower than a threshold voltage (Vth) of the HVPMOS transistor, the HVPMOS can be turned off to prevent a high voltage at the source from passing through the transistor. Conversely, when the voltage V(sg) between the source and gate is higher than threshold voltage Vth, the HVPMOS transistor can be turned on to conduct current between the source and drain. Thus, an HVPMOS transistor can be employed as a switch in many applications.
  • Breakdown voltage (BV) and on resistance (Ron) are important parameters for a HVPMOS transistor. Breakdown voltage BV can represent a maximum reverse voltage that can be accommodated by such power devices/transistors. Therefore, the higher the breakdown voltage, the better the power device (e.g., HVPMOS transistor) can perform, such as in a switching regulator application. Also, the lower the on resistance (Ron), the better the power device can decrease power losses across the power device. Referring now to FIG. 1, shown is a flow diagram of an example method of making an HVPMOS transistor using a BCD process. Also shown in FIG. 2 is a cross-section diagram of an example HVPMOS transistor formed by such a BCD process.
  • At S1, a P-type silicon substrate (PSUB) can be provided. At S2, N-type dopants can be implanted and dispersed to form a deep N-type well (DNWELL). For example, N-type impurities or dopants (e.g., phosphorus, etc.) can be implanted in the PSUB and dispersed to form a DNWELL as the channel of an HVPMOS transistor. At S3, P-type impurities or dopants (e.g., boron, etc.) can be implanted and dispersed to form a P-type well (Pwell). For example, P-type impurities can be implanted in the DNWELL, and then may be disbursed to form a Pwell as a “drift” region of the HVPMOS transistor.
  • At S4, an oxide layer can be grown. For example, the oxide can be grown over PSUB on a portion of DNWELL in which a Pwell has been formed. At S5, polysilicon can be deposited, e.g., on oxide to form a gate of the HVPMOS transistor. At S6, P+ dopants and N+ dopants to form the body, source, and drain regions and/or contact points, for the HVPMOS transistor. For example, on a portion of DNWELL that is not overlapped by oxide, P+ impurity can be implanted to form a source, and N+ impurity can be implanted to form a diffusion region for a body contact. Also, the drain can be formed by implanting P+ impurity on a portion of Pwell that is not overlapped by the oxide.
  • In some approaches, Pwell employed as the drift region can be formed by implanting and dispersing P-type impurity to make an HVPMOS transistor by a BCD process. However, with a BCD processing approach, it may be difficult to control the implantation dosage of the Pwell, and HVPMOS transistor performance limitations can result. For example, if the implantation dosage is too large, the breakdown voltage of the transistor may be decreased. Also, if the implantation dosage is too small, the on resistance of the HVPMOS transistor may be increased.
  • In one embodiment, method of making an HVPMOS transistor, can include: (i) providing a P-type substrate; (ii) implanting N-type dopants in the P-type substrate; (iii) dispersing the implanted N-type dopants in the P-type substrate to form a deep N-type well; (iv) implanting P-type dopants of different doping concentrations in the deep N-type well along a horizontal direction of the deep N-type well; and (v) dispersing the implanted P-type dopants to form a composite drift region having an increasing doping concentration and an increasing junction depth along the horizontal direction of the deep N-type well.
  • Referring now to FIG. 3, shown is a flow diagram of an example method of making an HVPMOS transistor with a composite drift region, in accordance with the embodiments of the present invention. This manufacturing method of an HVPMOS transistor with a composite drift region will be described in conjunction with the example transistor devices shown in FIGS. 6, 8, 11, and 13. At S11, a P-type substrate (PSUB) can be provided. At S12, N-type dopants (e.g., phosphorus, etc.) can be implanted in the P-type substrate, and then dispersed in the P-type substrate to form a deep N-type well (DNWELL), which can be configured as the channel of the HVPMOS transistor.
  • At S13, P-type dopants (e.g., boron, etc.) of different doping concentrations along a horizontal direction (e.g., left to right in FIG. 6) can be implanted in the deep N-type well (DNWELL), and then dispersed to form corresponding (adjacent) drift regions. For example, the doping concentrations and junction depths of the drift regions can be increased in sequence along the horizontal direction, with each drift region to the right having a higher doping concentration and junction depth than the drift region immediately to its left. In this fashion, a composite drift region of progressively increased doping concentration and junction depth can be configured along the horizontal direction of the deep N-type well (DNWELL). In particular embodiments, an HVPMOS transistor with a composite drift region can be formed, e.g., using S11 to S13, and which can include a P-type substrate, a deep N-type well in the P-type substrate, and a composite drift region with progressively increased doping concentration and junction depth in the deep N-type well along the horizontal direction.
  • Therefore, the composite drift region of the HVPMOS transistor does not utilize a conventional drift region that is formed by only once implanting single P-type dopants, such as in a BCD process. In certain embodiments, P-type dopants can be implanted several (e.g., at least two) times, and dispersed to form corresponding adjacent drift regions of the composite drift region. Also, the performance of the composite drift region can be regulated by adjustment of the doping concentration and/or junction depth of the drift region, such as at one or more of the drift region formation steps. Further, implantation dosage of the composite drift region can be more accurately controlled for an HVPMOS transistor in particular embodiments.
  • The composite drift region can be configured to be in the deep N-type well, and the surface of the deep N-type well that is adjacent to the P-type substrate may have better surface homogeneity, as compared to other approaches. Therefore, the intrinsic breakdown performance of an HVPMOS transistor of particular embodiments can be improved relative to the breakdown performance that can occur on a more conventional device surface. In addition, along the horizontal direction of the deep N-type well, the doping concentration of the drift region (e.g., at the far left) can be less, and the doping concentration of the remaining drift regions (e.g., in going from left to right in FIG. 6) can be progressively increased. Further, the doping concentration of the composite drift region can be still much higher than conventional approaches in order to decrease the on resistance of the HVPMOS transistor.
  • Referring now to FIG. 4, shown is a flow diagram of an example method of making a composite drift region of an HVPMOS transistor, in accordance with embodiments of the present invention. In this example, the example method of forming the composite drift region in step S13 can include the following steps. At S131, P-type dopants can be implanted in the deep N-type well, and may be disbursed at a first time to form a first drift region (Pwell1) with a lowest doping concentration and junction depth. For example, the first drift region (Pwell1) can be formed before formation of a single oxide layer. This can improve the conduction performance of the HVPMOS transistor, and the gate can be formed on the first drift region (Pwell1). This can improve the breakdown voltage due to the lowest doping concentration first drift region (Pwell1) preventing surface breakdown of the HVPMOS transistor when a higher voltage is supplied on the gate.
  • At S132, adjacent to the side wall of first drift region (Pwell1), P-type dopants of different doping concentrations can be implanted in the deep N-type well from left to right along a horizontal direction. This can be done in sequence at a corresponding second time through an nth time (e.g., second, third, fourth, . . . nth), and the P-type dopants can be dispersed to form a second drift region (Pwell2) through an nth drift region with progressively increasing doping concentrations and junction depths along the horizontal direction. For example, “n” can be an integer of at least two.
  • Although the doping concentration of first drift region Pwell1 is lower, the doping concentration of each of second drift region Pwell2 to the nth drift region can be progressively increased. This can also increase the doping concentration of the composite drift region to decrease the on resistance of the HVPMOS transistor in particular embodiments. In the examples discussed herein, n is two or three to facilitate the description. However, any suitable number of drift regions or value of “n” (of at least two) can be accommodated in particular embodiments, and thus may not limit the number of drift regions of the composite drift region. The particular number of drift regions can be adjusted for a given application to form a suitable composite drift region.
  • Referring now to FIG. 5, shown is a flow diagram of an example method of making an HVPMOS transistor with a single oxide layer and a composite drift region, in accordance with embodiments of the present invention. In this example, after formation of the composite drift region (including first and second drift regions), oxide material can be deposited on the composite drift region to form a single oxide layer, as shown in S14.
  • In one embodiment, an HVPMOS transistor can include: (i) a P-type substrate; (ii) a deep N-type well in the P-type substrate; and (iii) a composite drift region in the deep N-type well, where the composite drift region comprises an increasing doping concentration and an increasing junction depth along a horizontal direction of the deep N-type well. FIG. 6 shows a cross-section diagram of an example HVPMOS transistor with a single oxide layer and a composite drift region based on the flow diagram of FIG. 5, and in accordance with embodiments of the present invention.
  • Referring now to FIG. 7, shown is a flow diagram of another example method of making an HVPMOS transistor with a single oxide layer and a composite drift region, in accordance with embodiments of the present invention. After formation of the first drift region in S131, oxide material can be deposited to form a single oxide layer at S14. At S132, on a surface of a predetermined region of the composite drift region, the second drift region and third drift regions, etc., can be formed to form the composite drift region.
  • Referring now to FIG. 8, shown is a cross-section diagram of an example HVPMOS transistor with a single oxide layer and a composite drift region based on the flow diagram of FIG. 7, and in accordance with embodiments of the present invention. In this example, n=3, and three drift regions (e.g., Pwell1, Pwell2, and Pwell3) can form the composite drift region. Here, in step S14 of FIG. 7, the single oxide layer can be formed after the first drift region is formed. However, the sequence of steps of the single oxide layer and the second drift region through the nth drift regions can vary. In accordance with the steps from S11 to S14, the HVPMOS transistor can include a single oxide layer on the composite drift region, as shown in FIG. 8.
  • Furthermore, with reference to FIGS. 6 and 8, after S14, the example method of making an HVPMOS transistor with a composite drift region can also include depositing polysilicon substantially on the single oxide layer formed on the first drift region (Pwell1) of the composite drift region of a lowest doping concentration and junction depth, to form the gate of the HVPMOS transistor. Also, P+ dopants can be implanted to form the source, and N+ dopants can be implanted to form or allow for the body contact for the HVPMOS transistor, in a remaining region of the deep N-type outside of the composite drift region. Also, P+ dopants can be implanted in the nth drift region (e.g., Pwell3) of the highest doping concentration and junction depth that is adjacent to the single oxide layer to form the drain of the HVPMOS transistor.
  • In this way, an HVPMOS transistor of particular embodiments can include a gate on a single oxide layer that is on a composite drift region, as discussed herein. Also, the source and body diffusion regions for contacting can be formed in a remaining region of the deep N-type well outside or excluding the composite drift region. The drain can be formed in the drift region of highest doping concentration and junction depth of the composite drift region that is adjacent to the single oxide layer.
  • Referring now to FIG. 9, shown is a flow diagram of an example method of making an HVPMOS transistor with a composite oxide layer and a composite drift region, in accordance with the embodiments of the present invention. After formation of the composite drift region including the first and second drift regions, at S16, oxide material can be deposited on the composite drift region at least twice to form adjacent first oxide layer (Oxide1) and second oxide layer (Oxide2) from left to right in sequence (see, e.g., FIG. 11) to form a composite oxide layer. In this particular example, the first oxide layer (Oxide1) can be formed on the first drift region, and the second oxide layer (Oxide2) can be formed on the second drift region.
  • Referring now to FIG. 10, shown is a flow diagram of an example method of making an HVPMOS transistor with a composite oxide layer and a composite drift region, in accordance with the embodiments of the present invention. After formation of the first drift region, at S161, oxide material can be deposited on the first drift region to form the first oxide layer (Oxide1). In this example, at S132, the second drift region can be formed. At S162, oxide material can be deposited on the second drift region to form the second oxide layer (Oxide2).
  • Referring now to FIG. 11, shown is a cross-section diagram of an example HVPMOS transistor with a composite oxide layer and a composite drift region based on the flow diagrams of FIGS. 9 and 10, and in accordance with embodiments of the present invention. In this example, the first oxide layer and the second oxide layer are adjacent and arranged in sequence from left to right in a horizontal direction to form the composite oxide layer.
  • Referring now to FIG. 12, shown is a flow diagram of an example method of making an HVPMOS transistor with a composite oxide layer and a composite drift region, in accordance with embodiments of the present invention. In this example, after formation of the first drift region, oxide material can be deposited on predetermined regions of the composite drift region three times to form the first oxide layer (Oxide1), the second oxide layer (Oxide2), and the third oxide layer (Oxide3) adjacent in sequence from left to right to form the composite oxide layer. For example, the first oxide layer (Oxide1) can be on the first drift region, the second oxide layer (Oxide2) can be on the second drift region, and the third oxide layer (Oxide3) can be on the third drift region.
  • Referring now to FIG. 13, shown is a cross-section diagram of an example HVPMOS transistor with a composite oxide layer and a composite drift region based on the flow diagram of FIG. 12, and in accordance with embodiments of the present invention. Based on the implanting process of S132, the second and third drift regions can be formed together with the first drift region to form the composite drift region of Pwell1, Pwell2, and Pwell3.
  • Thus, an HVPMOS transistor in particular embodiments can also include a composite oxide layer on the composite drift region, which can include at least two adjacent oxide layers from left to right in sequence. Also, thickness of the oxide layers (e.g., Oxide1, Oxide2, Oxide3, etc.) in the composite oxide layer can be identical, or substantially the same, in some cases. In other cases, the thicknesses of the oxide layers (e.g., Oxide1, Oxide2, Oxide3, etc.) can be progressively increased from left to right along the horizontal direction of the deep N-type well, to coincide with the doping concentration and the junction depth of the drift regions. In particular embodiments, the composite oxide layer can be formed by multiple single oxide layers or oxide regions. The number of the single oxide “layers” can be adjusted in the manufacture of an HVPMOS transistor according for a given application.
  • Referring now to FIG. 14, shown is a flow diagram of an example method of making a single oxide layer and a drift region, in accordance with embodiments of the present invention. The composite oxide layer can include at least two single oxide layers or regions (e.g., Oxide1 and Oxide2), and the composite drift regions can include at least two drift regions. The formation of single oxide layers (Oxide1 and Oxide2) can be respectively labeled as A and B, and the formation of remaining drift regions other than the formation of first drift region (Pwell1) can be labeled as C. In particular embodiments, the sequence of steps A to C can be variable to change or optimize performance of breakdown voltage and/or on resistance of an HVPMOS transistor.
  • Furthermore, with reference to FIGS. 11 and 13, after S16, the example method of making an HVPMOS transistor with a composite drift region can also include depositing polysilicon substantially on the single oxide layer formed on the first drift region (Pwell1) of the composite drift region of a lowest doping concentration and junction depth to form the gate of the HVPMOS transistor. Also, P+ dopants can be implanted to form the source, and N+ dopants can be implanted to form or allow for the body contact for the HVPMOS transistor, in a remaining region of the deep N-type outside of the composite drift region. Also, P+ dopants can be implanted in the nth drift region of the highest doping concentration and junction depth that is adjacent to the single oxide layer to form the drain of the HVPMOS transistor.
  • When the thickness of the single oxide layers or regions (e.g., Oxide1, Oxide2, and Oxide3) is the same, the composite oxide layer of a homogeneous thickness between the gate and drain can be configured to accommodate the voltage drop between the gate and drain. However, the portion of the composite oxide layer or region adjacent to the gate can support a lower voltage drop, while the portion of the composite oxide layer adjacent to the drain can support a higher voltage drop. In particular embodiments, the thickness of the single oxide layers or regions (e.g., Oxide1, Oxide2, and Oxide3) can be progressively increased to form a composite oxide layer of progressively increased thickness between the gate and drain from left to right along the horizontal direction of the deep N-type well. This can be similar to the variation of the composite drift region of progressively increased doping concentrations and junction depths, to accommodate an increased voltage drop between the gate and drain.
  • The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilise the invention and various embodiments with modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.

Claims (15)

What is claimed is:
1. A high voltage PMOS (HVPMOS) transistor, comprising:
a) a P-type substrate;
b) a deep N-type well in said P-type substrate; and
c) a composite drift region in said deep N-type well, wherein said composite drift region comprises an increasing doping concentration and an increasing junction depth along a horizontal direction of said deep N-type well.
2. The HVPMOS transistor of claim 1, further comprising a single oxide layer on said composite drift region.
3. The HVPMOS transistor of claim 2, further comprising:
a) a gate on a portion of said single oxide layer that corresponds to a portion of said composite drift region having a lowest doping concentration and a lowest junction depth;
b) a source and a body in a portion of said deep N-type that is outside of said composite drift region; and
c) a drain in a portion of said composite drift region having a highest doping concentration and a highest junction depth, wherein said drain is adjacent to said single oxide layer.
4. The HVPMOS transistor of claim 1, further comprising a composite oxide layer on said composite drift region, wherein said composite oxide layer comprises at least two adjacent single oxide layers along said horizontal direction of said deep N-type well.
5. The HVPMOS transistor of claim 4, wherein said at least two adjacent single oxide layers comprises an increasing thickness along said horizontal direction of said deep N-type well.
6. The HVPMOS transistor of claim 5, further comprising:
a) a gate on a portion of said composite oxide layer that corresponds to a portion of said composite drift region having a lowest doping concentration and a lowest junction depth;
b) a source and a body in a portion of said deep N-type that is outside of said composite drift region; and
c) a drain in a portion of said composite drift region having a highest doping concentration and a highest junction depth, wherein said drain is adjacent to said composite oxide layer.
7. A method of making a high voltage PMOS (HVPMOS) transistor, the method comprising:
a) providing a P-type substrate;
b) implanting N-type dopants in said P-type substrate;
c) dispersing said implanted N-type dopants in said P-type substrate to form a deep N-type well;
d) implanting P-type dopants of different doping concentrations in said deep N-type well along a horizontal direction of said deep N-type well; and
e) dispersing said implanted P-type dopants to form a composite drift region having an increasing doping concentration and an increasing junction depth along said horizontal direction of said deep N-type well.
8. The method of claim 7, wherein said forming said composite drift region comprises:
a) implanting and dispersing, at a first time, P-type dopants in said deep N-type well to form a first drift region having a lowest doping concentration and a lowest junction depth; and
b) implanting and dispersing, beginning from a side wall of said first drift region and from at a second time to an nth time in sequence, P-type dopants of increasing doping concentrations along said horizontal direction in said deep N-type well, to form adjacent second to nth drift regions having progressively increasing doping concentrations and junction depths, wherein n is an integer of at least two.
9. The method of claim 8, further comprising depositing oxide material on said composite drift region to form a single oxide layer.
10. The method of claim 9, wherein:
a) forming said single oxide layer occurs after forming said first drift region; and
b) forming said single oxide layer occurs before or after forming said second drift region through said nth drift region.
11. The method of claim 9, further comprising:
a) forming a gate by depositing polysilicon on a portion of said single oxide layer that is on said first drift region;
b) forming a source and a body contact by implanting P+ dopants and N+ dopants separately in a portion of said deep N-type well outside of said composite drift region; and
c) forming a drain by implanting P+ dopants in a portion of said nth drift region adjacent to said single oxide layer.
12. The method of claim 8, further comprising forming a composite oxide layer by depositing oxide material on said composite drift region at least twice to form at least two adjacent single oxide layers along said horizontal direction.
13. The method of claim 12, wherein:
a) forming said composite oxide layer occurs after forming said first drift region; and
b) forming said composite oxide layer occurs before or after forming said second drift region through said nth drift region.
14. The method of claim 12, wherein said at least two adjacent single oxide layers comprises an increasing thickness along said horizontal direction of said deep N-type well.
15. The method of claim 12, further comprising:
a) forming a gate by depositing polysilicon on a portion of said composite oxide layer that is on said first drift region;
b) forming a source and a body contact by implanting P+ dopants and N+ dopants separately in a portion of said deep N-type well outside of said composite drift region; and
c) forming a drain by implanting P+ dopants in a portion of said nth drift region adjacent to said composite oxide layer.
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120286361A1 (en) * 2011-05-13 2012-11-15 Richtek Technology Corporation, R.O.C. High Voltage Device and Manufacturing Method Thereof
US20150194421A1 (en) * 2014-01-09 2015-07-09 Nxp B.V. Semiconductor die, integrated circuits and driver circuits, and methods of maufacturing the same
US20160172490A1 (en) * 2014-12-16 2016-06-16 Vanguard International Semiconductor Corporation High- voltage semiconductor device and method for manufacturing the same
US20160181400A1 (en) * 2014-01-21 2016-06-23 Wensheng QIAN LDMOS Device and Its Manufacturing Method
US11024722B1 (en) * 2020-01-15 2021-06-01 Nexchip Semiconductor Corporation Diffused field-effect transistor and method of fabricating same
US11152505B2 (en) * 2018-06-28 2021-10-19 Texas Instruments Incorporated Drain extended transistor
US20220130967A1 (en) * 2018-05-29 2022-04-28 Silergy Semiconductor Technology (Hangzhou) Ltd Ldmos transistor and method for manufacturing the same
CN114864667A (en) * 2022-07-11 2022-08-05 北京芯可鉴科技有限公司 NLDMOS device, preparation method of NLDMOS device and chip

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104638003B (en) * 2013-11-14 2019-04-09 上海华虹宏力半导体制造有限公司 Radio frequency LDMOS device and process
CN104979345B (en) * 2014-04-10 2017-12-19 北大方正集团有限公司 High-voltage CMOS integrated morphology and its manufacture method
CN112133758B (en) * 2020-11-25 2021-02-05 晶芯成(北京)科技有限公司 Power semiconductor device and method of manufacture
CN113690233B (en) * 2021-09-22 2024-03-08 江苏吉莱微电子股份有限公司 Unidirectional ESD protection device capable of enhancing current capacity and manufacturing method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020079509A1 (en) * 1998-12-04 2002-06-27 Taylor Efland Novel lateral double diffused metal oxide semiconductor device
US6897525B1 (en) * 1998-11-26 2005-05-24 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing the same
US7888222B2 (en) * 2003-11-13 2011-02-15 Volterra Semiconductor Corporation Method of fabricating a lateral double-diffused MOSFET
US20110156142A1 (en) * 2009-12-24 2011-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. High voltage device with partial silicon germanium epi source/drain
US20130234246A1 (en) * 2012-03-06 2013-09-12 Freescale Semiconductor, Inc. Semiconductor Device with Composite Drift Region

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3185656B2 (en) * 1996-03-22 2001-07-11 富士電機株式会社 Lateral field effect transistor and method of manufacturing the same
US6310378B1 (en) * 1997-12-24 2001-10-30 Philips Electronics North American Corporation High voltage thin film transistor with improved on-state characteristics and method for making same
US6023090A (en) * 1998-12-07 2000-02-08 Philips Electronics North America, Corporation Lateral thin-film Silicon-On-Insulator (SOI) device having multiple zones in the drift region
US6468878B1 (en) * 2001-02-27 2002-10-22 Koninklijke Philips Electronics N.V. SOI LDMOS structure with improved switching characteristics
US7719054B2 (en) * 2006-05-31 2010-05-18 Advanced Analogic Technologies, Inc. High-voltage lateral DMOS device
AU2003227926A1 (en) * 2003-05-13 2004-12-03 Cambridge Semiconductor Limited Lateral soi semiconductor device
DE102004009521B4 (en) 2004-02-27 2020-06-10 Austriamicrosystems Ag High-voltage PMOS transistor, mask for manufacturing a tub and method for manufacturing a high-voltage PMOS transistor
US7602037B2 (en) * 2007-03-28 2009-10-13 Taiwan Semiconductor Manufacturing Co., Ltd. High voltage semiconductor devices and methods for fabricating the same
US7964485B1 (en) * 2009-10-23 2011-06-21 National Semiconductor Corporation Method of forming a region of graded doping concentration in a semiconductor device and related apparatus
US8217452B2 (en) 2010-08-05 2012-07-10 Atmel Rousset S.A.S. Enhanced HVPMOS
CN102543738B (en) * 2010-12-20 2013-12-18 上海华虹Nec电子有限公司 High-voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacture method for same
US9209098B2 (en) 2011-05-19 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. HVMOS reliability evaluation using bulk resistances as indices
CN102437192B (en) * 2011-12-08 2014-04-16 东南大学 N-type silicon-on-insulator transverse double-diffusion field effect transistor
CN103456784B (en) * 2012-05-30 2017-02-15 上海华虹宏力半导体制造有限公司 High-voltage P-type LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6897525B1 (en) * 1998-11-26 2005-05-24 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing the same
US20020079509A1 (en) * 1998-12-04 2002-06-27 Taylor Efland Novel lateral double diffused metal oxide semiconductor device
US7888222B2 (en) * 2003-11-13 2011-02-15 Volterra Semiconductor Corporation Method of fabricating a lateral double-diffused MOSFET
US20110156142A1 (en) * 2009-12-24 2011-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. High voltage device with partial silicon germanium epi source/drain
US20130234246A1 (en) * 2012-03-06 2013-09-12 Freescale Semiconductor, Inc. Semiconductor Device with Composite Drift Region

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120286361A1 (en) * 2011-05-13 2012-11-15 Richtek Technology Corporation, R.O.C. High Voltage Device and Manufacturing Method Thereof
US9343538B2 (en) * 2011-05-13 2016-05-17 Richtek Technology Corporation High voltage device with additional isolation region under gate and manufacturing method thereof
US20150194421A1 (en) * 2014-01-09 2015-07-09 Nxp B.V. Semiconductor die, integrated circuits and driver circuits, and methods of maufacturing the same
US9570437B2 (en) * 2014-01-09 2017-02-14 Nxp B.V. Semiconductor die, integrated circuits and driver circuits, and methods of maufacturing the same
US20160181400A1 (en) * 2014-01-21 2016-06-23 Wensheng QIAN LDMOS Device and Its Manufacturing Method
US9997605B2 (en) * 2014-01-21 2018-06-12 Shanghai Huahong Grace Semiconductor Manufacturing Corporation LDMOS device and its manufacturing method
US20160172490A1 (en) * 2014-12-16 2016-06-16 Vanguard International Semiconductor Corporation High- voltage semiconductor device and method for manufacturing the same
US10629726B2 (en) * 2014-12-16 2020-04-21 Vanguard International Semiconductor Corporation High-voltage semiconductor device and method for manufacturing the same
US20220130967A1 (en) * 2018-05-29 2022-04-28 Silergy Semiconductor Technology (Hangzhou) Ltd Ldmos transistor and method for manufacturing the same
US11152505B2 (en) * 2018-06-28 2021-10-19 Texas Instruments Incorporated Drain extended transistor
US11024722B1 (en) * 2020-01-15 2021-06-01 Nexchip Semiconductor Corporation Diffused field-effect transistor and method of fabricating same
CN114864667A (en) * 2022-07-11 2022-08-05 北京芯可鉴科技有限公司 NLDMOS device, preparation method of NLDMOS device and chip

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