US20140287561A1 - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

Info

Publication number
US20140287561A1
US20140287561A1 US13/921,611 US201313921611A US2014287561A1 US 20140287561 A1 US20140287561 A1 US 20140287561A1 US 201313921611 A US201313921611 A US 201313921611A US 2014287561 A1 US2014287561 A1 US 2014287561A1
Authority
US
United States
Prior art keywords
semiconductor device
microwave
present
active layer
annealing process
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US13/921,611
Other versions
US9093427B2 (en
Inventor
Po-Tsun Liu
Li-Feng Teng
Yuan-Jou LO
Yao-Jen Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Yang Ming Chiao Tung University NYCU
Original Assignee
National Chiao Tung University NCTU
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Chiao Tung University NCTU filed Critical National Chiao Tung University NCTU
Assigned to NATIONAL CHIAO TUNG UNIVERSITY reassignment NATIONAL CHIAO TUNG UNIVERSITY ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LEE, YAO-JEN, LIU, PO-TSUN, LO, YUAN-JOU, TENG, LI-FENG
Publication of US20140287561A1 publication Critical patent/US20140287561A1/en
Application granted granted Critical
Publication of US9093427B2 publication Critical patent/US9093427B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/477—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02554—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous

Definitions

  • the present invention relates to a method for fabricating semiconductor device, and particularly to a method for fabricating semiconductor device by employing a microwave annealing process to increase the efficiency and electric reliability of semiconductor device.
  • the amorphous metal oxide semiconductor has the characteristics of high carrier mobility, low process temperature, high transmittance, excellent homogeneity and transparency, which is very suitable for applying in future relevant display and products and will become one of the mainstreams for the display of next generation.
  • the present invention provides a method for fabricating semiconductor device, which can be used to modify the defects in semiconductor device, and increase the efficiency of semiconductor device.
  • the abovementioned fabricating method comprises the following steps:
  • a gate is formed on a substrate.
  • a gate insulating layer is then formed on the gate, and further an active layer is disposed on the gate insulating layer, wherein the active layer is composed of a microwave absorbing material.
  • Source/drain is defined on the active layer to form the semiconductor device, and a microwave annealing process is finally performed thereon.
  • the microwave absorbing material comprises: the metal oxide, the metal nitride, and the metal oxide nitride.
  • the abovementioned active layer is: the amorphous material layer.
  • microwave frequency generated in the abovementioned microwave annealing process is between 2 GHz and 18 GHz.
  • microwave power generated in the abovementioned the microwave annealing process is less than 1500 W.
  • the treatment time for the abovementioned microwave annealing process is between 0 second and 600 seconds.
  • the temperature of the semiconductor device in the abovementioned microwave annealing process is less than 600° C.
  • FIG. 1 illustrates the flow chart of the method for fabricating semiconductor device according to an embodiment of the present invention
  • FIG. 2 illustrates the side view of the semiconductor device according to an embodiment of the present invention
  • FIG. 3A illustrates the relation between the drain current and the gate voltage of the semiconductor device fabricated at different microwave annealing condition
  • FIG. 3B illustrates the relation between the critical voltage drift and the stress time of the semiconductor device fabricated at different microwave annealing condition
  • FIG. 3C illustrates the comparison diagram for the electric performance between the semiconductor device provided by the first embodiment of the present invention and the prior device
  • FIG. 3D illustrates the comparison diagram for the electric reliability between the semiconductor device provided by the first embodiment of the present invention and the prior device
  • FIG. 3E illustrates the comparison diagram for the oxygen bonding energy between the semiconductor device provided by the first embodiment of the present invention and the prior device
  • FIG. 4A illustrates the relation between the drain current and the gate voltage of the semiconductor device provided by the second embodiment of the present invention and the prior device.
  • FIG. 4B illustrates the comparison diagram for the electric performance between the semiconductor device provided by the second embodiment of the present invention and the prior device.
  • FIG. 1 illustrates the flow chart of the method for fabricating semiconductor device according to an embodiment of the present invention.
  • FIG. 2 illustrates the side view of the semiconductor device according to an embodiment of the present invention. As shown in the
  • the present invention provides a method for fabricating semiconductor device, which comprises the following steps. Firstly, as shown in Step S 100 , a gate 20 is formed on a substrate 10 . As shown in Step S 102 , a gate insulating layer 30 is then formed on the gate 20 , and as shown in Step S 104 , an active layer 40 is further disposed on the gate insulating layer 30 . As shown in Step S 106 and Step S 108 , the source/drain 50 are defined on the active layer 40 to form the semiconductor device 100 , and a microwave annealing process is finally performed thereon.
  • the active layer 40 is composed of a microwave absorbing material.
  • the abovementioned microwave absorbing material may be a metal oxide, a metal nitride or a metal oxide-nitride.
  • the substrate used in the present invention is also hot limited, which may be the glass substrate or the plastic substrate.
  • Step S 100 100 nm of molybdenum (Mo) is deposited on the washed glass substrate 10 to form the gate 20 by the DV sputter.
  • Step S 102 150 nm silicon nitride is deposited on the gate 20 to form the gate insulating layer 30 by the plasma enhanced chemical vapor deposition (PECVD) conducted at 400° C.
  • PECVD plasma enhanced chemical vapor deposition
  • Step S 104 50 nm amorphous indium gallium zinc oxide (a-IGZO) is deposited on the gate insulating layer 30 to form the active layer 40 by the DV sputter.
  • the composition of indium gallium zinc oxide is 1:1:1:4 (In:Ga:Zn:O).
  • the power of sputtering system is 100 W, and the flow rate of argon is 100 sccm at room temperature. This is just a preferred the present invention, but the present invention does not limit to it.
  • Step S 106 100 nm indium tin oxide (ITO) is deposited on the active layer 40 by the RF sputter and etched by photomask process to form the source/drain, in order to achieve the semiconductor device 100 shown in FIG. 2 .
  • Step S 108 the semiconductor device 100 is treated by a microwave annealing process as follows:
  • Annealing treatment time 0 second ⁇ 600 second
  • Microwave power Less than 1500 W
  • Microwave frequency 2 GHz ⁇ 18 GHz
  • the semiconductor device can be roughly divided into four groups: 1P — 100 s (600 W of microwave power and 100 seconds of annealing treatment time), 1P — 300 s (600 W of microwave power and 300 seconds of annealing treatment time), 1P — 600 s (600 W of microwave power and 600 seconds of annealing treatment time) and 2P — 100 s (1200 W of microwave power and 100 seconds of annealing treatment time) for further evaluation of device characteristics.
  • Step S 100 100 nm tungsten molybdenum (MoW) is deposited on the substrate 10 to form the gate 20 by the DV sputter.
  • Step S 102 300 nm silicon dioxide is deposited on the gate 20 to form the gate insulating layer 30 by the plasma enhanced chemical vapor deposition (PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • Step S 104 50 nm amorphous nitrogen doped indium gallium zinc oxide (a-IGZO:N) is deposited on the gate insulating layer 30 to form the active layer 40 by the DV sputter.
  • Step S 106 100 nm indium tin oxide (ITO) is deposited on the active layer 40 by the RF sputter and etched by photomask process to form the source/drain, in order to achieve the semiconductor device 100 shown in FIG. 2 .
  • Step S 108 the semiconductor device 100 is treated by a microwave annealing process as follows:
  • FIG. 3A illustrates the relation between the drain current and the gate voltage of the semiconductor device fabricated at different microwave annealing condition.
  • FIG. 3B illustrates the relation between the critical voltage drift and the stress time of the semiconductor device fabricated at different microwave annealing condition.
  • FIG. 3C illustrates the comparison diagram for the electric performance between the semiconductor device provided by the first embodiment of the present invention and the prior device.
  • FIG. 3D illustrates the comparison diagram for the electric reliability between the semiconductor device provided by the first embodiment of the present invention and the prior device.
  • FIG. 3A illustrates the relation between the drain current and the gate voltage of the semiconductor device fabricated at different microwave annealing condition.
  • FIG. 3B illustrates the relation between the critical voltage drift and the stress time of the semiconductor device fabricated at different microwave annealing condition.
  • FIG. 3C illustrates the comparison diagram for the electric performance between the semiconductor device provided by the first embodiment of the present invention and the prior device.
  • FIG. 3D illustrates the comparison diagram for the electric reliability between the semiconductor device provided by the first
  • 3E illustrates the comparison diagram for the oxygen bonding energy between the semiconductor device provided by the first embodiment of the present invention and the prior device.
  • the abovementioned prior device is annealed by high-temperature furnace tube (450° C.) for an hour.
  • FIG. 3A illustrates the transfer characteristic curve, the electron mobility, and the critical voltage for the semiconductor device with the active layer of amorphous indium gallium zinc oxide (a-IGZO) at 11V of drain/ source voltage (V DS ) under different microwave annealing condition (such as 1P — 100 seconds, 1P — 300 seconds, 1P — 600 s, and 2P — 100 s).
  • a-IGZO amorphous indium gallium zinc oxide
  • V DS drain/ source voltage
  • the critical voltage of semiconductor device is decreased from 11.4V to 3.13V, and the electron mobility is increased from 4.86 cm 2 /Vs to 13.9 cm 2 /Vs. It means the electric performance of semiconductor device can be increased through the abovementioned microwave annealing treatment.
  • FIG. 3B When 2.5 MV/cm of electric field is applied to the gate and the source/drain are grounded, the influence of gate stress on the semiconductor device at different microwave annealing treatment condition is shown in FIG. 3B .
  • the critical voltage of semiconductor device after annealing treatment is decreased from 16.2V of 1P — 100 s to 1.6V of 2P — 100 s. It is known that after the abovementioned microwave annealing treatment, the electric reliability semiconductor device will also be increased. Similarly, the increase of microwave power and treatment time will also increase the microwave absorbing property of semiconductor device.
  • FIG. 3C , FIG. 3D and FIG. 3E continuously.
  • the abovementioned Figures illustrate the comparison diagram for the characteristics between the semiconductor device provided by the first embodiment of the present invention (treated by microwave annealing process as 2P — 100 s) and the prior device (treated by high-temperature furnace tube annealing process).
  • the electron mobility is higher than that of prior device, and the subcritical amplitude is smaller than that of prior device.
  • the defect density (N t ) of semiconductor device can be obtained by substituting the subcritical amplitude into the following equation:
  • the defect density of semiconductor device provided by the present invention and the prior device is 2.49 ⁇ 10 17 and 3.51 ⁇ 10 17 cm ⁇ 3 , respectively. It means that the defect density of semiconductor device provided by the first embodiment of present invention is lower than that of the prior device.
  • the semiconductor device treated by the microwave annealing process has higher oxygen bonding energy (see Peak A) and lower defect structure (see Peak B).
  • Peak A oxygen bonding energy
  • Peak B lower defect structure
  • FIG. 4A illustrates the relation between the drain current and the gate voltage of the semiconductor device provided by the second embodiment of the present invention.
  • FIG. 4B illustrates the comparison diagram for the electric performance between the semiconductor device provided by the second embodiment of the present invention and the conventional device.
  • the main difference between the first embodiment and the second embodiment is different material of the active layer.
  • the active layer is composed of the nitrogen doped indium gallium zinc oxide.
  • the curve (a) illustrates the semiconductor device treated by the microwave annealing process (600 W of microwave power and 300 seconds of treatment time) in the second embodiment of the present invention.
  • the curve (b) illustrates the semiconductor device treated by the high-temperature furnace tube annealing process (350° C. and 1 hr of treatment time).
  • the semiconductor device provided by the second embodiment of the present invention has lower critical voltage and subcritical amplitude, and has lower defect density compared to the prior device. It is known that the fabrication method provided by the present invention can also be used for the active layer composed of the microwave absorbing material, such as the metal nitride or the metal oxide-nitride.
  • the present invention provides a method for fabricating semiconductor device.
  • the purpose is to use the active layer with microwave absorbing characteristic and the follow-up microwave annealing process to modify the defect structure of device, and has the following features:
  • Step S 108 of the method for fabricating semiconductor device provided by the present invention the temperature of semiconductor device is not greater than 600° C., thus the whole process is a low heat budget process, which is able to reduce the consumption of heat;
  • the semiconductor device treated by the microwave annealing process has been better including basic electrical property, electron mobility, subcritical amplitude, and long-term operating reliability.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

A method for fabricating a semiconductor device is disclosed in the present invention. The abovementioned method comprises the following steps. Firstly, a gate is formed on a substrate. A gate insulating layer is then formed on the gate, and further an active layer is disposed on the gate insulating layer, wherein the active layer is composed of a microwave absorbing material. Source/drain is defined on the active layer to form the semiconductor device, and a microwave annealing process is finally performed thereon.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention The present invention relates to a method for fabricating semiconductor device, and particularly to a method for fabricating semiconductor device by employing a microwave annealing process to increase the efficiency and electric reliability of semiconductor device.
  • 2. Description of the Prior Art
  • Accompanying with the flourishing development of the Flat Panel Display (FPD) technology, the application of Thin Film Transistor (TFT) has been paid great attention. At present, the thin film device has been used to substitute the external integrated circuit set, in order to produce the System on Panel (SoP) for various displays and reach the goal of light, thin, low cost and high yield. Wherein, the amorphous metal oxide semiconductor has the characteristics of high carrier mobility, low process temperature, high transmittance, excellent homogeneity and transparency, which is very suitable for applying in future relevant display and products and will become one of the mainstreams for the display of next generation.
  • However, abovementioned technology and material have had many problems all the time, which face the bottleneck on the technological break-through. Firstly, based on the process of thin film transistor at present, there are often a lot of defects in the thin film transistor. The existence of these defects will cause low carrier mobility and low current. At the same time, they can cause high leakage current of device and reduce the reliability device.
  • Recently, there are many methods used to modify the defects, such as using the hydrogen or oxygen or ammonia plasma treatment, the high-temperature steam under the high-pressure treatment or the furnace tube annealing process etc. However, as for the abovementioned conventional furnace tube annealing process, the high-temperature, long-term process not only will cause the damage of device, but also will increase the burden of process.
  • Therefore, it is necessary to provide a method for fabricating semiconductor device, so as not only to modify the defects in semiconductor device, but also can increase the efficiency of semiconductor device.
    • SUMMARY OF THE INVENTION
  • The present invention provides a method for fabricating semiconductor device, which can be used to modify the defects in semiconductor device, and increase the efficiency of semiconductor device. The abovementioned fabricating method comprises the following steps:
  • Firstly, a gate is formed on a substrate. A gate insulating layer is then formed on the gate, and further an active layer is disposed on the gate insulating layer, wherein the active layer is composed of a microwave absorbing material. Source/drain is defined on the active layer to form the semiconductor device, and a microwave annealing process is finally performed thereon.
  • In an embodiment of the present invention, wherein the microwave absorbing material comprises: the metal oxide, the metal nitride, and the metal oxide nitride.
  • In an embodiment of the present invention, wherein the abovementioned active layer is: the amorphous material layer.
  • In an embodiment of the present invention, wherein the microwave frequency generated in the abovementioned microwave annealing process is between 2 GHz and 18 GHz.
  • In an embodiment of the present invention, wherein the microwave power generated in the abovementioned the microwave annealing process is less than 1500 W.
  • In an embodiment of the present invention, wherein the treatment time for the abovementioned microwave annealing process is between 0 second and 600 seconds.
  • In an embodiment of the present invention, wherein the temperature of the semiconductor device in the abovementioned microwave annealing process is less than 600° C.
  • Therefore, the advantage and spirit of the present invention can be understood further by the following detail description of invention and attached Figures.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
  • FIG. 1 illustrates the flow chart of the method for fabricating semiconductor device according to an embodiment of the present invention;
  • FIG. 2 illustrates the side view of the semiconductor device according to an embodiment of the present invention;
  • FIG. 3A illustrates the relation between the drain current and the gate voltage of the semiconductor device fabricated at different microwave annealing condition;
  • FIG. 3B illustrates the relation between the critical voltage drift and the stress time of the semiconductor device fabricated at different microwave annealing condition;
  • FIG. 3C illustrates the comparison diagram for the electric performance between the semiconductor device provided by the first embodiment of the present invention and the prior device;
  • FIG. 3D illustrates the comparison diagram for the electric reliability between the semiconductor device provided by the first embodiment of the present invention and the prior device;
  • FIG. 3E illustrates the comparison diagram for the oxygen bonding energy between the semiconductor device provided by the first embodiment of the present invention and the prior device;
  • FIG. 4A illustrates the relation between the drain current and the gate voltage of the semiconductor device provided by the second embodiment of the present invention and the prior device; and
  • FIG. 4B illustrates the comparison diagram for the electric performance between the semiconductor device provided by the second embodiment of the present invention and the prior device.
    •  DESCRIPTION OF THE PREFERRED EMBODIMENT
  • As the abovementioned description, please refer to FIG. 1 and FIG. 2. FIG. 1 illustrates the flow chart of the method for fabricating semiconductor device according to an embodiment of the present invention. FIG. 2 illustrates the side view of the semiconductor device according to an embodiment of the present invention. As shown in the
  • Figure, the present invention provides a method for fabricating semiconductor device, which comprises the following steps. Firstly, as shown in Step S 100, a gate 20 is formed on a substrate 10. As shown in Step S 102, a gate insulating layer 30 is then formed on the gate 20, and as shown in Step S104, an active layer 40 is further disposed on the gate insulating layer 30. As shown in Step S106 and Step S108, the source/drain 50 are defined on the active layer 40 to form the semiconductor device 100, and a microwave annealing process is finally performed thereon.
  • It has to describe that in the present invention, the active layer 40 is composed of a microwave absorbing material. No additional microwave absorbing unit or heating source is required for the semiconductor device provided by the present invention. Preferably, the abovementioned microwave absorbing material may be a metal oxide, a metal nitride or a metal oxide-nitride. In addition, the substrate used in the present invention is also hot limited, which may be the glass substrate or the plastic substrate.
  • The method for fabricating semiconductor device provided by the present invention will be described in detail by a first embodiment and a second embodiment as follows. Firstly, in the first embodiment of the present invention, as shown in Step S100, 100 nm of molybdenum (Mo) is deposited on the washed glass substrate 10 to form the gate 20 by the DV sputter. Then, as shown in Step S102, 150 nm silicon nitride is deposited on the gate 20 to form the gate insulating layer 30 by the plasma enhanced chemical vapor deposition (PECVD) conducted at 400° C.
  • Moreover, as shown in Step S104, 50 nm amorphous indium gallium zinc oxide (a-IGZO) is deposited on the gate insulating layer 30 to form the active layer 40 by the DV sputter. The composition of indium gallium zinc oxide is 1:1:1:4 (In:Ga:Zn:O). The power of sputtering system is 100 W, and the flow rate of argon is 100 sccm at room temperature. This is just a preferred the present invention, but the present invention does not limit to it.
  • As shown in Step S106, 100 nm indium tin oxide (ITO) is deposited on the active layer 40 by the RF sputter and etched by photomask process to form the source/drain, in order to achieve the semiconductor device 100 shown in FIG. 2. Finally, as shown in Step S108, the semiconductor device 100 is treated by a microwave annealing process as follows:
  • Annealing treatment time: 0 second˜600 second
  • Microwave power: Less than 1500 W
  • Microwave frequency: 2 GHz˜18 GHz
  • According to the process condition of Step S 108, the semiconductor device can be roughly divided into four groups: 1P—100 s (600 W of microwave power and 100 seconds of annealing treatment time), 1P —300 s (600 W of microwave power and 300 seconds of annealing treatment time), 1P —600 s (600 W of microwave power and 600 seconds of annealing treatment time) and 2P —100 s (1200 W of microwave power and 100 seconds of annealing treatment time) for further evaluation of device characteristics.
  • It has to note that though the indium gallium zinc oxide (i.e. metal oxide) is used for the active layer 40 in the first embodiment, the metal nitride or the metal oxide-nitride can also be used in the present invention. Thus, in the second embodiment of the present invention, as shown in Step S100, 100 nm tungsten molybdenum (MoW) is deposited on the substrate 10 to form the gate 20 by the DV sputter. Then, as shown in Step S102, 300 nm silicon dioxide is deposited on the gate 20 to form the gate insulating layer 30 by the plasma enhanced chemical vapor deposition (PECVD).
  • Then, as shown in Step S104, 50 nm amorphous nitrogen doped indium gallium zinc oxide (a-IGZO:N) is deposited on the gate insulating layer 30 to form the active layer 40 by the DV sputter. As shown in Step S106, 100 nm indium tin oxide (ITO) is deposited on the active layer 40 by the RF sputter and etched by photomask process to form the source/drain, in order to achieve the semiconductor device 100 shown in FIG. 2. Finally, as shown in Step S108, the semiconductor device 100 is treated by a microwave annealing process as follows:
  • Annealing treatment time: 300 seconds
  • Microwave power: 600 W
  • Microwave frequency: 5.8 GHz
  • Please refer to FIG. 3A , FIG. 3B, FIG. 3C, FIG. 3D and FIG. 3E for the characteristics of the semiconductor device fabricated by the method according to the first embodiment of the present invention. FIG. 3A illustrates the relation between the drain current and the gate voltage of the semiconductor device fabricated at different microwave annealing condition. FIG. 3B illustrates the relation between the critical voltage drift and the stress time of the semiconductor device fabricated at different microwave annealing condition. FIG. 3C illustrates the comparison diagram for the electric performance between the semiconductor device provided by the first embodiment of the present invention and the prior device. FIG. 3D illustrates the comparison diagram for the electric reliability between the semiconductor device provided by the first embodiment of the present invention and the prior device. FIG. 3E illustrates the comparison diagram for the oxygen bonding energy between the semiconductor device provided by the first embodiment of the present invention and the prior device. In addition, the abovementioned prior device is annealed by high-temperature furnace tube (450° C.) for an hour.
  • As shown in FIG. 3A, FIG. 3A illustrates the transfer characteristic curve, the electron mobility, and the critical voltage for the semiconductor device with the active layer of amorphous indium gallium zinc oxide (a-IGZO) at 11V of drain/ source voltage (VDS) under different microwave annealing condition (such as 1P —100 seconds, 1P—300 seconds, 1P —600 s, and 2P —100 s). As shown in Figure, when the microwave power is fixed at 100 W and the annealing treatment time is increased from 100 seconds to 600 seconds, the critical voltage of semiconductor device is decreased from 11.4V to 1.62V, but the electron mobility is increased. It is known that the increase of annealing treatment time will increase the electric performance of semiconductor device. Furthermore, when the microwave power is increased from 600 W to 1200 W and the annealing treatment time is maintained at 100 seconds, the critical voltage of semiconductor device is decreased from 11.4V to 3.13V, and the electron mobility is increased from 4.86 cm2/Vs to 13.9 cm2/Vs. It means the electric performance of semiconductor device can be increased through the abovementioned microwave annealing treatment.
  • When 2.5 MV/cm of electric field is applied to the gate and the source/drain are grounded, the influence of gate stress on the semiconductor device at different microwave annealing treatment condition is shown in FIG. 3B. The critical voltage of semiconductor device after annealing treatment is decreased from 16.2V of 1P —100 s to 1.6V of 2P —100 s. It is known that after the abovementioned microwave annealing treatment, the electric reliability semiconductor device will also be increased. Similarly, the increase of microwave power and treatment time will also increase the microwave absorbing property of semiconductor device.
  • Please refer to FIG. 3C, FIG. 3D and FIG. 3E continuously. The abovementioned Figures illustrate the comparison diagram for the characteristics between the semiconductor device provided by the first embodiment of the present invention (treated by microwave annealing process as 2P —100 s) and the prior device (treated by high-temperature furnace tube annealing process). Firstly, as shown in FIG. 3C, as for the semiconductor device with the microwave annealing treatment, the electron mobility is higher than that of prior device, and the subcritical amplitude is smaller than that of prior device. The defect density (Nt) of semiconductor device can be obtained by substituting the subcritical amplitude into the following equation:

  • S.S.=loge10×k B T/e[1+e(tN t +D it)/C i],
  • wherein KB is the Boltzmann constant, T is the temperature, Dit is the interface defect density, t is the thickness of active layer, and e is the charge. In addition, if tNt is the main item, then Dit can be neglected. At this time, the defect density of semiconductor device provided by the present invention and the prior device is 2.49×1017 and 3.51×1017 cm−3, respectively. It means that the defect density of semiconductor device provided by the first embodiment of present invention is lower than that of the prior device.
  • Finally, please refer to FIG. 3E. The semiconductor device treated by the microwave annealing process has higher oxygen bonding energy (see Peak A) and lower defect structure (see Peak B). Thus, the microwave energy can penetrate into the active layer of semiconductor device effectively, in order to modify and improve the defect structure in device, and increase the electric performance and reliability of semiconductor device.
  • Please refer to FIG. 4A and FIG. 4B. FIG. 4A illustrates the relation between the drain current and the gate voltage of the semiconductor device provided by the second embodiment of the present invention. FIG. 4B illustrates the comparison diagram for the electric performance between the semiconductor device provided by the second embodiment of the present invention and the conventional device. Basically, the main difference between the first embodiment and the second embodiment is different material of the active layer. In the second embodiment, the active layer is composed of the nitrogen doped indium gallium zinc oxide.
  • As shown in FIG. 4A and FIG. 4B, the curve (a) illustrates the semiconductor device treated by the microwave annealing process (600 W of microwave power and 300 seconds of treatment time) in the second embodiment of the present invention. The curve (b) illustrates the semiconductor device treated by the high-temperature furnace tube annealing process (350° C. and 1 hr of treatment time). The semiconductor device provided by the second embodiment of the present invention has lower critical voltage and subcritical amplitude, and has lower defect density compared to the prior device. It is known that the fabrication method provided by the present invention can also be used for the active layer composed of the microwave absorbing material, such as the metal nitride or the metal oxide-nitride.
  • In summary, the present invention provides a method for fabricating semiconductor device. The purpose is to use the active layer with microwave absorbing characteristic and the follow-up microwave annealing process to modify the defect structure of device, and has the following features:
  • 1. In the abovementioned Step S108 of the method for fabricating semiconductor device provided by the present invention, the temperature of semiconductor device is not greater than 600° C., thus the whole process is a low heat budget process, which is able to reduce the consumption of heat;
  • 2. Reduce the process time, and increase the production rate;
  • 3. It can focus on heating specific material or specific film layer (i.e. the abovementioned active layer), in order to reduce the influence of high temperature on other material layer;
  • 4. High even heat; and
  • 5. Compared to the prior device treated by furnace tube annealing process, the semiconductor device treated by the microwave annealing process has been better including basic electrical property, electron mobility, subcritical amplitude, and long-term operating reliability.
  • It is understood that various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope and spirit of this invention. Accordingly, it is not intended that the scope of the claims appended hereto be limited to the description as set forth herein, but rather that the claims be construed as encompassing all the features of patentable novelty that reside in the present invention, including all features that would be treated as equivalents thereof by those skilled in the art to which this invention pertains.

Claims (7)

What is claimed is:
1. A method for fabricating semiconductor device, for increasing the efficiency of semiconductor device, comprising:
forming a gate on a substrate;
forming a gate insulating layer on the gate;
forming an active layer on the gate insulating layer, and the active layer is composed of a microwave absorbing material;
defining a source/drain on the active layer to form the semiconductor device; and
performing a microwave annealing process.
2. The method according to claim 1, wherein the microwave absorbing material is selected from the group consisting of a metal oxide, a metal nitride and a metal oxide-nitride.
3. The method according to claim 2, wherein the active layer is an amorphous material layer.
4. The method according to claim 1, wherein the microwave frequency generated in the microwave annealing process is between 2 GHz and 18 GHz.
5. The method according to claim 1, wherein the microwave power generated in the microwave annealing process is less than 1500 W.
6. The method according to claim 1, wherein the treatment time of the microwave annealing process is between 0 second and 600 seconds.
7. The method according to claim 1, wherein the temperature of the semiconductor device in the microwave annealing process is less than 600° C.
US13/921,611 2013-03-21 2013-06-19 Method for fabricating semiconductor device Expired - Fee Related US9093427B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
TW102110004A TWI508191B (en) 2013-03-21 2013-03-21 Method for fabricating semiconductor device
TW102110004 2013-03-21
TW102110004A 2013-03-21

Publications (2)

Publication Number Publication Date
US20140287561A1 true US20140287561A1 (en) 2014-09-25
US9093427B2 US9093427B2 (en) 2015-07-28

Family

ID=51569435

Family Applications (1)

Application Number Title Priority Date Filing Date
US13/921,611 Expired - Fee Related US9093427B2 (en) 2013-03-21 2013-06-19 Method for fabricating semiconductor device

Country Status (2)

Country Link
US (1) US9093427B2 (en)
TW (1) TWI508191B (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150179448A1 (en) * 2013-12-20 2015-06-25 Lg Display Co., Ltd. Methods for Forming Crystalline IGZO Through Annealing
US9401274B2 (en) 2013-08-09 2016-07-26 Taiwan Semiconductor Manufacturing Company Limited Methods and systems for dopant activation using microwave radiation
DE102015106397A1 (en) * 2015-04-16 2016-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and systems for dopant activation using microwave irradiation
US10340391B2 (en) 2017-06-29 2019-07-02 United Microelectronics Corp. Semiconductor device and method for fabricating the same
CN112164656A (en) * 2020-09-24 2021-01-01 山东华芯半导体有限公司 Method for improving performance of flash memory unit by using ITO as source and drain

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110014745A1 (en) * 2009-07-17 2011-01-20 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW404070B (en) * 1999-02-02 2000-09-01 Nat Science Council Poly-silicon thin film transistor process
US7494841B2 (en) * 2006-05-12 2009-02-24 International Business Machines Corporation Solution-based deposition process for metal chalcogenides
TW200845220A (en) * 2007-05-04 2008-11-16 Univ Nat Chiao Tung Microwave annealing for enhancing the efficiency of polymer photovoltaic device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110014745A1 (en) * 2009-07-17 2011-01-20 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9401274B2 (en) 2013-08-09 2016-07-26 Taiwan Semiconductor Manufacturing Company Limited Methods and systems for dopant activation using microwave radiation
US9627212B2 (en) 2013-08-09 2017-04-18 Taiwan Semiconductor Manufacturing Company Limited Methods and systems for dopant activation using microwave radiation
US10522356B2 (en) 2013-08-09 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and systems for dopant activation using microwave radiation
US20150179448A1 (en) * 2013-12-20 2015-06-25 Lg Display Co., Ltd. Methods for Forming Crystalline IGZO Through Annealing
US9202690B2 (en) * 2013-12-20 2015-12-01 Intermolecular, Inc. Methods for forming crystalline IGZO through annealing
DE102015106397A1 (en) * 2015-04-16 2016-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and systems for dopant activation using microwave irradiation
DE102015106397B4 (en) * 2015-04-16 2019-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and systems for dopant activation using microwave irradiation
US10340391B2 (en) 2017-06-29 2019-07-02 United Microelectronics Corp. Semiconductor device and method for fabricating the same
US11133418B2 (en) 2017-06-29 2021-09-28 United Microelectronics Corp. Semiconductor device and method for fabricating the same
US11476367B2 (en) 2017-06-29 2022-10-18 United Microelectronics Corp. Semiconductor device
CN112164656A (en) * 2020-09-24 2021-01-01 山东华芯半导体有限公司 Method for improving performance of flash memory unit by using ITO as source and drain

Also Published As

Publication number Publication date
US9093427B2 (en) 2015-07-28
TW201438109A (en) 2014-10-01
TWI508191B (en) 2015-11-11

Similar Documents

Publication Publication Date Title
US9093427B2 (en) Method for fabricating semiconductor device
Cai et al. High-performance transparent AZO TFTs fabricated on glass substrate
CN105390451A (en) Manufacture method of low-temperature polysilicon TFT substrate
CN107507866B (en) Polycrystalline oxide flexible thin film transistor and preparation method thereof
Kandpal et al. Perspective of zinc oxide based thin film transistors: a comprehensive review
CN103985638A (en) Low temperature polycrystalline silicon thin film transistor, preparation method thereof, and display device
CN104599959A (en) Manufacturing method and structure of low-temperature polycrystalline silicon TFT substrate
CN104600028A (en) Manufacturing method and structure of low-temperature polycrystalline silicon TFT substrate
CN103346089A (en) Self-aligned double-layer channel metallic oxide thin film transistor and manufacturing method thereof
Lu et al. Two‐step plasma treatment designed for high‐performance flexible amorphous ZnAlSnO thin‐film transistors replacing thermal annealing
US20210082965A1 (en) Method for Manufacturing Thin Film Transistor, Thin Film Transistor, and Display Apparatus
US6548332B2 (en) Thermal treatment process for forming thin film transistors without the use of plasma treatment to further improve the output property of the thin film transistor
US8975164B2 (en) Method of manufacturing semiconductor device
US20180204858A1 (en) Display substrate having an organic layer and fabricating method thereof
CN107104151A (en) A kind of double grid electrode metal oxide thin-film transistor and preparation method thereof
US20170084643A1 (en) Storage Capacitors for Displays and Methods for Forming the Same
CN104157610A (en) Manufacture method of oxide semiconductor TFT substrate, and structure of the oxide semiconductor TFT substrate
CN103400765A (en) Manufacturing method of oxide thin-film transistor
US10217871B2 (en) Method of controlling electric conductivity of metal oxide thin film and thin film transistor including the metal oxide film having the controlled electric conductivity
CN110112102B (en) Array substrate and preparation method thereof
CN104716092A (en) Manufacturing method of array substrate and manufacturing device
US9923085B2 (en) Method for manufacturing a thin film transistor and an array substrate, and corresponding devices
CN102637742A (en) Oxide semiconductor thin-film transistor and preparation method thereof
CN107482063A (en) Low-temperature polysilicon film transistor and its manufacture method
CN106206745B (en) Manufacturing method of high-mobility metal oxide TFT

Legal Events

Date Code Title Description
AS Assignment

Owner name: NATIONAL CHIAO TUNG UNIVERSITY, TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIU, PO-TSUN;TENG, LI-FENG;LO, YUAN-JOU;AND OTHERS;REEL/FRAME:030658/0783

Effective date: 20130514

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YR, SMALL ENTITY (ORIGINAL EVENT CODE: M2551); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY

Year of fee payment: 4

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20230728