US20140258799A1 - Ip core design supporting user-added scan register option - Google Patents
Ip core design supporting user-added scan register option Download PDFInfo
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- US20140258799A1 US20140258799A1 US14/281,189 US201414281189A US2014258799A1 US 20140258799 A1 US20140258799 A1 US 20140258799A1 US 201414281189 A US201414281189 A US 201414281189A US 2014258799 A1 US2014258799 A1 US 2014258799A1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3177—Testing of logic operation, e.g. by logic analysers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318541—Scan latches or cell details
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318555—Control logic
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318583—Design for test
- G01R31/318586—Design for test with partial scan or non-scannable parts
Definitions
- the disclosure permits reuse of the IP core's TAP to access a user-added boundary scan register.
- FIG. 4 illustrates in greater detail the TAP control signals of FIGS. 3 and 3A .
- the conventional TAP 11 inhibits the operation of the IP core, connects the boundary scan register to the IC's TDI and TDO pins, and controls the boundary scan register to perform interconnect testing.
- the conventional TAP 11 adapts the IP core for testing, connects the boundary scan register to the IC's TDI and TDO pins, and controls the boundary scan register to perform testing on the IP core.
- the conventional TAP 11 inhibits the operation of the IP core, connects the internal Bypass register to the IC's TDI and TDO pins, and controls the boundary scan register to a predetermined static input/output condition.
- the conventional TAP 11 adapts the IP core for BIST testing, connects to the IC's TDI and TDO pins a specified internal test data register that will be used to access the pass/fail status of the BIST operation, and controls the boundary scan register to a predetermined static input/output condition.
- the conventional TAP 11 enables the operation of the IP core, connects the internal IDcode register (an 1149.1 specified 32-bit register for outputting vendor identification and other information) to the IC's TDI and TDO pins, and controls the boundary scan register to be transparent.
- the internal IDcode register an 1149.1 specified 32-bit register for outputting vendor identification and other information
- the conventional TAP 11 enables the operation of the IP core, connects the internal Usercode register (an 1149.1 specified register for outputting additional vendor information) to the IC's TDI and TDO pins, and controls the boundary scan register to be transparent.
- the ERP signal is captured and shifted out of the CSU register, along with other status inputs.
- the ERP input to the instruction CSU register allows a user of the IC (e.g. a system designer) to determine the presence or absence of a user-added boundary scan register.
- the decode section responds conventionally to 1149.1 instructions that access and/or control the boundary scan register.
- the decode section will preferably cause all 1149.1 instructions that normally access and/or control the boundary scan register to default to being Bypass instructions. This would mean that Extest, Intest, Sample/Preload, HighZ, and Clamp instructions all default to the Bypass instruction when ERP is low. Defaulting to the Bypass instruction is preferred because that is the default instruction that 1149.1 conventionally uses for unknown/undefined instructions scanned into the instruction register.
- the user-added scan register(s) at 60 are located in the IC physically outside of the core's boundary, that is, external relative to the core.
- the general purpose scan register 60 can be any scan register that does not perform boundary scan functions relative to the core boundary of FIG. 6 .
- scan register 60 could even have the same structure as boundary scan register 25 , but would not function as a boundary scan register relative to the core boundary.
- the core design can provide for addition of as many user-added scan registers as desired. In the arrangement of FIG. 6 , the IP core user can easily control and access a user-added scan register other than a user-added boundary scan register.
- FIG. 6A relates to FIG. 6 as FIG. 3A relates to FIG. 3 , showing only the FIG. 6 IP core as it would be provided by the IP core vendor.
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- Microelectronics & Electronic Packaging (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP lead 37. A scan register 25 encompasses the intellectual property core and ERP lead 37 carries a signal indicating the presence of the scan register.
Description
- This application is a divisional of application Ser. No. 13/969,079, filed Aug. 16, 2013, now U.S. Pat. No. 8,745,456, granted Jun. 3, 2014;
- Which was a divisional of application Ser. No. 13/765,251, filed Feb. 12, 2013, now U.S. Pat. No. 8,539,295, granted Sep. 17, 2013;
- Which was a divisional of application Ser. No. 13/486,138, filed Jun. 1, 2012, now U.S. Pat. No. 8,402,331, granted Mar. 19, 2013;
- Which was a divisional of application Ser. No. 13/238,564, filed Sep. 21, 2011, now U.S. Pat. No. 8,214,705, granted Jul. 3, 2012;
- Which was a divisional of application Ser. No. 12/889,091, filed Sep. 23, 2010, now U.S. Pat. No. 8,046,649, granted Oct. 25, 2011;
- Which was a divisional of application Ser. No. 12/575,893, filed Oct. 8, 2009, now U.S. Pat. No. 7,827,453, granted Nov. 2, 2010;
- Which was a divisional of application Ser. No. 12/203,475, filed Sep. 3, 2008, now U.S. Pat. No. 7,620,867, granted Nov. 17, 2009;
- Which was a divisional of application Ser. No. 11/380,965, filed May 1, 2006, now U.S. Pat. No. 7,441,170, granted Oct. 21, 2008;
- Which was a divisional of application Ser. No. 10/705,648, filed Nov. 10, 2003, now U.S. Pat. No. 7,065,692, granted Jun. 20, 2006;
- Which was a divisional of application Ser. No. 09/812,220, filed Mar. 19, 2001, now U.S. Pat. No. 6,658,615, granted Dec. 2, 2003;
- Which was a divisional of application Ser. No. 09/107,105, filed Jun. 30, 1998, now U.S. Pat. No. 6,223,315, granted Apr. 24, 2001;
- Which claims priority from Provisional Application No. 60/051,377, filed Jun. 30, 1997.
- The disclosure relates generally to testing of integrated circuits having embedded cores and, more particularly, to a core design that efficiently supports a user-added scan register option.
- Rapid design and deployment of high complexity integrated circuits (IC) can be achieved by reuse of preexisting intellectual property (IP) cores, such as digital signal processors, microcontrollers, processors, I/O peripherals, and memory. Such IP cores are discussed in “Blocking in a System on a Chip”, by Hunt and Rowson, published in the November 1996 edition of IEEE Spectrum and incorporated herein by reference. Marketing of IP cores, as a way to expedite the fabrication of highly complex system chips, changes the way the cores are designed for testability. Typically, most IP cores were first designed as stand alone ICs to be used on a circuit board. With today's advanced IC fabrication technology, it is possible to migrate what was once a circuit board of plural ICs into a single IC comprising plural cores embedded therein. Thus a transition from IC to embedded IP core is a technology trend.
- Many of the same testing problems currently seen in circuit boards designed with multiple ICs will be seen in ICs designed with multiple cores.
- The use of IC resident testability standard, IEEE Std 1149.1, incorporated herein by reference, has proven to be effective in resolving most test problems related to testing ICs and the interconnections between ICs at the circuit board level. This standard should be effective in resolving problems related to testing cores and the interconnections between cores at the IC level as well.
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FIG. 1 illustrates the architecture of IEEE Std. 1149.1 implemented in a conventional IC. The architecture includes (1) a test access port (TAP) 11 which further comprises a TAP controller and an instruction register, (2) a plurality of test data registers (boundary scan register and others), and (3) an 1149.1 test port interface which provides external I/O to the architecture via the TAP controller. These elements and their operation and function are well known and described in IEEE Std. 1149.1. The boundary scan register includes a scan cell at each input, output, control, and input/output pin of the IC. - In normal mode, the IC operates normally to internally process and externally communicate signals to other ICs via the transparent boundary scan register. In a first test mode, the functional circuitry of the IC is disabled and the boundary scan register is accessed and controlled, via TAP signal lines at 13, 15 and 17, to communicate external test signals between ICs to verify their interconnectivity. This external interconnect test mode is invoked by scanning an 1149.1 Extest instruction into the instruction register of the
TAP 11. In another test mode, the IC's functional circuitry may be functionally disabled but configured to be testable via scan access (from the TAP) to one or more of the test data registers. Instructions scanned into the instruction register of the TAP are used to connect the TAP up to a selected test data register(s), i.e. the boundary scan register and/or internal test data registers, so that serial test data can be input and output to the register to effectuate a given test or other type of operation. For example; when the Extest instruction is loaded into the instruction register, the TAP selects and connects up to the boundary scan register via itsserial input 15,serial output 13, andcontrol signals 17. Once connected, the TAP responds to the external test port signal pins of the IC to output control to the boundary scan register to communicate test data to the boundary scan register to execute interconnect testing. Similarly, other instructions can be loaded that allow the TAP to select and connect up to other test data registers so that other types of operations such as; internal scan testing, built in self test triggering (1149.1 Runbist instruction), or IC serial bypassing (1149.1 Bypass instruction), can be performed. - While the complete 1149.1 architecture of
FIG. 1 is almost always implemented in ICs to provide the external and internal testing mentioned above, it may not be completely implemented in an IP core version of an IC. More specifically, the boundary scan register portion of the architecture may not be implemented in IP cores because competition between IP core venders is largely based on IP core performance, and the boundary scan register inherently adds a disadvantageous delay (through a switch or multiplexer) to each input, output, and control (e.g. three-state control) signal associated with the IP core's boundary. A boundary scan register that is provided as part of an IP core will herein be termed a core-provided boundary scan register. An IP core having its own core-provided boundary scan register has the same general structure as the IC ofFIG. 1 . - If an IP core provider does not implement the boundary scan register due to performance considerations, and if the core itself cannot be modified by the user (i.e. a hard core), then the IP core user will have to add a TAP and boundary scan register around the IP core if the user wishes to achieve interconnect testing via boundary scan. Surrounding an IP core with a TAP and boundary scan register for the purpose of isolating the IP core and performing interconnect testing between the IP core and other IP cores is a known prior art technique and is illustrated in
FIG. 2 . - Within the broken-line box of
FIG. 2 is an IP core with appropriate 1149.1 architecture, but without the boundary scan register and associatedsignal lines FIG. 1 . A user-addedboundary scan register 25 andTAP 23 are shown outside the broken-line box. Theboundary scan register 25 is unshaded to distinguish it from the core-provided boundary scan register ofFIG. 1 . TheTAP 23 is provided by the user to access and control the user-providedboundary scan register 25 and is separate from theTAP 21 of the IP core. TheTAP 21 differs fromTAP 11 andTAP 23 becauseTAP 21 does not support conventional 1149.1 boundary scan instructions, namely Extest and Sample/Preload. The approach shown inFIG. 2 disadvantageously requires addingTAP 23 to provide access to and control of the user-added boundary scan register. Also, the user must be able to select either theTAP 21 for internal testing/emulation of the IP core, or theTAP 23 for interconnect testing (via the boundary scan register) between the IP core and other IP cores or circuits residing in the IC. - It is therefore desirable to permit the user to add boundary scan to an IP core without the overhead associated with adding a separate TAP to control boundary scan.
- The disclosure permits reuse of the IP core's TAP to access a user-added boundary scan register.
-
FIG. 1 illustrates a conventional integrated circuit with 1149.1 boundary scan capability, or alternatively, a conventional IP core with core-provided 1149.1 boundary scan capability. -
FIG. 2 illustrates the conventional configuration of an IP core with user-added boundary scan. -
FIG. 3 illustrates an IP core with user-added boundary scan according to the present disclosure. -
FIG. 3A illustrates an IP core arranged to support a user-added boundary scan register according to the present disclosure. -
FIG. 4 illustrates in greater detail the TAP control signals ofFIGS. 3 and 3A . -
FIG. 5 illustrates the structure of the instruction register in the TAP ofFIGS. 3 , 3A and 4. -
FIG. 6 is similar toFIG. 3 and illustrates another user-added scan register according to the disclosure. -
FIG. 6A is similar toFIG. 3A and illustrates an IP core arranged to support the user-added scan registers ofFIG. 6 . - Example
FIG. 3 illustrates, within the broken-line box, an IP core without a boundary scan register but having the necessary access and control lines for connection to a user-added scan register. In exampleFIG. 3 , it is seen that theTAP 39 of the IP core providessignal lines scan register 25. In this example, the user-added scan register is a boundary scan register (shown unshaded to distinguish from the core-provided boundary scan register ofFIG. 1 ). TheTAP 39 also includes an external register present (ERP)input 37 for indicating to the TAP whether or not a user-added scan register has been implemented. - Example
FIG. 4 shows in more detail theIP core TAP 39 ofFIG. 3 , which includes the conventional 1149.1 test port signals of TAP 21 (seeFIG. 2 ), namely test data input (TDI), test clock (TCK), test mode select (TMS), test reset (TRST), and test data output (TDO), along with theadditional signal lines TAP 39 to access and control the user-implemented boundary scan register. Control output from the instruction register ofTAP 39 is shown at 41.FIG. 4 shows that the aforementioned conventional 1149.1 test port signals are accessible at the external terminals of the IC. - In addition to providing the additional external signals mentioned above, the IP core provider must design the instruction register of the
TAP 39 to include all required 1149.1 instructions that are used by TAP 11 (seeFIG. 1 ) to access and control a core-provided boundary scan register. The required 1149.1 boundary scan instructions are the Extest and Sample/Preload instructions. Also, the IP core provider must design the instruction register of theTAP 39 to control the user-addedboundary scan register 25 exactly like a core-provided boundary scan register would be controlled byTAP 11 under the influence of other required instructions (e.g. conventional Bypass instruction), optional instructions (e.g. conventional Intest, HighZ, Clamp, Runbist, IDcode, and Usercode instructions), or proprietary IP core vendor-specific instructions. - During a conventional Extest instruction, the conventional TAP 11 (see
FIG. 1 ) inhibits the operation of the IP core, connects the boundary scan register to the IC's TDI and TDO pins, and controls the boundary scan register to perform interconnect testing. - During a conventional Sample/Preload instruction, the
conventional TAP 11 enables the operation of the IP core, connects the boundary scan register to the IC's TDI and TDO pins, and controls the boundary scan register to be transparent, while functional signals flowing through the boundary scan register are captured and shifted out for inspection. - During a conventional Bypass instruction, the
conventional TAP 11 enables the operation of the IP core, connects the internal Bypass register (an 1149.1 defined single bit test data register) to the IC's TDI and TDO pins, and controls the boundary scan register to be transparent. - During a conventional Intest instruction, the
conventional TAP 11 adapts the IP core for testing, connects the boundary scan register to the IC's TDI and TDO pins, and controls the boundary scan register to perform testing on the IP core. - During a conventional HighZ instruction, the
conventional TAP 11 inhibits the operation of the IP core, connects the internal Bypass register to the IC's TDI and TDO pins, and controls the boundary scan register outputs to the high impedance state. - During a conventional Clamp instruction, the
conventional TAP 11 inhibits the operation of the IP core, connects the internal Bypass register to the IC's TDI and TDO pins, and controls the boundary scan register to a predetermined static input/output condition. - During a conventional Runbist instruction, the
conventional TAP 11 adapts the IP core for BIST testing, connects to the IC's TDI and TDO pins a specified internal test data register that will be used to access the pass/fail status of the BIST operation, and controls the boundary scan register to a predetermined static input/output condition. - During a conventional IDcode instruction, the
conventional TAP 11 enables the operation of the IP core, connects the internal IDcode register (an 1149.1 specified 32-bit register for outputting vendor identification and other information) to the IC's TDI and TDO pins, and controls the boundary scan register to be transparent. - During a conventional Usercode instruction, the
conventional TAP 11 enables the operation of the IP core, connects the internal Usercode register (an 1149.1 specified register for outputting additional vendor information) to the IC's TDI and TDO pins, and controls the boundary scan register to be transparent. - With an IP core that provides the signals and instructions as described above, a user of the IP core need only design a boundary scan register around the IP core and connect the core-provided
signal lines - In example
FIG. 5 it is seen that the 1149.1 instruction register within the IP core TAP comprises a capture-shift-update (CSU) register section and a decode section. During conventional 1149.1 instruction scans, the CSU register section captures status information present on its parallel inputs and then shifts data from TDI to TDO. During the shift operation, the captured status information is shifted out as a new instruction is shifted in. At the end of the 1149.1 instruction scan, the new instruction shifted into the CSU register is updated and input to the decode section. The decode section decodes the new instruction and outputs control to cause the new instruction to take effect. The instruction can be, for example, any of the types previously mentioned. - When a user decides to connect a boundary scan register to an IP core TAP having the
external signal connections FIGS. 3 and 4 , the user sets the external register present (ERP) signal to a logic state indicative of the presence of the user-added boundary scan register. In this example, a high on ERP indicates the presence of a user-added ‘boundary scan register, and a low on ERP indicates the absence of a user-added boundary scan register. As seen inFIG. 5 , the ERP signal is input to both the instruction CSU register and decode sections. The ERP is a status input (i.e. a capture input) to the CSU register section. The ERP is an additional decode input to the decode section. - During instruction scan operations, the ERP signal is captured and shifted out of the CSU register, along with other status inputs. By examining the ERP signal scanned from the CSU register, it is possible to determine whether or not the user added a boundary scan register to the IP core (for example ERP high=added, ERP low=not added). So the ERP input to the instruction CSU register allows a user of the IC (e.g. a system designer) to determine the presence or absence of a user-added boundary scan register.
- If the ERP is set high, indicating the presence of a user-added boundary scan register, the decode section responds conventionally to 1149.1 instructions that access and/or control the boundary scan register. On the other hand, if the ERP is set low, indicating the absence of a user-added boundary scan register, the decode section will preferably cause all 1149.1 instructions that normally access and/or control the boundary scan register to default to being Bypass instructions. This would mean that Extest, Intest, Sample/Preload, HighZ, and Clamp instructions all default to the Bypass instruction when ERP is low. Defaulting to the Bypass instruction is preferred because that is the default instruction that 1149.1 conventionally uses for unknown/undefined instructions scanned into the instruction register.
-
FIG. 3A shows only the IP core within the broken-line box ofFIG. 3 , as it would be provided by the IP core vendor, that is, with core-providedsignal lines ERP line 37 arranged to be available for convenient connection to an appropriate logic level. If the core user does not add a boundary scan register, then lines 13, 15 and 17 will remain unconnected when the core is embedded in an IC. - Example
FIG. 6 is similar toFIG. 3 , but includes a further user-added scan register. In exampleFIG. 6 , a user-added generalpurpose scan register 60 is shown interfaced to the IP core, in addition to the previously described user-addedboundary scan register 25. In such instances, an additional signal indicates toTAP 39A the presence or absence of the additional scan register, and the control lines at 17A provide control fromTAP 39A to thescan register 60 as well as to register 25. Thescan input 15 andscan output 13 are used to access either the boundary scan or general purpose scan register. InFIG. 6 , ERP is used, as previously described, to indicate the presence or absence of the boundary scan register, and to enable access of the boundary scan register if it is present, or default to the bypass instruction if it is not present. Likewise, the ERP1 signal is used to enable access of the general purpose scan register if it is present, or to default to the bypass instruction if it is not present and access of it is attempted. The ERP and ERP1 signals are designated generally at 37A inFIG. 6 . Scan access to plural user-added scan registers operates the same as conventional 1149.1 scan access to plural core-provided scan registers. - The user-added scan register(s) at 60 are located in the IC physically outside of the core's boundary, that is, external relative to the core. The general
purpose scan register 60 can be any scan register that does not perform boundary scan functions relative to the core boundary ofFIG. 6 . Thus, scanregister 60 could even have the same structure asboundary scan register 25, but would not function as a boundary scan register relative to the core boundary. Also, the core design can provide for addition of as many user-added scan registers as desired. In the arrangement ofFIG. 6 , the IP core user can easily control and access a user-added scan register other than a user-added boundary scan register. User-added scan registers (such as 60) for general purpose scan based input/output (110), via a core resident TAP, could serve many applications inside a system-on-a-chip such as expanded testing of circuits external to the core, user defined chip status bit monitoring, user defined chip control bit settings, and programming of electrically programmable circuits inside the chip. -
FIG. 6A relates toFIG. 6 asFIG. 3A relates toFIG. 3 , showing only theFIG. 6 IP core as it would be provided by the IP core vendor. - Although exemplary embodiments of the present disclosure are described above, this description does not limit the scope of the disclosure, which can be practiced in a variety of embodiments.
Claims (14)
1. An integrated circuit comprising:
a. an intellectual property core free of any boundary scan register; and
b. a test access port formed in the core, the test access port including test port interface signal leads and additional test input, test output and test control signal leads.
2. The integrated circuit of claim 1 in which the additional test signal leads include an external register present signal lead.
3. The integrated circuit of claim 1 including a scan register formed on the integrated circuit outside of the core, the scan register being connected to the test access port through the additional test input, test output and control signal leads.
4. The integrated circuit of claim 3 in which the scan register is a boundary scan register and the additional test signal leads include an external register present lead connected to indicate the presence of the boundary scan register.
5. The integrated circuit of claim 3 in which the scan register is a boundary scan register.
6. The integrated circuit of claim 3 wherein the scan register is a general purpose scan register.
7. The integrated circuit of claim 3 in which the additional test signal leads include an external register present lead connected to indicate the presence of a connected scan register.
8. The integrated circuit of claim 3 including electrically programmable circuits, the scan register being connected to the electrically programmable circuits for programming the electrically programmable circuits.
9. The integrated circuit of claim 1 in which the test access port includes a capture-shift-update register, a decode section and an external register present lead connected to both the capture-shift-update register and the decode section.
10. The integrated circuit of claim 1 in which the test port interface signal leads include a test data input signal lead, a test clock signal lead, a test mode select signal lead, a test reset signal lead and a test data output signal lead and the additional test input, test output and test control signal leads include a serial data output signal lead, a serial data input signal lead, a control signal lead and an external register present signal lead.
11. A process of executing boundary scan instructions at a test access port comprising:
a. sensing that the external register present signal is in a logical condition indicating the absence of a user-added boundary scan register; and
b. causing all boundary scan instructions to default to a bypass instruction.
12. The process of claim 11 in which the causing includes causing at least one of extest, intest, sample/preload, highz and clamp instructions to default to the bypass instruction.
13. A process of determining the presence of a user-added scan register comprising:
a. capturing a logical state of an external register present signal in a shift register;
b. shifting the contents of the shift register out of the shift register; and
c. examining the logical state of the external register present signal in the contents of the shift register shifted out of the shift register.
14. The process of claim 12 including capturing other status signals in the shift register.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/281,189 US20140258799A1 (en) | 1997-06-30 | 2014-05-19 | Ip core design supporting user-added scan register option |
Applications Claiming Priority (13)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US5137797P | 1997-06-30 | 1997-06-30 | |
US09/107,105 US6223315B1 (en) | 1997-06-30 | 1998-06-30 | IP core design supporting user-added scan register option |
US09/812,220 US6658615B2 (en) | 1998-06-30 | 2001-03-19 | IC with IP core and user-added scan register |
US10/705,648 US7065692B2 (en) | 1997-06-30 | 2003-11-10 | IC with external register present lead connected to instruction register |
US11/380,965 US7441170B2 (en) | 1997-06-30 | 2006-05-01 | External scan circuitry connected to leads extending from core circuitry |
US12/203,475 US7620867B2 (en) | 1997-06-30 | 2008-09-03 | IP core design supporting user-added scan register option |
US12/575,893 US7827453B2 (en) | 1997-06-30 | 2009-10-08 | Core test circuits controlling boundary and general external scan circuits |
US12/889,091 US8046649B2 (en) | 1997-06-30 | 2010-09-23 | Scan circuits formed peripheral of core circuits with control leads |
US13/238,564 US8214705B2 (en) | 1997-06-30 | 2011-09-21 | IC with first and second external register present leads |
US13/486,138 US8402331B2 (en) | 1997-06-30 | 2012-06-01 | Signal connections extending from the periphery of an IP core |
US13/765,251 US8539295B2 (en) | 1997-06-30 | 2013-02-12 | Executing TAP instructions in IP core with ERP lead |
US13/969,079 US8745456B2 (en) | 1997-06-30 | 2013-08-16 | Controlling user-added boundary scan register with TAP of IP core |
US14/281,189 US20140258799A1 (en) | 1997-06-30 | 2014-05-19 | Ip core design supporting user-added scan register option |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/969,079 Division US8745456B2 (en) | 1997-06-30 | 2013-08-16 | Controlling user-added boundary scan register with TAP of IP core |
Publications (1)
Publication Number | Publication Date |
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US20140258799A1 true US20140258799A1 (en) | 2014-09-11 |
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ID=22314867
Family Applications (11)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/812,220 Expired - Lifetime US6658615B2 (en) | 1997-06-30 | 2001-03-19 | IC with IP core and user-added scan register |
US10/705,648 Expired - Lifetime US7065692B2 (en) | 1997-06-30 | 2003-11-10 | IC with external register present lead connected to instruction register |
US11/380,965 Expired - Fee Related US7441170B2 (en) | 1997-06-30 | 2006-05-01 | External scan circuitry connected to leads extending from core circuitry |
US12/203,475 Expired - Fee Related US7620867B2 (en) | 1997-06-30 | 2008-09-03 | IP core design supporting user-added scan register option |
US12/575,893 Expired - Fee Related US7827453B2 (en) | 1997-06-30 | 2009-10-08 | Core test circuits controlling boundary and general external scan circuits |
US12/889,091 Expired - Fee Related US8046649B2 (en) | 1997-06-30 | 2010-09-23 | Scan circuits formed peripheral of core circuits with control leads |
US13/238,564 Expired - Fee Related US8214705B2 (en) | 1997-06-30 | 2011-09-21 | IC with first and second external register present leads |
US13/486,138 Expired - Fee Related US8402331B2 (en) | 1997-06-30 | 2012-06-01 | Signal connections extending from the periphery of an IP core |
US13/765,251 Expired - Fee Related US8539295B2 (en) | 1997-06-30 | 2013-02-12 | Executing TAP instructions in IP core with ERP lead |
US13/969,079 Expired - Fee Related US8745456B2 (en) | 1997-06-30 | 2013-08-16 | Controlling user-added boundary scan register with TAP of IP core |
US14/281,189 Abandoned US20140258799A1 (en) | 1997-06-30 | 2014-05-19 | Ip core design supporting user-added scan register option |
Family Applications Before (10)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/812,220 Expired - Lifetime US6658615B2 (en) | 1997-06-30 | 2001-03-19 | IC with IP core and user-added scan register |
US10/705,648 Expired - Lifetime US7065692B2 (en) | 1997-06-30 | 2003-11-10 | IC with external register present lead connected to instruction register |
US11/380,965 Expired - Fee Related US7441170B2 (en) | 1997-06-30 | 2006-05-01 | External scan circuitry connected to leads extending from core circuitry |
US12/203,475 Expired - Fee Related US7620867B2 (en) | 1997-06-30 | 2008-09-03 | IP core design supporting user-added scan register option |
US12/575,893 Expired - Fee Related US7827453B2 (en) | 1997-06-30 | 2009-10-08 | Core test circuits controlling boundary and general external scan circuits |
US12/889,091 Expired - Fee Related US8046649B2 (en) | 1997-06-30 | 2010-09-23 | Scan circuits formed peripheral of core circuits with control leads |
US13/238,564 Expired - Fee Related US8214705B2 (en) | 1997-06-30 | 2011-09-21 | IC with first and second external register present leads |
US13/486,138 Expired - Fee Related US8402331B2 (en) | 1997-06-30 | 2012-06-01 | Signal connections extending from the periphery of an IP core |
US13/765,251 Expired - Fee Related US8539295B2 (en) | 1997-06-30 | 2013-02-12 | Executing TAP instructions in IP core with ERP lead |
US13/969,079 Expired - Fee Related US8745456B2 (en) | 1997-06-30 | 2013-08-16 | Controlling user-added boundary scan register with TAP of IP core |
Country Status (1)
Country | Link |
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US (11) | US6658615B2 (en) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7378355B2 (en) * | 1997-05-09 | 2008-05-27 | Semitool, Inc. | System and methods for polishing a wafer |
US6658615B2 (en) * | 1998-06-30 | 2003-12-02 | Texas Instruments Incorporated | IC with IP core and user-added scan register |
US7003707B2 (en) * | 2000-04-28 | 2006-02-21 | Texas Instruments Incorporated | IC tap/scan test port access with tap lock circuitry |
US7139947B2 (en) * | 2000-12-22 | 2006-11-21 | Intel Corporation | Test access port |
JP3785388B2 (en) * | 2002-09-17 | 2006-06-14 | 松下電器産業株式会社 | Failure detection method |
US7380163B2 (en) * | 2003-04-23 | 2008-05-27 | Dot Hill Systems Corporation | Apparatus and method for deterministically performing active-active failover of redundant servers in response to a heartbeat link failure |
US6883151B2 (en) * | 2003-05-13 | 2005-04-19 | National Taiwan University | Method and device for IC identification |
US6936920B2 (en) * | 2003-08-29 | 2005-08-30 | Lsi Logic Corporation | Voltage contrast monitor for integrated circuit defects |
WO2005078465A1 (en) * | 2004-02-17 | 2005-08-25 | Institut National Polytechnique De Grenoble | Integrated circuit chip with communication means enabling remote control of testing means of ip cores of the integrated circuit |
US7685327B1 (en) * | 2004-03-19 | 2010-03-23 | Xilinx, Inc. | Identification of multi-device systems |
US7546394B1 (en) | 2004-03-19 | 2009-06-09 | Xilinx, Inc. | Management of configuration data by generating a chain description data set that specifies an order of configuration chain for multi-device systems |
EP1881955A1 (en) * | 2005-05-12 | 2008-01-30 | Boehringer Ingelheim International GmbH | Bis-amination of aryl halides |
US7945834B2 (en) * | 2005-11-02 | 2011-05-17 | Nxp B.V. | IC testing methods and apparatus |
JP2011149775A (en) * | 2010-01-20 | 2011-08-04 | Renesas Electronics Corp | Semiconductor integrated circuit and core test circuit |
TR201903230T4 (en) | 2010-07-08 | 2019-03-21 | Indian Oil Corp Ltd | Upstream regeneration of fcc catalyst for multi-stage fractionation. |
WO2013164663A1 (en) * | 2012-05-02 | 2013-11-07 | Freescale Semiconductor, Inc. | System-on-chip, method of manufacture thereof and method of communicating diagnostic data |
CN107300666B (en) * | 2017-06-15 | 2020-10-30 | 西安微电子技术研究所 | Test access isolation structure of embedded IP hardcore on SOC |
EP4425196A1 (en) | 2023-03-03 | 2024-09-04 | STMicroelectronics International N.V. | Integrated circuit comprising a test circuit, related method and computer-program product |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5862152A (en) * | 1995-11-13 | 1999-01-19 | Motorola, Inc. | Hierarchically managed boundary-scan testable module and method |
US6173428B1 (en) * | 1994-11-16 | 2001-01-09 | Cray Research, Inc. | Apparatus and method for testing using clocked test access port controller for level sensitive scan designs |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US622315A (en) * | 1899-04-04 | Lynford wreede | ||
US665815A (en) * | 1900-05-23 | 1901-01-08 | George Turrell | Box. |
JP2973641B2 (en) * | 1991-10-02 | 1999-11-08 | 日本電気株式会社 | TAP controller |
US5627842A (en) * | 1993-01-21 | 1997-05-06 | Digital Equipment Corporation | Architecture for system-wide standardized intra-module and inter-module fault testing |
US5744949A (en) * | 1993-08-17 | 1998-04-28 | Texas Instruments Incorporated | Analog test cell circuit |
TW253031B (en) * | 1993-12-27 | 1995-08-01 | At & T Corp | |
US5544174A (en) * | 1994-03-17 | 1996-08-06 | The United States Of America As Represented By The Secretary Of The Air Force | Programmable boundary scan and input output parameter device for testing integrated circuits |
US5754410A (en) * | 1996-09-11 | 1998-05-19 | International Business Machines Corporation | Multi-chip module with accessible test pads |
US5900753A (en) * | 1997-03-28 | 1999-05-04 | Logicvision, Inc. | Asynchronous interface |
US5900573A (en) * | 1997-06-03 | 1999-05-04 | Barnes; Owen R. | Percussion accompaniment device |
JPH1183956A (en) * | 1997-06-30 | 1999-03-26 | Texas Instr Inc <Ti> | Integrated circuit |
US6658615B2 (en) * | 1998-06-30 | 2003-12-02 | Texas Instruments Incorporated | IC with IP core and user-added scan register |
EP0997541A1 (en) * | 1998-10-26 | 2000-05-03 | ALUMINIUM RHEINFELDEN GmbH | Heat treating box for annealing and degreasing pieces made of aluminium |
-
2001
- 2001-03-19 US US09/812,220 patent/US6658615B2/en not_active Expired - Lifetime
-
2003
- 2003-11-10 US US10/705,648 patent/US7065692B2/en not_active Expired - Lifetime
-
2006
- 2006-05-01 US US11/380,965 patent/US7441170B2/en not_active Expired - Fee Related
-
2008
- 2008-09-03 US US12/203,475 patent/US7620867B2/en not_active Expired - Fee Related
-
2009
- 2009-10-08 US US12/575,893 patent/US7827453B2/en not_active Expired - Fee Related
-
2010
- 2010-09-23 US US12/889,091 patent/US8046649B2/en not_active Expired - Fee Related
-
2011
- 2011-09-21 US US13/238,564 patent/US8214705B2/en not_active Expired - Fee Related
-
2012
- 2012-06-01 US US13/486,138 patent/US8402331B2/en not_active Expired - Fee Related
-
2013
- 2013-02-12 US US13/765,251 patent/US8539295B2/en not_active Expired - Fee Related
- 2013-08-16 US US13/969,079 patent/US8745456B2/en not_active Expired - Fee Related
-
2014
- 2014-05-19 US US14/281,189 patent/US20140258799A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6173428B1 (en) * | 1994-11-16 | 2001-01-09 | Cray Research, Inc. | Apparatus and method for testing using clocked test access port controller for level sensitive scan designs |
US5862152A (en) * | 1995-11-13 | 1999-01-19 | Motorola, Inc. | Hierarchically managed boundary-scan testable module and method |
Also Published As
Publication number | Publication date |
---|---|
US8745456B2 (en) | 2014-06-03 |
US20120007622A1 (en) | 2012-01-12 |
US7441170B2 (en) | 2008-10-21 |
US20020010887A1 (en) | 2002-01-24 |
US7620867B2 (en) | 2009-11-17 |
US7065692B2 (en) | 2006-06-20 |
US20080320350A1 (en) | 2008-12-25 |
US6658615B2 (en) | 2003-12-02 |
US20100023822A1 (en) | 2010-01-28 |
US7827453B2 (en) | 2010-11-02 |
US8402331B2 (en) | 2013-03-19 |
US20040107394A1 (en) | 2004-06-03 |
US20130151917A1 (en) | 2013-06-13 |
US20060242512A1 (en) | 2006-10-26 |
US20120239994A1 (en) | 2012-09-20 |
US20110016366A1 (en) | 2011-01-20 |
US20130346818A1 (en) | 2013-12-26 |
US8046649B2 (en) | 2011-10-25 |
US8214705B2 (en) | 2012-07-03 |
US8539295B2 (en) | 2013-09-17 |
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Legal Events
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STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |