US20140219279A1 - Methods and systems for network address lookup engines - Google Patents

Methods and systems for network address lookup engines Download PDF

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US20140219279A1
US20140219279A1 US14/175,108 US201414175108A US2014219279A1 US 20140219279 A1 US20140219279 A1 US 20140219279A1 US 201414175108 A US201414175108 A US 201414175108A US 2014219279 A1 US2014219279 A1 US 2014219279A1
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input
data
address
neural network
output
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Warren GROSS
Naoya Onizawa
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Royal Institution for the Advancement of Learning
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    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/003—Arrangements for allocating sub-channels of the transmission path
    • H04L5/0053—Allocation of signaling, i.e. of overhead other than pilot signals
    • H04L5/0057—Physical resource allocation for CQI
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J11/00—Orthogonal multiplex systems, e.g. using WALSH codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J13/00—Code division multiplex systems
    • H04J13/0007—Code type
    • H04J13/004—Orthogonal
    • H04J13/0048—Walsh
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J13/00—Code division multiplex systems
    • H04J13/10—Code generation
    • H04J13/12—Generation of orthogonal codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0023—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the signalling
    • H04L1/0026—Transmission of channel quality indication
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0023—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the signalling
    • H04L1/0028—Formatting
    • H04L1/0029—Reduction of the amount of signalling, e.g. retention of useful signalling or differential signalling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/74—Address processing for routing
    • H04L45/745—Address table lookup; Address filtering
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/0001—Arrangements for dividing the transmission path
    • H04L5/0014—Three-dimensional division
    • H04L5/0016—Time-frequency-code
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/003—Arrangements for allocating sub-channels of the transmission path
    • H04L5/0044—Arrangements for allocating sub-channels of the transmission path allocation of payload
    • H—ELECTRICITY
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    • H—ELECTRICITY
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    • H04L5/003—Arrangements for allocating sub-channels of the transmission path
    • H04L5/0048—Allocation of pilot signals, i.e. of signals known to the receiver
    • H04L5/005—Allocation of pilot signals, i.e. of signals known to the receiver of common pilots, i.e. pilots destined for multiple users or terminals
    • H—ELECTRICITY
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    • H04L5/0053—Allocation of signaling, i.e. of overhead other than pilot signals
    • H04L5/0055—Physical resource allocation for ACK/NACK
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/003—Arrangements for allocating sub-channels of the transmission path
    • H04L5/0058—Allocation criteria
    • H04L5/006—Quality of the received signal, e.g. BER, SNR, water filling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/0091—Signaling for the administration of the divided path
    • H04L5/0094—Indication of how sub-channels of the path are allocated
    • H04L61/1552—
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
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    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
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    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/1607—Details of the supervisory signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/46—Cluster building
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/0001—Arrangements for dividing the transmission path
    • H04L5/0003—Two-dimensional division
    • H04L5/0005—Time-frequency
    • H04L5/0007—Time-frequency the frequencies being orthogonal, e.g. OFDM(A), DMT
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/003—Arrangements for allocating sub-channels of the transmission path
    • H04L5/0053—Allocation of signaling, i.e. of overhead other than pilot signals

Definitions

  • one destination address may match more than one routing table entry.
  • the most specific table entry the one with the highest subnet mask, being called the longest prefix match.
  • IPv4 Internet Protocol version 4
  • IPv6 Internet Protocol version 6
  • a low-power large-scale IP lookup engine may be implemented exploiting clustered neural networks (CNNs).
  • CNNs clustered neural networks
  • FIGS. 2A and 2B depict an IP lookup engine exploiting CNNs without wildcards in learning and retrieving processes
  • FIGS. 3A to 3C depict an IP lookup engine according to an embodiment of the invention exploiting wildcards in local storing, dummy neuron activation, and global storing processes;
  • FIGS. 11A and 11B depict circuits schematics for memory blocks providing local storing (MLS) and global storing (MGS) forming portions of an IP lookup engine according to the second implementation architecture in FIG. 10 ;
  • FIGS. 13A and 13B depict circuits schematics for decoding modules based upon ILSW and MILSW respectively forming portions of IP lookup engines according to the second implementation architecture in FIG. 10 for ILSW and MILSW variants;
  • FIGS. 14A and 14B depict circuits schematics for ambiguity elimination block and output selector forming portions of IP lookup engines according to the second implementation architecture in FIG. 10 ;
  • CNNs clustered neural networks
  • a CNN is a neural network which stores data using only binary weighted connections between several clusters, see for example Gripon et al. in “Sparse neural networks with large learning diversity” (IEEE Trans. Neural Networks, Vol. 22, No. 7, pp. 1087-1096).
  • HNN Hopfield Neural Network
  • the CNN requires less complex functions while learning (storing) larger number of messages.
  • a hardware implementation for a CNN has been reported by Jarollahi et. al. in “Architecture and implementation of an associative memory using sparse clustered networks” (Proc. ISCAS 2012, pp. 2901-2904).
  • IP addresses and their corresponding rules are stored.
  • a k-th (1 ⁇ k ⁇ N) learning address m k is composed of c-sub-messages m k1 . . . m kc and a k-th learning rule m′ k is composed of c′-sub-messages m′ k1 . . . m′ kc′ .
  • N is the number of stored addresses.
  • the length of the address is c*log 2 l bits and that of the rule is c′ ⁇ log 2 l′ bits.
  • the learnt message 1.9.10.X has a wildcard.
  • the wildcard is replaced by XORing 9 ⁇ 1 that are the two sub-messages in the first two input clusters, hence the wildcard becomes 8.
  • process (1) is performed by using md k instead of m k in order to make connections between the input and output clusters and then these connections are stored.
  • the dummy sub-message (sub-address) is converted to an l-bit one-hot signal that activates the corresponding dummy neuron in an input cluster associated with the wildcard.
  • the M stored messages are now defined by M 1 , . . . , M M which include the updated input addresses and output rule (port) and connections between the input and the output activated neurons are stored as shown in FIG. 3C and are given by Equation (10).
  • Equations (5) and (6) are executed.
  • Table 1 the learnt messages as a result of the “Local decoding” and “Global decoding” processes described supra in respect of FIGS. 3 and 4 are presented showing the IP address, IP address with dummy and the associated rule.
  • the MILSW there are two types of “wrongly” activated neurons in the input clusters from (c ⁇ c b ) to c. These two types of the activated neurons affect the probability.
  • the first type related to (12) when a sub-message that is not stored is wrongly treated as a “stored sub-message”, the corresponding neuron is wrongly activated.
  • the average number of wrongly activated neurons per input cluster in the first type ( ⁇ 1 ) is given by Equation (19).
  • P amb without wildcards is defined by Equation (7).
  • P anib with wildcards was evaluated by simulations. Unlike IPv4, since packet traces for the long prefix table are not available to the public and the prefix table is still small, see for example “Border Gateway Protocol (BGP)” (http://bgp.potaroo.net), addresses were chosen randomly for the evaluation. The stored addresses are uniformly distributed. Random-length wildcards appear in the last half of addresses (72 bits). If the range of addresses that have wildcards is changed, the prefix length can be changed.
  • BGP Border Gateway Protocol
  • FIG. 7 there is depicted an overall structure 700 of an IP lookup engine according to an embodiment of the invention with wildcards.
  • the learning process is “Local learning” using Equation (8) and “Global learning” as presented in respect of Equations (9) and (1).
  • the retrieving process employed exploits the following process:
  • FIG. 11 shows the MLS contains (c ⁇ l) l 2 -bit sub-memory blocks and the MGS contains c*c′ ll′-bit sub-memory blocks. Both the ILSW and the MILSW use the same memory block.
  • an external processing unit e.g. a central processing unit (CPU) or microprocessor.
  • CPU central processing unit
  • l bits of ⁇ ′ (i,j)(i′,j′) are serially sent from the CPU and are stored in the SRAM shown in FIG.
  • FIG. 12A depicts a circuit diagram of the input-replacement module based on the ILSW.
  • the updated input address (ms in ) is generated using the stored connections read from the MLS in (12) at the first clock cycle.
  • a flip-flop is enabled to store ms inj1 and transfers it to the MGS.
  • FIG. 12B depicts a circuit diagram of the dummy generator for the MILSW.
  • the matched word selects its corresponding port from the registers through a one-hot encoder and a multiplexer and then m out is transferred to an output selector shown in FIG. 14B .
  • the signal (mismatch) is low when the matched word is found in the TCAM and high when it is not found. If the matched word is found, m out is selected as an output port in the output selector. Otherwise, the output port is selected from the global decoding module.
  • the proposed IP lookup engine described in respect of Section 4.2 Implementation 2 and FIGS. 10 to 14 respectively was designed based upon the Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) 65 nm CMOS technology.
  • the MLS and the MGS both exploit 15 SRAM blocks (256 kb) and 32 SRAM blocks (256 kb), respectively.
  • a reference TCAM was also designed.
  • the TCAM cell is designed using a NAND-type cell that consists of 16 transistors, as per Pagiamtzis et al in “Content-Addressable Memory (CAM) Circuits and Architectures: A tutorial and Survey” (IEEE J. Solid State Circuits, Vol. 41, No. 3, pp.
  • the worst-case delay is 1.31 ns in the block that includes the max-function block. This delay is 89.1% of the previous method (Ozinawa2) that includes an ambiguity checker after Global decoding.
  • the delay of the max-function block is 65.8% of the whole delay.
  • the worst-case delay is 0.62 ns.
  • throughput may be defined by (address length)/(worst-case delay)/(retrieving clock cycles) the MILSW offers increased throughput compared to the previous method (Ozinawa2) and the ILSW.
  • IP lookup search engines and context driven search engines discussed supra
  • other applications of embodiments of the invention include, but are no limited, CPU fully associative cache controllers and translation lookaside buffers, database search engines, database engines, data compression, artificial neural networks, and electronic intrusion prevention system.
  • Implementation of the techniques, blocks, steps and means described above may be done in various ways. For example, these techniques, blocks, steps and means may be implemented in hardware, software, or a combination thereof.
  • the processing units may be implemented within one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, other electronic units designed to perform the functions described above and/or a combination thereof.
  • ASICs application specific integrated circuits
  • DSPs digital signal processors
  • DSPDs digital signal processing devices
  • PLDs programmable logic devices
  • FPGAs field programmable gate arrays
  • processors controllers, micro-controllers, microprocessors, other electronic units designed to perform the functions described above and/or a combination thereof.
  • the methodologies described herein are, in one or more embodiments, performable by a machine which includes one or more processors that accept code segments containing instructions. For any of the methods described herein, when the instructions are executed by the machine, the machine performs the method. Any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine are included.
  • a typical machine may be exemplified by a typical processing system that includes one or more processors.
  • Each processor may include one or more of a CPU, a graphics-processing unit, and a programmable DSP unit.
  • the processing system further may include a memory subsystem including main RAM and/or a static RAM, and/or ROM.
  • a bus subsystem may be included for communicating between the components.
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CN106875011A (zh) * 2017-01-12 2017-06-20 南京大学 二值权重卷积神经网络加速器的硬件架构及其计算流程
US10027739B1 (en) 2014-12-16 2018-07-17 Amazon Technologies, Inc. Performance-based content delivery
US10104009B2 (en) 2008-09-29 2018-10-16 Amazon Technologies, Inc. Managing resource consolidation configurations
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US10148542B2 (en) 2008-09-29 2018-12-04 Amazon Technologies, Inc. Monitoring domain allocation performance
US10462025B2 (en) 2008-09-29 2019-10-29 Amazon Technologies, Inc. Monitoring performance and operation of data exchanges
US10284446B2 (en) 2008-09-29 2019-05-07 Amazon Technologies, Inc. Optimizing content management
US10205644B2 (en) 2008-09-29 2019-02-12 Amazon Technologies, Inc. Managing network data display
US10104009B2 (en) 2008-09-29 2018-10-16 Amazon Technologies, Inc. Managing resource consolidation configurations
US10410085B2 (en) 2009-03-24 2019-09-10 Amazon Technologies, Inc. Monitoring web site content
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CN106875011A (zh) * 2017-01-12 2017-06-20 南京大学 二值权重卷积神经网络加速器的硬件架构及其计算流程
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