US20140175545A1 - Double diffused metal oxide semiconductor device and manufacturing method thereof - Google Patents
Double diffused metal oxide semiconductor device and manufacturing method thereof Download PDFInfo
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- US20140175545A1 US20140175545A1 US13/726,579 US201213726579A US2014175545A1 US 20140175545 A1 US20140175545 A1 US 20140175545A1 US 201213726579 A US201213726579 A US 201213726579A US 2014175545 A1 US2014175545 A1 US 2014175545A1
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- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 16
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 210000000746 body region Anatomy 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims description 46
- 230000000694 effects Effects 0.000 abstract description 16
- 238000005468 ion implantation Methods 0.000 description 19
- 238000001459 lithography Methods 0.000 description 19
- 239000012535 impurity Substances 0.000 description 12
- 239000007943 implant Substances 0.000 description 10
- 150000002500 ions Chemical class 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000002513 implantation Methods 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000001015 X-ray lithography Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
Definitions
- the present invention relates to a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof; particularly, it relates to such DMOS device and manufacturing method thereof wherein electrostatic discharge (ESD) effect is mitigated.
- DMOS double diffused metal oxide semiconductor
- FIGS. 1A-1B show a cross-section view and a top view of a prior art LDMOS device 100 respectively.
- FIGS. 2A-2B show a cross-section view and a top view of a prior art DDDMOS device 200 respectively.
- a field oxide region 12 is formed in a P-type substrate 11 , wherein the field oxide region 12 for example is a shallow trench isolation (STI) structure or a local oxidation of silicon (LOCOS) structure, the latter being shown in FIG. 1A .
- STI shallow trench isolation
- LOC local oxidation of silicon
- the LDMOS device 100 includes a gate 13 , an N-type high voltage well 14 , an N-type source 15 , an N-type drain 16 , a P-type body region 17 , and a P-type body electrode 18 .
- the N-type high voltage well 14 , the N-type source 15 and the N-type drain 16 are defined by lithography process steps and formed by ion implantation process steps, wherein the lithography process step defines the implantation region by a photoresist mask together with a self-alignment effect provided by all or part of the gate 13 and the field oxide region 12 , and the ion implantation process step implants N-type impurities to the defined region in the form of accelerated ions.
- the P-type body region 17 and the P-type body electrode 18 are defined by lithography process steps and formed by ion implantation process steps, wherein the lithography process step defines the implantation region by a photoresist mask together with a self-alignment effect provided by all or part of the gate 13 and the field oxide region 12 , and the ion implantation process step implants P-type impurities to the defined region in the form of accelerated ions.
- the source 15 and the drain 16 are below the gate 13 and at different sides thereof respectively.
- part of the gate 13 is located on the field oxide region 12 .
- FIG. 1A is a cross-section taken in a lateral direction along a cross-section line AB indicated in the top view FIG. 1B . Referring to FIG. 1B , in a vertical direction, a conductive layer 19 connects both the source 15 and the body electrode 18 , such that the source 15 and the body region 17 are kept at a same voltage level, such as a ground level.
- FIGS. 2A-2B show the cross-section view and the top view of the prior art DDDMOS device 200 respectively.
- the DDDMOS device 200 is different from the aforementioned LDMOS device 100 in that, a gate 23 of the DDDMOS device 200 is entirely on an upper surface of a P-type substrate 21 with no part on a field oxide region.
- the DDDMOS device 200 includes the gate 23 , an N-type high voltage well 24 , an N-type source 25 , an N-type drain 26 , a P-type body region 27 , and a P-type body electrode 28 .
- the N-type high voltage well 24 , the N-type source 25 and the N-type drain 26 are defined by lithography process steps and formed by ion implantation process steps, wherein the lithography process step defines the implantation region by a photoresist mask together with a self-alignment effect provided by all or part of the gate 23 , and the ion implantation process step implants N-type impurities to the defined region in the form of accelerated ions.
- the P-type body region 27 and the P-type body electrode 28 are defined by lithography process steps and formed by ion implantation process steps, wherein the lithography process step defines the implantation region by a photoresist mask together with a self-alignment effect provided by all or part of the gate 23 , and the ion implantation process step implants P-type impurities to the defined region in the form of accelerated ions.
- the source 25 and the drain 26 are below the gate 23 and at different sides thereof respectively. Referring to FIG. 2 B, in a vertical direction, a conductive layer 29 connects both the source 25 and the body electrode 28 , such that the source 25 and the body region 27 are kept at a same voltage level, such as the ground level.
- the LDMOS and DDDMOS devices are DMOS devices.
- a very high electric field is formed at the end of the DMOS device, and the lateral channel between the source and the drain at the end of the DMOS device in the vertical direction often is not fully conductive, so a breakdown usually occurs at an end of the DMOS device in the vertical direction, which may damage the DMOS device.
- the prior art DMOS devices have limited capability of sustaining the ESD, and the application range of the DMOS devices is limited, because the end of the DMOS device in the vertical direction can not sustain the high electrostatic voltage and tends to breakdown.
- the present invention proposes a DMOS device and a manufacturing method thereof, wherein the ESD effect of the DMOS device is mitigated, so that the DMOS device may have a broader application range.
- a first objective of the present invention is to provide a double diffused metal oxide semiconductor (DMOS) device.
- DMOS double diffused metal oxide semiconductor
- a second objective of the present invention is to provide a manufacturing method of a DMOS device.
- the present invention provides a double diffused metal oxide semiconductor (DMOS) device, including: a first conductive type substrate, which has an upper surface; a second conductive type high voltage well, which is formed in the substrate below the upper surface; a gate, which is formed on the upper surface, wherein at least part of the gate is located in the high voltage well from top view, and the gate has a first side and a second side opposite to each other in a vertical direction; a first conductive type body region, which is formed in the high voltage well below the upper surface, wherein at least part of the body region is located outside the first side; a source and a drain with second conductive type, which are formed below the upper surface outside the gate, the source being located in the body region outside the first side, and the drain being located outside the second side, wherein the drain and the gate are separated by the high voltage well, and when the DMOS device turns ON, a lateral channel is formed between the source and the drain below the upper surface; a first conductive type body
- the present invention provides a manufacturing method of a double diffused metal oxide semiconductor (DMOS) device, including: providing a first conductive type substrate, which has an upper surface; forming a second conductive type high voltage well in the substrate below the upper surface; forming a gate on the upper surface, wherein at least part of the gate is located in the high voltage well from top view, and the gate has a first side and a second side opposite to each other in a vertical direction; forming a first conductive type body region in the high voltage well below the upper surface, wherein at least part of the body region is located outside the first side; forming a source and a drain with second conductive type below the upper surface outside the gate, the source being located in the body region outside the first side, and the drain being located outside the second side, wherein the drain and the gate are separated by the high voltage well, and when the DMOS device turns ON, a lateral channel is formed between the source and the drain below the upper surface; forming a first conductive type body electrode in the body region below the
- the floating region is located outside one vertical end of the source from top view, and is directly or not directly in contact with the source.
- the floating region separates the source to a first source and a second source in the vertical direction, and the floating region and the source are separated by part of the body region.
- the DMOS device may be a double diffused drain metal oxide semiconductor (DDDMOS) device or a lateral double diffused metal oxide semiconductor (LDMOS) device.
- DDDMOS double diffused drain metal oxide semiconductor
- LDMOS lateral double diffused metal oxide semiconductor
- the floating region and the body electrode are formed by a same process step.
- FIGS. 1A-1B show a cross-section view and a top view of a prior art LDMOS device 100 respectively.
- FIGS. 2A-2B show a cross-section view and a top view of a prior art DDDMOS device 200 respectively.
- FIGS. 3A-3B show a first embodiment of the present invention.
- FIG. 4 shows current-voltage characteristic curves of DMOS devices of the prior art and the present invention obtained by a transmission-line pulse ESD test.
- FIGS. 5A-5L show a second embodiment of the present invention.
- FIGS. 6A-6C show a third, a fourth, and a fifth embodiments of the present invention, respectively.
- FIGS. 3A and 3B are schematic diagrams of a DDDMOS device 300 according to a first embodiment of the present invention from cross-section and top view, wherein FIG. 3A shows the cross-section view taken along a cross-section line CD of the top view shown in FIG. 3B .
- the DDDMOS device 300 includes a substrate 31 , a gate 33 , an N-type high voltage well 34 , an N-type source 35 , an N-type drain 36 , a P-type body region 37 , a P-type body electrode 38 , and a P-type floating region 38 a.
- the substrate 31 for example is P-type but not limited to P-type, and the substrate 31 has an upper surface 311 .
- the gate 33 is formed on the upper surface 311 .
- the N-type high voltage well 34 , the N-type source 35 , and the N-type drain 36 are formed below the upper surface 311 in the substrate 31 .
- the N-type high voltage well 34 , the N-type source 35 , and the N-type drain 36 are defined by lithography process steps and formed by ion implantation process steps, wherein the lithography process step defines the implantation region by a photoresist mask together with a self-alignment effect provided by all or part of the gate 33 , and the ion implantation process step implants N-type impurities to the defined region in the form of accelerated ions.
- the P-type body region 37 , the P-type body electrode 38 , and the P-type floating region 38 a are formed below the upper surface 311 and defined by lithography process steps and formed by ion implantation process steps, wherein the lithography process step defines the implantation region by a photoresist mask together with a self-alignment effect provided by all or part of the gate 33 and the field oxide region 12 , and the ion implantation process step implants P-type impurities to the defined region in the form of accelerated ions.
- the source 35 and the drain 36 are below the gate 33 and at different sides thereof respectively. At least part of the gate 33 is located in the high voltage well 34 from the top view FIG.
- the gate 33 has a first side 33 a and a second side 33 b opposite to each other in the vertical direction.
- the body region 37 is formed in the high voltage well 34 below the upper surface 311 , wherein at least part of the body region 37 is located outside the first side 33 a.
- the source 35 and the drain 36 are formed below the upper surface 311 outside the gate 31 .
- the source 35 is located in the body region 37 outside the first side 33 a, and the drain 36 is located outside the second side 33 b.
- the drain 36 and the gate 33 are separated by the high voltage well 34 .
- a lateral channel (not shown) is formed between the source 35 and the drain 36 below the upper surface 311 .
- the body electrode 38 is formed in the body region 37 below the upper surface 311 as an electrically contact of the body region 37 .
- the DDDMOS device 300 has the floating region 38 a formed in the body region 37 below the upper surface 311 , wherein the floating region 38 a is electrically floating and electrically isolated from the source 35 and the gate 33 , i.e., the floating region 38 a has an independent voltage level which is not directly related to the voltage levels of the source 35 and the gate 33 .
- the arrangement of the floating region 38 a in this embodiment of the present invention is advantageous in that, first, the floating region 38 a and the body electrode 38 may be (but not limited to) formed in the substrate 31 by a same process step without any additional mask or process step, such that the manufacturing cost can be reduced; second, more importantly, when the DDDMOS device 300 electrically contacts a high voltage ESD, because of the floating region 38 a, the channel of the DDDMOS device 300 can be fully turned ON to release the high voltage ESD before the high voltage ESD damages the DDDMOS device 300 , such that the ESD effect is mitigated.
- FIG. 4 shows current-voltage characteristic curves obtained by a transmission-line pulse ESD test of the present invention and a prior art DMOS device.
- the prior art DMOS device has a trigger voltage of about 40V, which is higher than the trigger voltage of the DMOS device of the present invention (about 30V); this means that the DMOS device of the present invention turns ON earlier when an electrostatic voltage is applied, so the ESD effect is mitigated in the present invention as compared with the prior art.
- the ESD breakdown voltage i.e., the voltage causing an obvious leakage current, of the present invention is higher than the prior art DMOS device. Therefore, the DMOS device of the present invention can sustain a higher electrostatic voltage and a higher electrostatic current. The above shows that the present invention is advantageous over the prior art.
- FIGS. 5A-5L are schematic diagrams showing a manufacturing method of the DDDMOS device 300 according to the present invention.
- FIGS. 5A-5B are schematic diagrams showing a manufacturing method of the DDDMOS device 300 according to the present invention.
- the substrate 31 with the upper surface 311 is provided, which has for example but not limited to the P-type conductivity.
- the N-type high voltage well 34 is formed in the P-type substrate 31 below the upper surface 311 .
- the gate 33 is formed on the upper surface 311 . From the top view FIG. 5C , the gate 33 is located in the high voltage well 34 , wherein the gate 33 has the first side 33 a and the second side 33 b opposite to each other in the vertical direction.
- the body region 37 is defined by a lithography process step with for example but not limited to a photoresist mask 37 a together with a self-alignment effect provided by part of the gate 33 , and an ion implantation process step implants P-type impurities to the defined region in the N-type high voltage well 34 in the form of accelerated ions as indicated by the dashed arrow lines. Part of the P-type impurities will diffuse to the gate 33 below, to form a P-type region of the channel. Therefore, part of the body region 37 is below the gate 33 and other part of the body region 37 is outside the first side 33 a.
- the N-type source 35 and drain 36 are defined by a lithography process step with for example but not limited to a photoresist mask 36 a together with a self-alignment effect provided by part of the gate 33 , and an ion implantation process step implants N-type impurities to the defined regions in the P-type body region 37 and the N-type high voltage well 34 respectively, in the form of accelerated ions as indicated by the dashed arrow lines.
- the source 35 is located in the body region 37 outside the first side 33 a, and the drain 36 is located outside the second side 33 b, and the drain 36 and the gate 33 are separated by the high voltage well 34 (so the source 35 and the drain 36 are further separated).
- a lateral channel (not shown) is formed between the source 35 and the drain 36 below the upper surface 311 .
- FIGS. 5I and 5J the P-type body electrode 38 and the P-type floating region 38 a are formed by the same or different process steps in the body region 37 below the upper surface 311 , wherein the floating region 38 a is electrically floating and electrically isolated from the source 35 and the gate 33 .
- FIG. 5J is a cross-section view taken along a cross-section line EF in the top view FIG. 5I , so FIG. 5J does not show the floating region 38 a .
- the P-type body electrode 38 and the P-type floating region 38 a are formed by, for example but not limited to, the same ion implantation process step.
- the floating region 38 a is formed, for example but not limited to, outside the source 35 in the vertical direction and in contact with the source 35 .
- FIGS. 5K and 5L show a top view and a cross-section view taken along a cross-section line GH in the top view of the DDDMOS device 300 , respectively.
- a conductive layer 39 which connects the source 35 and the body region 38 is formed, such that the source 35 and the body region 37 are electrically connected.
- the source 35 and the body electrode may connect to different conductive layers respectively, such that the source 35 and the body region 37 are not electrically connected.
- the latter arrangement also belongs to the scope of the present invention.
- the conductive layer 39 does not connect to the floating region 38 a, such that the voltage level of the floating region 38 a is unaffected and remains floating.
- FIGS. 6A-6C show a third, fourth, and a fifth embodiments of the present invention, respectively, to show that the floating region of the present invention may be embodied in various different forms.
- this embodiment is different from the first embodiment in that, a floating region 38 b of a DDDMOS device 400 is located outside the source 35 in the body region 37 in the vertical direction from top view FIG. 6A , and is not in contact to the source 35 .
- FIG. 6B shows the fourth embodiment of the present invention.
- This embodiment is different from the first embodiment in that, a floating region 38 c of a DDDMOS device 500 separates the source 35 to a first source 35 a and a second source 35 b in the vertical direction as shown by the top view FIG.
- first source 35 a and the second source 35 b are separated, they may be electrically connected by one or more conductive layers (not shown) electrically connecting the separated conductive layers 39 .
- FIG. 6C shows the fifth embodiment of the present invention.
- the LDMOS device 600 includes: a substrate 61 , a field oxide region 62 , a gate 63 , an N-type high voltage well 64 , an N-type source 65 , an N-type drain 66 , a P-type body region 67 , a P-type body electrode 68 , and a P-type floating region 68 a.
- the substrate 61 is for example but not limited to P-type.
- the N-type high voltage well 64 , the N-type source 65 , and the N-type drain 66 are formed by lithography process steps and ion implantation process steps, wherein the lithography process step defines the implantation region by a photoresist mask together with a self-alignment effect provided by all or part of the gate 63 with the field oxide region 62 , and the ion implantation process step implants N-type impurities to the defined region in the form of accelerated ions.
- the P-type body region 67 , the P-type body electrode 68 , and the P-type floating region 68 a are formed by lithography process steps and ion implantation process steps, wherein the lithography process step defines the implantation region by a photoresist mask together with a self-alignment effect provided by all or part of the gate 63 with the field oxide region 62 , and the ion implantation process step implants P-type impurities to the defined region in the form of accelerated ions.
- the source 65 and the drain 66 are below the gate 63 and at different sides thereof respectively.
- the source 65 and the gate 63 are separated by the high voltage well 64 .
- the source 65 , the body electrode 68 , and the floating region 68 a are formed in the body region 67 .
- the present invention has been described in considerable detail with reference to certain preferred embodiments thereof. It should be understood that the description is for illustrative purpose, not for limiting the scope of the present invention. Those skilled in this art can readily conceive variations and modifications within the spirit of the present invention. For example, other process steps or structures which do not affect the primary characteristic of the device, such as a threshold voltage adjustment region, etc., can be added; for another example, the lithography step described in the above can be replaced by electron beam lithography, X-ray lithography, etc.; for another example, in all the aforementioned embodiments, the conductive type of each region is not limited to P-type, such as the body region, the body electrode, and the floating region, etc.
- N-type such as the high voltage well, the source, and the drain, etc.
- P-type N-type
- the present invention is not limited to be applied in the DDDMOS device or the LDMOS device, but may be applied in other high voltage devices.
- An embodiment or a claim of the present invention does not need to achieve all the objectives or advantages of the present invention.
- the title and abstract are provided for assisting searches but not for limiting the scope of the present invention.
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Abstract
Description
- 1. Field of Invention
- The present invention relates to a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof; particularly, it relates to such DMOS device and manufacturing method thereof wherein electrostatic discharge (ESD) effect is mitigated.
- 2. Description of Related Art
- Lateral double diffused metal oxide semiconductor (LDMOS) device and double diffused drain metal oxide semiconductor (DDDMOS) are typical high voltage devices, which are both referred to as DMOS devices.
FIGS. 1A-1B show a cross-section view and a top view of a priorart LDMOS device 100 respectively. AndFIGS. 2A-2B show a cross-section view and a top view of a priorart DDDMOS device 200 respectively. As shown inFIGS. 1A-1B , afield oxide region 12 is formed in a P-type substrate 11, wherein thefield oxide region 12 for example is a shallow trench isolation (STI) structure or a local oxidation of silicon (LOCOS) structure, the latter being shown inFIG. 1A . TheLDMOS device 100 includes agate 13, an N-typehigh voltage well 14, an N-type source 15, an N-type drain 16, a P-type body region 17, and a P-type body electrode 18. The N-type high voltage well 14, the N-type source 15 and the N-type drain 16 are defined by lithography process steps and formed by ion implantation process steps, wherein the lithography process step defines the implantation region by a photoresist mask together with a self-alignment effect provided by all or part of thegate 13 and thefield oxide region 12, and the ion implantation process step implants N-type impurities to the defined region in the form of accelerated ions. The P-type body region 17 and the P-type body electrode 18 are defined by lithography process steps and formed by ion implantation process steps, wherein the lithography process step defines the implantation region by a photoresist mask together with a self-alignment effect provided by all or part of thegate 13 and thefield oxide region 12, and the ion implantation process step implants P-type impurities to the defined region in the form of accelerated ions. Thesource 15 and thedrain 16 are below thegate 13 and at different sides thereof respectively. In theLDMOS device 100, part of thegate 13 is located on thefield oxide region 12.FIG. 1A is a cross-section taken in a lateral direction along a cross-section line AB indicated in the top viewFIG. 1B . Referring toFIG. 1B , in a vertical direction, aconductive layer 19 connects both thesource 15 and thebody electrode 18, such that thesource 15 and thebody region 17 are kept at a same voltage level, such as a ground level. -
FIGS. 2A-2B show the cross-section view and the top view of the priorart DDDMOS device 200 respectively. TheDDDMOS device 200 is different from theaforementioned LDMOS device 100 in that, agate 23 of theDDDMOS device 200 is entirely on an upper surface of a P-type substrate 21 with no part on a field oxide region. TheDDDMOS device 200 includes thegate 23, an N-typehigh voltage well 24, an N-type source 25, an N-type drain 26, a P-type body region 27, and a P-type body electrode 28. The N-type high voltage well 24, the N-type source 25 and the N-type drain 26 are defined by lithography process steps and formed by ion implantation process steps, wherein the lithography process step defines the implantation region by a photoresist mask together with a self-alignment effect provided by all or part of thegate 23, and the ion implantation process step implants N-type impurities to the defined region in the form of accelerated ions. The P-type body region 27 and the P-type body electrode 28 are defined by lithography process steps and formed by ion implantation process steps, wherein the lithography process step defines the implantation region by a photoresist mask together with a self-alignment effect provided by all or part of thegate 23, and the ion implantation process step implants P-type impurities to the defined region in the form of accelerated ions. Thesource 25 and thedrain 26 are below thegate 23 and at different sides thereof respectively. Referring to FIG. 2B, in a vertical direction, aconductive layer 29 connects both thesource 25 and the body electrode 28, such that thesource 25 and thebody region 27 are kept at a same voltage level, such as the ground level. - The LDMOS and DDDMOS devices are DMOS devices. In general applications such as in an ESD test or actual operation, when the drain is electrically connected to a high voltage, especially an electrostatic voltage with a relatively high level, a very high electric field is formed at the end of the DMOS device, and the lateral channel between the source and the drain at the end of the DMOS device in the vertical direction often is not fully conductive, so a breakdown usually occurs at an end of the DMOS device in the vertical direction, which may damage the DMOS device. The prior art DMOS devices have limited capability of sustaining the ESD, and the application range of the DMOS devices is limited, because the end of the DMOS device in the vertical direction can not sustain the high electrostatic voltage and tends to breakdown.
- In view of above, to overcome the drawbacks in the prior art, the present invention proposes a DMOS device and a manufacturing method thereof, wherein the ESD effect of the DMOS device is mitigated, so that the DMOS device may have a broader application range.
- A first objective of the present invention is to provide a double diffused metal oxide semiconductor (DMOS) device.
- A second objective of the present invention is to provide a manufacturing method of a DMOS device.
- To achieve the objectives mentioned above, from one perspective, the present invention provides a double diffused metal oxide semiconductor (DMOS) device, including: a first conductive type substrate, which has an upper surface; a second conductive type high voltage well, which is formed in the substrate below the upper surface; a gate, which is formed on the upper surface, wherein at least part of the gate is located in the high voltage well from top view, and the gate has a first side and a second side opposite to each other in a vertical direction; a first conductive type body region, which is formed in the high voltage well below the upper surface, wherein at least part of the body region is located outside the first side; a source and a drain with second conductive type, which are formed below the upper surface outside the gate, the source being located in the body region outside the first side, and the drain being located outside the second side, wherein the drain and the gate are separated by the high voltage well, and when the DMOS device turns ON, a lateral channel is formed between the source and the drain below the upper surface; a first conductive type body electrode, which is formed in the body region below the upper surface as an electrically contact of the body region; and a first conductive type floating region, which is formed in the body region below the upper surface, wherein the floating region is electrically floating and electrically isolated from the source and the gate.
- From another perspective, the present invention provides a manufacturing method of a double diffused metal oxide semiconductor (DMOS) device, including: providing a first conductive type substrate, which has an upper surface; forming a second conductive type high voltage well in the substrate below the upper surface; forming a gate on the upper surface, wherein at least part of the gate is located in the high voltage well from top view, and the gate has a first side and a second side opposite to each other in a vertical direction; forming a first conductive type body region in the high voltage well below the upper surface, wherein at least part of the body region is located outside the first side; forming a source and a drain with second conductive type below the upper surface outside the gate, the source being located in the body region outside the first side, and the drain being located outside the second side, wherein the drain and the gate are separated by the high voltage well, and when the DMOS device turns ON, a lateral channel is formed between the source and the drain below the upper surface; forming a first conductive type body electrode in the body region below the upper surface as an electrically contact of the body region; and forming a first conductive type floating region in the body region below the upper surface, wherein the floating region is electrically floating and electrically isolated from the source and the gate.
- In one preferable embodiment, the floating region is located outside one vertical end of the source from top view, and is directly or not directly in contact with the source.
- In another preferable embodiment, the floating region separates the source to a first source and a second source in the vertical direction, and the floating region and the source are separated by part of the body region.
- In the aforementioned embodiment, the DMOS device may be a double diffused drain metal oxide semiconductor (DDDMOS) device or a lateral double diffused metal oxide semiconductor (LDMOS) device.
- In one another preferable embodiment, the floating region and the body electrode are formed by a same process step.
- The objectives, technical details, features, and effects of the present invention will be better understood with regard to the detailed description of the embodiments below.
-
FIGS. 1A-1B show a cross-section view and a top view of a priorart LDMOS device 100 respectively. -
FIGS. 2A-2B show a cross-section view and a top view of a priorart DDDMOS device 200 respectively. -
FIGS. 3A-3B show a first embodiment of the present invention. -
FIG. 4 shows current-voltage characteristic curves of DMOS devices of the prior art and the present invention obtained by a transmission-line pulse ESD test. -
FIGS. 5A-5L show a second embodiment of the present invention. -
FIGS. 6A-6C show a third, a fourth, and a fifth embodiments of the present invention, respectively. - The drawings as referred to throughout the description of the present invention are for illustration only, to show the interrelations between the regions and the process steps, but not drawn according to actual scale.
-
FIGS. 3A and 3B are schematic diagrams of aDDDMOS device 300 according to a first embodiment of the present invention from cross-section and top view, whereinFIG. 3A shows the cross-section view taken along a cross-section line CD of the top view shown inFIG. 3B . As shown in the figures, theDDDMOS device 300 includes asubstrate 31, agate 33, an N-type high voltage well 34, an N-type source 35, an N-type drain 36, a P-type body region 37, a P-type body electrode 38, and a P-type floating region 38 a. Thesubstrate 31 for example is P-type but not limited to P-type, and thesubstrate 31 has anupper surface 311. Thegate 33 is formed on theupper surface 311. The N-type high voltage well 34, the N-type source 35, and the N-type drain 36 are formed below theupper surface 311 in thesubstrate 31. The N-type high voltage well 34, the N-type source 35, and the N-type drain 36 are defined by lithography process steps and formed by ion implantation process steps, wherein the lithography process step defines the implantation region by a photoresist mask together with a self-alignment effect provided by all or part of thegate 33, and the ion implantation process step implants N-type impurities to the defined region in the form of accelerated ions. The P-type body region 37, the P-type body electrode 38, and the P-type floating region 38 a are formed below theupper surface 311 and defined by lithography process steps and formed by ion implantation process steps, wherein the lithography process step defines the implantation region by a photoresist mask together with a self-alignment effect provided by all or part of thegate 33 and thefield oxide region 12, and the ion implantation process step implants P-type impurities to the defined region in the form of accelerated ions. Thesource 35 and thedrain 36 are below thegate 33 and at different sides thereof respectively. At least part of thegate 33 is located in the high voltage well 34 from the top viewFIG. 3B , and thegate 33 has afirst side 33 a and asecond side 33 b opposite to each other in the vertical direction. Thebody region 37 is formed in the high voltage well 34 below theupper surface 311, wherein at least part of thebody region 37 is located outside thefirst side 33 a. Thesource 35 and thedrain 36 are formed below theupper surface 311 outside thegate 31. Thesource 35 is located in thebody region 37 outside thefirst side 33 a, and thedrain 36 is located outside thesecond side 33 b. Thedrain 36 and thegate 33 are separated by thehigh voltage well 34. When theDMOS device 300 turns ON, a lateral channel (not shown) is formed between thesource 35 and thedrain 36 below theupper surface 311. Thebody electrode 38 is formed in thebody region 37 below theupper surface 311 as an electrically contact of thebody region 37. - This embodiment is different from the prior art in that, in this embodiment, the
DDDMOS device 300 has the floatingregion 38 a formed in thebody region 37 below theupper surface 311, wherein the floatingregion 38 a is electrically floating and electrically isolated from thesource 35 and thegate 33, i.e., the floatingregion 38 a has an independent voltage level which is not directly related to the voltage levels of thesource 35 and thegate 33. - The arrangement of the floating
region 38 a in this embodiment of the present invention is advantageous in that, first, the floatingregion 38 a and thebody electrode 38 may be (but not limited to) formed in thesubstrate 31 by a same process step without any additional mask or process step, such that the manufacturing cost can be reduced; second, more importantly, when theDDDMOS device 300 electrically contacts a high voltage ESD, because of the floatingregion 38 a, the channel of theDDDMOS device 300 can be fully turned ON to release the high voltage ESD before the high voltage ESD damages theDDDMOS device 300, such that the ESD effect is mitigated. -
FIG. 4 shows current-voltage characteristic curves obtained by a transmission-line pulse ESD test of the present invention and a prior art DMOS device. Referring toFIG. 4 , the prior art DMOS device has a trigger voltage of about 40V, which is higher than the trigger voltage of the DMOS device of the present invention (about 30V); this means that the DMOS device of the present invention turns ON earlier when an electrostatic voltage is applied, so the ESD effect is mitigated in the present invention as compared with the prior art. Besides, the ESD breakdown voltage, i.e., the voltage causing an obvious leakage current, of the present invention is higher than the prior art DMOS device. Therefore, the DMOS device of the present invention can sustain a higher electrostatic voltage and a higher electrostatic current. The above shows that the present invention is advantageous over the prior art. - Please refer to
FIGS. 5A-5L for a second embodiment according to the present invention, whereinFIGS. 5A-5L are schematic diagrams showing a manufacturing method of theDDDMOS device 300 according to the present invention. To be illustrative, top views and cross-section views are shown at left and right sides in contrast with each other. As shown inFIGS. 5A and 5B , thesubstrate 31 with theupper surface 311 is provided, which has for example but not limited to the P-type conductivity. As shown in the figure, in the P-type substrate 31 below theupper surface 311, the N-typehigh voltage well 34 is formed. - Next, as shown in
FIGS. 5C and 5D , thegate 33 is formed on theupper surface 311. From the top viewFIG. 5C , thegate 33 is located in the high voltage well 34, wherein thegate 33 has thefirst side 33 a and thesecond side 33 b opposite to each other in the vertical direction. - Next, as shown in
FIGS. 5E and 5F , thebody region 37 is defined by a lithography process step with for example but not limited to aphotoresist mask 37 a together with a self-alignment effect provided by part of thegate 33, and an ion implantation process step implants P-type impurities to the defined region in the N-type high voltage well 34 in the form of accelerated ions as indicated by the dashed arrow lines. Part of the P-type impurities will diffuse to thegate 33 below, to form a P-type region of the channel. Therefore, part of thebody region 37 is below thegate 33 and other part of thebody region 37 is outside thefirst side 33 a. - Next, as shown in
FIGS. 5G and 5H , by the same or different process steps, the N-type source 35 and drain 36 are defined by a lithography process step with for example but not limited to aphotoresist mask 36 a together with a self-alignment effect provided by part of thegate 33, and an ion implantation process step implants N-type impurities to the defined regions in the P-type body region 37 and the N-type high voltage well 34 respectively, in the form of accelerated ions as indicated by the dashed arrow lines. Thesource 35 is located in thebody region 37 outside thefirst side 33 a, and thedrain 36 is located outside thesecond side 33 b, and thedrain 36 and thegate 33 are separated by the high voltage well 34 (so thesource 35 and thedrain 36 are further separated). When theDMOS device 300 turns ON, a lateral channel (not shown) is formed between thesource 35 and thedrain 36 below theupper surface 311. - Next, as shown in
FIGS. 5I and 5J , the P-type body electrode 38 and the P-type floating region 38 a are formed by the same or different process steps in thebody region 37 below theupper surface 311, wherein the floatingregion 38 a is electrically floating and electrically isolated from thesource 35 and thegate 33. (FIG. 5J is a cross-section view taken along a cross-section line EF in the top viewFIG. 5I , soFIG. 5J does not show the floatingregion 38 a.) - Note that the P-
type body electrode 38 and the P-type floating region 38 a are formed by, for example but not limited to, the same ion implantation process step. In this embodiment, as shown inFIG. 5I , the floatingregion 38 a is formed, for example but not limited to, outside thesource 35 in the vertical direction and in contact with thesource 35. - Next,
FIGS. 5K and 5L show a top view and a cross-section view taken along a cross-section line GH in the top view of theDDDMOS device 300, respectively. In theDDDMOS device 300, aconductive layer 39 which connects thesource 35 and thebody region 38 is formed, such that thesource 35 and thebody region 37 are electrically connected. Certainly, this arrangement is only one of the embodiments, and the present invention is not limited to this arrangement. For example, thesource 35 and the body electrode may connect to different conductive layers respectively, such that thesource 35 and thebody region 37 are not electrically connected. The latter arrangement also belongs to the scope of the present invention. Note that theconductive layer 39 does not connect to the floatingregion 38 a, such that the voltage level of the floatingregion 38 a is unaffected and remains floating. -
FIGS. 6A-6C show a third, fourth, and a fifth embodiments of the present invention, respectively, to show that the floating region of the present invention may be embodied in various different forms. Referring toFIG. 6A , this embodiment is different from the first embodiment in that, a floatingregion 38 b of aDDDMOS device 400 is located outside thesource 35 in thebody region 37 in the vertical direction from top viewFIG. 6A , and is not in contact to thesource 35.FIG. 6B shows the fourth embodiment of the present invention. This embodiment is different from the first embodiment in that, a floatingregion 38 c of aDDDMOS device 500 separates thesource 35 to afirst source 35 a and asecond source 35 b in the vertical direction as shown by the top viewFIG. 6B , and the floatingregion 38 c and thesource 35 are separated by part of thebody region 37. Although thefirst source 35 a and thesecond source 35 b are separated, they may be electrically connected by one or more conductive layers (not shown) electrically connecting the separatedconductive layers 39. -
FIG. 6C shows the fifth embodiment of the present invention. This embodiment shows that the present invention maybe applied in anLDMOS device 600. As shown in the figure, theLDMOS device 600 includes: asubstrate 61, afield oxide region 62, agate 63, an N-type high voltage well 64, an N-type source 65, an N-type drain 66, a P-type body region 67, a P-type body electrode 68, and a P-type floating region 68 a. Thesubstrate 61 is for example but not limited to P-type. The N-type high voltage well 64, the N-type source 65, and the N-type drain 66 are formed by lithography process steps and ion implantation process steps, wherein the lithography process step defines the implantation region by a photoresist mask together with a self-alignment effect provided by all or part of thegate 63 with thefield oxide region 62, and the ion implantation process step implants N-type impurities to the defined region in the form of accelerated ions. The P-type body region 67, the P-type body electrode 68, and the P-type floating region 68 a are formed by lithography process steps and ion implantation process steps, wherein the lithography process step defines the implantation region by a photoresist mask together with a self-alignment effect provided by all or part of thegate 63 with thefield oxide region 62, and the ion implantation process step implants P-type impurities to the defined region in the form of accelerated ions. Thesource 65 and thedrain 66 are below thegate 63 and at different sides thereof respectively. Thesource 65 and thegate 63 are separated by thehigh voltage well 64. Thesource 65, thebody electrode 68, and the floatingregion 68 a are formed in thebody region 67. - The present invention has been described in considerable detail with reference to certain preferred embodiments thereof. It should be understood that the description is for illustrative purpose, not for limiting the scope of the present invention. Those skilled in this art can readily conceive variations and modifications within the spirit of the present invention. For example, other process steps or structures which do not affect the primary characteristic of the device, such as a threshold voltage adjustment region, etc., can be added; for another example, the lithography step described in the above can be replaced by electron beam lithography, X-ray lithography, etc.; for another example, in all the aforementioned embodiments, the conductive type of each region is not limited to P-type, such as the body region, the body electrode, and the floating region, etc. (or N-type, such as the high voltage well, the source, and the drain, etc.), but it may be changed to N-type (or P-type) with conductive type and/or impurity concentration modifications in other regions; for another example, the present invention is not limited to be applied in the DDDMOS device or the LDMOS device, but may be applied in other high voltage devices. In view of the foregoing, the spirit of the present invention should cover all such and other modifications and variations, which should be interpreted to fall within the scope of the following claims and their equivalents. An embodiment or a claim of the present invention does not need to achieve all the objectives or advantages of the present invention. The title and abstract are provided for assisting searches but not for limiting the scope of the present invention.
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US10121779B2 (en) * | 2016-12-13 | 2018-11-06 | Globalfoundries Singapore Pte. Ltd. | Integrated circuits with high current capacity and methods for producing the same |
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