US20140165025A1 - Computing device and method for checking signal transmission line - Google Patents
Computing device and method for checking signal transmission line Download PDFInfo
- Publication number
- US20140165025A1 US20140165025A1 US13/873,157 US201313873157A US2014165025A1 US 20140165025 A1 US20140165025 A1 US 20140165025A1 US 201313873157 A US201313873157 A US 201313873157A US 2014165025 A1 US2014165025 A1 US 2014165025A1
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- United States
- Prior art keywords
- signal transmission
- transmission lines
- transmission line
- checked
- displayed
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- G06F17/5081—
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
Definitions
- Embodiments of the present disclosure relates to circuit simulation systems and methods, and particularly, to a computing device and a method for checking whether signals transmission lines of a group are laid out in the same layer in a printed circuit board (PCB) layout.
- PCB printed circuit board
- FIG. 1 is a block diagram of one embodiment of a computing device executing a signal transmission line check system.
- FIG. 2 is a block diagram of one embodiment of function modules of the signal transmission line check system.
- FIGS. 3-4 are schematic views to show user interfaces provided by the signal transmission line check system of FIG. 2 .
- FIG. 5 is a flowchart of one embodiment of a signal transmission line check method.
- FIG. 1 shows a block diagram of one embodiment of a computing device 100 .
- the computing device 100 includes a processor 20 , a storage unit 30 , and a display unit 40 .
- the storage unit 30 may be a computer, a smart media card, a secure digital card, or a flash card.
- the storage unit 30 stores computerized codes of a signal transmission line check system 10 and at least one PCB layout 50 .
- the signal transmission line check system 10 includes various software components and/or a set of instructions, which may be implemented by the processor 20 to automatically check whether all signal transmission line of a group are laid out in a same layer and automatically mark the signal transmission lines that do not satisfy design standards.
- FIG. 2 shows a block diagram of the function modules of the signal transmission line check system 10 in the computing device 100 of FIG. 1 .
- the signal transmission line check system 10 includes a determining module 13 , a check module 14 , and a marking module 15 .
- the determining module 13 includes various software components and/or set of instructions, which may be implemented by the processor 20 to determine a to-be-checked signal transmission line group in a PCB layout displayed on the display unit 40 .
- the check module 14 includes various software components and/or a set of instructions, which may be implemented by the processor 20 to check whether all signal transmission lines of the to-be-checked signal transmission line group are laid out in a same layer of the displayed PCB layout according to an input serial number of a chipset and layer properties of the to-be-checked signal transmission lines, and determine the signal transmission lines which do not satisfy design standards when not all of the to-be-checked signal transmission lines are laid out in a same layer.
- the marking module 15 includes various software components and/or a set of instructions, which may be implemented by the processor 20 to mark the signal transmission lines that do not satisfy design standards in the displayed PCB layout.
- a user interface provided by the signal line transmission check system 10 includes a signal transmission line group selection button, a chipset number input box, and a number of display windows, for example, a name display window, and an information display window to show information of signal transmission lines which do not satisfy design standards.
- a search interface for searching to-be-checked signal transmission line groups are displayed.
- the chipset number input box is for users to input a serial number of a transmitter connected to to-be-checked signal transmission lines.
- the name display window first display names of to-be-checked signal transmission line groups. After finishing check, the name display window displays names of the signal transmission lines that do not satisfy design standards.
- the search interface includes a group name input box, a search result display window, and a selection result display window.
- the signal transmission line check system 10 searches signal transmission line groups according to the input group names, and display the found signal transmission line groups in the search result display window.
- the selected signal transmission line group is displayed in the selection result display window and can be taken as a to-be-checked signal transmission line group.
- FIG. 5 is a flowchart of one embodiment of a signal transmission line check method. Depending on the embodiment, additional blocks may be added, others removed, and the ordering of the blocks may be changed.
- the determining module 13 determines a to-be-checked signal transmission line group in a PCB layout displayed on the display unit 40 .
- the check module 13 checks whether all signal transmission lines of the to-be-checked signal transmission line group are laid out in a same layer of the displayed PCB layout according to an input serial number of a chipset and layer properties of the to-be-checked signal transmission lines, and determines the signal transmission lines which do not satisfy design standards when not all of the to-be-checked signal transmission lines are laid out in a same layer.
- the marking module 15 marks the signal transmission lines that do not satisfy design standards in the displayed PCB layout.
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Abstract
Description
- 1. Technical Field
- Embodiments of the present disclosure relates to circuit simulation systems and methods, and particularly, to a computing device and a method for checking whether signals transmission lines of a group are laid out in the same layer in a printed circuit board (PCB) layout.
- 2. Description of Related Art
- In designing a PCB layout, signal transmission lines of a group should be laid out in a same layer. Generally, checking whether all signal transmission lines of a group are laid out in a same layer of a displayed PCB layout is often visually done by a technician, which is time-consuming and error-prone.
- The components of the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout several views.
-
FIG. 1 is a block diagram of one embodiment of a computing device executing a signal transmission line check system. -
FIG. 2 is a block diagram of one embodiment of function modules of the signal transmission line check system. -
FIGS. 3-4 are schematic views to show user interfaces provided by the signal transmission line check system ofFIG. 2 . -
FIG. 5 is a flowchart of one embodiment of a signal transmission line check method. - The disclosure, including the accompanying drawings in which like references indicate similar elements, is illustrated by way of examples and not by way of limitation. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one.
-
FIG. 1 shows a block diagram of one embodiment of acomputing device 100. Thecomputing device 100 includes aprocessor 20, astorage unit 30, and adisplay unit 40. Thestorage unit 30 may be a computer, a smart media card, a secure digital card, or a flash card. Thestorage unit 30 stores computerized codes of a signal transmissionline check system 10 and at least onePCB layout 50. The signal transmissionline check system 10 includes various software components and/or a set of instructions, which may be implemented by theprocessor 20 to automatically check whether all signal transmission line of a group are laid out in a same layer and automatically mark the signal transmission lines that do not satisfy design standards. -
FIG. 2 shows a block diagram of the function modules of the signal transmissionline check system 10 in thecomputing device 100 ofFIG. 1 . In one embodiment, the signal transmissionline check system 10 includes a determining module 13, acheck module 14, and amarking module 15. - The determining module 13 includes various software components and/or set of instructions, which may be implemented by the
processor 20 to determine a to-be-checked signal transmission line group in a PCB layout displayed on thedisplay unit 40. - The
check module 14 includes various software components and/or a set of instructions, which may be implemented by theprocessor 20 to check whether all signal transmission lines of the to-be-checked signal transmission line group are laid out in a same layer of the displayed PCB layout according to an input serial number of a chipset and layer properties of the to-be-checked signal transmission lines, and determine the signal transmission lines which do not satisfy design standards when not all of the to-be-checked signal transmission lines are laid out in a same layer. - The
marking module 15 includes various software components and/or a set of instructions, which may be implemented by theprocessor 20 to mark the signal transmission lines that do not satisfy design standards in the displayed PCB layout. - Referring to
FIG. 3 , a user interface provided by the signal linetransmission check system 10 includes a signal transmission line group selection button, a chipset number input box, and a number of display windows, for example, a name display window, and an information display window to show information of signal transmission lines which do not satisfy design standards. When the signal transmission line group selection button is clicked, a search interface (seeFIG. 4 ) for searching to-be-checked signal transmission line groups are displayed. The chipset number input box is for users to input a serial number of a transmitter connected to to-be-checked signal transmission lines. The name display window first display names of to-be-checked signal transmission line groups. After finishing check, the name display window displays names of the signal transmission lines that do not satisfy design standards. When one signal transmission line name is clicked, information of the signal transmission line is displayed in the information display window. The search interface includes a group name input box, a search result display window, and a selection result display window. The signal transmissionline check system 10 searches signal transmission line groups according to the input group names, and display the found signal transmission line groups in the search result display window. When one signal transmission line group in the search result display window is clicked, the selected signal transmission line group is displayed in the selection result display window and can be taken as a to-be-checked signal transmission line group. -
FIG. 5 is a flowchart of one embodiment of a signal transmission line check method. Depending on the embodiment, additional blocks may be added, others removed, and the ordering of the blocks may be changed. - In block S501, the determining module 13 determines a to-be-checked signal transmission line group in a PCB layout displayed on the
display unit 40. - In block S502, the check module 13 checks whether all signal transmission lines of the to-be-checked signal transmission line group are laid out in a same layer of the displayed PCB layout according to an input serial number of a chipset and layer properties of the to-be-checked signal transmission lines, and determines the signal transmission lines which do not satisfy design standards when not all of the to-be-checked signal transmission lines are laid out in a same layer.
- In block S503, the
marking module 15 marks the signal transmission lines that do not satisfy design standards in the displayed PCB layout. - Although certain inventive embodiments of the present disclosure have been specifically described, the present disclosure is not to be construed as being limited thereto. Various changes or modifications may be made to the present disclosure without departing from the scope and spirit of the present disclosure.
Claims (4)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210525590.0A CN103870610A (en) | 2012-12-10 | 2012-12-10 | System and method for inspecting signal wires |
CN2012105255900 | 2012-12-10 |
Publications (2)
Publication Number | Publication Date |
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US20140165025A1 true US20140165025A1 (en) | 2014-06-12 |
US8769472B1 US8769472B1 (en) | 2014-07-01 |
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Application Number | Title | Priority Date | Filing Date |
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US13/873,157 Expired - Fee Related US8769472B1 (en) | 2012-12-10 | 2013-04-29 | Computing device and method for checking signal transmission line |
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US (1) | US8769472B1 (en) |
CN (1) | CN103870610A (en) |
TW (1) | TW201426366A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104732018A (en) * | 2015-03-06 | 2015-06-24 | 小米科技有限责任公司 | PCB wiring treatment method and device |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN110398681B (en) * | 2019-07-26 | 2021-08-31 | 苏州浪潮智能科技有限公司 | Double-strip-line inspection method and related device |
TWI782707B (en) * | 2021-09-15 | 2022-11-01 | 英業達股份有限公司 | Signal path searching method, electronic device and non-transitory computer readable medium |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4341152B2 (en) * | 2000-06-02 | 2009-10-07 | ソニー株式会社 | Printed circuit board wiring structure check system |
US20080109773A1 (en) * | 2006-11-02 | 2008-05-08 | Daniel Douriet | Analyzing Impedance Discontinuities In A Printed Circuit Board |
JP5120447B2 (en) * | 2008-03-31 | 2013-01-16 | 富士通株式会社 | WIRING BOARD DESIGN SUPPORT DEVICE, WIRING BOARD DESIGN SUPPORT METHOD, WIRING BOARD DESIGN SUPPORT PROGRAM, AND COMPUTER-READABLE RECORDING MEDIUM CONTAINING THE PROGRAM |
JP5477244B2 (en) * | 2010-09-29 | 2014-04-23 | 富士通株式会社 | Printed circuit board design support apparatus, method and program |
CN102592000B (en) * | 2011-01-13 | 2016-05-25 | 国网山东省电力公司鄄城县供电公司 | Circuit board wiring detection system |
JP5884424B2 (en) * | 2011-11-15 | 2016-03-15 | 富士通株式会社 | Wiring design support device, wiring design support program, and wiring design support method |
-
2012
- 2012-12-10 CN CN201210525590.0A patent/CN103870610A/en active Pending
- 2012-12-13 TW TW101147129A patent/TW201426366A/en unknown
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104732018A (en) * | 2015-03-06 | 2015-06-24 | 小米科技有限责任公司 | PCB wiring treatment method and device |
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Publication number | Publication date |
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US8769472B1 (en) | 2014-07-01 |
TW201426366A (en) | 2014-07-01 |
CN103870610A (en) | 2014-06-18 |
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Owner name: HON HAI PRECISION INDUSTRY CO., LTD., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LI, YAN-JUN;HUANG, YA-LING;PAI, CHIA-NAN;AND OTHERS;SIGNING DATES FROM 20130409 TO 20130422;REEL/FRAME:030311/0553 Owner name: HONG FU JIN PRECISION INDUSTRY (SHENZHEN) CO., LTD Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LI, YAN-JUN;HUANG, YA-LING;PAI, CHIA-NAN;AND OTHERS;SIGNING DATES FROM 20130409 TO 20130422;REEL/FRAME:030311/0553 |
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