US20140091339A1 - Semiconductor device, display, and electronic apparatus - Google Patents
Semiconductor device, display, and electronic apparatus Download PDFInfo
- Publication number
- US20140091339A1 US20140091339A1 US14/099,895 US201314099895A US2014091339A1 US 20140091339 A1 US20140091339 A1 US 20140091339A1 US 201314099895 A US201314099895 A US 201314099895A US 2014091339 A1 US2014091339 A1 US 2014091339A1
- Authority
- US
- United States
- Prior art keywords
- inner edges
- cavity
- semiconductor device
- wall structures
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000011344 liquid material Substances 0.000 claims abstract description 13
- 239000007788 liquid Substances 0.000 claims abstract description 7
- 239000004020 conductor Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 description 23
- 239000000463 material Substances 0.000 description 14
- 239000002184 metal Substances 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000001035 drying Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 239000006185 dispersion Substances 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- 239000000654 additive Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000002209 hydrophobic effect Effects 0.000 description 1
- 238000007641 inkjet printing Methods 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 230000005499 meniscus Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000004094 surface-active agent Substances 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/17—Passive-matrix OLED displays
- H10K59/173—Passive-matrix OLED displays comprising banks or shadow masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/10—Deposition of organic active material
- H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
- H10K71/13—Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing
- H10K71/135—Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing using ink-jet printing
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/10—Deposition of organic active material
- H10K71/191—Deposition of organic active material characterised by provisions for the orientation or alignment of the layer to be deposited
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/60—Forming conductive regions or layers, e.g. electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
- H10K77/10—Substrates, e.g. flexible substrates
- H10K77/111—Flexible substrates
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/549—Organic PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the invention relates to a method of manufacturing a semiconductor device.
- the invention further relates to a semiconductor device, a display and an electronic apparatus comprising the same.
- a method for manufacturing a semiconductor device is known from WO2006/051457 A1.
- the known method comprises arranging a series of wall structures on a surface of a suitable substrate provided with portions of a patterned metal layer.
- the wall structures which may be manufactured from a resist material define a series of barriers and cavities which serve to guide subsequently printed materials.
- a suitable liquid material conceived to form a semiconductor region may be provided in these cavities.
- respective shapes of the cavities are constructed to maintain registration between layers of a device structure.
- the known method provides for self-aligned layers of the semiconductor device.
- a method for manufacturing a semiconductor device.
- the method includes providing, on a substrate, a layer of a conducting material in a pattern comprising isolated elements having a first set of inner edges.
- the method includes the further step of providing on the substrate a series of wall structures for forming one or more cavities there between.
- the wall structures have a second set of inner edges cooperating with the first set of inner edges.
- the second set of inner edges is positioned outside the first set of inner edges with respect to a center of the cavity formed by a first inner edges and the second inner edges by a pre-defined distance.
- the method disclosed herein includes the further step of depositing a liquid material in the cavities.
- respective edges of the wall structures are positioned outside the edges of the isolated elements by a distance of 1 to 20 micrometers, more specifically by a distance of 1 to 10 micrometers, yet more particularly by a distance of 1 to 5 micrometers, and even more particularly by a distance of 1-3 micrometers.
- the term “positioned outside” is defined in a direction outwardly from a center of a cavity. This feature will be discussed in further detail with reference to FIGS. 1 a - 1 d.
- a semiconductor device is also described wherein the device includes a substrate having a layer of conducting material comprising a set of isolated elements having a first set of inner edges.
- the isolated elements also include wall structures having a second set of inner edges cooperating with the first set of inner edges.
- the second set of inner edges is positioned outside the first set of inner edges with respect to a cavity formed by the first inner edges and the second inner edges by a pre-defined distance.
- the invention further relates to a display and an electronic apparatus including the above-described semiconductor device.
- FIGS. 1 a- 1 d provide schematic views of respective exemplary embodiments of a lateral displacement between edges of the wall structures and edges of the isolated elements;
- FIG. 2 schematically presents an embodiment of the method according to the invention
- FIG. 3 schematically presents exemplary embodiments of wall structures
- FIG. 4 schematically presents an embodiment of methods for manufacturing curved wall structures
- FIG. 5 schematically presents an embodiment of a method for patterning wall structures using photolithography
- FIG. 6 schematically presents a top view of an embodiment shown in FIG. 5 demonstrating a further exemplary embodiment of the method according to the invention.
- FIGS. 1 a - 1 d provide schematic views of respective exemplary embodiments of a semiconductor device, depicting a lateral displacement between edges of the wall structures and edges of the isolated elements.
- the semiconductor structure 10 a comprises a substrate 1 on top of which a metal layer may be arranged, which is subsequently patterned into a suitable plurality of laterally isolated elements 2 a, 2 b. For simplicity reasons only two isolated elements are shown.
- a set of wall structures 3 a, 3 b are arranged so that a cavity is formed there between.
- the inner edges of the wall structures are outwardly displaced in a lateral direction L, with respect to the inner edges of the isolated elements with which they cooperate, by a pre-determined distance x1, x2.
- the predetermined distance is selected in a range of 1 to 20 micrometers, and more particularly in a range of 1 to 10 micrometers, yet more particularly in a range of 1 to 5 micrometers, and even more particularly in a range of 1-3 micrometers. It will be appreciated that the distance x1 may or may not be equal to the distance x2.
- the wall structures may be suitably formed, for example, by means of a lithography process by exposing a suitable resist from the top through a suitable photo-mask.
- the resulting cavities between the thus formed wall structures are filled with a suitable liquid material 4 .
- a suitable liquid material 4 Either a semiconductor material, or a precursor material is selected for the liquid material.
- the wall structures 3 a, 3 b are joined together by respective regions 3 d, 3 e at a periphery of the semiconductor device 10 a thereby forming a closed structure.
- the embodiment shown in FIG. la relates to a configuration wherein a single channel semiconductor device, for example, a TFT is provided.
- FIG. 1 b presents a schematic view of an embodiment of a semiconductor device 10 b, according to illustrative embodiments, wherein a plurality of interconnected cavities are provided.
- the upper view relates to a top view on the semiconductor device 10 b while the lower view relates to a cross-section taken along the line B-B′.
- a substrate 1 includes a set of elements 2 a, 2 b, 2 c, 2 d, and 2 e, isolated in a lateral direction L, and a set of wall structures 3 a, 3 b, 3 c, 3 d, and 3 e cooperating with the set of elements 2 a, 2 b, 2 c, 2 d, and 2 e so that inner edges of the wall structures 3 a, 3 b, 3 c, 3 d, and 3 e are laterally outwardly displaced with respect to the inner edges of the elements 2 a, 2 b, 2 c, 2 d, and 2 e.
- the individual cavities 4 a, 4 b, 4 c, and 4 d are interconnected by regions 4 e, 4 f, and 4 g shown in the top view.
- FIG. 1 c schematically presents a further embodiment of the semiconductor device 10 c according to illustrative embodiments wherein a pitch of the isolated elements is not equal to a pitch of the wall structures.
- the upper view relates to a top view on the semiconductor device 10 c while the lower view relates to a cross-section taken along a line C-C′.
- the substrate 1 is provided with a set of isolated elements 2 a, 2 b, 2 c whereby a cavity is defined by the wall structures 3 a, 3 b, said cavity being larger, for example being about twice as large as a distance between adjacent elements 2 a, 2 b.
- the pitch P 2 of the wall structures is, therefore, not equal to the pitch P 1 of the elements 2 a, 2 b, 2 c.
- respective inner edges of the wall structures 3 a, 3 b cooperating with inner edges of the elements 2 a, 2 c are outwardly displaced in a lateral direction L from the inner edges of the elements 2 a, 2 c.
- the cavity is then filled by the semiconductor material 4 a, 4 b.
- regions 4 a, 4 b of the semiconductor are joined together by a bridge 4 c, shown in the upper view.
- FIG. 1 d A still further embodiment of a semiconductor device 10 d is schematically depicted in FIG. 1 d.
- the upper view relates to a top view on the semiconductor structure while the lower view relates to a cross-section taken along the line D-D′.
- This exemplary embodiment like embodiments shown in FIGS. 1 b and 1 c, relates to a multiple channel semiconductor structure, for example a TFT.
- the channels 4 a and 4 b are interconnected by a bridge 4 c.
- a dimension of the elements 2 b in the lateral direction L is different, for example larger than respective dimensions of the elements 2 a and 2 c.
- the other features of the structure 10 d are substantially the same as discussed with reference to FIG. 1 b.
- FIG. 2 schematically presents an embodiment of the method according to exemplary embodiments.
- a suitable metal layer is first deposited on a substrate.
- the metal layer is patterned for obtaining a set of isolated elements.
- isolated elements relates to a configuration wherein individual elements may be identified along a lateral direction on the substrate, as is schematically shown in any of the FIGS. 1 a - 1 d.
- the elements are interconnected at a peripheral region by a lateral bridge thereby at least partially confining respective cavities.
- the wall structures are patterned adjacent the laterally isolated elements of a metal layer.
- the metal layer relates, for example, to a source-drain layer of a semiconductor device, in particular, of a TFT device.
- the wall structures comprise a second set of edges cooperating with a first set of edges of the isolated elements, the second set of edges are laterally outwardly displaced with respect to the first set of edges. Accordingly, a layer of a conducting material provided on a substrate in a pattern and comprising isolated elements having a first set of inner edges is created which is arranged to cooperate with a series of wall structures arranged for forming one or more cavities there between.
- the wall structures have a second set of inner edges cooperating with the first set of inner edges, wherein the second set of inner edges is positioned outside the first set of inner edges with respect to a center of the cavity formed by first inner edges and second inner edges by a pre-defined distance. Accordingly, the first inner edges are preceding the second inner edges with respect to a cavity boundary.
- the wall structures are provided either with straight or with curved side walls. These embodiments are discussed in further detail with reference to FIG. 3 .
- surfaces of the wall structures and/or surfaces of the underlying layers conceived to come into contact with a liquid material which at least partially fills the thus provided cavities are treated for modifying wettability properties of such surfaces.
- wettability properties regarding water or a solvent are modified.
- the surfaces of the wall structures, like surfaces facing the cavity and/or top surfaces are hydrophobic and/or solvophobic.
- the cavities are filled with a suitable liquid material, which relate to a semiconductor or a precursor material.
- a suitable liquid material which relate to a semiconductor or a precursor material.
- this step is followed by deposition of one or several dielectric, semiconducting or metal layers.
- the semiconductor layer comprises a soluble or dispersible organic or inorganic material.
- additives are provided such as, for example, binders and/or surfactants.
- FIG. 3 schematically presents exemplary embodiments 30 of wall structures. For simplicity reasons, isolated elements of a metal layer shown in FIGS. 1 a - 1 d are not depicted.
- a substrate 31 is provided with wall structures 30 a, 30 b having side walls inclined towards the center of the cavity. It is found that, for a constant contact angle .theta. an inclination angle .alpha. may influence the height of a meniscus of the liquid material 34 deposited in the cavity. The angle .alpha. may have a positive influence on relative relation between a height of the liquid h1+h2 near the wall structure and a height of the liquid h2 in the center of the cavity. It is advantageous when the height h1 is minimized.
- h1 schematically indicates a difference between the liquid height at the edge and at the center of the cavity.
- a value of h2 increases with respect to a value of h2 for side walls 30 a, 30 b.
- a value of h2 still further increases and h1 tends to zero.
- FIG. 4 presents, in a schematic way, embodiments of a method for manufacturing curved wall structures.
- a substantially rectangular side wall 43 for example comprising a thermoplastic or wax material arranged on a substrate 41 , may be heated yielding a structure 43 a with a convex wall profile.
- a bulk wall structure provided on a substrate 41 may be isotropically etched to yield two wall structures 43 b, 43 b ′ having a concave wall profile. Subsequently, the mask used for etching process is stripped leaving the concave wall structures 43 b, 43 b ′ on the substrate 41 . It will be appreciated that for simplicity reasons the isolated elements discussed with reference to FIGS. 1 a - 1 d are not shown.
- FIG. 5 schematically presents an embodiment of a method for patterning wall structures using photolithography.
- view 50 a shows a substrate 51 being lithographically processed from a rear surface R using a beam of radiation 55 a emanating from a suitable source 55 of a lithographic apparatus (not shown).
- the isolated elements 52 a, 52 b of the metal layer are used as mask features for patterning suitable wall structures in a photosensitive material 56 , which is arranged as a bulk layer atop the isolated elements 52 a, 52 b.
- desired wall profiles are obtained, see view 50 b indicating a post-exposure condition.
- FIG. 6 schematically presents a top view of an embodiment shown in FIG. 5 demonstrating a further embodiment of the method generally disclosed herein.
- a substrate 61 is shown (corresponding to the substrate 51 shown in FIG. 5 ), whereon a cavity 66 is formed by a layer comprising isolated elements 62 a, 62 b cooperating with wall structures 63 , 63 ′.
- areas 66 a, 66 b of the cavity are kept minimal to avoid leakage of the fluid there through.
- a layer from which the wall structures are formed may comprise superfluous regions 63 a, 63 b. In order to remove these regions, the layer is frontally exposed during a suitable lithographic step.
- View 60 b schematically shows a photomask pattern 64 overlaid on the wall layer, leaving superfluous area 63 a, 63 b uncovered.
- View 60 b shows results of a frontal lithography step through the photomask pattern 64 wherein electrode areas 64 a, 64 b are revealed.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Thin Film Transistor (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
A semiconductor device having a substrate is disclosed. The substrate includes a first set of inner edges and a second set of inner edges cooperating with the first set of inner edges. The second set of inner edges is positioned outside the first set of inner edges with respect to a cavity formed by the first inner edges and the second inner edges by a pre-defined distance. The substrate further includes a layer within the cavity, including a dried liquid material formed from a liquid deposited within the cavity. The layer within the cavity is formed between the respective first inner edges and the second inner edges. The semiconductor device may be implemented in a display of an electronic device.
Description
- This Application is a divisional of U.S. patent application Ser. No. 12/694,969, filed on Jan. 27, 2010, the entirety of which is incorporated by reference herein.
- The invention relates to a method of manufacturing a semiconductor device. The invention further relates to a semiconductor device, a display and an electronic apparatus comprising the same.
- A method for manufacturing a semiconductor device is known from WO2006/051457 A1. The known method comprises arranging a series of wall structures on a surface of a suitable substrate provided with portions of a patterned metal layer. The wall structures, which may be manufactured from a resist material define a series of barriers and cavities which serve to guide subsequently printed materials. For example, a suitable liquid material conceived to form a semiconductor region may be provided in these cavities. In the known method respective shapes of the cavities are constructed to maintain registration between layers of a device structure. In particular, the known method provides for self-aligned layers of the semiconductor device.
- It is a disadvantage of the known method that surface inhomogeneities or precipitations from a suitable solution or dispersion on the substrate can cause the liquid-solid contact line of a drying fluid drop to become pinned, i.e. to become fixed at a certain position on the substrate. In this case, relatively faster evaporation may result in material transport to the drop perimeter. This may manifest itself in a ring-like deposit of a solute after complete drying of a solution or dispersion. This effect may be particularly pronounced when a semiconductor area is defined by solution deposition on pre-patterned surfaces, e.g. inkjet printing of a semiconductor solution into well-like surface features.
- In view of the above, a method is described herein for manufacturing a semiconductor device. The method includes providing, on a substrate, a layer of a conducting material in a pattern comprising isolated elements having a first set of inner edges. The method includes the further step of providing on the substrate a series of wall structures for forming one or more cavities there between. The wall structures have a second set of inner edges cooperating with the first set of inner edges. Furthermore, the second set of inner edges is positioned outside the first set of inner edges with respect to a center of the cavity formed by a first inner edges and the second inner edges by a pre-defined distance. The method disclosed herein includes the further step of depositing a liquid material in the cavities.
- Laterally shifting the features of the wall structures with respect to the features of the isolated elements, like respective edges of the isolated elements, provides an advantageous geometry for drying of a liquid material. It is found that when respective edges of the wall structures define a slightly broader cavity than would have been defined by the edges of the isolated materials a substantially homogeneous semiconductor layer is provided. Therefore, in particular embodiments, respective edges of the wall structure are positioned outside the edges of the isolated elements by a distance of 1 to 20 micrometers, more specifically by a distance of 1 to 10 micrometers, yet more particularly by a distance of 1 to 5 micrometers, and even more particularly by a distance of 1-3 micrometers. It will be appreciated that the term “positioned outside” is defined in a direction outwardly from a center of a cavity. This feature will be discussed in further detail with reference to
FIGS. 1 a-1 d. - A semiconductor device is also described wherein the device includes a substrate having a layer of conducting material comprising a set of isolated elements having a first set of inner edges. The isolated elements also include wall structures having a second set of inner edges cooperating with the first set of inner edges. The second set of inner edges is positioned outside the first set of inner edges with respect to a cavity formed by the first inner edges and the second inner edges by a pre-defined distance.
- The invention further relates to a display and an electronic apparatus including the above-described semiconductor device.
- These and other aspects of the invention will be further discussed with reference to drawings wherein like reference signs represent like elements. It will be appreciated that the drawings are presented for illustrative purposes only and may not limit the scope of the appended claims.
- While the claims set forth the features of the present invention with particularity, the invention, together with its objects and advantages, may be best understood from the following detailed description taken in conjunction with the accompanying drawing of which:
-
FIGS. 1 a-1 d provide schematic views of respective exemplary embodiments of a lateral displacement between edges of the wall structures and edges of the isolated elements; -
FIG. 2 schematically presents an embodiment of the method according to the invention; -
FIG. 3 schematically presents exemplary embodiments of wall structures; -
FIG. 4 schematically presents an embodiment of methods for manufacturing curved wall structures; -
FIG. 5 schematically presents an embodiment of a method for patterning wall structures using photolithography; and -
FIG. 6 schematically presents a top view of an embodiment shown inFIG. 5 demonstrating a further exemplary embodiment of the method according to the invention. -
FIGS. 1 a-1 d provide schematic views of respective exemplary embodiments of a semiconductor device, depicting a lateral displacement between edges of the wall structures and edges of the isolated elements. An embodiment, schematically shown inFIG. 1 a, depicts a top view (above) and a cross-section taken along the line A-A′ (below) of asemiconductor structure 10 a according to an exemplary embodiment. - The
semiconductor structure 10 a comprises asubstrate 1 on top of which a metal layer may be arranged, which is subsequently patterned into a suitable plurality of laterally isolatedelements wall structures - When the wall structures may be suitably formed, for example, by means of a lithography process by exposing a suitable resist from the top through a suitable photo-mask. The resulting cavities between the thus formed wall structures are filled with a suitable liquid material 4. Either a semiconductor material, or a precursor material is selected for the liquid material.
- The
wall structures respective regions semiconductor device 10 a thereby forming a closed structure. The embodiment shown in FIG. la relates to a configuration wherein a single channel semiconductor device, for example, a TFT is provided. -
FIG. 1 b presents a schematic view of an embodiment of asemiconductor device 10 b, according to illustrative embodiments, wherein a plurality of interconnected cavities are provided. Likewise, the upper view relates to a top view on thesemiconductor device 10 b while the lower view relates to a cross-section taken along the line B-B′. - A
substrate 1 includes a set ofelements wall structures elements wall structures elements individual cavities regions -
FIG. 1 c schematically presents a further embodiment of thesemiconductor device 10 c according to illustrative embodiments wherein a pitch of the isolated elements is not equal to a pitch of the wall structures. Also inFIG. 1 c the upper view relates to a top view on thesemiconductor device 10 c while the lower view relates to a cross-section taken along a line C-C′. Thesubstrate 1 is provided with a set ofisolated elements wall structures adjacent elements elements wall structures elements elements semiconductor material embodiment regions bridge 4 c, shown in the upper view. - A still further embodiment of a
semiconductor device 10 d is schematically depicted inFIG. 1 d. The upper view relates to a top view on the semiconductor structure while the lower view relates to a cross-section taken along the line D-D′. This exemplary embodiment, like embodiments shown inFIGS. 1 b and 1 c, relates to a multiple channel semiconductor structure, for example a TFT. Thechannels bridge 4 c. In this particular embodiment a dimension of theelements 2 b in the lateral direction L is different, for example larger than respective dimensions of theelements structure 10 d are substantially the same as discussed with reference toFIG. 1 b. -
FIG. 2 schematically presents an embodiment of the method according to exemplary embodiments. In accordance withmethod 20, a suitable metal layer is first deposited on a substrate. Subsequently, atstep 21 the metal layer is patterned for obtaining a set of isolated elements. It will be appreciated that the term isolated elements relates to a configuration wherein individual elements may be identified along a lateral direction on the substrate, as is schematically shown in any of theFIGS. 1 a-1 d. The elements are interconnected at a peripheral region by a lateral bridge thereby at least partially confining respective cavities. - At
step 22 the wall structures are patterned adjacent the laterally isolated elements of a metal layer. The metal layer relates, for example, to a source-drain layer of a semiconductor device, in particular, of a TFT device. The wall structures comprise a second set of edges cooperating with a first set of edges of the isolated elements, the second set of edges are laterally outwardly displaced with respect to the first set of edges. Accordingly, a layer of a conducting material provided on a substrate in a pattern and comprising isolated elements having a first set of inner edges is created which is arranged to cooperate with a series of wall structures arranged for forming one or more cavities there between. The wall structures have a second set of inner edges cooperating with the first set of inner edges, wherein the second set of inner edges is positioned outside the first set of inner edges with respect to a center of the cavity formed by first inner edges and second inner edges by a pre-defined distance. Accordingly, the first inner edges are preceding the second inner edges with respect to a cavity boundary. - It is possible to use a plurality of suitable deposition and/or patterning techniques for providing the wall structures on the substrate. For example, spin-coating followed by photolithography and/or etching may be used. The wall structures are provided either with straight or with curved side walls. These embodiments are discussed in further detail with reference to
FIG. 3 . - At
step 23 surfaces of the wall structures and/or surfaces of the underlying layers conceived to come into contact with a liquid material which at least partially fills the thus provided cavities, are treated for modifying wettability properties of such surfaces. In particular wettability properties regarding water or a solvent are modified. Preferably, the surfaces of the wall structures, like surfaces facing the cavity and/or top surfaces are hydrophobic and/or solvophobic. - At
step 24 the cavities are filled with a suitable liquid material, which relate to a semiconductor or a precursor material. Optionally this step is followed by deposition of one or several dielectric, semiconducting or metal layers. The semiconductor layer comprises a soluble or dispersible organic or inorganic material. Optionally a variety of additives are provided such as, for example, binders and/or surfactants. -
FIG. 3 schematically presentsexemplary embodiments 30 of wall structures. For simplicity reasons, isolated elements of a metal layer shown inFIGS. 1 a-1 d are not depicted. In a first exemplary embodiment asubstrate 31 is provided withwall structures liquid material 34 deposited in the cavity. The angle .alpha. may have a positive influence on relative relation between a height of the liquid h1+h2 near the wall structure and a height of the liquid h2 in the center of the cavity. It is advantageous when the height h1 is minimized. By increasing the angle .alpha., the homogeneity of a height profile of theliquid material 34 in the cavity is improved as h2 increases and h1 tends to zero. It is noted that h1 schematically indicates a difference between the liquid height at the edge and at the center of the cavity. - For example, it is found that for substantially vertically arranged side walls of the
wall structures 30 c, 30 d a value of h2 increases with respect to a value of h2 forside walls side walls -
FIG. 4 presents, in a schematic way, embodiments of a method for manufacturing curved wall structures. In amethod 40 a, a substantially rectangular side wall 43, for example comprising a thermoplastic or wax material arranged on asubstrate 41, may be heated yielding astructure 43 a with a convex wall profile. - Alternatively, in
method 40 b, a bulk wall structure provided on asubstrate 41 may be isotropically etched to yield twowall structures concave wall structures substrate 41. It will be appreciated that for simplicity reasons the isolated elements discussed with reference toFIGS. 1 a-1 d are not shown. -
FIG. 5 schematically presents an embodiment of a method for patterning wall structures using photolithography. In this embodiment, view 50 a shows asubstrate 51 being lithographically processed from a rear surface R using a beam ofradiation 55 a emanating from asuitable source 55 of a lithographic apparatus (not shown). In this arrangement theisolated elements photosensitive material 56, which is arranged as a bulk layer atop theisolated elements wall structures 56, desired wall profiles are obtained, seeview 50 b indicating a post-exposure condition. For example, by overexposing and/or overdeveloping a positive-type photoresist material it is possible to create a wall structure with edges that are set back by the distances x1 and x2 from the edges of the conducting pattern. Similarly, by adjusting the lithography and/or material parameters it is possible to create a wall structure with slanted or curved sidewalls. -
FIG. 6 schematically presents a top view of an embodiment shown inFIG. 5 demonstrating a further embodiment of the method generally disclosed herein. Inview 60 a, asubstrate 61 is shown (corresponding to thesubstrate 51 shown inFIG. 5 ), whereon acavity 66 is formed by a layer comprisingisolated elements wall structures areas superfluous regions -
View 60 b schematically shows aphotomask pattern 64 overlaid on the wall layer, leavingsuperfluous area View 60 b shows results of a frontal lithography step through thephotomask pattern 64 whereinelectrode areas - It will be appreciated that while specific exemplary embodiments of the invention have been described above, that the invention may be practiced otherwise than as described. Figures are provided for illustrative purposes and may not be used for limiting the scope of the invention as is set forth in the appended claims. In addition, isolated features discussed with reference to different figures may be combined.
Claims (9)
1. A semiconductor device comprising:
a substrate including:
a first set of inner edges and a second set of inner edges cooperating with the first set of inner edges, wherein the second set of inner edges is positioned outside the first set of inner edges with respect to a cavity formed by the first inner edges and the second inner edges by a pre-defined distance; and
a layer within the cavity, comprising a dried liquid material formed from a liquid deposited within the cavity, the layer within the cavity formed between the respective first inner edges and the second inner edges.
2. The semiconductor device according to claim 1 , wherein the first set of inner edges are defined by a set of isolated elements of a layer of electrically conducting material, and the second set of inner edges are defined by wall structures provided on the isolated elements.
3. The semiconductor device according to claim 1 , wherein the predetermined distance is in a range of 1 to 20 micrometers.
4. A display comprising:
a semiconductor device comprising:
a substrate including:
a first set of inner edges and a second set of inner edges cooperating with the first set of inner edges, wherein the second set of inner edges is positioned outside the first set of inner edges with respect to a cavity formed by the first inner edges and the second inner edges by a pre-defined distance; and
a layer within the cavity, comprising a dried liquid material formed from a liquid deposited within the cavity, the layer within the cavity formed between the respective first inner edges and the second inner edges.
5. The display according to claim 4 , wherein the first set of inner edges are defined by a set of isolated elements of a layer of electrically conducting material, and the second set of inner edges are defined by wall structures provided on the isolated elements.
6. The display according to claim 4 wherein the substrate is flexible.
7. The display according to claim 6 , wherein the display is collapsible.
8. An electronic apparatus comprising a display including a semiconductor device, the semiconductor device comprising:
a substrate including:
a first set of inner edges and a second set of inner edges cooperating with the first set of inner edges, wherein the second set of inner edges is positioned outside the first set of inner edges with respect to a cavity formed by the first inner edges and the second inner edges by a pre-defined distance; and
a layer within the cavity, comprising a dried liquid material formed from a liquid deposited within the cavity, the layer within the cavity formed between the respective first inner edges and the second inner edges.
9. The electronic apparatus according to claim 8 , wherein the first set of inner edges are defined by a set of isolated elements of a layer of electrically conducting material, and the second set of inner edges are defined by wall structures provided on the isolated elements.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/099,895 US20140091339A1 (en) | 2010-01-27 | 2013-12-06 | Semiconductor device, display, and electronic apparatus |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/694,969 US8603922B2 (en) | 2010-01-27 | 2010-01-27 | Semiconductor device, display, electronic apparatus and method of manufacturing a semiconductor device |
US14/099,895 US20140091339A1 (en) | 2010-01-27 | 2013-12-06 | Semiconductor device, display, and electronic apparatus |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/694,969 Division US8603922B2 (en) | 2010-01-27 | 2010-01-27 | Semiconductor device, display, electronic apparatus and method of manufacturing a semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
US20140091339A1 true US20140091339A1 (en) | 2014-04-03 |
Family
ID=43806798
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/694,969 Expired - Fee Related US8603922B2 (en) | 2010-01-27 | 2010-01-27 | Semiconductor device, display, electronic apparatus and method of manufacturing a semiconductor device |
US14/099,895 Abandoned US20140091339A1 (en) | 2010-01-27 | 2013-12-06 | Semiconductor device, display, and electronic apparatus |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/694,969 Expired - Fee Related US8603922B2 (en) | 2010-01-27 | 2010-01-27 | Semiconductor device, display, electronic apparatus and method of manufacturing a semiconductor device |
Country Status (6)
Country | Link |
---|---|
US (2) | US8603922B2 (en) |
EP (1) | EP2529426A1 (en) |
JP (1) | JP2013518428A (en) |
KR (1) | KR20120127621A (en) |
CN (1) | CN102725876A (en) |
WO (1) | WO2011093706A1 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI442088B (en) | 2012-02-24 | 2014-06-21 | Ind Tech Res Inst | Electrowetting display device |
KR102244018B1 (en) | 2014-11-20 | 2021-04-23 | 삼성디스플레이 주식회사 | Display device and manufacturing method thereof |
US9726634B1 (en) * | 2016-10-03 | 2017-08-08 | International Business Machines Corporation | Superhydrophobic electrode and biosensing device using the same |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8120010B2 (en) * | 2008-11-05 | 2012-02-21 | Samsung Electronics Co., Ltd. | Quantum dot electroluminescent device and method for fabricating the same |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6953891B2 (en) * | 2003-09-16 | 2005-10-11 | Micron Technology, Inc. | Moisture-resistant electronic device package and methods of assembly |
CN101057347B (en) * | 2004-11-09 | 2013-02-20 | 创造者科技有限公司 | Self-aligned process to manufacture organic transistors |
GB0517195D0 (en) * | 2005-08-23 | 2005-09-28 | Cambridge Display Tech Ltd | Molecular electronic device structures and fabrication methods |
KR101186740B1 (en) * | 2006-02-17 | 2012-09-28 | 삼성전자주식회사 | Method for Fabricating Bank and Organic Thin Film Transistor Having the Bank |
JP5181586B2 (en) * | 2006-09-26 | 2013-04-10 | 大日本印刷株式会社 | Organic semiconductor device, organic semiconductor device manufacturing method, organic transistor array, and display |
GB2448174B (en) * | 2007-04-04 | 2009-12-09 | Cambridge Display Tech Ltd | Organic thin film transistors |
JP4512146B2 (en) * | 2007-05-25 | 2010-07-28 | パナソニック株式会社 | Manufacturing method of organic transistor |
GB0724774D0 (en) * | 2007-12-19 | 2008-01-30 | Cambridge Display Tech Ltd | Organic thin film transistors, active matrix organic optical devices and methods of making the same |
KR101424012B1 (en) * | 2008-03-04 | 2014-08-04 | 삼성디스플레이 주식회사 | Display device and manufacturing method thereof |
JP5325465B2 (en) * | 2008-06-03 | 2013-10-23 | 株式会社日立製作所 | THIN FILM TRANSISTOR AND DEVICE USING THE SAME |
-
2010
- 2010-01-27 US US12/694,969 patent/US8603922B2/en not_active Expired - Fee Related
-
2011
- 2011-01-27 WO PCT/NL2011/050054 patent/WO2011093706A1/en active Application Filing
- 2011-01-27 KR KR1020127022301A patent/KR20120127621A/en not_active Application Discontinuation
- 2011-01-27 EP EP11703280A patent/EP2529426A1/en not_active Withdrawn
- 2011-01-27 JP JP2012551107A patent/JP2013518428A/en active Pending
- 2011-01-27 CN CN2011800075892A patent/CN102725876A/en active Pending
-
2013
- 2013-12-06 US US14/099,895 patent/US20140091339A1/en not_active Abandoned
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8120010B2 (en) * | 2008-11-05 | 2012-02-21 | Samsung Electronics Co., Ltd. | Quantum dot electroluminescent device and method for fabricating the same |
Also Published As
Publication number | Publication date |
---|---|
US20110180816A1 (en) | 2011-07-28 |
WO2011093706A1 (en) | 2011-08-04 |
US8603922B2 (en) | 2013-12-10 |
JP2013518428A (en) | 2013-05-20 |
CN102725876A (en) | 2012-10-10 |
KR20120127621A (en) | 2012-11-22 |
EP2529426A1 (en) | 2012-12-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8476170B2 (en) | Method of forming pattern, method of manufacturing semiconductor device, and method of manufacturing template | |
US8003300B2 (en) | Methods for fabricating complex micro and nanoscale structures and electronic devices and components made by the same | |
US8083958B2 (en) | Patterning method using a combination of photolithography and copolymer self-assemblying lithography techniques | |
KR101854796B1 (en) | Method of manufacturing mask | |
US7498119B2 (en) | Process for forming a feature by undercutting a printed mask | |
JP4483801B2 (en) | Patterning method, thin film transistor array manufacturing method, and display device manufacturing method | |
US20100264113A1 (en) | Template, method of manufacturing the same, and method of forming pattern | |
US7501348B2 (en) | Method for forming a semiconductor structure having nanometer line-width | |
US20140091339A1 (en) | Semiconductor device, display, and electronic apparatus | |
KR20120126725A (en) | Method for forming semiconductor device | |
US7537883B2 (en) | Method of manufacturing nano size-gap electrode device | |
US9766546B2 (en) | Method of producing a resist structure with undercut sidewall | |
TWI517218B (en) | Configuration and manufacturing method of low-resistance gate structure for semiconductor device and circuits | |
US20130236658A1 (en) | Pattern formation method | |
US11978660B2 (en) | Manufacturing method of original plate and semiconductor device | |
US10474028B2 (en) | Template, method for fabricating template, and method for manufacturing semiconductor device | |
KR101052290B1 (en) | Manufacturing Method of Semiconductor Pillar and Field Effect Transistor with Semiconductor Pillar | |
US9514938B2 (en) | Method of forming pattern | |
US20230350287A1 (en) | Imprint method | |
CN113448163B (en) | DSA-based photoetching method | |
US20220350247A1 (en) | Wet-dry bilayer resist | |
KR100562299B1 (en) | A method for forming a trench of a semiconductor device, and a method for forming a mask pattern thereof | |
JP2004301928A (en) | Thin film deposition method and body to be processed having thin film | |
US20100055617A1 (en) | Method of forming pattern in semiconductor device | |
JP2009038185A (en) | Forming method of conductive film pattern, wiring board, and display device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CREATOR TECHNOLOGY B.V.;REEL/FRAME:038214/0991 Effective date: 20160317 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |