US20140087537A1 - Semiconductor devices including multilayer source/drain stressors and methods of manufacturing the same - Google Patents
Semiconductor devices including multilayer source/drain stressors and methods of manufacturing the same Download PDFInfo
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
Abstract
A semiconductor device including source drain stressors and methods of manufacturing the same are provided. The methods may include forming a recess region in the substrate at a side of a gate pattern, and an inner surface of the recess region may include a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes. The method may further include performing a first selective epitaxial growth (SEG) process to form a base epitaxial pattern on the inner surface of the recess region at a process pressure in a range of about 50 Torr to about 300 Torr. The method may also include performing a second selective epitaxial growth (SEG) process to form a bulk epitaxial pattern on the base epitaxial pattern.
Description
- This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2012-0105825, filed on Sep. 24, 2012, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.
- The present disclosure generally relates to the field of electronics, and more particularly semiconductor devices.
- Semiconductor devices are widely used in various industries such as electronic devices, cars and/or vehicles because of their small size, lightness, and low manufacture costs. An electric field transistor (hereinafter, referred to as a transistor) may be one of important components constituting semiconductor devices. Generally, a transistor may include a source, a drain, and a gate electrode. The source and the drain may be spaced apart from each other in a semiconductor substrate, and the gate electrode may be disposed over a channel region between the drain and the source. The source and the drain may be formed by implanting dopant ions into the semiconductor substrate. The gate electrode may be electrically insulated from the channel region by a gate oxide layer therebetween.
- The transistors may be widely used as a switching component and/or components constituting a logic circuit in the semiconductor device. Recently, high speed transistors have been increasingly demanded. On the contrary, sizes of the transistors have been more reduced with high integration of semiconductor devices. Thus, a turn-on current of a transistor may, be reduced and performance of the transistor may deteriorate, such that reliability of a semiconductor device may deteriorate. Additionally, an operating speed of the semiconductor device may be reduced. Therefore, various researches have been conducted for increasing the turn-on current of the transistor.
- Source drain stressors may be used to increase the carrier mobility in the channel region of the MOS transistor. Tensile stressors may be used for an NMOS transistor and compressive stressors may be used for a PMOS transistor. Stressor materials may be epitaxial layers.
- A semiconductor device may include a substrate including a first semiconductor element and a gate pattern on the substrate. The device may further include a base epitaxial pattern on an inner surface of a recess region in the substrate at a side of the gate pattern. The inner surface of the recess region may include a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes. The base epitaxial pattern may include a second semiconductor element different from the first semiconductor element. The device may also include a bulk epitaxial pattern on the base epitaxial pattern and the bulk epitaxial pattern may include the second semiconductor element. The base epitaxial pattern may have a first thickness on the first surface and a second thickness on the second surface, and a ratio of the second thickness to the first thickness of the base epitaxial pattern may be in a range of about ¾ to about 1.
- In various embodiments, a second semiconductor element concentration in the base epitaxial pattern may be less than a second semiconductor element concentration in the bulk epitaxial pattern.
- According to various embodiments, the substrate may include first dopants of a first conductivity type and the bulk epitaxial pattern may include second dopants of a second conductivity type different from the first conductivity type. A second dopant concentration in the base epitaxial pattern may be less than a second dopant concentration in the bulk epitaxial pattern.
- In various embodiments, the base epitaxial pattern may be free of the second dopants
- According to various embodiments, the base epitaxial pattern may be formed at a process pressure in a range of about 50 Torr to about 300 Torr.
- In various embodiments, the recess region may include an undercut region tapered toward a region under the gate pattern.
- According to various embodiments, the semiconductor device may additionally include a buffer epitaxial pattern between the base epitaxial pattern and the bulk epitaxial pattern. The buffer epitaxial pattern may include the second semiconductor element, and a second semiconductor element concentration in the buffer epitaxial pattern may be less than a second semiconductor element concentration in the bulk epitaxial pattern and may be greater than a second semiconductor element concentration in the base epitaxial pattern.
- According to various embodiments, the buffer epitaxial pattern may have a third thickness on the first surface and a fourth thickness on the second surface and a ratio of the fourth thickness to the third thickness of the buffer epitaxial pattern may be less than the ratio of the second thickness to the first thickness of the base epitaxial pattern.
- In various embodiments, the substrate may include first dopants of a first conductivity type, the bulk epitaxial pattern and the buffer epitaxial pattern may include second dopants of a second conductivity type different from the first conductivity type. A second dopant concentration in the buffer epitaxial pattern may be less than a second dopant concentration in the bulk epitaxial pattern, and the base epitaxial pattern may be free of the second dopants or a second dopant concentration in the base epitaxial pattern may be less than the second dopant concentration in the buffer epitaxial pattern.
- A method of manufacturing a semiconductor device may include forming a gate pattern on a substrate including a first semiconductor element and forming a recess region in the substrate at a side of the gate pattern. An inner surface of the recess region may include a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes. The method may further include performing a first selective epitaxial growth (SEG) process to form a base epitaxial pattern on the inner surface of the recess region at a process pressure in a range of about 50 Torr to about 300 Torr. The base epitaxial pattern may include a second semiconductor element different from the first semiconductor element. The method may also include performing a second selective epitaxial growth (SEG) process to form a bulk epitaxial pattern including the second semiconductor element on the base epitaxial pattern.
- In various embodiments, a second semiconductor element concentration in the base epitaxial pattern may be less than a second semiconductor element concentration in the bulk epitaxial pattern. The base epitaxial pattern may have a first thickness on the first surface and a second thickness on the second surface, and a ratio of the second thickness to the first thickness of the base epitaxial pattern may be in a range about ¾ to about 1.
- According to various embodiments, the substrate may include first dopants of a first conductivity type and the bulk epitaxial pattern may include second dopants of a second conductivity type different from the first conductivity type. The base epitaxial pattern may be free of the second dopants or a second dopant concentration in the base epitaxial pattern may be less than a second dopant concentration in the bulk epitaxial pattern.
- In various embodiments, forming the recess region may include performing an anisotropic dry etching process to form a concave region in the substrate at a side of the gate pattern and performing an anisotropic wet etching process in the concave region to form the recess region. The anisotropic wet etching process may use {111} crystal planes of the substrate as etch stop surfaces.
- In various embodiments, the method may further include performing an additional selective epitaxial growth (SEG) process to form a buffer epitaxial pattern including the second semiconductor element on the base epitaxial pattern before performing the second SEG process. A process pressure of the additional SEG process may be lower than the process pressure of the first SEG process.
- According to various embodiments, a second semiconductor element concentration in the buffer epitaxial pattern may be less than a second semiconductor element concentration in the bulk epitaxial pattern and may be greater than a second semiconductor element concentration in the base epitaxial pattern.
- A method of manufacturing an integrated circuit device may include forming a recess in a substrate including a first element. An inner surface of the recess may include a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes. The method may further include forming a first epitaxial layer on the inner surface of the recess. The method may also include forming a second epitaxial layer in the recess on the first epitaxial layer. The first epitaxial layer may extend between the inner surface of the recess and the second epitaxial layer, and the second epitaxial layer may include a second element having a lattice size different from a lattice size of the first element.
- In various embodiments, forming the first epitaxial layer may include performing an epitaxial growth process at a process pressure in a range of about 50 Torr to about 300 Torr.
- According to various embodiments, the first epitaxial layer may include a portion of a first thickness on the first surface and a portion of a second thickness on the second surface, and a ratio of the second thickness to the first thickness may be in a range of about ¾ to about 1.
- According to various embodiments, the method of claim may further include forming a gate structure on the substrate. A portion of the recess, whose inner surface may include the second surface, may be tapered toward a region under the gate structure.
- In various embodiments, the first epitaxial layer may include the second element, and a second element concentration of the first epitaxial layer may be less than a second element concentration of the second epitaxial layer.
- In various embodiments, the second epitaxial layer may include a first dopant of a first conductivity type, and a first dopant concentration of the second epitaxial layer may be greater than a first dopant concentration of the first epitaxial layer.
- According to various embodiments, the first epitaxial layer may be free of the first dopant.
- In various embodiments, the substrate may include a second dopant of a second conductivity type opposite to the first conductivity type.
- According to various embodiments, the method of claim may further include forming a third epitaxial layer on the first epitaxial layer before forming the second epitaxial layer.
- According to various embodiments, forming the first epitaxial layer may include performing a first epitaxial growth process at a first process pressure and forming the third epitaxial layer may include performing a second epitaxial growth process at a second process pressure less than the first process pressure.
- In various embodiments, the first epitaxial layer may include a portion of a first thickness on the first surface and a portion of a second thickness on the second surface, and the third epitaxial layer may include a portion of a third thickness on the first surface and a portion of a fourth thickness on the second surface. A ratio of the second thickness to the first thickness may be greater than a ratio of the fourth thickness to the third thickness.
- According to various embodiments, the first and third epitaxial layers may include the second element, and a second element concentration of the third epitaxial layer may be greater than a second element concentration of the first epitaxial layer and may be less than a second element concentration of the second epitaxial layer.
- According to various embodiments, the second and third epitaxial layers may include a dopant of a first conductivity type and a dopant concentration of the second epitaxial layer may be greater than a dopant concentration of the third epitaxial layer.
- In various embodiments, the first epitaxial layer may be free of the dopant or a dopant concentration of the first epitaxial layer may be less than the dopant concentration of the third epitaxial layer.
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FIG. 1A is a cross-sectional view illustrating a semiconductor device according to some embodiments of the inventive concepts; -
FIG. 1B is an enlarged view of a portion ‘A’ ofFIG. 1A ; -
FIG. 2A is a cross-sectional view illustrating a semiconductor device according to some embodiments of the inventive concepts; -
FIG. 2B is an enlarged view of a portion ‘B’ ofFIG. 2A ; -
FIG. 3 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the inventive concepts; -
FIGS. 4 to 9 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to some embodiments of the inventive concepts; -
FIGS. 10 and 11 are cross-sectional views illustrating a modified example of a method of manufacturing a semiconductor device according to some embodiments of the inventive concepts; -
FIGS. 12 to 17 are cross-sectional views illustrating another modified example of a method of manufacturing a semiconductor device according to some embodiments of the inventive concepts; -
FIG. 18 is a block diagram illustrating an example of electronic systems including semiconductor devices according to some embodiments of the inventive concepts; and -
FIG. 19 is a block diagram illustrating an example of memory cards including semiconductor devices according to some embodiments of the inventive concepts. - Example embodiments are described below with reference to the accompanying drawings. Many different forms and embodiments are possible without deviating from the spirit and teachings of this disclosure and so the disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the disclosure to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference numbers refer to like elements throughout.
- Example embodiments of the inventive concepts are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments and intermediate structures of example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments of the inventive concepts should not be construed as limited to the particular shapes illustrated herein but include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle may have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.
- Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
- The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
- It will be understood that when an element is referred to as being “coupled,” “connected,” or “responsive” to, or “on,” another element, it can be directly coupled, connected, or responsive to, or on, the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly coupled,” “directly connected,” or “directly responsive” to, or “directly on,” another element, there are no intervening elements present. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items.
- It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element could be termed a second element without departing from the teachings of the present embodiments.
- Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.
-
FIG. 1A is a cross-sectional view illustrating a semiconductor device according to some embodiments of the inventive concepts, andFIG. 1B is an enlarged view of a portion ‘A’ ofFIG. 1A . - Referring to
FIG. 1A ,gate patterns 110 may be disposed on asubstrate 100. Thesubstrate 100 may include a first semiconductor element. For example, thesubstrate 100 may be formed of silicon. In other words, the first semiconductor element may be silicon. Thesubstrate 100 may have a single-crystalline state. Thesubstrate 100 may be doped with dopants of a first conductivity type. Each of thegate patterns 110 may include agate insulating layer 102, agate electrode 104, and acapping insulation pattern 106 which are sequentially stacked on thesubstrate 100. In some embodiments, the cappinginsulation pattern 106, thegate electrode 104, and thegate insulating layer 102 in thegate pattern 110 may have sidewalls aligned with each other, respectively. For example, thegate insulating layer 102 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and high-k dielectric (e.g., an insulating metal oxide such as aluminum oxide and/or hafnium oxide). Thegate electrode 104 may include at least one of a doped semiconductor material (e.g., doped silicon), a metal (e.g., tungsten, titanium, and/or tantalum), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and/or tungsten nitride), and a metal-semiconductor compound (e.g., a metal silicide). The cappinginsulation pattern 106 may include silicon nitride and/or silicon oxynitride. -
Gate spacers 115 may be disposed on both sidewalls of each of thegate patterns 110, respectively. For example, thegate spacer 115 may include silicon oxide, silicon nitride, and/or silicon oxynitride. - Recess
regions 120 may be disposed in thesubstrate 100 adjacent to both sides of thegate pattern 110. An inner surface of each of therecess regions 120 may include afirst surface 122 and asecond surface 124. Thefirst surface 122 is a (100) crystal plane of thesubstrate 100. Thesecond surface 124 is one of {111} crystal planes of thesubstrate 100. The inner surface of each of therecess regions 120 may include a plurality of {111} crystal planes. As illustrated inFIG. 1A , each of therecess regions 120 may include an undercut region tapered toward achannel region 114 under thegate pattern 110. Ends of two {111} crystal planes may be in contact with each other to define the tapered undercut region. - A
base epitaxial pattern 130 may be disposed on the inner surface of each of therecess regions 120. Thebase epitaxial pattern 130 may extend along the inner surface of therecess region 120. Thebase epitaxial pattern 130 may be in contact with the inner surface of therecess region 120. Abulk epitaxial pattern 135 may be disposed on thebase epitaxial pattern 130 so as to fill therecess region 120. In some embodiments, thebulk epitaxial pattern 135 may be in contact with thebase epitaxial pattern 130. - The
base epitaxial pattern 130 and thebulk epitaxial pattern 135 include a second semiconductor element different from the first semiconductor element of thesubstrate 100. An atomic diameter of the second semiconductor element is different from an atomic diameter of the first semiconductor element. Thus, lattice sizes of the base and bulkepitaxial patterns substrate 100. As a result, the base and bulkepitaxial patterns channel region 114, such that mobility of charges may increase in thechannel region 114. - Referring to
FIGS. 1A and 1B , thebase epitaxial pattern 130 has a first thickness T1 on thefirst surface 122 of therecess region 120 and a second thickness T2 on thesecond surface 124 of therecess region 120. A ratio of the second thickness T2 to the first thickness T1 may have a range of about 0.75:1 to about 1:1. In other words, the second thickness T2 may have a range of about 75% to about 100% of the first thickness T1. Thus, thebase epitaxial pattern 130 may be substantially conformally disposed along the inner surface of therecess region 120. As a result, a volume of thebulk epitaxial pattern 135 filling therecess region 120 may be maximized. A concentration of the second semiconductor element of thebulk epitaxial pattern 135 is greater than a concentration of the second semiconductor element of thebase epitaxial pattern 130. Thus, the specific force applied by thebulk epitaxial pattern 135 may increase, and thebase epitaxial pattern 130 may relax stress caused by difference between the lattice sizes of thebulk epitaxial pattern 135 and the inner surface of therecess region 120. - As described above, the
first surface 122 of therecess region 120 is the (100) crystal plane and thesecond surface 124 is one of the {111} crystal planes. Generally, a growth rate of an epitaxial layer on the (100) crystal plane may be greater than a growth rate of an epitaxial layer on the {111} crystal planes, such that an epitaxial layer on the (100) crystal plane may be thicker than an epitaxial layer on the {111} crystal planes. Thus, if the epitaxial layer on the {111} crystal planes is thick enough to relax the stress, the epitaxial layer on the (100) crystal plane may be thicker. Therefore, a volume of a bulk epitaxial layer may be reduced such that a specific force applied to achannel region 114 may be reduced. - However, according to some embodiments of the inventive concepts, it is possible to reduce or minimize difference between a growth rate of the
base epitaxial pattern 130 on thesecond surface 124 and a growth rate of thebase epitaxial pattern 130 on thefirst surface 122, so that the ratio of the second thickness T2 to the first thickness T1 of thebase epitaxial pattern 130 has the range of about 0.75:1 to about 1:1. Thus, thebase epitaxial pattern 130 may be substantially conformally formed on the inner surface of therecess region 120, and thus the volume of thebulk epitaxial pattern 135 may be increased or maximized. As a result, the specific force applied to thechannel region 114 may be increased while thebase epitaxial pattern 130 may relax the stress between thebulk epitaxial pattern 135 and the inner surface of therecess region 120. Thebase epitaxial pattern 130 may be formed by a selective epitaxial growth (SEG) process under a high process pressure in a range of about 50 Torr to about 300 Torr to reduce the difference between the growth rate of thebase epitaxial pattern 130 on thesecond surface 124 and the growth rate of thebase epitaxial pattern 130 on thefirst surface 122. - If a transistor including the
channel region 114 and thegate pattern 110 is a PMOS transistor, the base and bulkepitaxial patterns channel region 114. Thus, mobility of holes may be increased in a channel generated in thechannel region 114. The atomic diameter of the second semiconductor element of the base and bulkepitaxial patterns substrate 100. For example, if the substrate is a silicon substrate, the base and bulkepitaxial patterns - Alternatively, if the transistor including the
channel region 114 and thegate pattern 110 is a NMOS transistor, the base and bulkepitaxial patterns channel region 114. Thus, mobility of electrons may be increased in the channel generated in thechannel region 114. The atomic diameter of the second semiconductor element of the base and bulkepitaxial patterns substrate 100. For example, if thesubstrate 100 is a silicon substrate, the base and bulkepitaxial patterns - The
substrate 100 is doped with dopants of the first conductivity type, and thebulk epitaxial patterns 135 are doped with dopants of a second conductivity type different from the first conductivity type. Thebulk epitaxial patterns 135 may correspond to source/drain regions of the transistor. One of the first and second conductivity types is an N-type and another of the first and second conductivity types is a P-type. Thebulk epitaxial pattern 135 may be heavily doped. - The
base epitaxial pattern 130 may have a dopant concentration less than a concentration of the dopants of the second conductivity type in thebulk epitaxial pattern 135. For example, thebase epitaxial pattern 130 may be undoped. Alternatively, thebase epitaxial pattern 130 may be doped with dopants of the second conductivity type and have a concentration of the dopants of the second conductivity type less than the concentration of the dopants of the second conductivity type in thebulk epitaxial pattern 135. Since thebase epitaxial pattern 130 is undoped or has the low concentration of the dopants of the second conductivity type, a leakage current of the transistor may be reduced. - In an embodiment, a low concentration doped
region 112 may be disposed in thesubstrate 100 between thechannel region 114 and thebase epitaxial pattern 130. The low concentration dopedregion 112 is doped with dopants of the second conductivity. A concentration of the dopants in the low concentration dopedregion 112 may be less than the concentration of the dopants in thebulk epitaxial pattern 135. Thus, the low concentration doped region and thebulk epitaxial pattern 135 may be realized as a Lightly Doped Drains (LDD) source/drain region or an extension source/drain. - A capping
epitaxial pattern 140 may be disposed on each of thebulk epitaxial patterns 135. A top surface of the cappingepitaxial pattern 140 may be higher than a top surface of thesubstrate 100. For example, the cappingepitaxial pattern 140 may be formed of silicon. Anohmic pattern 145 may be disposed on thecapping epitaxial pattern 140. For example, theohmic pattern 145 may be formed of a metal-semiconductor compound (e.g., a metal silicide). For example, theohmic pattern 145 may be formed by reaction between a metal and the cappingepitaxial pattern 140. Theohmic pattern 145 may be formed of, for example, cobalt silicide, nickel silicide, and/or titanium silicide. - Next, modified examples of the semiconductor device according to some embodiments of the inventive concepts will be described with reference to the drawings. For the purpose of ease and convenience, the descriptions of the same components as in the above embodiment will be omitted or mentioned briefly.
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FIG. 2A is a cross-sectional view illustrating a semiconductor device according to some embodiments of the inventive concepts, andFIG. 2B is an enlarged view of a portion ‘B’ ofFIG. 2A . - Referring to
FIGS. 2A and 2B , abuffer epitaxial pattern 133 may be disposed between the baseepitaxial pattern 130 and thebulk epitaxial pattern 135. Thebuffer epitaxial pattern 133 includes the second semiconductor element. For example, if the transistor is the PMOS transistor, thebuffer epitaxial pattern 133 may include silicon-germanium (SiGe). If the transistor is the NMOS transistor, thebuffer epitaxial pattern 133 may include silicon carbide (SiC). - A concentration of the second semiconductor element of the
buffer epitaxial pattern 133 may be less than the concentration of the second semiconductor element of thebulk epitaxial pattern 135. In some embodiments, the concentration of the second semiconductor element of thebuffer epitaxial pattern 133 may be greater than the concentration of the second semiconductor element of thebase epitaxial pattern 130. - As illustrated in
FIG. 2B , thebuffer epitaxial pattern 133 may have a third thickness Ta on thefirst surface 122 of therecess region 120 and a fourth thickness Tb on thesecond surface 124 of therecess region 120. A ratio of the fourth thickness Tb to the third thickness Ta of thebuffer epitaxial pattern 133 may be less than the ratio of the second thickness T2 to the first thickness T1 of thebase epitaxial pattern 130. In other words, the ratio of the fourth thickness Tb to the third thickness Ta of thebuffer epitaxial pattern 133 may be less than about 0.75:1. - Referring to
FIGS. 2A and 2B , thebuffer epitaxial pattern 133 may be doped with dopants of the second conductivity type. A concentration of the dopants of thebuffer epitaxial pattern 133 may be less than the concentration of the dopants of thebulk epitaxial pattern 135. The dopant concentration of thebase epitaxial pattern 133 may be equal to 0 (zero) and or may be less than the concentration of the dopants of thebuffer epitaxial pattern 133. -
FIG. 3 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the inventive concepts. In the present modified example, a gate pattern may have a structure different from that of thegate pattern 110 ofFIGS. 1A and 2A . - Referring to
FIG. 3 , agate pattern 180 may include agate insulating pattern 165 a and a gate electrode which are sequentially stacked on thesubstrate 100. In an embodiment, the gate electrode may include a barrierconductive pattern 170 a and ametal pattern 175 a which are sequentially stacked. Both ends of the barrierconductive pattern 170 a may extend upward to cover both sidewalls of themetal pattern 175 a, respectively. Both ends of thegate insulating pattern 165 a may extend upward to cover both sidewalls of the gate electrode, respectively. Each of the extending portions of the barrierconductive pattern 170 a may be disposed between themetal pattern 175 and each of the extending portions of thegate insulating pattern 165 a. - A top surface of the
gate pattern 180 may be substantially coplanar with top surfaces ofgate spacers 115 a and an interlayer insulatinglayer 150 a which are disposed at both sides of thegate pattern 180. The interlayer insulatinglayer 150 a may cover theohmic pattern 145. Thegate insulating pattern 165 a may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k dielectric (e.g., an insulating metal oxide such as hafnium oxide and/or aluminum oxide). The barrierconductive pattern 170 a may include a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and/or tungsten nitride). Themetal pattern 175 a may include tungsten and/or aluminum. - The
gate pattern 180 according to the present modified example may be replaced with thegate pattern 110 ofFIG. 1A . - The semiconductor devices according to some may be various kinds of semiconductor devices such as semiconductor memory devices, logic devices, and system on chips (SOCs).
-
FIGS. 4 to 9 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to some embodiments of the inventive concepts. - Referring to
FIG. 4 ,gate patterns 110 may be formed on asubstrate 100 which is formed of a first semiconductor element and is doped with dopants of a first conductivity type. Each of thegate patterns 110 may include agate insulating layer 102, agate electrode 104, and acapping insulating pattern 106 which are sequentially stacked on thesubstrate 100. Dopants of a second conductivity type may be implanted into thesubstrate 100 at both sides of thegate pattern 110, thereby forming low concentration dopedregions 112.Gate spacers 115 may be formed on both sidewalls of each of thegate patterns 110, respectively. - Referring to
FIG. 5 , an anisotropic dry etching process may be performed on thesubstrate 100 using thecapping insulating patterns 106 and the gate spacers 155 as etch masks. Thus,concave regions 117 may be formed in thesubstrate 100 at both sides of each of thegate patterns 110. - Referring to
FIG. 6 , an anisotropic wet etching process may be performed inconcave regions 117 to formrecess regions 120. The anisotropic wet etching process may use {111} crystal planes of crystal planes of thesubstrate 100 as etch stop surfaces. In other words, the anisotropic wet etching process may etch the {111} crystal planes very slowly compared with other crystal planes of thesubstrate 100. Sidewalls of theconcave regions 117 may be laterally etched by the anisotropic wet etching process to form therecess regions 120 including tapered undercut regions under thegate pattern 110. The tapered undercut region may be laterally tapered toward achannel region 114 under thegate pattern 110. Due to the anisotropic wet etching process, an inner surface of therecess region 120 includes afirst surface 122 of a (100) crystal plane and asecond surface 124 of one of the {111} crystal planes. Thefirst surface 122 may correspond to a bottom surface of therecess region 120. - In some embodiments, if the
substrate 100 is a silicon substrate, the anisotropic wet etching process may include an anisotropic etchant including ammonium hydroxide (NH4OH) and/or tetramethyl ammonium hydroxide (TMAH). - Referring to
FIG. 7 , a first selective epitaxial growth (SEG) process may be performed to form abase epitaxial pattern 130 on the inner surface of therecess region 120. The first SEG process may be performed under a high process pressure in a range of about 50 Torr to about 300 Torr. The first SEG process may use a process gas including a semiconductor source gas. The semiconductor source gas may include a second semiconductor element different from the first semiconductor element. Additionally, the semiconductor source gas may further include the first semiconductor element. For example, if a transistor including thegate pattern 110 is a PMOS transistor, the semiconductor source gas may include silicon and germanium. If the transistor is a NMOS transistor, the semiconductor source gas may include silicon and carbon. - Since the first SEG process is performed under the high process pressure, the semiconductor source gas may be sufficiently supplied to the second surface 124 (i.e., one of the {111} crystal planes) of the
recess region 120. Thus, it is possible to reduce or minimize difference between a growth rate of thebase epitaxial pattern 130 on thesecond surface 124 and a growth rate of thebase epitaxial pattern 130 on thefirst surface 122. As a result, thebase epitaxial pattern 130 may be substantially conformally formed on the inner surface of therecess region 120. In other words, a ratio of a thickness of thebase epitaxial pattern 130 on thesecond surface 124 to a thickness of thebase epitaxial pattern 130 on thefirst surface 122 may be in a range of about 0.75:1 to about 1:1. - The
base epitaxial pattern 130 may be undoped. Alternatively, thebase epitaxial pattern 130 may be lightly doped with dopants of a second conductivity type different from the first conductivity type. In this case, thebase epitaxial pattern 130 may be doped in-situ. In other words, the process gas of the first SEG process may further include a dopant source gas having dopants of the second conductivity type. - Referring to
FIG. 8 , a second selective epitaxial growth (SEG) process may be performed on thebase epitaxial pattern 130 to form abulk epitaxial pattern 135. Thebulk epitaxial pattern 135 may fill therecess region 120 on thebase epitaxial pattern 130. A process gas of the second SEG process includes a semiconductor source gas. The semiconductor source gas of the second SEG process includes the second semiconductor element. Additionally, the semiconductor source gas of the second SEG process may further include the first semiconductor element. For example, if the transistor is the PMOS transistor, the semiconductor source gas of the second SEG process may include silicon and germanium. If the transistor is the NMOS transistor, the semiconductor source gas of the second SEG process may include silicon and carbon. - The amount of the second semiconductor element in the semiconductor source gas of the second SEG process is greater than the amount of the second semiconductor element in the semiconductor source gas of the first SEG process. Thus, a concentration of the second semiconductor element in the
bulk epitaxial pattern 135 may be greater than a concentration of the second semiconductor element in thebase epitaxial pattern 130. - The
bulk epitaxial pattern 135 is doped with dopants of the second conductivity type. Thebulk epitaxial pattern 135 may be doped in-situ. For example, the process gas of the second SEG process may further include a dopant source gas having dopants of the second conductivity type. Thebulk epitaxial pattern 135 may be heavily doped with the dopants of the second conductivity type. A process pressure of the second SEG process may be in a range of about 10 Torr to about 100 Torr. The first and second SEG processes may be sequentially performed in one process chamber. - Referring to
FIG. 9 , a third selective epitaxial growth (SEG) process may be performed on thebulk epitaxial pattern 135 to form acapping epitaxial pattern 140. For example, the cappingepitaxial pattern 140 may be formed of the first semiconductor element. For example, the cappingepitaxial pattern 140 may be formed of silicon. The cappingepitaxial pattern 140 may be doped with dopants of the second conductivity type. Subsequently, a metal layer may be formed on thesubstrate 100, and the metal layer may react with the cappingepitaxial pattern 140, thereby forming theohmic pattern 145 ofFIG. 1A . - According to the method of manufacturing the semiconductor device described above, the
base epitaxial pattern 130 is formed under the high process pressure. Thus, it is possible to reduce the difference between the growth rate of thebase epitaxial pattern 130 on thesecond surface 124 and the growth rate of thebase epitaxial pattern 130 on thefirst surface 122. As a result, thebase epitaxial pattern 130 may be substantially conformally formed on the inner surface of therecess region 120. -
FIGS. 10 and 11 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to some embodiments of the inventive concepts. - Referring to
FIGS. 7 and 10 , an additional selective epitaxial growth (SEG) process may be performed on thebase epitaxial pattern 130 to form abuffer epitaxial pattern 133. A process pressure of the additional SEG process may be lower than the process pressure of the first SEG process. Thus, a ratio of a thickness of thebuffer epitaxial pattern 133 on thesecond surface 124 to a thickness of thebuffer epitaxial pattern 133 on thefirst surface 122 may be lower than the ratio of the thickness of thebase epitaxial pattern 130 on thesecond surface 124 to the thickness of thebase epitaxial pattern 130 on thefirst surface 122. For example, the process pressure of the additional SEG process may be in a range of about 10 Torr to 30 Torr. - A process gas of the additional SEG process may include the second semiconductor element. Additionally, the process gas of the additional SEG process may further include the first semiconductor element. The
buffer epitaxial pattern 133 may be doped with dopants of the second conductivity type. For example, thebuffer epitaxial pattern 133 may be doped in-situ. In this case, the process gas of the additional SEG process may further include a dopant source gas including dopants of the second conductivity type. - Referring to
FIG. 11 , the SEG process may be performed on thebuffer epitaxial pattern 133 to form abulk epitaxial pattern 135 on thebuffer epitaxial pattern 133. - The amount of the second semiconductor element in the semiconductor source gas of the additional SEG process may be greater than the amount of the second semiconductor element in the semiconductor source gas of the first SEG process and less than the amount of the second semiconductor element in the semiconductor source of the second SEG process. Thus, a concentration of the second semiconductor element in the
buffer epitaxial pattern 133 may be greater than the concentration of the second semiconductor element in thebase epitaxial pattern 130 and less than the concentration of the second semiconductor element in thebulk epitaxial pattern 135. - The third SEG process described with reference to
FIG. 9 may be performed to form thecapping epitaxial pattern 140 and theohmic pattern 145 ofFIG. 2A may be formed on thecapping epitaxial pattern 140. -
FIGS. 12 to 17 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to exemplary embodiments of the inventive concepts. - Referring to
FIG. 12 ,dummy gate patterns 210 may be formed on asubstrate 100. Low concentration dopedregions 112 may be formed in the substrate at both sides of each of thedummy gate patterns 210.Gate spacers 115 may be formed on both sidewalls of each of thedummy gate patterns 210, respectively. Thedummy gate pattern 210 may include a material having an etch selectivity with respect to thegate spacer 115 and an interlayer insulatinglayer 150 formed through a subsequent process. In some embodiments, thedummy gate pattern 210 may include alower pattern 205 and anupper pattern 207 which are sequentially stacked on thesubstrate 100. For example, if thegate spacer 115 is formed of silicon nitride and the interlayer insulatinglayer 150 is formed of silicon oxide, thelower pattern 205 may be formed of a semiconductor material (e.g., silicon) and theupper pattern 207 may be formed of silicon oxide. In some embodiments, a buffer oxide layer (not illustrated) may be formed between thedummy gate pattern 210 and thesubstrate 100. - Referring to
FIG. 13 , therecess regions 120 may be formed in thesubstrate 100 at both sides of each of thedummy gate patterns 210, respectively. Therecess regions 120 may be formed by the processes described with reference toFIGS. 5 and 6 . - Referring to
FIG. 14 , the base, buffer, and bulkepitaxial patterns recess regions 120. In some embodiments, the formation ofbuffer epitaxial pattern 133 may be omitted. The cappingepitaxial pattern 140 may be formed on thebulk epitaxial pattern 135, and theohmic pattern 145 may be formed on thecapping epitaxial pattern 140. The interlayer insulatinglayer 150 may be formed on an entire surface of thesubstrate 100. - Referring to
FIG. 15 , theinterlayer insulating layer 150 and theupper pattern 207 of thedummy gate pattern 210 may be planarized until thelower pattern 205 is exposed. Upper portions of thegate spacers 115 may also be planarized by the planarizing process. As mentioned above, thelower pattern 205 of thedummy gate pattern 210 may have the etch selectivity with respect to the planarizedinterlayer insulating layer 150 a and theplanarized gate spacers 115 a. - Referring to
FIG. 16 , the exposedlower patterns 205 may be removed to formopenings 160. If the buffer oxide layer is formed, the buffer oxide layer may be removed to expose thesubstrate 100 under theopenings 160 after the removal of thelower patterns 205. - Referring to
FIG. 17 , agate insulating layer 165 and a gate conductive layer may be sequentially formed on thesubstrate 100 having theopenings 160. In some embodiments, the gate conductive layer may include a barrierconductive layer 170 and ametal layer 175 which are sequentially stacked. Thegate insulating layer 165 may be formed by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. Thus, thegate insulating layer 165 may be substantially conformally formed on thesubstrate 100. Alternatively, thegate insulating layer 165 may be formed by an oxidation process and/or a nitridation process. In this case, thegate insulating layer 165 may be selectively formed on thesubstrate 100 exposed by each of theopenings 160. - The
metal layer 175, the barrierconductive layer 170, and thegate insulating layer 165 may be planarized until the planarizedinterlayer insulating layer 150 a is exposed. Thus, thegate patterns 180 ofFIG. 3 may be formed. As described above, thegate pattern 180 may include thegate insulating pattern 165 a, the barrierconductive pattern 170 a, and themetal pattern 175 a. - The semiconductor devices described above may be encapsulated using various packaging techniques. For example, the semiconductor devices according to the aforementioned embodiments may be encapsulated using any one of a package on package (POP) technique, a ball grid arrays (BGAs) technique, a chip scale packages (CSPs) technique, a plastic leaded chip carrier (PLCC) technique, a plastic dual in-line package (PDIP) technique, a die in waffle pack technique, a die in wafer form technique, a chip on board (COB) technique, a ceramic dual in-line package (CERDIP) technique, a plastic metric quad flat package (PMQFP) technique, a plastic quad flat package (PQFP) technique, a small outline package (SOIC) technique, a shrink small outline package (SSOP) technique, a thin small outline package (TSOP) technique, a thin quad flat package (TQFP) technique, a system in package (SIP) technique, a multi chip package (MCP) technique, a wafer-level fabricated package (WFP) technique and a wafer-level processed stack package (WSP) technique.
- The package in which the semiconductor device according to some embodiments is mounted may further include at least one semiconductor device (e.g., a controller and/or a logic device) that controls the semiconductor memory device.
-
FIG. 18 is a block diagram illustrating an example of electronic systems including semiconductor devices according to some embodiments of the inventive concepts. - Referring to
FIG. 18 , anelectronic system 1100 according to an embodiment may include acontroller 1110, an input/output (I/O)unit 1120, amemory device 1130, aninterface unit 1140 and adata bus 1150. At least two of thecontroller 1110, the I/O unit 1120, thememory device 1130 and theinterface unit 1140 may communicate with each other through thedata bus 1150. Thedata bus 1150 may correspond to a path through which electrical signals are transmitted. - The
controller 1110 may include at least one of a microprocessor, a digital signal processor, a microcontroller or another logic device. The other logic device may have a similar function to any one of the microprocessor, the digital signal processor and the microcontroller. The I/O unit 1120 may include a keypad, a keyboard and/or a display unit. Thememory device 1130 may store data and/or commands. Thememory device 1130 and/or thecontroller 1110 may include at least one of the semiconductor devices according to some embodiments described above. - The
interface unit 1140 may transmit electrical data to a communication network or may receive electrical data from a communication network. Theinterface unit 1140 may operate by wireless or cable. For example, theinterface unit 1140 may include an antenna for wireless communication or a transceiver for cable communication. Theelectronic system 1100 may further include a fast DRAM device and/or a fast SRAM device which acts as a cache memory for improving an operation of thecontroller 1110. - The
electronic system 1100 may be applied to a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card or other electronic products. The other electronic products may receive or transmit information data by wireless. -
FIG. 19 is a block diagram illustrating an example of memory cards including semiconductor devices according to some embodiments of the inventive concepts. - Referring to
FIG. 19 , amemory card 1200 according to an embodiment of the inventive concepts may include amemory device 1210. The semiconductor devices according to the aforementioned embodiments comprise semiconductor memory devices, thememory device 1210 may include at least one of the semiconductor devices according to some embodiments mentioned above. Thememory card 1200 may include amemory controller 1220 that controls data communication between a host and thememory device 1210. - The
memory controller 1220 may include a central processing unit (CPU) 1222 that controls overall operations of thememory card 1200. In addition, thememory controller 1220 may include anSRAM device 1221 as an operation memory of theCPU 1222. Moreover, thememory controller 1220 may further include ahost interface unit 1223 and amemory interface unit 1225. Thehost interface unit 1223 may be configured to include a data communication protocol between thememory card 1200 and the host. Thememory interface unit 1225 may connect thememory controller 1220 to thememory device 1210. Thememory controller 1220 may further include an error check and correction (ECC)block 1224. TheECC block 1224 may detect and correct errors of data which are read out from thememory device 1210. Thememory card 1200 may further include a read only memory (ROM) device that stores code data to interface with the host. Thememory card 1200 may be used as a portable data storage card. Alternatively, thememory card 1200 may be solid state disks (SSD) which are used as hard disks of computer systems. - According to various embodiments of the inventive concepts as described above, the ratio of the second thickness to the first thickness of the base epitaxial pattern may have the range of about 0.75:1 to about 1:1. Thus, the base epitaxial pattern may be substantially conformally formed on the inner surface of the recess region. As a result, the volume of the bulk epitaxial pattern may increase in the recess region, such that the specific force (e.g., the compressive force or the tensile force) may be sufficiently applied to the channel region under the gate pattern.
- The first SEG process for the formation of the base epitaxial pattern may be performed under the high process pressure of about 50 Torr to about 300 Torr. Thus, the semiconductor source gas may be sufficiently supplied to the {111} crystal planes of the inner surface of the recess region. As a result, it is possible to improve uniformity of the thickness of the base epitaxial pattern.
- The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the inventive concepts. Thus, to the maximum extent allowed by law, the scope is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.
Claims (21)
1.-9. (canceled)
10. A method of manufacturing a semiconductor device comprising:
forming a gate pattern on a substrate comprising a first semiconductor element;
forming a recess region in the substrate at a side of the gate pattern, an inner surface of the recess region including a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes;
performing a first selective epitaxial growth (SEG) process to form a base epitaxial pattern on the inner surface of the recess region at a process pressure in a range of about 50 Torr to about 300 Torr, the base epitaxial pattern comprising a second semiconductor element different from the first semiconductor element; and
performing a second selective epitaxial growth (SEG) process to form a bulk epitaxial pattern comprising the second semiconductor element on the base epitaxial pattern.
11. The method of claim 10 , wherein a second semiconductor element concentration in the base epitaxial pattern is less than a second semiconductor element concentration in the bulk epitaxial pattern, and wherein the base epitaxial pattern has a first thickness on the first surface and a second thickness on the second surface, and a ratio of the second thickness to the first thickness of the base epitaxial pattern is in a range about ¾ to about 1.
12. The method of claim 10 , wherein the substrate comprises first dopants of a first conductivity type and the bulk epitaxial pattern comprises second dopants of a second conductivity type different from the first conductivity type, and wherein the base epitaxial pattern is free of the second dopants or a second dopant concentration in the base epitaxial pattern is less than a second dopant concentration in the bulk epitaxial pattern.
13. The method of claim 10 , wherein forming the recess region comprises:
performing an anisotropic dry etching process to form a concave region in the substrate at a side of the gate pattern; and
performing an anisotropic wet etching process in the concave region to form the recess region,
wherein the anisotropic wet etching process uses {111} crystal planes of the substrate as etch stop surfaces.
14. The method of claim 10 , further comprising:
performing an additional selective epitaxial growth (SEG) process to form a buffer epitaxial pattern comprising the second semiconductor element on the base epitaxial pattern before performing the second SEG process,
wherein a process pressure of the additional SEG process is lower than the process pressure of the first SEG process.
15. The method of claim 14 , wherein a second semiconductor element concentration in the buffer epitaxial pattern is less than a second semiconductor element concentration in the bulk epitaxial pattern and is greater than a second semiconductor element concentration in the base epitaxial pattern.
16. A method of manufacturing an integrated circuit device comprising:
forming a recess in a substrate comprising a first element, wherein an inner surface of the recess comprises a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes;
forming a first epitaxial layer on the inner surface of the recess; and
forming a second epitaxial layer in the recess on the first epitaxial layer, wherein the first epitaxial layer extends between the inner surface of the recess and the second epitaxial layer, and wherein the second epitaxial layer comprises a second element having a lattice size different from a lattice size of the first element.
17. The method of claim 16 , wherein forming the first epitaxial layer comprises performing an epitaxial growth process at a process pressure in a range of about 50 Torr to about 300 Torr.
18. The method of claim 16 , wherein the first epitaxial layer comprises a portion of a first thickness on the first surface and a portion of a second thickness on the second surface, and wherein a ratio of the second thickness to the first thickness is in a range of about ¾ to about 1.
19. The method of claim 16 , further comprising forming a gate structure on the substrate, wherein a portion of the recess, whose inner surface comprises the second surface, is tapered toward a region under the gate structure.
20. The method of claim 16 , wherein the first epitaxial layer comprises the second element, and wherein a second element concentration of the first epitaxial layer is less than a second element concentration of the second epitaxial layer.
21. The method of claim 16 , wherein the second epitaxial layer comprises a first dopant of a first conductivity type, and wherein a first dopant concentration of the second epitaxial layer is greater than a first dopant concentration of the first epitaxial layer.
22. The method of claim 21 , wherein the first epitaxial layer is free of the first dopant.
23. The method of claim 21 , wherein the substrate comprise a second dopant of a second conductivity type opposite to the first conductivity type.
24. The method of claim 16 , further comprising forming a third epitaxial layer on the first epitaxial layer before forming the second epitaxial layer.
25. The method of claim 24 , wherein forming the first epitaxial layer comprises performing a first epitaxial growth process at a first process pressure and forming the third epitaxial layer comprises performing a second epitaxial growth process at a second process pressure less than the first process pressure.
26. The method of claim 24 , wherein the first epitaxial layer comprises a portion of a first thickness on the first surface and a portion of a second thickness on the second surface, and the third epitaxial layer comprises a portion of a third thickness on the first surface and a portion of a fourth thickness on the second surface, and wherein a ratio of the second thickness to the first thickness is greater than a ratio of the fourth thickness to the third thickness.
27. The method of claim 24 , wherein the first and third epitaxial layers comprise the second element, and wherein a second element concentration of the third epitaxial layer is greater than a second element concentration of the first epitaxial layer and is less than a second element concentration of the second epitaxial layer.
28. The method of claim 24 , wherein the second and third epitaxial layers comprise a dopant of a first conductivity type, and wherein a dopant concentration of the second epitaxial layer is greater than a dopant concentration of the third epitaxial layer.
29. The method of claim 28 , wherein the first epitaxial layer is free of the dopant or a dopant concentration of the first epitaxial layer is less than the dopant concentration of the third epitaxial layer.
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Also Published As
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KR20140039544A (en) | 2014-04-02 |
US20150179795A1 (en) | 2015-06-25 |
US9299836B2 (en) | 2016-03-29 |
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