JP5200476B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device whose operating speed is improved by applying strain and a method for manufacturing the same.

  In recent LSIs of the so-called 90 nm node and beyond, further miniaturization has been demanded, and it has become difficult to improve the performance of transistors. This is because the standby off-leakage current increases as the gate length is shortened, so that it is extremely difficult to improve the current driving capability if the off-leakage current is kept constant. For this reason, new approaches for improving the performance of transistors are being searched.

One such attempt is strained silicon technology. This is a technique for improving current driving capability by applying a stress to the channel region to change the band structure, reduce the effective mass of carriers, and improve carrier mobility.
In a p-channel MOS transistor, it is known that carrier mobility is improved by applying a uniaxial compressive stress to a channel region. As a specific example of applying compressive stress to the channel region, a so-called embedded transistor in which a recess is formed in the source / drain region and a SiGe layer is embedded in the recess by an epitaxial method has been proposed (see Patent Document 1). ).

  SiGe has a larger lattice constant than silicon, and the crystal of the SiGe layer lattice matches with the silicon substrate in the in-plane direction of the substrate. Therefore, the silicon substrate is stretched in the direction perpendicular to the substrate. As a result, compressive strain is introduced into the channel region in the in-plane direction of the substrate, that is, in the channel direction, and compressive stress is applied. As a result of such uniaxial compressive stress being applied to the channel region, the symmetry of the Si crystal constituting the channel region is locally modulated. Further, with such a change in symmetry, the degeneration of the valence band of heavy holes and the valence band of light holes can be solved, so that the hole mobility in the channel region is increased and the operation speed of the transistor is improved. Such an increase in hole mobility due to stress locally induced in the channel region and an accompanying improvement in transistor operation speed are particularly noticeable in an ultrafine semiconductor device having a gate length of 100 nm or less.

JP 2006-186240 A International Publication No. 2004/097943 Pamphlet JP 2006-332337 A

  In the embedded structure transistor in which the SiGe layer is embedded in the source / drain region, by introducing compressive strain into the channel, the hole mobility is increased and the current driving capability of the transistor is improved. However, after the 45 nm node, it is necessary to further increase the current drive capability improvement rate.

  Therefore, conventionally, methods such as increasing the Ge concentration of the SiGe layer and narrowing the interval between the SiGe layers have been considered, but all have disadvantages. The former method increases the strain in the channel region, but has a problem that dislocations are generated in the SiGe layer and a current leak path is easily formed. The latter technique increases the distortion in the channel region, but has a problem that the roll-off characteristics of the transistor are impaired.

  The present invention has been made in view of the above problems, and greatly increases the amount of distortion introduced into the channel region without causing problems such as the occurrence of a current leak path and the deterioration of roll-off characteristics. An object of the present invention is to provide a highly reliable semiconductor device and a method for manufacturing the same capable of improving the characteristics.

According to a method of manufacturing a semiconductor device of the present invention, a gate insulating film and a gate electrode are formed on a semiconductor substrate, a channel region is formed on the semiconductor substrate, and a first sidewall is formed on a side surface of the gate electrode. Forming a non-doped first semiconductor layer on the semiconductor substrate adjacent to the first sidewall; and forming a first non-doped semiconductor layer on the first sidewall and the non-doped first semiconductor layer. A step of forming a recess by etching the non-doped first semiconductor layer and the semiconductor substrate using the second sidewall as a mask, and a step of forming a recess in the recess. Forming a semiconductor layer.
According to another aspect of the method for manufacturing a semiconductor device of the present invention, a gate insulating film and a gate electrode are formed on a semiconductor substrate, a channel region is formed on the semiconductor substrate, and a first side is formed on a side surface of the gate electrode. Forming a wall; forming a first semiconductor layer on the semiconductor substrate adjacent to the first sidewall; and forming a first semiconductor layer on the first sidewall and the first semiconductor layer. Forming a recess by etching the first semiconductor layer and the semiconductor substrate using the second sidewall as a mask, and forming the recess in the recess. Forming a second semiconductor layer having a lattice constant larger than that of the layer and having a shape in which a side surface protrudes toward the channel region .
According to another aspect of the method for manufacturing a semiconductor device of the present invention, a gate insulating film and a gate electrode are formed on a semiconductor substrate, a channel region is formed on the semiconductor substrate, and a first side is formed on a side surface of the gate electrode. Forming a wall; forming a first semiconductor layer on the semiconductor substrate adjacent to the first sidewall; and forming a first semiconductor layer on the first sidewall and the first semiconductor layer. And forming a recess by etching the first semiconductor layer and the semiconductor substrate using the second sidewall as a mask, and a lattice of the semiconductor substrate in the recess. Forming a second semiconductor layer having a lattice constant larger than a constant and having a shape in which a side surface projects toward the channel region. Serial portion of the second semiconductor layer is in contact with the semiconductor substrate.

A semiconductor device of the present invention includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate , a gate electrode formed on the gate insulating film, a channel region formed on the semiconductor substrate, and the gate a sidewall formed on the side surface of the electrode, the sidewall in contact, and the semiconductor substrate and the gate insulating film and the first semiconductor layer of undoped formed at a position higher than the position of the interface, non-doped of the first And a second semiconductor layer embedded in the semiconductor substrate.
Another aspect of the semiconductor device of the present invention includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and a channel region formed on the semiconductor substrate. A sidewall formed on a side surface of the gate electrode; a first semiconductor layer in contact with the sidewall; and formed at a position higher than an interface position between the semiconductor substrate and the gate insulating film; A second semiconductor layer embedded in the semiconductor substrate, wherein the second semiconductor layer has a lattice constant larger than that of the first semiconductor layer, and has a side surface. Has a shape protruding toward the channel region.
Another aspect of the semiconductor device of the present invention includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and a channel region formed on the semiconductor substrate. A sidewall formed on a side surface of the gate electrode; a first semiconductor layer in contact with the sidewall; and formed at a position higher than an interface position between the semiconductor substrate and the gate insulating film; A second semiconductor layer in contact with one semiconductor layer, embedded in the semiconductor substrate, having a lattice constant larger than that of the semiconductor substrate and having a shape in which a side surface protrudes toward the channel region; The portion of the second semiconductor layer that includes and protrudes most by the protrusion is in contact with the semiconductor substrate.

  According to the present invention, it is possible to greatly increase the amount of distortion introduced into the channel region and improve the operation speed without causing a problem such as occurrence of a current leak path or deterioration of roll-off characteristics, and reliability can be improved. High-semiconductor device is realized.

  Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the drawings. In these embodiments, a MOS transistor is exemplified as a semiconductor device, but the present invention is not limited to a MOS transistor, and can be applied to a semiconductor device having a gate electrode, such as various MIS transistors and semiconductor memories.

-First embodiment-
In this embodiment, a p-channel MOS transistor is exemplified as the MOS transistor.

(Configuration of p-channel MOS transistor)
FIG. 1 is a schematic cross-sectional view showing the configuration of the p-channel MOS transistor according to the first embodiment.
In this p-channel MOS transistor, for example, an active region 1A is defined by an STI element isolation structure 2 formed in an element isolation region of a silicon substrate 1 having a (001) orientation. A well 10 is formed in the active region 1A by introducing an n-type impurity.

  In the active region 1A of the silicon substrate 1, a high-quality gate insulating film 3 made of, for example, a thermal oxide film or a SiON film is formed to a thickness of about 1.2 nm. On the gate insulating film 3, a gate electrode 4 made of a polycrystalline silicon film doped with p-type impurities and having a height of about 100 nm and a length of about 30 nm is formed.

  Sidewalls 5 are formed on both side surfaces of the gate electrode 4. In the sidewall 5, an Si epitaxial layer, which is a first semiconductor layer raised by, for example, epitaxial growth on a position higher than the interface position between the silicon substrate 1 and the gate insulating film 3, here, on the surface of the silicon substrate 1. The layer 6 is formed with a film thickness (height) of about 10 nm, for example. The Si epi layer 6 is preferably a non-doped layer into which impurities are not introduced. When impurities are introduced, a fringe capacitance is formed between the gate electrode 4 and the side wall 5, which causes the high frequency response characteristics to be impaired. Here, as the first semiconductor layer, instead of the Si epi layer 6, for example, a SiC epi layer containing carbon (C) in Si, a SiGe epi layer containing germanium (Ge) in Si, or C and Ge in Si. It is also suitable to form as a SiGeC epilayer.

  The side wall 5 is composed of a first side wall 11 that directly covers the side surface of the gate electrode 4 and a second side wall 12 that covers the surface of the first side wall 11 except for its lower portion. The Si epi layer 6 is formed under the two sidewalls 12.

The first sidewall 11 is formed so as to cover the surface of the silicon oxide film 11a and the thin silicon oxide film 11a formed so as to cover from the side surface of the gate electrode 4 to a part of the surface of the silicon substrate 1 ( That is, the silicon nitride film 11b is formed above the silicon substrate 1 via the silicon oxide film 11a.
The second sidewall 12 is formed so as to cover the surface of the silicon oxide film 12a and the thin silicon oxide film 12a formed so as to directly cover the surface of the silicon nitride film 11b over the Si epi layer 6 (that is, the silicon oxide film 12a). And a silicon nitride film 12b formed above the Si epi layer 6 via a silicon oxide film 12a.

  Here, the thicknesses of the silicon oxide film 11a, the silicon nitride film 11b, the silicon oxide film 12a, and the silicon nitride film 12b are, for example, about 3 nm, about 7 nm, about 5 nm, and about 35 nm.

  In the surface layer of the silicon substrate 1, a p-type impurity is introduced and an extension region 7 which is a shallow junction formed in alignment with the gate electrode 4, and partially overlaps with the extension region 7, so that the second side A source / drain region 8 which is a junction deeper than the extension region 7 formed in alignment with the wall 12 is formed.

  A recess 1 a is formed on the source / drain region 8 of the silicon substrate 1. Then, a second semiconductor layer is formed in the recess 1a so as to come into contact with the Si epi layer 6 and close to the gate electrode 4 through the Si epi layer 6 so that the upper portion protrudes from the surface of the silicon substrate 1. Yes. This second semiconductor layer is, for example, a SiGe layer formed by epitaxial growth, and is hereinafter referred to as a SiGe epilayer 9. A silicide layer 13 is formed on the gate electrode 4 and the SiGe epilayer 9. Here, as the second semiconductor layer, instead of the SiGe epilayer 9, for example, a SiC epilayer containing C in Si or a SiGeC epilayer containing C and Ge in Si is suitable.

Here, the recess 1 a has a shape in which the side surface of the inner wall protrudes toward the gate electrode 4. Since the SiGe epilayer 9 is embedded in the recess 1a, the side surface of the SiGe epilayer 9 protrudes toward the gate electrode 4 following the shape of the recess 1a, and the protruding apex 9a is the channel region 1b. Located in a shallow part. The SiGe epilayer 9 contains boron (B) having a Ge ratio of, for example, about 20% and a concentration of about 1 × 10 ²⁰ / cm ³ , and is raised from the surface of the silicon substrate 1 by, for example, about 20 nm. Is formed.

  In the present embodiment, the SiGe epilayer 9 introduces compressive strain into the channel region 1b through the epi-Si layer 6 raised above the surface of the channel region 1b immediately below the gate insulating film 3, and thereby the channel region 1b is in a state where compressive stress is applied. In this case, highly efficient compressive stress can be applied as follows.

  In the present embodiment, by forming the epi-Si layer 6 by adjusting the film thickness to a predetermined thickness before forming the recess 1a, the protruding vertex on the inner wall side surface of the recess 1a is positioned at a shallow portion of the channel region 1b. The concave portion 1a can be formed by a method described later. Along with this, the SiGe epilayer 9 formed in the recess 1a is similarly formed so that the protruding vertex 9a is located at a shallow predetermined portion of the channel region 1b. As shown in FIG. 2A, the compressive stress applied from the SiGe epilayer 9 to the channel region 1b is concentrated at the apex 9a (shown by a region surrounded by a broken line in FIG. 2), and the most compressive stress is necessary. A large compressive stress is efficiently applied to such a part. On the other hand, in the configuration without the conventional epi-Si layer 6 (for convenience, the same reference numerals are given to the structural members common to FIG. 2A), as shown in FIG. Since the formation position cannot be adjusted, the apex 9a is not located at the site where the most compressive stress is required in the channel region 1b, and sufficient compressive stress cannot be applied to the sufficient channel region 1b.

The epi-Si layer 6 is lattice-matched with SiGe having a larger lattice constant than Si at a contact portion with the SiGe epi-layer 9 (a region surrounded by a broken line in FIG. 1). With this configuration, expansion of the silicon substrate 1 in the substrate vertical direction is promoted, and the compressive strain from the SiGe epilayer 9 to the channel region 1b further increases.
From the above, in the present embodiment, the compressive stress applied to the channel region 1b is increased without taking measures to increase the Ge concentration of the SiGe epilayer 9 or to narrow the interval between the SiGe epilayers 9 and to increase the current. The operation speed of the transistor can be improved without causing a problem such as occurrence of a leak path or deterioration of roll-off characteristics.

Specifically, for the p-channel MOS transistor according to the present embodiment, a stress simulation is performed on the compressive stress applied to the channel region based on a comparison with a conventional p-channel MOS transistor having no epi-Si layer (for example, Patent Document 1). It was examined by experiment. The result is shown in FIG. In FIG. 3, the horizontal axis represents a separation distance with the central portion of the channel region as a reference (0 μm), and the vertical axis represents stress (compressive stress is a negative value). Here, as a conventional example, three types having slightly different side surface shapes of the SiGe epilayer are used, and in this embodiment, two types of the side wall formed by a silicon nitride film and a type formed by a silicon oxide film ( Accordingly, although slightly different from the above-described transistor configuration, it is not essentially different).
Thus, it can be seen that in the p-channel MOS transistor of this embodiment, the compressive stress applied to the channel region is increased more than twice as compared with the conventional one.

  Patent Document 2 discloses a configuration in which extension regions are raised on both sides of a gate electrode, and Patent Document 3 discloses a configuration in which SiGe is formed in an extension region immediately below both sides of a gate electrode. However, the configurations of Patent Documents 2 and 3 do not adopt a configuration in which SiGe is formed in the source / drain regions, and are different from the present invention.

(Manufacturing method of p-channel MOS transistor)
Hereinafter, a specific method for manufacturing the above-described p-channel MOS transistor will be described.
4 and 5 are schematic cross-sectional views showing the method of manufacturing the p-channel MOS transistor according to the first embodiment in the order of steps.

First, as shown in FIG. 4A, an STI element isolation structure 2, a well 10, a gate insulating film 3, and a gate electrode 4 are sequentially formed on a silicon substrate 1.
Specifically, first, for example, a silicon substrate 1 having a (001) plane orientation is prepared, and an element groove 1c is formed in an element isolation region of the silicon substrate 1 by, for example, STI (Shallow Trench Isolation), and the element groove 1c is formed. An insulating film such as a silicon oxide film is deposited by CVD or the like so as to be embedded, and the silicon oxide film is polished and planarized by chemical mechanical polishing (CMP). As a result, the STI element isolation structure 2 formed by filling the element trench 1c with the silicon oxide film is formed. An active region 1 </ b> A is defined on the silicon substrate 1 by the STI element isolation structure 2.

Next, n-type impurities, here phosphorus (P ⁺ ), are ion-implanted into the active region 1A under conditions of an acceleration energy of 360 keV and a dose of 3 × 10 ¹³ / cm ² , and activation annealing is performed. Thereby, the well 10 is formed in the active region 1A.

Next, a silicon oxide film or a silicon oxynitride film is deposited to a thickness of, for example, about 1.2 nm by a thermal oxidation method or a CVD method to form the gate insulating film 3.
Next, a polycrystalline silicon film (not shown) is deposited to a thickness of about 100 nm, for example, on the entire surface by CVD or the like. The polycrystalline silicon film and the gate insulating film 3 are processed into an electrode shape by lithography and anisotropic dry etching to form the gate electrode 4 via the gate insulating film 3 on the active region 1A.

Subsequently, as shown in FIG. 4B, a pair of extension regions 7 and first sidewalls 11 are sequentially formed.
More specifically, first, using the gate electrode 4 as a mask, a p-type impurity, here boron (B ⁺ ), is ion-implanted into the active region 1A under conditions of an acceleration energy of 0.3 keV and a dose of 1 × 10 ¹⁴ / cm ^2. Then, a pair of extension regions 7 are formed in the surface layer of the active region 1A on both sides of the gate electrode 4. The extension region 7 is formed by activating an impurity by an annealing process described later. Here, for convenience of illustration, the extension region 7 is clearly shown as being formed.

Next, for example, a silicon oxide film 11a is formed to a thickness of, for example, about 3 nm by a CVD method using a mixed gas of, for example, binary butylaminosilane and oxygen and a processing temperature of 400 ° C. to 600 ° C. Then, Si ₂ H ₆ , SiH ₄ The silicon nitride film 11b is formed to a thickness of, for example, about 7 nm by a CVD method using a mixed gas of Si source gas and NH ₃ gas or the like, or a mixed gas of binary butylaminosilane and NH ₃ gas at a processing temperature of 400 ° C. to 600 ° C. To form. Then, the entire surfaces of the silicon nitride film 11b and the silicon oxide film 11a are subjected to anisotropic dry etching (etchback) to leave the silicon oxide film 11a and the silicon nitride film 11b only on both side surfaces of the gate electrode 4. Thus, the first sidewall 11 is formed by laminating the silicon oxide film 11a and the silicon nitride film 11b. Here, the silicon oxide film 11a functions as an etching stopper for the silicon nitride film 11b during the etch back. A sufficient etching selectivity with the silicon substrate 1 cannot be maintained with only the silicon nitride film, and the silicon oxide film 11a can be additionally formed so that the desired and accurate etching of the silicon nitride film 11b becomes possible. .

Subsequently, as shown in FIG. 4C, a Si epi layer 6 is formed on the surface of the extension region 7.
Specifically, selective epitaxial growth of Si is performed, and a Si epitaxial layer 6 having a predetermined film thickness, here about 10 nm, is raised on the surface of the extension region 7. This is done by supplying a mixed gas of SiH ₄ , HCl, and H ₂ by LPCVD at a processing temperature of 550 ° C. to 700 ° C., so that the Si epi layer 6 is selectively formed only on the portion where the Si surface is exposed. Can be formed. At this time, since the Si surface is exposed also on the upper surface of the gate electrode 4, the poly-Si layer 6 is similarly formed. If necessary, only the poly-Si layer 6 grown on the gate electrode 4 is selectively etched with a mixed gas of H ₂ and HCl or Cl ₂ . For example, only the poly-Si layer 6 on the gate electrode 4 is etched without removing the Si epi layer 6 by exposure to a mixed gas of H ₂ having a partial pressure of 20 Torr and HCl having a partial pressure of 0.5 Torr at 700 ° C. Can do.

Subsequently, as shown in FIG. 4D, the second sidewall 12 and the source / drain region 8 are sequentially formed.
More specifically, first, for example, a silicon oxide film 12a is formed to a film thickness of, for example, about 5 nm by a CVD method at a processing temperature of 400 ° C. to 600 ° C. using, for example, a mixed gas of binary butylaminosilane and oxygen, and then Si ₂ H _6. A silicon nitride film 12b is formed, for example, by CVD using a mixed gas of Si source gas such as SiH ₄ and NH ₃ gas or a mixed gas of binary butylaminosilane and NH ₃ gas at a processing temperature of 400 ° C. to 600 ° C. It is formed to a thickness of about 35 nm. Then, the entire surfaces of the silicon nitride film 11b and the silicon oxide film 11a are subjected to anisotropic dry etching (etchback), and the silicon oxide film 12a and the silicon nitride film 12b are formed on both side surfaces of the first sidewall 11 and the Si epi layer 6. Leave only on a part of. Thus, the second sidewall 12 is formed by laminating the silicon oxide film 12a and the silicon nitride film 12b. Here, the silicon oxide film 12a functions as an etching stopper for the silicon nitride film 12b during the etch back. A sufficient etching selectivity with the silicon substrate 1 cannot be maintained with only the silicon nitride film, and the silicon oxide film 12a can be additionally formed so that the silicon nitride film 12b can be accurately etched. . A structure including the first and second sidewalls 11 and 12 is referred to as a sidewall 5.

Next, using the gate electrode 4 and the sidewall 5 as a mask, a p-type impurity, here boron (B ⁺ ), is ion-implanted into the active region 1A under the conditions of an acceleration energy of 10 keV and a dose of 3 × 10 ¹³ / cm ² . A source / drain region 8 partially overlapping with the extension region 7 is formed on the surface layer of the active region 1A on both sides of the second sidewall 12. Here, the ion implantation forms a junction for PN separation of the well 10 and the source / drain region 8, and doping is performed later for reducing contact resistance with a silicide layer to be formed later. This amount is sufficient because it is introduced into the SiGe epilayer at a high concentration.

  The source / drain region 8 is formed together with the extension region 7 by activating impurities by an annealing process described later. Here, for convenience of illustration, the source / drain region 8 is formed as an extension region 7 and source / drain regions. The drain region 8 is clearly shown.

Subsequently, as shown in FIG. 5A, a recess 1 a is formed in the Si epilayer 6 and the silicon substrate 1.
Specifically, a recess 1a having a depth of, for example, 30 nm is formed by anisotropic dry etching so as to penetrate through the Si epi layer 6 and cover the upper portion of the source / drain region 8 therebelow. At this time, the upper part of the poly Si layer 6 and the side wall 5 on the gate electrode 4 is removed by the anisotropic dry etching, and the Si epi layer 6 remains only under the second side wall 12.

Subsequently, as shown in FIG. 5B, the recess 1a is wet-etched.
Specifically, the recess 1a is wet-etched using TMAH (tetramethylammonium). As a specific example, wet etching is performed for about 10 seconds to 3 minutes with TMAH / H ₂ O at a dilution concentration of about 5% to 40% and a temperature of about 30 ° C. to 50 ° C. As a result, the recess 1a is further etched from the state of FIG. 5A by about 10 nm to 20 nm, here about 15 nm deep, and the inner wall side surface protrudes toward the gate electrode 4, and is formed on the inner wall side surface. A (111) flat surface is formed. In the present embodiment, the epitaxial Si layer 6 is formed to a predetermined thickness before the recess 1a is formed. Due to the presence of this epitaxial Si layer 6, the protruding vertex on the inner wall side surface of the recess 1a becomes the channel region 1b. It is adjusted so that it is located in a shallow part.

  Patent Document 1 discloses that by performing wet etching using TMAH subsequent to anisotropic dry etching, the inner wall side surface of the recess can be formed in a shape protruding toward the gate electrode. However, in patent document 1, since it does not have the epi-Si layer 6 of this embodiment, the position of the protrusion vertex of the inner wall side surface of a recessed part cannot be adjusted. In such a manufacturing method, the protruding apex of the inner wall side surface of the recess is located in a portion deeper in the substrate vertical direction than the surface of the channel region. Therefore, even if the SiGe epi layer is formed in the recess, the channel region is efficiently distorted. Can not be introduced.

  On the other hand, in the present embodiment, the inner wall of the recess 1a is formed by performing wet etching using TMAH on the recess 1a formed in the portion having the epitaxial Si layer 6 raised above the surface of the channel region 1b. The projecting apex of the side surface can be positioned in a shallow portion of the channel region 1b, that is, a portion where the most compressive stress is required, and a stronger strain can be efficiently applied to the channel portion 1b. Specifically, by appropriately controlling the film thickness (height) of the epi-Si layer 6, the anisotropic dry etching amount of the recess 1a, and the wet etching amount by TMAH to the recess 1a, the inner wall side surface of the recess 1a is controlled. Adjust the protruding vertex. As described above, the thickness (height) of the epi-Si layer 6 is about 10 nm, the anisotropic dry etching amount of the recess 1a is about 30 nm deep in the substrate vertical direction, and the wet etching amount by TMAH is deep in the substrate vertical direction. By setting the thickness to about 15 nm, the protruding apex of the inner wall side surface of the recess 1a is positioned at the site where the compressive stress is most required in the channel region 1b.

Subsequently, as shown in FIG. 5C, the SiGe epilayer 9 is formed in the recess 1a.
More specifically, by supplying a mixed gas of H ₂ , SiH ₄ , GeH ₄ , HCl, and B ₂ H ₆ by a CVD method at a processing temperature of 500 ° C. to 550 ° C., an exposed portion of Si, that is, a recess 1a. SiGe is selectively epitaxially grown on the inner wall of the substrate. Thus, the SiGe epilayer 9 is formed in the recess 1a so that the upper portion protrudes from the surface of the silicon substrate 1 and the side surface protrudes toward the gate electrode 4 following the shape of the recess 1a. The protruding vertex 9a of the SiGe epilayer 9 is located in a predetermined shallow portion of the channel region 1b. The SiGe epilayer 9 contains boron (B) having a Ge ratio of, for example, about 20% and a concentration of about 1 × 10 ²⁰ / cm ³ , and is raised from the surface of the silicon substrate 1 by, for example, about 20 nm. Here, it is formed to a thickness of about 70 nm.

Here, if necessary, a silicon layer (not shown) containing boron (B) may be selectively grown to a film thickness of, for example, 10 nm as a sacrificial layer for stably forming a silicide film described later. In this case, it is possible to perform selective growth similarly to the SiGe epilayer 9 by using a mixed gas of H ₂ , SiH ₄ , HCl, and B ₂ H ₆ .
Thereafter, activation annealing is performed to electrically activate each introduced impurity (including each impurity in the extension region 7, the source / drain region 8, and the SiGe epilayer 9).

Subsequently, as shown in FIG. 5D, silicide layers 13 are respectively formed on the gate electrode 4 and the SiGe epilayer 9 by a salicide process.
Specifically, a metal, here Ni (not shown), is deposited to a thickness of, for example, about 10 nm to 20 nm by sputtering or the like, and is subjected to rapid annealing (Rapid Thermal Annealing: RTA) at, for example, 300 ° C. The upper part of the electrode 4 and the upper part of the SiGe epilayer 9 are reacted. Thereby, NiSi is formed on the upper portion of Ni and the gate electrode 4 and on the upper portion of the SiGe epilayer 9. Thereafter, unreacted Ni is removed by washing using, for example, hydrogen sulfate sulfate. Thus, the silicide layer 13 made of NiSi is formed on the Ni and the gate electrode 4 and on the SiGe epilayer 9, respectively. As the metal, for example, an alloy containing Pt in Ni may be used instead of Ni.
Here, it is also preferable to form a silicide layer having a further low resistance by performing a heat treatment at 400 ° C. to 500 ° C. on the silicide layer 13.

  Thereafter, the p-channel MOS transistor is completed through subsequent processes such as formation of an interlayer insulating film, contact holes, and formation of wiring.

  As described above, according to the present embodiment, the amount of distortion introduced into the channel region 1b is significantly increased and the operation speed is improved without causing problems such as the occurrence of a current leak path and the deterioration of roll-off characteristics. Therefore, a highly reliable p-channel MOS transistor is realized.

(Modification)
Here, a modification of the first embodiment will be described.
In this example, the method of forming the recess 1a and the shape of the side surface of the inner wall are different from those of the first embodiment. In addition, this example is applicable also to the 2nd-4th embodiment mentioned later.
FIG. 6 is a schematic cross-sectional view showing the main steps in the method of manufacturing a p-channel MOS transistor according to a modification of the first embodiment.

In this example, as in the first embodiment, after the steps of FIG. 4A to FIG. 4D, the Si epi layer 6 and the silicon substrate 1 are formed as shown in FIG. The recess 1a is formed.
Specifically, the recess 1a having a depth of, for example, 45 nm is formed by, for example, chemical dry etching (CDE: a kind of isotropic dry etching) so as to penetrate through the Si epi layer 6 and cover the upper portion of the source / drain region 8 therebelow. Form. Here, for example, CDE is performed by plasma using a mixed gas of CF ₄ and O ₂ .

  At this time, the epitaxial Si layer 6 is formed to be adjusted to a predetermined thickness before forming the recess 1a. Due to the presence of the epitaxial Si layer 6, the protruding vertex on the inner wall side surface of the recess 1a is shallow in the channel region 1b. Adjusted to be located in the part. In this example, the inner wall side surface of the recess 1a is a gently curved surface as compared with the first embodiment.

  In this example, the protruding apex of the inner wall side surface of the recess 1a can be positioned in a shallow portion of the channel region 1b, that is, a portion requiring the most compressive stress, and a stronger strain can be efficiently applied to the channel portion 1b. become. Specifically, by appropriately controlling the film thickness (height) of the epi-Si layer 6 and the etching amount by CDE of the recess 1a, the protruding vertex of the inner wall side surface of the recess 1a is adjusted. As described above, when the film thickness (height) of the epi-Si layer 6 is about 10 nm and the etching amount by CDE of the recess 1a is about 45 nm in the vertical direction of the substrate, the protruding vertex of the inner wall side surface of the recess 1a can be obtained. In the channel region 1b, it is located at the site where the most compressive stress is required.

  Thereafter, similarly to the first embodiment, the p-channel MOS transistor shown in FIG. 6B is completed through the steps shown in FIGS. 5C and 5D and various post-processes. .

  As described above, according to this example, the amount of distortion introduced into the channel region 1b is significantly increased and the operation speed is improved without causing problems such as the occurrence of a current leak path and the deterioration of roll-off characteristics. Thus, a highly reliable p-channel MOS transistor is realized.

  In this example, the inner wall side surface of the recess 1a is not as steep as the inner wall side surface of the recess 1a in the first embodiment, but a sufficiently strong strain can be applied to the channel portion 1b. Further, since the recess 1a can be formed by a single etching process using CDE, the number of processes can be reduced.

-Second Embodiment-
In this embodiment, a p-channel MOS transistor is exemplified as a MOS transistor as in the first embodiment, but is different in that the configuration of the sidewall 5 in the final transistor structure is different. In addition, about the structural member etc. similar to 1st Embodiment, the same code | symbol is described and detailed description is abbreviate | omitted.

(Configuration of p-channel MOS transistor)
FIG. 7 is a schematic cross-sectional view showing the configuration of the p-channel MOS transistor according to the second embodiment.
The p-channel MOS transistor according to the present embodiment has substantially the same configuration as that of the first embodiment, but instead of the sidewall 5, a single layer, here, a sidewall 21 made of only a silicon oxide film is formed. Yes.

  In this embodiment, by providing the sidewall 21 made of a silicon oxide film having a Young's modulus lower than that of the silicon nitride film, it is more efficiently applied to the channel region 1b without canceling the compressive stress received from the SiGe epilayer 9. Is possible. According to the experimental results of the stress simulation shown in FIG. 3, it is predicted that the strain is stronger when the silicon oxide film is used as the sidewall material than the silicon nitride film.

(Manufacturing method of p-channel MOS transistor)
Hereinafter, a specific method for manufacturing the above-described p-channel MOS transistor will be described.
FIG. 8 is a schematic cross-sectional view showing main steps in the method of manufacturing the p-channel MOS transistor according to the second embodiment.

In the present embodiment, first, similarly to the first embodiment, the respective steps of FIGS. 4A to 5C are performed. Thereafter, as shown in FIG. 8A, the sidewall 5 is removed.
Specifically, first, the silicon nitride film 12b of the second sidewall 12 is removed by wet etching using, for example, phosphoric acid.
Next, the silicon oxide film 12a on the second sidewall 12 is removed by wet etching using, for example, an HF aqueous solution.
Next, the silicon nitride film 11b of the first sidewall 11 is removed by, for example, wet etching using phosphoric acid.
Next, the silicon oxide film 11a on the first sidewall 11 is removed by wet etching using, for example, an HF aqueous solution.

Subsequently, as shown in FIG. 8B, sidewalls 21 are formed.
More specifically, a silicon oxide film (not shown) is deposited to a thickness of, for example, about 40 nm to 80 nm on the entire surface by a CVD method using, for example, a mixed gas of binary butylaminosilane and oxygen at a processing temperature of 500 ° C. to 550 ° C. Then, the entire surface of the silicon oxide film is subjected to anisotropic dry etching (etchback), and the silicon oxide film is formed only on both side surfaces of the gate electrode 4 so as to include the Si epi layer 6 and cover a part of the SiGe epi layer 9. Leave. Thereby, the sidewall 21 is formed.

  Thereafter, similarly to the first embodiment, the p-channel MOS transistor is completed through the process shown in FIG. 5D and various subsequent processes.

  As described above, according to the present embodiment, the amount of distortion introduced into the channel region 1b is further greatly increased without causing problems such as the occurrence of a current leak path and the deterioration of the roll-off characteristics, and the operation speed is increased. Further improvement is possible, and a highly reliable p-channel MOS transistor is realized.

-Third embodiment-
In this embodiment, an n-channel MOS transistor is exemplified as the MOS transistor. In addition, about the structural member etc. similar to 1st Embodiment, the same code | symbol is described and detailed description is abbreviate | omitted.

(Configuration of n-channel MOS transistor)
FIG. 9 is a schematic cross-sectional view showing the configuration of the n-channel MOS transistor according to the third embodiment.
The p-channel MOS transistor according to the present embodiment has substantially the same configuration as that of the first embodiment, but a SiC epi layer 31 is formed instead of the SiGe epi layer 9 of the first embodiment.

Here, the recess 1 a has a shape in which the side surface of the inner wall protrudes toward the gate electrode 4. Since the SiC epi layer 31 is embedded in the recess 1a, the side surface of the SiC epi layer 31 protrudes toward the gate electrode 4 following the shape of the recess 1a, and the protruding apex 31a is the channel region 1b. Located in a shallow part. The SiC epi layer 31 contains phosphorus (P) having a C ratio of, for example, about 1% and a concentration of about 1 × 10 ²⁰ / cm ³ , and is raised from the surface of the silicon substrate 1 by, for example, a height of about 20 nm. Is formed.

  In the present embodiment, the SiC epilayer 31 introduces tensile strain into the channel region 1b through the epi-Si layer 6 raised above the surface of the channel region 1b immediately below the gate insulating film 3, thereby the channel region. Reference numeral 1b denotes a state in which a tensile stress is applied. In this case, highly efficient tensile stress can be applied as follows.

  In the present embodiment, by forming the epi-Si layer 6 by adjusting the film thickness to a predetermined thickness before forming the recess 1a, the protruding vertex on the inner wall side surface of the recess 1a is positioned at a shallow portion of the channel region 1b. The concave portion 1a can be formed by a method described later. Accordingly, the SiC epi layer 31 formed in the recess 1a is similarly formed so that the protruding apex 31a is located at a shallow predetermined portion of the channel region 1b. At the apex 31a, the tensile stress applied from the SiC epi layer 31 to the channel region 1b is concentrated, and a large tensile stress is efficiently applied to a portion where the most tensile stress is required. On the other hand, in the configuration without the conventional epi-Si layer 6, the formation position of the apex 31a cannot be adjusted, and therefore the apex 31a is not positioned at the site where the most tensile stress is required in the channel region 1b, and the channel region is sufficient. A sufficient tensile stress cannot be applied to 1b.

The epi-Si layer 6 is lattice-matched with SiC having a lattice constant smaller than that of Si at the contact portion with the SiC epi layer 31. With this configuration, shrinkage of the silicon substrate 1 in the substrate vertical direction is promoted, and tensile strain from the SiC epi layer 31 to the channel region 1b is further increased.
From the above, in the present embodiment, the tensile stress applied to the channel region 1b is increased without taking measures to increase the C concentration of the SiC epi layer 31 or narrow the interval between the SiC epi layers 31, and The operation speed of the transistor can be improved without causing a problem such as occurrence of a leak path or deterioration of roll-off characteristics.

(Manufacturing method of n-channel MOS transistor)
The present embodiment differs from the manufacturing method shown in FIGS. 4A to 5D in the first embodiment only in the process of FIG. 5C. Here, only the process of this embodiment which replaces the process of FIG.5 (c) is demonstrated.
FIG. 10 is a schematic cross-sectional view showing the main steps in the method for manufacturing an n-channel MOS transistor according to a modification of the third embodiment.

In this embodiment, after passing through each process of Fig.4 (a)-FIG.5 (b), as shown in FIG. 10, the SiC epilayer 31 is formed in the recessed part 1a.
Specifically, a mixed gas of H ₂ (hydrogen), SiH ₄ (monosilane), SiH ₃ CH ₃ (monomethylsilane), and PH ₃ (phosphine) is supplied by a CVD method at a processing temperature of 500 ° C. to 550 ° C. As a result, SiC is epitaxially grown on the exposed portion of Si, that is, on the inner wall of the recess 1a. At this time, amorphous or poly SiC grows on the insulating film. Thereafter, SiC on the insulating film is selectively etched with a mixed gas of H ₂ and Cl ₂ to leave only the epitaxial SiC grown in the recess 1a. Thereby, it is possible to selectively form epi SiC only in the recess. In general, selective growth employs a method of suppressing growth on the insulating film by adding HCl gas during growth, but in the case of SiC, HCl added during growth greatly deteriorates the crystallinity of SiC. Simultaneous addition of HCl during growth is not appropriate. Thereby, the SiC epi layer 31 is formed in the recess 1a so that the upper portion protrudes from the surface of the silicon substrate 1 and the side surface protrudes toward the gate electrode 4 following the shape of the recess 1a. The protruding vertex 31a of the SiC epi layer 31 is located at a shallow predetermined portion of the channel region 1b. The SiC epi layer 31 contains phosphorus (P) having a C ratio of, for example, about 1% and a concentration of about 1 × 10 ²⁰ / cm ³ , and is raised from the surface of the silicon substrate 1 by, for example, a height of about 20 nm. Here, it is formed to a thickness of about 70 nm.

Here, if necessary, a silicon layer (not shown) containing phosphorus (P) may be selectively grown to a film thickness of, for example, 10 nm as a sacrificial layer for stably forming a silicide film described later. In this case, the CVD method with a processing temperature of 500 ° C. to 550 ° C. is performed by growing the entire surface with a mixed gas of H ₂ (hydrogen), SiH ₄ (monosilane), and PH ₃ (phosphine), and then a mixed gas of H ₂ and Cl ₂ . Thus, only Si on the insulating film can be etched and selectively grown in the same manner as the SiC epi layer 31. Alternatively, Si may be selectively grown only on the epi-SiC and the gate electrode 4 by a mixed gas in which HCl (hydrogen chloride) is added to H ₂ (hydrogen), SiH ₄ (monosilane), and PH ₃ (phosphine).

    As described above, according to the present embodiment, the amount of distortion introduced into the channel region 1b is significantly increased and the operation speed is improved without causing problems such as the occurrence of a current leak path and the deterioration of roll-off characteristics. Thus, a highly reliable n-channel MOS transistor is realized.

-Fourth Embodiment-
In this embodiment, an n-channel MOS transistor is exemplified as a MOS transistor as in the third embodiment, but is different in that the configuration of the sidewall 5 in the final transistor structure is different. In addition, about the structural member etc. similar to 3rd Embodiment, the same code | symbol is described and detailed description is abbreviate | omitted.

(Configuration of p-channel MOS transistor)
FIG. 11 is a schematic cross-sectional view showing the configuration of the n-channel MOS transistor according to the fourth embodiment.
The n-channel MOS transistor according to the present embodiment has substantially the same configuration as that of the third embodiment, but instead of the sidewall 5, a single layer, here, a sidewall 41 made of only a silicon oxide film is formed. Yes.

  In the present embodiment, by providing the sidewall 41 made of a silicon oxide film having a Young's modulus lower than that of the silicon nitride film, the tensile stress received from the SiC epi layer 31 is more efficiently applied to the channel region 1b. Is possible.

(Manufacturing method of n-channel MOS transistor)
In the present embodiment, first, similarly to the third embodiment, the respective steps of FIG. 4A to FIG. 5B and FIG. 10 are performed. Thereafter, an n-channel MOS transistor is completed through the steps shown in FIGS. 8A, 8B, and 5D of the second embodiment and various post-processes.

  As described above, according to the present embodiment, the amount of distortion introduced into the channel region 1b is further greatly increased without causing problems such as the occurrence of a current leak path and the deterioration of the roll-off characteristics, and the operation speed is increased. Further improvement is possible, and a highly reliable n-channel MOS transistor is realized.

  In the above first to fourth embodiments, a p-channel MOS transistor or an n-channel MOS transistor is exemplified, but a CMOS transistor having both a p-channel MOS transistor and an n-channel MOS transistor on a silicon substrate is used. The present invention may be applied. In this case, the first or second embodiment (including the modification) is applied to the p-channel MOS transistor, the n-channel MOS transistor has a normal transistor structure, and the third or fourth n-channel MOS transistor has the third or fourth configuration. The embodiment is applied, and the p-channel MOS transistor has a normal transistor structure, the first or second embodiment (including the modified example) is applied to the p-channel MOS transistor, and the third is applied to the n-channel MOS transistor. Alternatively, the fourth embodiment may be applied.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Additional remark 1) The process of forming a gate insulating film and a gate electrode on a semiconductor substrate,
Forming a first sidewall on a side surface of the gate electrode;
Forming a first semiconductor layer on the semiconductor substrate adjacent to the first sidewall;
Forming a second sidewall on the first sidewall and on the first semiconductor layer;
Etching the first semiconductor layer and the semiconductor substrate to form a recess using the second sidewall as a mask;
Forming a second semiconductor layer in the recess. A method for manufacturing a semiconductor device, comprising:

(Appendix 2) After forming the second semiconductor layer, removing the first sidewall and the second sidewall;
The method for manufacturing a semiconductor device according to appendix 1, further comprising: forming a third sidewall on a side surface of the gate electrode.

  (Additional remark 3) The said 1st semiconductor layer is one selected from Si layer, SiGe layer, SiGeC layer, and SiC layer, The manufacturing method of the semiconductor device of Additional remark 1 or 2 characterized by the above-mentioned .

  (Additional remark 4) The said 2nd semiconductor layer is a SiGe layer, a SiGeC layer, or a SiC layer, The manufacturing method of the semiconductor device of any one of Additional remarks 1-3 characterized by the above-mentioned.

  (Supplementary note 5) The method for manufacturing a semiconductor device according to any one of supplementary notes 1 to 4, wherein in the step of forming the recess, isotropic etching is performed as the etching.

  (Supplementary note 6) The method for manufacturing a semiconductor device according to any one of supplementary notes 1 to 4, wherein in the step of forming the recess, dry etching and wet etching are sequentially performed as the etching.

  (Additional remark 7) The manufacturing method of the semiconductor device of Additional remark 6 characterized by performing the said wet etching using a TMAH solution.

(Appendix 8) a semiconductor substrate;
A gate insulating film formed on the semiconductor substrate;
A gate electrode formed on the gate insulating film;
A sidewall formed on a side surface of the gate insulating film;
The first semiconductor layer formed in a position higher than an interface position between the semiconductor substrate and the gate insulating film in contact with the sidewall;
And a second semiconductor layer embedded in the semiconductor substrate in contact with the first semiconductor layer.

  (Supplementary note 9) The semiconductor device according to claim 8, wherein a side surface of the second semiconductor layer protrudes toward the gate electrode.

  (Supplementary Note 10) The semiconductor device according to Supplementary Note 8 or 9, wherein the first semiconductor layer is one selected from a Si layer, a SiGe layer, a SiGeC layer, and a SiC layer.

  (Supplementary note 11) The semiconductor device according to any one of Supplementary notes 8 to 10, wherein the second semiconductor layer is one selected from a SiGe layer, a SiGeC layer, and a SiC layer.

  (Supplementary note 12) The sidewall is formed in contact with a side surface of the gate electrode, and the first sidewall formed in contact with the first sidewall and on the first semiconductor layer. The semiconductor device according to any one of appendices 8 to 11, wherein the semiconductor device is formed with two sidewalls.

  (Additional remark 13) The said sidewall is formed as a single layer, The semiconductor device of any one of Additional remark 8-11 characterized by the above-mentioned.

1 is a schematic cross-sectional view showing a configuration of a p-channel MOS transistor according to a first embodiment. It is a schematic sectional drawing which expands and shows the neighborhood of a SiGe epilayer. FIG. 6 is a characteristic diagram showing compressive stress applied to a channel region based on a comparison with a p-channel MOS transistor having no conventional epi-Si layer in the p-channel MOS transistor according to the present embodiment. FIG. 6 is a schematic cross-sectional view showing the method of manufacturing the p-channel MOS transistor according to the first embodiment in order of processes. FIG. 5 is a schematic cross-sectional view showing the method of manufacturing the p-channel MOS transistor according to the first embodiment in order of processes subsequent to FIG. 4. It is a schematic sectional drawing which shows the main processes in the manufacturing method of the p channel MOS transistor by the modification of 1st Embodiment. It is a schematic sectional drawing which shows the structure of the p channel MOS transistor by 2nd Embodiment. It is a schematic sectional drawing which shows the main processes in the manufacturing method of the p channel MOS transistor by 2nd Embodiment. It is a schematic sectional drawing which shows the structure of the n channel MOS transistor by 3rd Embodiment. It is a schematic sectional drawing which shows the main processes in the manufacturing method of the n channel MOS transistor by the modification of 3rd Embodiment. It is a schematic sectional drawing which shows the structure of the n channel MOS transistor by 4th Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 1A Active region 1a Recess 1b Channel region 1c Element groove 2 STI element isolation structure 3 Gate insulating film 4 Gate electrodes 5, 21, 41 Side wall 6 Si epi layer 7 Extension region 8 Source / drain region 9 SiGe epi layer 10 Well 11 First sidewall 11a, 11a Silicon oxide film 12 Second sidewall 12a, 12a Silicon nitride film 13 Silicide layer 31 SiC epi layer

Claims (13)

Forming a gate insulating film and a gate electrode on a semiconductor substrate, and forming a channel region in the semiconductor substrate ;
Forming a first sidewall on a side surface of the gate electrode;
Forming a non-doped first semiconductor layer on the semiconductor substrate adjacent to the first sidewall;
Forming a second sidewall on the first sidewall and on the non-doped first semiconductor layer;
Etching the non-doped first semiconductor layer and the semiconductor substrate using the second sidewall as a mask to form a recess;
Forming a second semiconductor layer in the recess. A method for manufacturing a semiconductor device, comprising:   The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the recess, isotropic etching is performed as the etching.   The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the recess, dry etching and wet etching are sequentially performed as the etching. A semiconductor substrate;
A gate insulating film formed on the semiconductor substrate;
A gate electrode formed on the gate insulating film;
A channel region formed in the semiconductor substrate;
A sidewall formed on a side surface of the gate electrode ;
A non-doped first semiconductor layer formed in a position higher than an interface position between the semiconductor substrate and the gate insulating film in contact with the sidewall;
A semiconductor device comprising: a second semiconductor layer embedded in the semiconductor substrate in contact with the non-doped first semiconductor layer. The semiconductor device according to claim 4, wherein the second semiconductor layer has a shape in which a side surface protrudes toward the channel region . Forming a gate insulating film and a gate electrode on a semiconductor substrate, and forming a channel region in the semiconductor substrate;
  Forming a first sidewall on a side surface of the gate electrode;
  Forming a first semiconductor layer on the semiconductor substrate adjacent to the first sidewall;
  Forming a second sidewall on the first sidewall and on the first semiconductor layer;
  Etching the first semiconductor layer and the semiconductor substrate to form a recess using the second sidewall as a mask;
  Forming in the recess a second semiconductor layer having a lattice constant larger than that of the first semiconductor layer and having a shape in which a side surface protrudes toward the channel region;
  A method for manufacturing a semiconductor device, comprising: A semiconductor substrate;
  A gate insulating film formed on the semiconductor substrate;
  A gate electrode formed on the gate insulating film;
  A channel region formed in the semiconductor substrate;
  A sidewall formed on a side surface of the gate electrode;
  A first semiconductor layer in contact with the sidewall and formed at a position higher than an interface position between the semiconductor substrate and the gate insulating film;
  A second semiconductor layer in contact with the first semiconductor layer and embedded in the semiconductor substrate;
  Including
  The semiconductor device, wherein the second semiconductor layer has a lattice constant larger than that of the first semiconductor layer, and has a side surface protruding toward the channel region. Forming a gate insulating film and a gate electrode on a semiconductor substrate, and forming a channel region in the semiconductor substrate;
  Forming a first sidewall on a side surface of the gate electrode;
  Forming a first semiconductor layer on the semiconductor substrate adjacent to the first sidewall;
  Forming a second sidewall on the first sidewall and on the first semiconductor layer;
  Etching the first semiconductor layer and the semiconductor substrate to form a recess using the second sidewall as a mask;
  Forming, in the recess, a second semiconductor layer having a lattice constant larger than that of the semiconductor substrate and having a shape in which a side surface protrudes toward the channel region;
  Including
  The method of manufacturing a semiconductor device, wherein the portion of the second semiconductor layer that protrudes most by the protrusion is in contact with the semiconductor substrate. A semiconductor substrate;
  A gate insulating film formed on the semiconductor substrate;
  A gate electrode formed on the gate insulating film;
  A channel region formed in the semiconductor substrate;
  A sidewall formed on a side surface of the gate electrode;
  A first semiconductor layer in contact with the sidewall and formed at a position higher than an interface position between the semiconductor substrate and the gate insulating film;
  A second semiconductor layer in contact with the first semiconductor layer, embedded in the semiconductor substrate, having a lattice constant larger than that of the semiconductor substrate and having a shape in which a side surface protrudes toward the channel region When
  Including
  The portion of the second semiconductor layer that protrudes most by the protrusion is in contact with the semiconductor substrate.   9. The method of manufacturing a semiconductor device according to claim 1, wherein a lattice constant of the second semiconductor layer is larger than a lattice constant of the first semiconductor layer. The semiconductor device according to claim 4, wherein a lattice constant of the second semiconductor layer is larger than a lattice constant of the first semiconductor layer. 11. The method of manufacturing a semiconductor device according to claim 6, wherein an upper surface of the first semiconductor layer is higher than an interface position between the semiconductor substrate and the gate insulating film. . The method for manufacturing a semiconductor device according to claim 1, wherein the second semiconductor layer has a shape in which a side surface protrudes toward the channel region.

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