US20140032795A1 - Input/output processing - Google Patents

Input/output processing Download PDF

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Publication number
US20140032795A1
US20140032795A1 US14/009,761 US201114009761A US2014032795A1 US 20140032795 A1 US20140032795 A1 US 20140032795A1 US 201114009761 A US201114009761 A US 201114009761A US 2014032795 A1 US2014032795 A1 US 2014032795A1
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Prior art keywords
data
data flow
lower device
flow identifier
host
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US14/009,761
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English (en)
Inventor
Michael R. Krause
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Hewlett Packard Enterprise Development LP
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Hewlett Packard Development Co LP
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Assigned to HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. reassignment HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KRAUSE, MICHAEL R.
Publication of US20140032795A1 publication Critical patent/US20140032795A1/en
Assigned to HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP reassignment HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2017—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where memory access, memory control or I/O control functionality is redundant
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques
    • G06F11/2025—Failover techniques using centralised failover control functionality
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2053—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where persistent mass storage functionality or persistent mass storage control functionality is redundant
    • G06F11/2056—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where persistent mass storage functionality or persistent mass storage control functionality is redundant by mirroring
    • G06F11/2066—Optimisation of the communication load
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
    • G06F11/2007—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication media
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/31—Providing disk cache in a specific location of a storage system
    • G06F2212/314—In storage network, e.g. network attached cache

Definitions

  • I/O protocols generally involve a large overhead of control commands associated with the information transmitted between the host and the peripheral device. For example, processing one Ethernet frame may involve 5 to 10 PCI transactions, which may result in a high degree of latency as well as inefficient use of the PCI bus or link.
  • the techniques used to improve latency and efficiency often introduce added degrees of complexity in an I/O transaction.
  • the peripheral device can improperly access the host memory and cause silent data corruption, which is data corruption that goes undetected possibly resulting in system instability. Accordingly, various memory protection protocols are followed to reduce the likelihood that a peripheral device will access memory not allocated to it.
  • the memory protection protocols add yet another level of complexity to the I/O processes.
  • FIG. 6 is a process flow diagram of an example of an inbound write operation, in accordance with an embodiment
  • FIG. 10 is a process flow diagram of a method of conducting a storage write, in accordance with an embodiment
  • the I/O processing system may include a processor-integrated upper I/O device, referred to herein as the “upper device,” and a lower I/O device, referred to herein as the “lower device.”
  • the upper device handles host resource management and error processing through a set of logic that is common to all I/O devices. Further, work queues, completion queues, data management structures, error handling structures, and other state information structures provisioned by the device driver are stored in resources associated with or integrated into the upper device.
  • the processor 102 may be configured with a coherency protocol that manages the consistency of data stored in the various memory resources available to the processor, such as the caches 116 and the main memory 114 .
  • the coherency protocol is used to notify all processes running in the coherency protocol of changes to shared values.
  • the upper device 106 operates in the coherency domain of the processor 102 , meaning that the upper device 106 is notified with regard to memory changes and provides notification to the other processors regarding memory accessed by the upper device 106 .
  • the I/O system 100 does not include a PCIe Root Complex or the associated Root ports associated with traditional PCIe local I/O systems.
  • the upper device 106 can control the flow of data between the memory resources associated with the processor 102 and the lower devices 104 .
  • the upper device 106 may be integrated with the processor 102 or may be included in the system 100 as a discrete I/O device operatively coupled to the processor 102 .
  • a processor 102 may have a plurality of upper devices 106 , for example, hundreds or thousands of upper devices 106 .
  • the upper device 106 may be integrated into the same circuit package or silicon chip as the processor 102 .
  • the upper device 106 may include a variety data flow resources such as data and control buffers, which reside in reserved registers of main memory 114 , upper-device integrated memory, processor-integrated memory such as cache 116 , discrete memory associated with the upper device 106 , or some combination thereof.
  • the data flow resources of the upper device 106 can include one or more transmit/receive queues 118 .
  • Each transmit/receive queue 118 can include a work queue 120 , receive queue 122 , and completion queue 124 used to process the various I/O operations received from or sent to the lower device 104 .
  • I/O operations can include configuration operations, status operations, error handling and notification, memory reads, and memory writes, among others.
  • the upper device 106 includes an I/O memory management unit (IOMMU) 130 used to identify physical memory address associated with memory read and write operations.
  • IOMMU 130 can also be used to validate memory access operations to ensure that a particular process attempting to access memory has the appropriate access rights for the memory address or addresses targeted by the process.
  • the IOMMU 130 can include a translation agent 132 and translation cache 134 .
  • the translation agent 132 may be configured to identify a physical memory address for memory read or write operations.
  • the translation cache 134 may be used to store memory address translations for more frequently used memory locations.
  • Each packet pushed from the lower device 104 to the upper device 106 or pushed from the upper device 104 to the lower device 106 will include one or more data flow identifiers, which are used to identify the targeted resources.
  • the lower device 104 does not operate in the coherency domain of the system 100 , meaning that it does not have knowledge of physical memory address and does not receive direct notification with regard to memory or processor cache control and update operations.
  • the data flow lookup table 154 may be a filter table, which associates each internal or external resource with a unique data flow identifier.
  • the data flow lookup table 154 may be populated, for example, by a device driver running on the processor 102 .
  • the device driver that populates the data flow lookup table 154 may be a general purpose device driver or a dedicated device driver associated with the specific device.
  • the data flow lookup table 154 may be used by the lower device 104 to target a specific resource of the upper device 106 when receiving data from or pushing data to the upper device 106 .
  • the specific configuration of the data flow lookup table 154 may vary depending on the particular implementation.
  • This parsed data may then be applied to the data flow lookup table 154 to identify a corresponding data flow identifier used for transferring the data to the upper device 106 .
  • Ethernet-based communications received by the lower device 104 from the upper device 106 may also include the same data flow identifier.
  • the lower device 104 may then use the data flow identifier to identify the corresponding fields used to generate an Ethernet frame to be transmitted to the external device.
  • the GPU-based lower device 104 may be shared by multiple virtual machines. Each virtual machine may be represented by a specific data flow identifier that allows the virtualization software to comprehend which set of upper devices 106 and lower resources 104 are being used by a given virtual machine. This may enable solutions to optimize the operations and improve scaling.
  • the receive queue element includes a data structure with a set of virtual memory addresses.
  • the upper device 106 can access the receive queue element and determine what portion of the packet corresponds with the different virtual address ranges.
  • the upper device 106 determines the real physical addresses and places or copies the data to these locations, which may or may not be contiguous.
  • the receive queue may contain an address where the network headers are to be written and an address where the data payload is to be written. The network headers are consumed by a network stack while the data payload may be directly placed in the application's memory, thus providing real copy avoidance.
  • the upper device 106 When the upper device 106 detects this flag, it targets the destination VM's resources, translates the destination buffers via the IOMMU 130 , and performs the appropriate data movement.
  • vSwitch software virtual switch
  • VB device-integrated Virtual Ethernet Bridge
  • the upper device 106 can also include a data cache 202 that holds data to be transmitted to or received from the lower device 104 .
  • the data cache 202 may be continuously updated to or from caches of the processor cores 108 , the memory controller 110 , or the main memory 110 through the coherency interface 200 . Furthermore, some processing related to the moving of packets, such as packet header manipulations, may be performed on the data stored to the data cache.
  • the upper device 106 also includes transmit/receive work queues 118 , which contain work requests initiated by a read or write request from the lower device 104 or a request from a processor core 108 to push data to the lower device 104 , for example. Each of the transmit/receive work queues 118 may be associated with a different data flow identifier.
  • the lower device 104 may implement one or more packet interfaces 300 .
  • Each packet interface 300 may communicate with one or more upper devices 106 through either point-to-point, bus-based, or switch-based fabrics.
  • the lower device 106 may communicate through two or more of the packet interfaces 300 to a given upper device 106 , which also supports two or more packet interfaces 208 .
  • the packet interfaces 300 / 208 may be configured as active-active, wherein all packet interfaces 300 / 208 are used to transmit and receive packets between the devices at the same time.
  • the packet interfaces 300 / 208 may also be configured as active-passive where one set of packet interfaces is active and the others are treated as stand by.
  • the I/O packet may include any suitable combination of fields, which may be used to identify the next steps to be taken by the upper device 106 or the lower device 104 to process the data.
  • the I/O packet 400 can include a destination data flow identifier 406 and a source data flow identifier 408 .
  • the upper device 106 and the lower device 104 may determine the destination of the payload data pushed to it using the destination data flow identifier 406 alone or in combination with the source data flow identifier 408 .
  • the source data flow identifier 408 may be useful when an upper device 106 is coupled to two or more lower devices 104 .
  • FIG. 6 is a process flow diagram of an example of an inbound write operation, in accordance with embodiments.
  • the inbound write operation is referred to by the reference number 600 .
  • an inbound write operation 600 may be initiated by the lower device 104 .
  • an inbound write operation 600 may be initiated by a process running on the lower device 104 or an event such as receipt of a packet by the lower device 104 from an external device.
  • the lower device 104 acquires a data flow identifier corresponding to the inbound write.
  • the upper device 106 Upon receipt of the data packets, the upper device 106 parses the I/O packet header to identify the corresponding data flow resources of the upper device 106 , based on the data flow identifiers contained in the packet header. For example, the flow identifier may be used to identify a receive queue corresponding to the inbound write. In embodiments, the receive queue includes a virtual memory address or lookup address associated with the write operation. As indicated by arrow 606 , the upper device 106 may then send an access control request and an address translation request to the IOMMU 130 using the corresponding virtual memory address or lookup address. The IOMMU 130 identifies a physical memory address corresponding to the operation and determines whether the requesting process has access rights to the corresponding memory address.
  • software may separately store the configuration information for the upper device 106 and the lower device 104 to memory 114 or 116 , including any subsequent updates should something change over time.
  • the memory may be, for example, a processor integrated memory or cache, discrete memory or cache, or upper device-integrated memory or cache.
  • an Ethernet device driver may be invoked.
  • resources of the upper device 106 may be allocated to the device driver, which programs the allocated resources with the appropriate memory gather list and any device-specific control information, including one or more data flow identifiers.
  • the lower device 104 may contain resource sets for one or more MAC addresses, and each data flow identifier constructed during the configuration process may identify one of these MAC resource sets.
  • the data flow resource may be configured with the source and destination MAC addresses to use as well as all of the information needed to construct an Ethernet frame.
  • the upper device 106 validates access rights, gathers the payload data and control information into a single packet, and pushes the packet to the lower device 104 . Data transfers that exceed a single local communication packet size can be segmented into multiple packets.
  • the upper device 106 updates the completion queue when it completes the last packet pushed to the lower device 104 .
  • FIG. 9 is a process flow diagram of a method of processing an inbound Ethernet frame, in accordance with embodiments.
  • the method is referred to by reference number 900 .
  • the processes described in blocks 902 - 906 may be performed by the lower device 104 and the processed described in blocks 908 - 914 may be performed by the upper device 106 .
  • the lower device 104 is an Ethernet-based communications device, such as a network interface card.
  • the upper device 106 sends the payload data to the coherency packet interface 200 and updates the corresponding completion queues. Unlike traditional PCI communications, the lower device 104 does not track any of the host resources.

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  • Engineering & Computer Science (AREA)
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  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
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  • Memory System Of A Hierarchy Structure (AREA)
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