US20130273726A1 - Method of fabricating semiconductor device including process monitoring pattern having overlapping input/output pad array area - Google Patents
Method of fabricating semiconductor device including process monitoring pattern having overlapping input/output pad array area Download PDFInfo
- Publication number
- US20130273726A1 US20130273726A1 US13/861,984 US201313861984A US2013273726A1 US 20130273726 A1 US20130273726 A1 US 20130273726A1 US 201313861984 A US201313861984 A US 201313861984A US 2013273726 A1 US2013273726 A1 US 2013273726A1
- Authority
- US
- United States
- Prior art keywords
- area
- forming
- internal
- monitoring pattern
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 125
- 238000012544 monitoring process Methods 0.000 title claims abstract description 103
- 238000000034 method Methods 0.000 title claims abstract description 80
- 230000008569 process Effects 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 230000002093 peripheral effect Effects 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims description 19
- 238000000059 patterning Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 129
- 238000012545 processing Methods 0.000 description 20
- 235000012431 wafers Nutrition 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 229910021332 silicide Inorganic materials 0.000 description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 11
- 239000000463 material Substances 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- 238000003491 array Methods 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 239000002184 metal Substances 0.000 description 6
- 230000015654 memory Effects 0.000 description 5
- 238000004891 communication Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000011982 device technology Methods 0.000 description 3
- 238000007667 floating Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 2
- 238000013500 data storage Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 230000006855 networking Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- Example embodiments of the inventive concepts relate to a semiconductor device and a method of fabricating the same, and more particularly, to technology for improving the productivity of semiconductor devices.
- a method of increasing the number of semiconductor chips per wafer may be used.
- a process of fabricating semiconductor devices is performed in units of wafers, and thus the cost of processing each wafer is the same.
- semiconductor chips obtained by processing one wafer are increased, reducing costs of the semiconductor devices and increasing the yield and productivity of the semiconductor devices is possible.
- the present invention provides a semiconductor device including a monitoring pattern in an input/output (I/O) pad array area.
- the present invention also provides a semiconductor module, an electronic circuit board, and an electronic system including the semiconductor device including a monitoring pattern in an I/O pad array area.
- the present invention also provides a method of fabricating a semiconductor device including a monitoring pattern in an I/O pad array area.
- the semiconductor device includes a process monitoring pattern and an input/output (I/O) pad array area, the process monitoring pattern including a lower layer having a peripheral area surrounding a first internal area, the first internal area exposed by an internal open area, an external structure on the peripheral area of the lower layer, and a first dam disposed in the peripheral area spaced apart from the external structure by an external open area, the first dam defining the first internal area.
- the peripheral area overlaps the input/output (I/O) pad array area of the semiconductor device.
- a method of fabricating a semiconductor device includes forming a first insulating layer on a lower layer overlapping an input/output (I/O) pad array area, the lower layer having a peripheral area surrounding a first internal area; patterning the first insulating layer to form an external structure on the peripheral area, the peripheral area having a quadrangular shape; forming a first dam in the peripheral area spaced apart from the external structure, the first dam defining the first internal area and having a quadrangular band shape; and exposing a surface of the lower layer between the external structure and the external dam to form an external open area, and the first internal area to form an internal open area.
- I/O input/output
- a method of fabricating a semiconductor device includes forming a process monitoring pattern on a substrate, wherein forming the process monitoring pattern includes, forming a lower layer on the substrate, the lower layer having a peripheral area surrounding a first internal area, forming an external structure on the peripheral area, the peripheral area having a quadrangular shape, and forming a first dam in the quadrangular peripheral area, the first dam defining the first internal area; and forming an input/output (I/O) pad array area overlapping the peripheral area.
- I/O input/output
- a semiconductor module includes a module board, a plurality of semiconductor devices disposed on the module board, and module contact terminals formed in a line at one edge of the module board and electrically connected with the semiconductor devices.
- At least one of the semiconductor devices includes a process monitoring pattern and an input/output (I/O) pad array area, the process monitoring pattern including a lower layer having a peripheral area surrounding a first internal area, the first internal area exposed by an internal open area, an external structure on the peripheral area of the lower layer, and a first dam disposed in the peripheral area spaced apart from the external structure by an external open area, the first dam defining the first internal area.
- the peripheral area overlaps the input/output (I/O) pad array area of the semiconductor device.
- an electronic circuit includes a circuit board, a microprocessor disposed on the circuit board, a main storage circuit configured to communicate with the microprocessor, and an I/O signal processing circuit configured to exchange instructions with the microprocessor.
- the main storage circuit includes at least one semiconductor device.
- the semiconductor device includes a process monitoring pattern and an input/output (I/O) pad array area, the process monitoring pattern including a lower layer having a peripheral area surrounding a first internal area, the first internal area exposed by an internal open area, an external structure on the peripheral area of the lower layer, and a first dam disposed in the peripheral area spaced apart from the external structure by an external open area, the first dam defining the first internal area.
- the peripheral area overlaps the input/output (I/O) pad array area of the semiconductor device.
- an electronic system includes a control unit, an I/O unit, and a storage unit.
- the storage unit includes at least one semiconductor device.
- the semiconductor device includes a process monitoring pattern and an input/output (I/O) pad array area, the process monitoring pattern including a lower layer having a peripheral area surrounding a first internal area, the first internal area exposed by an internal open area, an external structure on the peripheral area of the lower layer, and a first dam disposed in the peripheral area spaced apart from the external structure by an external open area, the first dam defining the first internal area.
- the peripheral area overlaps the input/output (I/O) pad array area of the semiconductor device.
- FIG. 1A is a schematic top view of a wafer that has been fabricated or is being fabricated according to an example embodiment of the inventive concepts, and FIG. 1B is an enlarged view of an area A shown in FIG. 1A ;
- FIGS. 2A through 5B show top views and longitudinal sectional views of process monitoring patterns according to example embodiments of the inventive concepts
- FIGS. 6A through 6G show top views and longitudinal sectional views illustrating a method of fabricating a process monitoring pattern according to example embodiments of the inventive concepts.
- FIGS. 7 through 9 are schematic diagrams of a semiconductor module, an electronic circuit board, and an electronic system including a semiconductor device including a process monitoring pattern according to example embodiments of the inventive concepts.
- first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concepts.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
- Example embodiments are described herein with reference to longitudinal sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present inventive concepts.
- FIG. 1A is a schematic top view of a wafer that has been fabricated or is being fabricated according to an example embodiment of the inventive concepts
- FIG. 1B is an enlarged view of an area A shown in FIG. 1A
- the wafer W may be a flat zone type or a notch type, and the drawings show the wafer W of the flat zone type as an example.
- the semiconductor chips C may also be formed in a variety of quadrangular shapes, and the drawings show the semiconductor chips C formed in a square shape as an example.
- each of the semiconductor chips C includes cell arrays CA and peripheral circuit arrays PC.
- peripheral circuit arrays PC peripheral circuit arrays PC disposed at the center include plural input/output (I/O) pad array areas PA.
- the semiconductor chips C include the cell arrays CA and the peripheral circuit arrays PC as circuit areas and the I/O pad array areas PA as non-circuit areas.
- the semiconductor chips C include the circuit arrays CA and PC and the I/O pad array areas PA.
- the term “non-circuit areas” should not be interpreted as solely referring to the I/O pad array areas PA.
- test pattern areas and/or key pattern areas for alignment may be formed in the external area of the semiconductor chips C, that is, the scribe lanes SL. Patterns formed in these pattern areas have various shapes according to needs. Also, to aid in understanding example embodiments of the inventive concepts, only the I/O pad array areas PA, and not particular circuit blocks, are shown in the peripheral circuit arrays PC.
- FIG. 1B is not a top view of a semiconductor chip in a specific semiconductor fabrication process but a top view of a semiconductor chip in a random one of all semiconductor fabrication processes.
- at least one of the plural I/O pad array areas PA is formed to overlap a monitoring pattern.
- an I/O pad array area may denote a lower area of an I/O pad. Specifically, an I/O pad is formed to be exposed on a surface of the semiconductor device.
- an I/O pad is one of the patterns formed on the highest level, and is formed near the back end process of semiconductor fabrication processes.
- no pattern is formed in the I/O pad array areas PA before an I/O pad is formed.
- monitoring patterns are formed in the I/O pad array areas PA before I/O pads are formed, so that an area on the wafer W occupied by the semiconductor chip C can be reduced, and the number of semiconductor chips on a wafer of a semiconductor process can be increased.
- Forming of monitoring patterns in the I/O pad array areas PA means that the monitoring patterns are formed to overlap the position where I/O pads are formed.
- an I/O pad array area denotes an area under a position where an I/O pad is formed.
- I/O pads, I/O pad array areas, and monitoring patterns have quadrangular shapes.
- FIG. 2A shows a schematic top view of a monitoring pattern formed in one of I/O pad array areas according to example embodiments of the inventive concepts, and a longitudinal sectional view of the monitoring pattern along line 2 A- 2 A′.
- a monitoring pattern 200 a is formed in an I/O pad array area.
- the monitoring pattern 200 a may include a lower layer 210 a , open areas 230 a and 250 a that expose a surface of the lower layer 210 a , and dams 240 a .
- the lower layer 210 a may be a semiconductor substrate or an insulating layer.
- the lower layer 210 a includes a peripheral area P and a first internal area I 1 .
- the lower layer 210 a may include silicon, silicon oxide, silicon nitride, silicon oxynitride, a metal, a metal silicide, or a metal compound.
- the monitoring pattern 200 a may be formed in external structures 220 a.
- the external structures 220 a may define the peripheral area P overlapping an I/O pad array area, or the monitoring pattern 200 a .
- the peripheral area P may be a quadrangular area.
- the external structures 220 a may include silicon oxide.
- the external structures 220 a may be formed on the same level as a material layer referred to as an interlayer insulating layer in a process of fabricating a cell area of a semiconductor device.
- the external structures 220 a may be formed on the same level as an interlayer insulating layer that is formed on a semiconductor substrate to be in direct contact with a surface of the semiconductor substrate.
- the external structures 220 a may be formed directly on the lower layer 210 a .
- the open areas 230 a and 250 a may include external open areas 230 a and an internal open area 250 a .
- the external open areas 230 a may be separated from the internal open area 250 a by the dams 240 a .
- the external open areas 230 a may be disposed between the external structures 220 a and the dams 240 a , and the internal open area 250 a may be disposed in the dams 240 a.
- the external open areas 230 a may be formed in a quadrangular band shape.
- the internal open area 250 a may be formed in a square shape.
- the dams 240 a may also be formed as a quadrangular band shape in the top view, and as a wall shape in the side view.
- the dams 240 a may be formed to be a closed shape. In other words, the dams 240 a may be formed in a single body without a discontinuous portion.
- the dams 240 a may be formed to the same height as an interlayer insulating layer in a process of fabricating a cell area of a semiconductor device.
- the dams 240 a have no specific restrictions on their width, but may be formed to a width of 1 ⁇ m to 3 ⁇ m.
- the width of the dams 240 a may be set to vary according to an experimentor's intention or a design rule, and characteristics of fabrication processes.
- the dams 240 a may prevent or reduce movement of materials flowing from the external structures 220 a , that is, the outside, to the internal open area 250 a , that is, the inside.
- the dams 240 a may prevent or reduce photoresist, an organic anti-reflection layer, a planarization material, etc. from excessively flowing to the internal open area 250 a and deteriorating the characteristic of planarity.
- the flow of materials toward the internal open area 250 a may cause the same result as applying a physical pressure to an edge, etc. of the external structures 220 a .
- the monitoring pattern 200 a , the I/O pad array area, etc. may not be accurately defined.
- One side of the external structures 220 a , the external open areas 230 a , or the dams 240 a has a length similar to the size of the I/O pad array area, which is about several tens of micrometers. For example, the length may be 50 ⁇ m to 100 ⁇ m.
- the monitoring pattern 200 a may be used to monitor a process of selectively removing a portion of an interlayer insulating layer during a process of fabricating a semiconductor device.
- the monitoring pattern 200 a may be used to monitor a process of forming a contact hole.
- FIG. 2B shows a schematic top view of a monitoring pattern formed in one of I/O pad array areas according to example embodiments of the inventive concepts, and a longitudinal sectional view of the monitoring pattern along line 2 B- 2 B′.
- a monitoring pattern 200 b is formed in an I/O pad array area.
- the monitoring pattern 200 b may include a lower layer 210 b , open areas 230 b , 235 b and 250 b that expose a surface of the lower layer 210 b , and dams 240 b and 245 b .
- the open areas 230 b , 235 b and 250 b may include external open areas 230 b , middle open areas 235 b and an internal open area 250 b .
- the dams 240 b and 245 b may include first dams 240 b and second dams 245 b .
- the monitoring pattern 200 b may also be formed in external structures 220 b .
- the external structures 220 b are described with reference to FIG. 2A .
- the external open areas 230 b may be formed between the external structures 220 b and the first dams 240 b .
- the middle open areas 235 b may be formed between the external dams 240 b and the second dams 245 b .
- the internal open area 250 b may be formed in the second internal area I 2 .
- the shapes and mutual relationships of the external, middle and internal open areas 230 b , 235 b and 250 b and the first and second dams 240 b and 245 b are described with reference to FIG. 2B .
- the monitoring pattern 200 b includes the first and second dams 240 b and 245 b , thereby better preventing or reducing the flow of fluid materials.
- FIG. 2C shows a schematic top view of a monitoring pattern formed in one of I/O pad array areas according to example embodiments of the inventive concepts, and a longitudinal sectional view of the monitoring pattern along line 2 C- 2 C′.
- a monitoring pattern 200 c is formed in an I/O pad array area.
- the monitoring pattern 200 c may include a lower layer 210 c , open areas 230 c and 235 c that expose a surface of the lower layer 210 c , and dams 240 c and 245 c .
- the open areas 230 c and 235 c may include external open areas 230 c and internal open areas 235 c .
- the external open areas 230 c are described with reference to FIGS. 2 A and 2 Bs.
- the internal open areas 235 c may be arranged as plural separate islands.
- the monitoring pattern 200 c may also be formed in external structures 220 c .
- the dams 240 c and 245 c include first dams 240 c and plural second dams 245 c arranged in the form of a lattice.
- the plural second dams 245 c may be formed extending in horizontal and vertical directions. In other words, the plural second dams 245 c may be formed as lattice shapes.
- FIG. 3A shows a schematic top view of a monitoring pattern formed in one of I/O pad array areas according to example embodiments of the inventive concepts, and a longitudinal sectional view of the monitoring pattern along line 3 A- 3 A′.
- a monitoring pattern 300 a is formed in an I/O pad array area.
- the monitoring pattern 300 a may include a lower layer 310 a , open areas 330 a and 350 a , dams 340 a , and a dummy pattern 360 a .
- the open areas 330 a and 350 a may include external open areas 330 a and an internal open area 350 a .
- the dams 340 a may be formed between the external open areas 330 a and the internal open area 350 a .
- the monitoring pattern 300 a may also be formed in external structures 320 a .
- the dummy pattern 360 a may be formed directly on the lower layer 310 a.
- the dummy pattern 360 a may include a gate stack structure.
- the dummy pattern 360 a may include a polysilicon layer 361 a , a silicide layer 363 a , a capping layer 365 a , and a sidewall 367 a of the gate stack structure.
- the silicide layer 363 a may be a metal layer.
- the capping layer 365 a may be formed of silicon nitride.
- the sidewall 367 a may include silicon oxide or silicon nitride.
- the dummy pattern 360 a may be formed as a large plate.
- the external open areas 330 a may expose a surface of the lower layer 310 a .
- the internal open area 350 a may expose a surface of the dummy pattern 360 a .
- the dams 340 a may overlap the edge of the dummy pattern 360 a . In other words, a portion of the dams 340 a may be formed on the dummy pattern 360 a.
- FIG. 3B shows a schematic top view of a monitoring pattern formed in one of I/O pad array areas according to example embodiments of the inventive concepts, and a longitudinal sectional view of the monitoring pattern along line 3 B- 3 B′.
- a monitoring pattern 300 b is formed in an I/O pad array area.
- the monitoring pattern 300 b may include a lower layer 310 b , open areas 330 b , 335 b and 350 b , dams 340 b and 345 b , and a dummy pattern 360 b .
- the open areas 330 b , 335 b and 350 b include external open areas 330 b and internal open areas 335 b and 350 b .
- the external open areas 330 b may be formed in a band shape between external structures 320 b and the external dams 340 b .
- the internal open areas 335 b and 350 b include first internal open areas 335 b and a second internal open area 350 b .
- the dams 340 b and 345 b include external dams 340 b and internal dams 345 b .
- the external dams 340 b may be formed in a band shape between the external open areas 330 b and the first internal open areas 335 b .
- the first internal open areas 335 b may be disposed in a band shape between the external dams 340 b and the internal dams 345 b.
- the internal dams 345 b may be formed in a band shape between the first internal open areas 335 b and the second internal open area 350 b .
- the dummy pattern 360 b may be formed directly on the lower layer 310 b .
- the dummy pattern 360 b may also include a gate stack structure. Respective components 361 b , 363 b , 365 b and 367 b of the dummy pattern 360 b are described with reference to FIG. 3A .
- the dummy pattern 360 b may also be formed as a large plate.
- the internal open areas 335 b and 350 b may expose a surface of the dummy pattern 360 b .
- the external open areas 330 b may expose a surface of the lower layer 310 b .
- the external dams 340 b may overlap the edge of the dummy pattern 360 b . In other words, a portion of the external dams 340 a may be formed on the dummy pattern 360 b .
- the internal dams 345 b may be formed on the dummy pattern 360 b.
- FIG. 3C shows a schematic top view of a monitoring pattern formed in one of I/O pad array areas according to example embodiments of the inventive concepts, and a longitudinal sectional view of the monitoring pattern along line 3 C- 3 C′.
- a monitoring pattern 300 c is formed in an I/O pad array area.
- the monitoring pattern 300 c may include a lower layer 310 c , open areas 330 c and 335 c , dams 340 c and 345 c , and a dummy pattern 360 c .
- Respective components 361 c 363 c , 365 c and 367 c included in the dummy pattern 360 c are described with reference to FIG. 3A .
- the monitoring pattern 300 c may also be formed in external structures 320 c .
- the open areas 330 c and 335 c include external open areas 330 c and internal open areas 335 c .
- the external open areas 330 c may expose a surface of the lower layer 310 c .
- the internal open areas 335 c may expose a surface of the dummy pattern 360 c .
- the internal open areas 335 c may be arranged as islands.
- the dams 340 c and 345 c include external dams 340 c and internal dams 345 c .
- the external dams 340 c may be formed in a band shape along the external open areas 330 c , and the internal dams 345 c may be formed as plural linear patterns that are parallel in horizontal and vertical directions and cross each other.
- the external dams 340 c and the internal dams 345 c may be physically connected.
- the external dams 340 c and the internal dams 345 c may be formed as lattice shapes.
- FIG. 4A shows a schematic top view of a monitoring pattern formed in one of I/O pad array areas according to example embodiments of the inventive concepts, and a longitudinal sectional view of the monitoring pattern along line 4 A- 4 A′.
- a monitoring pattern 400 a is formed in an I/O pad array area.
- the monitoring pattern 400 a may include a lower layer 410 a , open areas 430 a and 450 a , dams 440 a , and dummy patterns 460 a .
- the open areas 430 a and 450 a may include external open areas 430 a and an internal open area 450 a .
- the dams 440 a may be formed between the external open areas 430 a and the internal open area 450 a .
- the monitoring pattern 400 a may also be formed in external structures 420 a.
- the dummy patterns 460 a may be formed directly on the lower layer 410 a .
- the dummy patterns 460 a may include a gate stack structure.
- the dummy patterns 460 a may include a polysilicon layer 461 a , a silicide layer 463 a , a capping layer 465 a , and a sidewall 467 a of the gate stack structure.
- the silicide layer 463 a may include a metal layer.
- the capping layer 465 a may include silicon nitride.
- the sidewall 467 a may include silicon oxide or silicon nitride.
- the dummy patterns 460 a may be formed to be the same as or similar to the gate stack structure.
- the dummy patterns 460 a may further include a gate insulating layer between the lower layer 410 a and the polysilicon layer 461 a .
- the polysilicon layer 461 a may correspond to a floating gate
- the silicide layer 463 a may correspond to a control gate.
- An inter-gate dielectric layer (not shown) may be additionally formed between the polysilicon layer 461 a and the silicide layer 463 a.
- the inter-gate dielectric layer may be formed of plural layers of a silicon oxide layer/silicon nitride layer/silicon oxide layer.
- the dummy patterns 460 a may be formed along the dams 440 a in a shape that is the same as or similar to the dams 440 a .
- the dummy patterns 460 a may be formed in a quadrangular band shape or four bar shapes.
- all the dummy patterns 460 a need not be connected as a single body.
- the boundaries of the dummy patterns 460 a covered by the dams 440 a are indicated by dotted lines.
- the external open areas 430 a may expose a surface of the lower layer 410 a.
- the internal open area 450 a may expose the lower layer 410 a and also portions of the dummy patterns 460 a .
- the dams 440 a may overlap the edges of the dummy patterns 460 a . In other words, portions of the dams 440 a may be formed on the dummy patterns 460 a . Also, the dams 440 a may completely surround the dummy patterns 460 a . When the dummy patterns 460 a are completely surrounded by the dams 440 a , the internal open area 450 a may not expose the dummy patterns 460 a at all.
- FIG. 4B shows a schematic top view of a monitoring pattern formed in one of I/O pad array areas according to example embodiments of the inventive concepts, and a longitudinal sectional view of the monitoring pattern along line 4 B- 4 B′.
- a monitoring pattern 400 b is formed in an I/O pad array area.
- the monitoring pattern 400 b may include a lower layer 410 b , open areas 430 b and 450 b , dams 440 b , and dummy patterns 460 b .
- the open areas 430 b and 450 b include external open areas 430 b and an internal open area 450 b .
- the dams 440 b may be formed between the external open areas 430 b and the internal open area 450 b .
- the monitoring pattern 400 b may also be formed in external structures 420 b .
- the dummy patterns 460 b are described with reference to FIG. 4A .
- the dummy patterns 460 b may be formed in a plural parallel line or bar shape.
- the dummy patterns 460 b may be formed in a lattice shape referring to FIGS. 2C and 3C .
- the external open areas 430 b may expose the lower layer 410 b .
- the internal open area 450 b may expose only a surface of the lower layer 410 b , only portions of the dummy patterns 460 b , or one entire dummy pattern 460 b .
- the internal open area 450 b exposes a surface of the lower layer 410 b , two entire dummy patterns 460 b , and portions of other dummy patterns 460 b .
- the dummy patterns 460 b may be formed in a single body. However, the dummy patterns 460 b do not have to be formed in a single body. In other words, the dummy patterns 460 b may include at least one portion at which the dummy patterns 460 b are not physically connected with each other.
- FIG. 5A shows a schematic top view of a monitoring pattern formed in one of I/O pad array areas according to example embodiments of the inventive concepts, and a longitudinal sectional view of the monitoring pattern along line 5 A- 5 A′.
- a monitoring pattern 500 a is formed in an I/O pad array area.
- the monitoring pattern 500 a may include a lower layer 510 a , open areas 530 a and 550 a , dams 540 a , dummy patterns 560 a , and dummy contacts 570 a .
- the monitoring pattern 500 a may also be formed in external structures 520 a .
- the lower layer 510 a , the open areas 530 a and 550 a , the dams 540 a , and the dummy patterns 560 a are described with reference to FIGS. 4A and 4B .
- the dummy contacts 570 a may be formed between the dummy patterns 560 a .
- the dummy contacts 570 a may be formed in a pillar or plug shape in the side view.
- the dummy contacts 570 a may be formed as islands in the top view. However, the dummy contacts 570 a do not have to be formed as islands.
- the dummy contacts 570 a may be formed in a linear or bar shape to fill a valley between the dummy patterns 560 a .
- a plural number of the dummy contacts 570 a may be arranged in a direction in which the dummy patterns 560 a are extended.
- FIG. 5B shows a schematic top view of a monitoring pattern formed in one of I/O pad array areas according to example embodiments of the inventive concepts, and a longitudinal sectional view of the monitoring pattern along line 5 B- 5 B′.
- a monitoring pattern 500 b is formed in an I/O pad array area.
- the monitoring pattern 500 b may include a lower layer 510 b , open areas 530 b and 550 b , dams 540 b , dummy patterns 560 b , and dummy contacts 570 b .
- the monitoring pattern 500 b may also be formed in external structures 520 b .
- the lower layer 510 b , the open areas 530 b and 550 b , and the dams 540 b are described with reference to FIGS. 4B and 5A .
- the dummy patterns 560 b are described with reference to FIG. 4B .
- the dummy patterns 560 b may be formed in a plural parallel line or bar shape, or a lattice shape.
- the dummy contacts 570 b are described with reference to FIG. 5A .
- a plural number of the dummy contacts 570 b may also be arranged in a direction perpendicular to a direction in which the dummy patterns 560 b are extended.
- the dummy contacts 570 b may be arranged in the form of a lattice.
- the dummy contacts 570 b may be arranged in a “+” shape to be parallel in horizontal and vertical directions and cross each other, or in a “x” shape to be parallel with two diagonal lines crossing at right angles.
- FIG. 5A A method of fabricating a monitoring pattern in one of I/O pad array areas according to example embodiments of the inventive concepts will be described below.
- the monitoring pattern 500 a shown in FIG. 5A will be fabricated as an example of various monitoring patterns. Methods of fabricating respective monitoring patterns according to other example embodiments of the inventive concepts will be easily inferred from the following description.
- FIGS. 6A through 6G show schematic top views and longitudinal sectional views along line VI-VI', illustrating a method of fabricating a monitoring pattern in one of I/O pad array areas according to example embodiments of the inventive concepts.
- gate stack structures 660 are formed on a substrate 610 overlapping an I/O pad array area.
- the gate stack structures 660 may include polysilicon layers 661 , silicide layers 663 , capping layers 665 , and sidewalls 667 .
- the polysilicon layers 661 , the silicide layers 663 , the capping layers 665 , and the sidewalls 667 are typical components of the gate stack structures 660 to aid in understanding example embodiments of the inventive concepts.
- the gate stack structures 660 may be formed to have the same structure as a cell transistor, that is, a cell gate structure in a cell region of a semiconductor device.
- the gate stack structures 660 may further include a gate insulating layer between the substrate 610 and the polysilicon layers 661 , and the silicide layers 663 may include metal layers.
- the polysilicon layers 661 of the gate stack structures 660 may correspond to floating gates, and the silicide layers 663 may correspond to control gates.
- Inter-gate dielectric layers may be additionally formed between the floating gates and the control gates.
- the inter-gate dielectric layers may include plural layers of a silicon oxide layer/silicon nitride layer/silicon oxide layer.
- the gate stack structures 660 may be formed at the same time in the same process as a cell gate formed in the cell region of the semiconductor device.
- a first insulating layer 623 is formed on an entire area overlapping the I/O pad array area.
- the first insulating layer 623 may be formed to completely cover the gate stack structures 660 .
- the first insulating layer 623 is a silicon oxide layer, and may be formed of the same material and/or in the same process as an interlayer insulating layer formed in the cell region of the semiconductor device.
- the first insulating layer pattern 623 a may include contact holes 671 .
- the contact holes 671 may expose a surface of the substrate 610 between the adjacent gate stack structures 660 .
- the contact holes 671 may be formed as islands at separate positions.
- the contact holes 671 may be formed in a contact forming process in which the cell region of the semiconductor device is formed. This process is also referred to as a contact pad hole forming process, a landing pad hole forming process, a lower contact hole forming process, etc.
- plugs 675 that fill the contact holes 671 are formed on the first insulating layer pattern 623 a .
- the plugs 675 may include silicon.
- the plugs 675 may be formed of the same material and/or in the same process as a cell contact plug formed in the cell region of the semiconductor device.
- the cell contact plug is also referred to as a contact pad, a landing pad, a lower contact plug, a self-aligned contact, etc.
- a planarization process is performed to form contact plugs 670 .
- An etch-back process or a chemical mechanical polishing (CMP) process may be performed as the planarization process.
- CMP chemical mechanical polishing
- the height of the first insulating pattern 623 a may be reduced to form a first insulating pattern 623 b.
- a second insulating layer 625 is formed all over the contact plugs 670 and the first insulating layer pattern 623 b .
- the second insulating layer 625 may include a silicon oxide layer, and be formed of the same material and/or in the same process as an interlayer insulating layer among processes of forming various interlayer insulating layers in the cell region of the semiconductor device.
- the second insulating layer 625 may be formed in one of processes of forming interlayer insulating layers on higher levels than the upper surfaces of the cell gates in the cell region.
- the boundary between the first insulating layer 623 b and the second insulating layer 625 may be disappeared.
- the boundary is indicated by a dotted line for an imaginary in the drawing.
- the external structures 620 may define an area in which a monitoring pattern 600 is formed.
- the open areas 630 and 650 may include external open areas 630 and an internal open area 650 .
- the external open areas 630 may expose a surface of the substrate 610
- the internal open area 650 may exposes the surface of the substrate 610 , portions of the gate stack structures 660 , and surfaces of the plugs 670 .
- the external open areas 630 may be formed in a quadrangular band shape along the external structures 620 .
- the internal open area 650 may be formed in a large quadrangular window shape.
- the dams 640 may be disposed in quadrangular band shapes between the external open areas 630 and the internal open area 650 .
- FIG. 7 is a schematic diagram of a semiconductor module including a semiconductor device including a process monitoring pattern overlapping an I/O pad array area according to example embodiments of the inventive concepts.
- a semiconductor module 700 according to example embodiments of the inventive concepts includes a module substrate 710 , a plurality of semiconductor devices 720 disposed on the module substrate 710 , and module contact terminals 730 formed in a line on one edge of the module substrate 710 and electrically connected with the semiconductor devices 720 .
- the module substrate 710 may be a printed circuit board (PCB). Both surfaces of the module substrate 710 may be used.
- the semiconductor devices 720 may be disposed on the front side and the back side of the module substrate 710 . It is shown in FIG. 7 that eight semiconductor devices 720 are disposed on the front side of the module substrate 710 , but this is merely an example.
- the semiconductor module 700 may further include a logic semiconductor device for controlling the semiconductor devices or the semiconductor packages.
- the number of the semiconductor devices 720 constituting the semiconductor module 700 shown in FIG. 7 is variable.
- At least one of the semiconductor devices 720 may include a process monitoring pattern overlapping an I/O pad array area according to example embodiments of the inventive concepts.
- the module contact terminals 730 may be formed of a metal, and may have resistance to oxidation.
- the module contact terminals 730 may be set to vary according to the standard of the semiconductor module 700 . Thus, the number of module contact terminals 730 shown in the drawing is not meaningful.
- FIG. 8 is a schematic block diagram of an electronic circuit board including a semiconductor device including a process monitoring pattern overlapping an I/O pad array area according to example embodiments of the inventive concepts.
- an electronic circuit board 800 according to example embodiments of the inventive concepts includes a microprocessor 820 disposed on a circuit board 810 , a main storage circuit 830 and a supplementary storage circuit 840 communicating with the microprocessor 820 , an input signal processing circuit 850 sending an instruction to the microprocessor 820 , an output signal processing circuit 860 receiving an instruction from the microprocessor 820 , and a communicating signal processing circuit 870 exchanging electrical signals with other circuit boards. Arrows denote paths through which electrical signals can be transferred.
- the microprocessor 820 may receive and process a variety of electrical signals to output the processed results, and may control other components of the electronic circuit board 810 .
- the microprocessor 820 may be, for example, a central processing unit (CPU), a main control unit (MCU), etc.
- the main storage circuit 830 may temporarily store data that is always or frequently required for pre- and post-processing data.
- the main storage circuit 830 requires a rapid response and thus may be a semiconductor memory.
- the main storage circuit 830 may be a semiconductor memory referred to as cache, or may include a static RAM (SRAM), a DRAM, a resistive RAM (RRAM), and applied semiconductor memories, for example, a utilized RAM, a ferro-electric RAM, a fast cycle RAM, a phase changeable RAM, a magnetic RAM, and other semiconductor memories.
- the main storage circuit 830 may be volatile or non-volatile, and may include a RAM.
- the main storage circuit 830 may include at least one semiconductor device including a process monitoring pattern overlapping an I/O pad array area according to an example embodiment of the inventive concepts, or at least one semiconductor module 700 including the semiconductor device.
- the supplementary storage circuit 840 is a mass storage device, and may be a non-volatile semiconductor memory such as a flash memory, a hard disk drive (HDD) using a magnetic field, or a compact disk (CD) drive using light.
- the supplementary storage circuit 840 may be used to store a relatively large amount of data without requiring a higher speed than the main storage circuit 830 .
- the supplementary storage circuit 840 may include a random access memory and/or non-random access memory such as a non-volatile storage device.
- the supplementary storage circuit 840 may include at least one semiconductor device including a process monitoring pattern overlapping an I/O pad array area according to an example embodiment of the inventive concepts, or at least one semiconductor module 700 including the semiconductor device.
- the input signal processing circuit 850 may convert an external instruction into an electrical signal or transfer an electrical signal received from the outside to the microprocessor 820 .
- the instruction or electrical signal received from the outside may be an operation instruction, an electrical signal to be processed, or data to be stored.
- the input signal processing circuit 850 may be a terminal signal processing circuit that processes a signal transferred from a keyboard, a mouse, a touchpad, an image recognition device, or a variety of sensors, an image signal processing circuit that processes an image signal input from a scanner or a camera, various sensors or an input signal interface, or so on.
- the input signal processing circuit 850 may include at least one semiconductor device including a process monitoring pattern overlapping an I/O pad array area according to an example embodiment of the inventive concepts, or at least one semiconductor module 700 including the semiconductor device.
- the output signal processing circuit 860 may be a component for transferring an electrical signal processed by the microprocessor 820 to the outside.
- the output signal processing circuit 860 may be a graphic card, an image processor, an optical transducer, a beam panel card, or an interface circuit having various functions.
- the output signal processing circuit 860 may include at least one semiconductor device including a process monitoring pattern overlapping an I/O pad array area according to an example embodiment of the inventive concepts, or at least one semiconductor module 700 including the semiconductor device.
- the communicating signal processing circuit 870 is a component for directly exchanging electrical signals with another electronic system or another circuit board not through the input signal processing circuit 850 or the output signal processing circuit 860 .
- the communicating signal processing circuit 870 may be a modem, a local area network (LAN) card, various interface circuits, etc. of a personal computer (PC) system.
- the communicating signal processing circuit 870 may include at least one semiconductor device including a process monitoring pattern overlapping an I/O pad array area according to an example embodiment to the inventive concepts, or at least one semiconductor module 700 including the semiconductor device.
- FIG. 9 is a schematic block diagram of an electronic system including a semiconductor device including a process monitoring pattern overlapping an I/O pad array area according to example embodiments of the inventive concepts, or a semiconductor module including the semiconductor device.
- an electronic system 900 according to example embodiments of the inventive concepts includes a control unit 910 , an input unit 920 , an output unit 930 , and a storage unit 940 , and may further include a communication unit 950 and/or an operation unit 960 .
- the control unit 910 may control the electronic system 900 and all the respective units.
- the control unit 910 may be considered a central processor or a central controller, and may include the electronic circuit board 800 according to example embodiments of the inventive concepts. Also, the control unit 910 may include at least one semiconductor device including a process monitoring pattern overlapping an I/O pad array area according to an example embodiment of the inventive concepts, or at least one semiconductor module 700 including the semiconductor device.
- the input unit 920 may send an electrical instruction signal to the control unit 910 .
- the input unit 920 may be a keyboard, a keypad, a mouse, a touchpad, an image recognizer such as a scanner, or various input sensors.
- the input unit 920 may include at least one semiconductor device including a process monitoring pattern overlapping an I/O pad array area according to an example embodiment of the inventive concepts, or at least one semiconductor module 700 including the semiconductor device.
- the output unit 930 may receive the electrical instruction signal from the control unit 910 and output a result processed by the electronic system 900 .
- the output unit 930 may be a monitor, a printer, a beam projector, or various mechanical devices.
- the output unit 930 may include at least one semiconductor device including a process monitoring pattern overlapping an I/O pad array area according to an example embodiment of the inventive concepts, or at least one semiconductor module 700 including the semiconductor device.
- the storage unit 940 may be a component for temporarily or permanently storing an electrical signal that will be processed or has been processed by the control unit 910 .
- the storage unit 940 may be physically and electrically connected or combined with the control unit 910 .
- the storage unit 940 may be a semiconductor memory, a magnetic storage device such as a HDD, an optical storage device such as a CD, or a server having other data storage functions.
- the storage unit 940 may include at least one semiconductor device including a process monitoring pattern overlapping an I/O pad array area according to an example embodiment of the inventive concepts, or at least one semiconductor module 700 including the semiconductor device.
- the communication unit 950 may receive the electrical instruction signal from the control unit 910 and send or receive an instruction signal to or from another electronic system.
- the communication unit 950 may be a wired transceiver device such as a modem and a LAN card, a wireless transceiver device such as a wireless broadband (WiBro) interface, an infrared port, etc.
- the communication unit 950 may include at least one semiconductor device including a process monitoring pattern overlapping an I/O pad array area according to an example embodiment of the inventive concepts, or at least one semiconductor module 700 including the semiconductor device.
- the operation unit 960 may perform a physical or mechanical operation according to an instruction of the control unit 910 .
- the operation unit 960 may be a component that performs a mechanical operation, such as a plotter, an indicator, and an up/down operator.
- An electronic system may be a computer, a network server, a networking printer or scanner, a wireless controller, a terminal for mobile communication, an exchanger, or an electronic product performing other programmed operations.
- a monitoring pattern is formed to overlap an I/O pad array area. Accordingly, reducing the width or area of a scribe lane may be possible. Also, an area on a wafer occupied by the semiconductor chip can be reduced, and thus the productivity of the semiconductor device can be improved.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
- This application is a divisional application of U.S. application Ser. No. 12/962,991, filed Dec. 8, 2010, now allowed, which claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2010-0010515 filed on Feb. 4, 2010, the disclosure of which is hereby incorporated by reference in its entirety.
- 1. Field
- Example embodiments of the inventive concepts relate to a semiconductor device and a method of fabricating the same, and more particularly, to technology for improving the productivity of semiconductor devices.
- 2. Description of Related Art
- To improve the productivity of semiconductor devices, a method of increasing the number of semiconductor chips per wafer may be used. A process of fabricating semiconductor devices is performed in units of wafers, and thus the cost of processing each wafer is the same. Thus, when semiconductor chips obtained by processing one wafer are increased, reducing costs of the semiconductor devices and increasing the yield and productivity of the semiconductor devices is possible.
- The present invention provides a semiconductor device including a monitoring pattern in an input/output (I/O) pad array area. The present invention also provides a semiconductor module, an electronic circuit board, and an electronic system including the semiconductor device including a monitoring pattern in an I/O pad array area. The present invention also provides a method of fabricating a semiconductor device including a monitoring pattern in an I/O pad array area.
- In accordance with an example embodiment of the inventive concepts, the semiconductor device includes a process monitoring pattern and an input/output (I/O) pad array area, the process monitoring pattern including a lower layer having a peripheral area surrounding a first internal area, the first internal area exposed by an internal open area, an external structure on the peripheral area of the lower layer, and a first dam disposed in the peripheral area spaced apart from the external structure by an external open area, the first dam defining the first internal area. The peripheral area overlaps the input/output (I/O) pad array area of the semiconductor device.
- In accordance with another example embodiment of the inventive concepts, a method of fabricating a semiconductor device includes forming a first insulating layer on a lower layer overlapping an input/output (I/O) pad array area, the lower layer having a peripheral area surrounding a first internal area; patterning the first insulating layer to form an external structure on the peripheral area, the peripheral area having a quadrangular shape; forming a first dam in the peripheral area spaced apart from the external structure, the first dam defining the first internal area and having a quadrangular band shape; and exposing a surface of the lower layer between the external structure and the external dam to form an external open area, and the first internal area to form an internal open area.
- In accordance with still another example embodiment of the inventive concepts, a method of fabricating a semiconductor device includes forming a process monitoring pattern on a substrate, wherein forming the process monitoring pattern includes, forming a lower layer on the substrate, the lower layer having a peripheral area surrounding a first internal area, forming an external structure on the peripheral area, the peripheral area having a quadrangular shape, and forming a first dam in the quadrangular peripheral area, the first dam defining the first internal area; and forming an input/output (I/O) pad array area overlapping the peripheral area.
- In accordance with yet another example embodiment of the inventive concepts, a semiconductor module includes a module board, a plurality of semiconductor devices disposed on the module board, and module contact terminals formed in a line at one edge of the module board and electrically connected with the semiconductor devices. At least one of the semiconductor devices includes a process monitoring pattern and an input/output (I/O) pad array area, the process monitoring pattern including a lower layer having a peripheral area surrounding a first internal area, the first internal area exposed by an internal open area, an external structure on the peripheral area of the lower layer, and a first dam disposed in the peripheral area spaced apart from the external structure by an external open area, the first dam defining the first internal area. The peripheral area overlaps the input/output (I/O) pad array area of the semiconductor device.
- In accordance with yet another example embodiment of the inventive concepts, an electronic circuit includes a circuit board, a microprocessor disposed on the circuit board, a main storage circuit configured to communicate with the microprocessor, and an I/O signal processing circuit configured to exchange instructions with the microprocessor. The main storage circuit includes at least one semiconductor device. The semiconductor device includes a process monitoring pattern and an input/output (I/O) pad array area, the process monitoring pattern including a lower layer having a peripheral area surrounding a first internal area, the first internal area exposed by an internal open area, an external structure on the peripheral area of the lower layer, and a first dam disposed in the peripheral area spaced apart from the external structure by an external open area, the first dam defining the first internal area. The peripheral area overlaps the input/output (I/O) pad array area of the semiconductor device.
- In accordance with yet another example embodiment of the inventive concepts, an electronic system includes a control unit, an I/O unit, and a storage unit. The storage unit includes at least one semiconductor device. The semiconductor device includes a process monitoring pattern and an input/output (I/O) pad array area, the process monitoring pattern including a lower layer having a peripheral area surrounding a first internal area, the first internal area exposed by an internal open area, an external structure on the peripheral area of the lower layer, and a first dam disposed in the peripheral area spaced apart from the external structure by an external open area, the first dam defining the first internal area. The peripheral area overlaps the input/output (I/O) pad array area of the semiconductor device.
- Other details of example embodiments of the inventive concepts are included in detailed description and drawings.
- The foregoing and other features and advantages of the inventive concepts will be apparent from the more particular description of example embodiments of the inventive concepts, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the inventive concepts. In the drawings:
-
FIG. 1A is a schematic top view of a wafer that has been fabricated or is being fabricated according to an example embodiment of the inventive concepts, andFIG. 1B is an enlarged view of an area A shown inFIG. 1A ; -
FIGS. 2A through 5B show top views and longitudinal sectional views of process monitoring patterns according to example embodiments of the inventive concepts; -
FIGS. 6A through 6G show top views and longitudinal sectional views illustrating a method of fabricating a process monitoring pattern according to example embodiments of the inventive concepts; and -
FIGS. 7 through 9 are schematic diagrams of a semiconductor module, an electronic circuit board, and an electronic system including a semiconductor device including a process monitoring pattern according to example embodiments of the inventive concepts. - Various embodiments will now be described more fully with reference to the accompanying drawings in which some embodiments are shown. These inventive concepts may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough and complete and fully conveys the inventive concepts to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.
- It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numerals refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
- It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concepts.
- Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
- The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present inventive concepts. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
- Example embodiments are described herein with reference to longitudinal sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present inventive concepts.
- Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concepts belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
-
FIG. 1A is a schematic top view of a wafer that has been fabricated or is being fabricated according to an example embodiment of the inventive concepts, andFIG. 1B is an enlarged view of an area A shown inFIG. 1A . Referring toFIG. 1A , several tens to hundreds of semiconductor chips C are arranged in the form of a lattice on a wafer W. Scribe lanes SL are between the semiconductor chips C. The wafer W may be a flat zone type or a notch type, and the drawings show the wafer W of the flat zone type as an example. The semiconductor chips C may also be formed in a variety of quadrangular shapes, and the drawings show the semiconductor chips C formed in a square shape as an example. - Referring to
FIG. 1B , each of the semiconductor chips C includes cell arrays CA and peripheral circuit arrays PC. Among the peripheral circuit arrays PC, peripheral circuit arrays PC disposed at the center include plural input/output (I/O) pad array areas PA. In other words, the semiconductor chips C include the cell arrays CA and the peripheral circuit arrays PC as circuit areas and the I/O pad array areas PA as non-circuit areas. In other words, the semiconductor chips C include the circuit arrays CA and PC and the I/O pad array areas PA. The term “non-circuit areas” should not be interpreted as solely referring to the I/O pad array areas PA. In the external area of the semiconductor chips C, that is, the scribe lanes SL, a variety of test pattern areas and/or key pattern areas for alignment may be formed. Patterns formed in these pattern areas have various shapes according to needs. Also, to aid in understanding example embodiments of the inventive concepts, only the I/O pad array areas PA, and not particular circuit blocks, are shown in the peripheral circuit arrays PC. - As mentioned above,
FIG. 1B is not a top view of a semiconductor chip in a specific semiconductor fabrication process but a top view of a semiconductor chip in a random one of all semiconductor fabrication processes. According to an example embodiment of the inventive concepts, at least one of the plural I/O pad array areas PA is formed to overlap a monitoring pattern. In an example embodiment of the inventive concepts, an I/O pad array area may denote a lower area of an I/O pad. Specifically, an I/O pad is formed to be exposed on a surface of the semiconductor device. - In other words, an I/O pad is one of the patterns formed on the highest level, and is formed near the back end process of semiconductor fabrication processes. In general, no pattern is formed in the I/O pad array areas PA before an I/O pad is formed. According to an example embodiment of the inventive concepts, monitoring patterns are formed in the I/O pad array areas PA before I/O pads are formed, so that an area on the wafer W occupied by the semiconductor chip C can be reduced, and the number of semiconductor chips on a wafer of a semiconductor process can be increased. Forming of monitoring patterns in the I/O pad array areas PA means that the monitoring patterns are formed to overlap the position where I/O pads are formed. In example embodiments, an I/O pad array area denotes an area under a position where an I/O pad is formed. Also, I/O pads, I/O pad array areas, and monitoring patterns have quadrangular shapes.
-
FIG. 2A shows a schematic top view of a monitoring pattern formed in one of I/O pad array areas according to example embodiments of the inventive concepts, and a longitudinal sectional view of the monitoring pattern alongline 2A-2A′. Referring toFIG. 2A , amonitoring pattern 200 a is formed in an I/O pad array area. Themonitoring pattern 200 a may include alower layer 210 a,open areas lower layer 210 a, anddams 240 a. Thelower layer 210 a may be a semiconductor substrate or an insulating layer. Thelower layer 210 a includes a peripheral area P and a first internal area I1. Specifically, thelower layer 210 a may include silicon, silicon oxide, silicon nitride, silicon oxynitride, a metal, a metal silicide, or a metal compound. Themonitoring pattern 200 a may be formed inexternal structures 220 a. - The
external structures 220 a may define the peripheral area P overlapping an I/O pad array area, or themonitoring pattern 200 a. The peripheral area P may be a quadrangular area. Theexternal structures 220 a may include silicon oxide. Theexternal structures 220 a may be formed on the same level as a material layer referred to as an interlayer insulating layer in a process of fabricating a cell area of a semiconductor device. - For example, the
external structures 220 a may be formed on the same level as an interlayer insulating layer that is formed on a semiconductor substrate to be in direct contact with a surface of the semiconductor substrate. InFIG. 2A , theexternal structures 220 a may be formed directly on thelower layer 210 a. Theopen areas open areas 230 a and an internalopen area 250 a. The externalopen areas 230 a may be separated from the internalopen area 250 a by thedams 240 a. The externalopen areas 230 a may be disposed between theexternal structures 220 a and thedams 240 a, and the internalopen area 250 a may be disposed in thedams 240 a. - The external
open areas 230 a may be formed in a quadrangular band shape. The internalopen area 250 a may be formed in a square shape. Thedams 240 a may also be formed as a quadrangular band shape in the top view, and as a wall shape in the side view. Thedams 240 a may be formed to be a closed shape. In other words, thedams 240 a may be formed in a single body without a discontinuous portion. As mentioned above, thedams 240 a may be formed to the same height as an interlayer insulating layer in a process of fabricating a cell area of a semiconductor device. Thedams 240 a have no specific restrictions on their width, but may be formed to a width of 1 μm to 3 μm. The width of thedams 240 a may be set to vary according to an experimentor's intention or a design rule, and characteristics of fabrication processes. Thedams 240 a may prevent or reduce movement of materials flowing from theexternal structures 220 a, that is, the outside, to the internalopen area 250 a, that is, the inside. - For example, the
dams 240 a may prevent or reduce photoresist, an organic anti-reflection layer, a planarization material, etc. from excessively flowing to the internalopen area 250 a and deteriorating the characteristic of planarity. The flow of materials toward the internalopen area 250 a may cause the same result as applying a physical pressure to an edge, etc. of theexternal structures 220 a. Themonitoring pattern 200 a, the I/O pad array area, etc. may not be accurately defined. One side of theexternal structures 220 a, the externalopen areas 230 a, or thedams 240 a has a length similar to the size of the I/O pad array area, which is about several tens of micrometers. For example, the length may be 50 μm to 100 μm. - Since the external
open areas 230 a and thedams 240 a have widths of several micrometers, the internalopen area 250 a has a much larger area than other components, and thus the flow of materials may cause a relatively large defect. Themonitoring pattern 200 a may be used to monitor a process of selectively removing a portion of an interlayer insulating layer during a process of fabricating a semiconductor device. For example, themonitoring pattern 200 a may be used to monitor a process of forming a contact hole. -
FIG. 2B shows a schematic top view of a monitoring pattern formed in one of I/O pad array areas according to example embodiments of the inventive concepts, and a longitudinal sectional view of the monitoring pattern alongline 2B-2B′. Referring toFIG. 2B , amonitoring pattern 200 b is formed in an I/O pad array area. Themonitoring pattern 200 b may include alower layer 210 b,open areas lower layer 210 b, anddams open areas open areas 230 b, middleopen areas 235 b and an internalopen area 250 b. Thedams first dams 240 b andsecond dams 245 b. Themonitoring pattern 200 b may also be formed inexternal structures 220 b. Theexternal structures 220 b are described with reference toFIG. 2A . - The external
open areas 230 b may be formed between theexternal structures 220 b and thefirst dams 240 b. The middleopen areas 235 b may be formed between theexternal dams 240 b and thesecond dams 245 b. The internalopen area 250 b may be formed in the second internal area I2. The shapes and mutual relationships of the external, middle and internalopen areas second dams FIG. 2B . Themonitoring pattern 200 b includes the first andsecond dams -
FIG. 2C shows a schematic top view of a monitoring pattern formed in one of I/O pad array areas according to example embodiments of the inventive concepts, and a longitudinal sectional view of the monitoring pattern alongline 2C-2C′. Referring toFIG. 2C , amonitoring pattern 200 c is formed in an I/O pad array area. Themonitoring pattern 200 c may include alower layer 210 c,open areas lower layer 210 c, anddams open areas open areas 230 c and internalopen areas 235 c. The externalopen areas 230 c are described with reference to FIGS. 2A and 2Bs. - The internal
open areas 235 c may be arranged as plural separate islands. Themonitoring pattern 200 c may also be formed inexternal structures 220 c. Thedams first dams 240 c and pluralsecond dams 245 c arranged in the form of a lattice. The pluralsecond dams 245 c may be formed extending in horizontal and vertical directions. In other words, the pluralsecond dams 245 c may be formed as lattice shapes. -
FIG. 3A shows a schematic top view of a monitoring pattern formed in one of I/O pad array areas according to example embodiments of the inventive concepts, and a longitudinal sectional view of the monitoring pattern alongline 3A-3A′. Referring toFIG. 3A , amonitoring pattern 300 a is formed in an I/O pad array area. Themonitoring pattern 300 a may include alower layer 310 a,open areas dams 340 a, and adummy pattern 360 a. Theopen areas open areas 330 a and an internalopen area 350 a. Thedams 340 a may be formed between the externalopen areas 330 a and the internalopen area 350 a. Themonitoring pattern 300 a may also be formed inexternal structures 320 a. Thedummy pattern 360 a may be formed directly on thelower layer 310 a. - The
dummy pattern 360 a may include a gate stack structure. For example, thedummy pattern 360 a may include apolysilicon layer 361 a, asilicide layer 363 a, acapping layer 365 a, and asidewall 367 a of the gate stack structure. Thesilicide layer 363 a may be a metal layer. Thecapping layer 365 a may be formed of silicon nitride. Thesidewall 367 a may include silicon oxide or silicon nitride. Thedummy pattern 360 a may be formed as a large plate. The externalopen areas 330 a may expose a surface of thelower layer 310 a. The internalopen area 350 a may expose a surface of thedummy pattern 360 a. Thedams 340 a may overlap the edge of thedummy pattern 360 a. In other words, a portion of thedams 340 a may be formed on thedummy pattern 360 a. -
FIG. 3B shows a schematic top view of a monitoring pattern formed in one of I/O pad array areas according to example embodiments of the inventive concepts, and a longitudinal sectional view of the monitoring pattern alongline 3B-3B′. Referring toFIG. 3B , amonitoring pattern 300 b is formed in an I/O pad array area. Themonitoring pattern 300 b may include alower layer 310 b,open areas dams dummy pattern 360 b. Theopen areas open areas 330 b and internalopen areas open areas 330 b may be formed in a band shape betweenexternal structures 320 b and theexternal dams 340 b. The internalopen areas open areas 335 b and a second internalopen area 350 b. Thedams external dams 340 b andinternal dams 345 b. Theexternal dams 340 b may be formed in a band shape between the externalopen areas 330 b and the first internalopen areas 335 b. The first internalopen areas 335 b may be disposed in a band shape between theexternal dams 340 b and theinternal dams 345 b. - The
internal dams 345 b may be formed in a band shape between the first internalopen areas 335 b and the second internalopen area 350 b. Thedummy pattern 360 b may be formed directly on thelower layer 310 b. Thedummy pattern 360 b may also include a gate stack structure.Respective components dummy pattern 360 b are described with reference toFIG. 3A . Thedummy pattern 360 b may also be formed as a large plate. The internalopen areas dummy pattern 360 b. The externalopen areas 330 b may expose a surface of thelower layer 310 b. Theexternal dams 340 b may overlap the edge of thedummy pattern 360 b. In other words, a portion of theexternal dams 340 a may be formed on thedummy pattern 360 b. Theinternal dams 345 b may be formed on thedummy pattern 360 b. -
FIG. 3C shows a schematic top view of a monitoring pattern formed in one of I/O pad array areas according to example embodiments of the inventive concepts, and a longitudinal sectional view of the monitoring pattern alongline 3C-3C′. Referring toFIG. 3C , amonitoring pattern 300 c is formed in an I/O pad array area. Themonitoring pattern 300 c may include alower layer 310 c,open areas dams dummy pattern 360 c.Respective components 361 c 363 c, 365 c and 367 c included in thedummy pattern 360 c are described with reference toFIG. 3A . Themonitoring pattern 300 c may also be formed inexternal structures 320 c. Theopen areas open areas 330 c and internalopen areas 335 c. The externalopen areas 330 c may expose a surface of thelower layer 310 c. The internalopen areas 335 c may expose a surface of thedummy pattern 360 c. The internalopen areas 335 c may be arranged as islands. Thedams external dams 340 c andinternal dams 345 c. Theexternal dams 340 c may be formed in a band shape along the externalopen areas 330 c, and theinternal dams 345 c may be formed as plural linear patterns that are parallel in horizontal and vertical directions and cross each other. Theexternal dams 340 c and theinternal dams 345 c may be physically connected. Theexternal dams 340 c and theinternal dams 345 c may be formed as lattice shapes. -
FIG. 4A shows a schematic top view of a monitoring pattern formed in one of I/O pad array areas according to example embodiments of the inventive concepts, and a longitudinal sectional view of the monitoring pattern alongline 4A-4A′. Referring toFIG. 4A , amonitoring pattern 400 a is formed in an I/O pad array area. Themonitoring pattern 400 a may include alower layer 410 a,open areas dams 440 a, anddummy patterns 460 a. Theopen areas open areas 430 a and an internalopen area 450 a. Thedams 440 a may be formed between the externalopen areas 430 a and the internalopen area 450 a. Themonitoring pattern 400 a may also be formed inexternal structures 420 a. - The
dummy patterns 460 a may be formed directly on thelower layer 410 a. Thedummy patterns 460 a may include a gate stack structure. For example, thedummy patterns 460 a may include apolysilicon layer 461 a, asilicide layer 463 a, acapping layer 465 a, and asidewall 467 a of the gate stack structure. Thesilicide layer 463 a may include a metal layer. Thecapping layer 465 a may include silicon nitride. Thesidewall 467 a may include silicon oxide or silicon nitride. Thedummy patterns 460 a may be formed to be the same as or similar to the gate stack structure. Although not shown in the drawing to avoid complicating the drawing, thedummy patterns 460 a may further include a gate insulating layer between thelower layer 410 a and thepolysilicon layer 461 a. Also, when thedummy patterns 460 a are applied to flash memory semiconductor device technology, thepolysilicon layer 461 a may correspond to a floating gate, and thesilicide layer 463 a may correspond to a control gate. An inter-gate dielectric layer (not shown) may be additionally formed between thepolysilicon layer 461 a and thesilicide layer 463 a. - The inter-gate dielectric layer may be formed of plural layers of a silicon oxide layer/silicon nitride layer/silicon oxide layer. The
dummy patterns 460 a may be formed along thedams 440 a in a shape that is the same as or similar to thedams 440 a. For example, thedummy patterns 460 a may be formed in a quadrangular band shape or four bar shapes. Unlike thedams 440 a, all thedummy patterns 460 a need not be connected as a single body. In the drawing, the boundaries of thedummy patterns 460 a covered by thedams 440 a are indicated by dotted lines. The externalopen areas 430 a may expose a surface of thelower layer 410 a. - The internal
open area 450 a may expose thelower layer 410 a and also portions of thedummy patterns 460 a. Thedams 440 a may overlap the edges of thedummy patterns 460 a. In other words, portions of thedams 440 a may be formed on thedummy patterns 460 a. Also, thedams 440 a may completely surround thedummy patterns 460 a. When thedummy patterns 460 a are completely surrounded by thedams 440 a, the internalopen area 450 a may not expose thedummy patterns 460 a at all. -
FIG. 4B shows a schematic top view of a monitoring pattern formed in one of I/O pad array areas according to example embodiments of the inventive concepts, and a longitudinal sectional view of the monitoring pattern alongline 4B-4B′. Referring toFIG. 4B , amonitoring pattern 400 b is formed in an I/O pad array area. Themonitoring pattern 400 b may include alower layer 410 b,open areas dams 440 b, anddummy patterns 460 b. Theopen areas open areas 430 b and an internalopen area 450 b. Thedams 440 b may be formed between the externalopen areas 430 b and the internalopen area 450 b. Themonitoring pattern 400 b may also be formed inexternal structures 420 b. Thedummy patterns 460 b are described with reference toFIG. 4A . Also, thedummy patterns 460 b may be formed in a plural parallel line or bar shape. Furthermore, thedummy patterns 460 b may be formed in a lattice shape referring toFIGS. 2C and 3C . - The external
open areas 430 b may expose thelower layer 410 b. The internalopen area 450 b may expose only a surface of thelower layer 410 b, only portions of thedummy patterns 460 b, or oneentire dummy pattern 460 b. In the drawing, the internalopen area 450 b exposes a surface of thelower layer 410 b, twoentire dummy patterns 460 b, and portions ofother dummy patterns 460 b. Thedummy patterns 460 b may be formed in a single body. However, thedummy patterns 460 b do not have to be formed in a single body. In other words, thedummy patterns 460 b may include at least one portion at which thedummy patterns 460 b are not physically connected with each other. -
FIG. 5A shows a schematic top view of a monitoring pattern formed in one of I/O pad array areas according to example embodiments of the inventive concepts, and a longitudinal sectional view of the monitoring pattern alongline 5A-5A′. Referring toFIG. 5A , amonitoring pattern 500 a is formed in an I/O pad array area. Themonitoring pattern 500 a may include alower layer 510 a,open areas dams 540 a,dummy patterns 560 a, anddummy contacts 570 a. Themonitoring pattern 500 a may also be formed inexternal structures 520 a. Thelower layer 510 a, theopen areas dams 540 a, and thedummy patterns 560 a are described with reference toFIGS. 4A and 4B . - The
dummy contacts 570 a may be formed between thedummy patterns 560 a. Thedummy contacts 570 a may be formed in a pillar or plug shape in the side view. Thedummy contacts 570 a may be formed as islands in the top view. However, thedummy contacts 570 a do not have to be formed as islands. For example, thedummy contacts 570 a may be formed in a linear or bar shape to fill a valley between thedummy patterns 560 a. A plural number of thedummy contacts 570 a may be arranged in a direction in which thedummy patterns 560 a are extended. -
FIG. 5B shows a schematic top view of a monitoring pattern formed in one of I/O pad array areas according to example embodiments of the inventive concepts, and a longitudinal sectional view of the monitoring pattern alongline 5B-5B′. Referring toFIG. 5B , amonitoring pattern 500 b is formed in an I/O pad array area. Themonitoring pattern 500 b may include alower layer 510 b,open areas dams 540 b,dummy patterns 560 b, anddummy contacts 570 b. Themonitoring pattern 500 b may also be formed inexternal structures 520 b. Thelower layer 510 b, theopen areas dams 540 b are described with reference toFIGS. 4B and 5A . Thedummy patterns 560 b are described with reference toFIG. 4B . - Specifically, the
dummy patterns 560 b may be formed in a plural parallel line or bar shape, or a lattice shape. Thedummy contacts 570 b are described with reference toFIG. 5A . A plural number of thedummy contacts 570 b may also be arranged in a direction perpendicular to a direction in which thedummy patterns 560 b are extended. Thedummy contacts 570 b may be arranged in the form of a lattice. Thedummy contacts 570 b may be arranged in a “+” shape to be parallel in horizontal and vertical directions and cross each other, or in a “x” shape to be parallel with two diagonal lines crossing at right angles. - A method of fabricating a monitoring pattern in one of I/O pad array areas according to example embodiments of the inventive concepts will be described below. In the method, the
monitoring pattern 500 a shown inFIG. 5A will be fabricated as an example of various monitoring patterns. Methods of fabricating respective monitoring patterns according to other example embodiments of the inventive concepts will be easily inferred from the following description. -
FIGS. 6A through 6G show schematic top views and longitudinal sectional views along line VI-VI', illustrating a method of fabricating a monitoring pattern in one of I/O pad array areas according to example embodiments of the inventive concepts. Referring toFIG. 6A ,gate stack structures 660 are formed on asubstrate 610 overlapping an I/O pad array area. Thegate stack structures 660 may includepolysilicon layers 661, silicide layers 663, cappinglayers 665, and sidewalls 667. The polysilicon layers 661, the silicide layers 663, the capping layers 665, and thesidewalls 667 are typical components of thegate stack structures 660 to aid in understanding example embodiments of the inventive concepts. Thegate stack structures 660 may be formed to have the same structure as a cell transistor, that is, a cell gate structure in a cell region of a semiconductor device. For example, in dynamic random access memory (DRAM) semiconductor device technology, thegate stack structures 660 may further include a gate insulating layer between thesubstrate 610 and the polysilicon layers 661, and the silicide layers 663 may include metal layers. - Also, in flash memory semiconductor device technology, the polysilicon layers 661 of the
gate stack structures 660 may correspond to floating gates, and the silicide layers 663 may correspond to control gates. Inter-gate dielectric layers may be additionally formed between the floating gates and the control gates. The inter-gate dielectric layers may include plural layers of a silicon oxide layer/silicon nitride layer/silicon oxide layer. Thegate stack structures 660 may be formed at the same time in the same process as a cell gate formed in the cell region of the semiconductor device. - Referring to
FIG. 6B , a first insulatinglayer 623 is formed on an entire area overlapping the I/O pad array area. The first insulatinglayer 623 may be formed to completely cover thegate stack structures 660. The first insulatinglayer 623 is a silicon oxide layer, and may be formed of the same material and/or in the same process as an interlayer insulating layer formed in the cell region of the semiconductor device. - Referring to
FIG. 6C , a first insulatinglayer pattern 623 a is formed. The first insulatinglayer pattern 623 a may include contact holes 671. The contact holes 671 may expose a surface of thesubstrate 610 between the adjacentgate stack structures 660. The contact holes 671 may be formed as islands at separate positions. The contact holes 671 may be formed in a contact forming process in which the cell region of the semiconductor device is formed. This process is also referred to as a contact pad hole forming process, a landing pad hole forming process, a lower contact hole forming process, etc. - Referring to
FIG. 6D , plugs 675 that fill the contact holes 671 are formed on the first insulatinglayer pattern 623 a. Theplugs 675 may include silicon. Theplugs 675 may be formed of the same material and/or in the same process as a cell contact plug formed in the cell region of the semiconductor device. The cell contact plug is also referred to as a contact pad, a landing pad, a lower contact plug, a self-aligned contact, etc. - Referring to
FIG. 6E , a planarization process is performed to form contact plugs 670. An etch-back process or a chemical mechanical polishing (CMP) process may be performed as the planarization process. In this process, the height of the firstinsulating pattern 623 a may be reduced to form a firstinsulating pattern 623 b. - Referring to
FIG. 6F , a second insulatinglayer 625 is formed all over the contact plugs 670 and the first insulatinglayer pattern 623 b. The secondinsulating layer 625 may include a silicon oxide layer, and be formed of the same material and/or in the same process as an interlayer insulating layer among processes of forming various interlayer insulating layers in the cell region of the semiconductor device. For example, the second insulatinglayer 625 may be formed in one of processes of forming interlayer insulating layers on higher levels than the upper surfaces of the cell gates in the cell region. In this process, when the first insulatinglayer pattern 623 b having a reduced height and the second insulatinglayer 625 are formed of the same materials, e.g., a silicon oxide layer, a boundary between the first insulatinglayer 623 b and the second insulatinglayer 625 may be disappeared. Thus, the boundary is indicated by a dotted line for an imaginary in the drawing. - Referring to
FIG. 6G ,external structures 620,open areas dams 640 are formed. Theexternal structures 620 may define an area in which amonitoring pattern 600 is formed. Theopen areas open areas 630 and an internalopen area 650. The externalopen areas 630 may expose a surface of thesubstrate 610, and the internalopen area 650 may exposes the surface of thesubstrate 610, portions of thegate stack structures 660, and surfaces of theplugs 670. The externalopen areas 630 may be formed in a quadrangular band shape along theexternal structures 620. The internalopen area 650 may be formed in a large quadrangular window shape. Thedams 640 may be disposed in quadrangular band shapes between the externalopen areas 630 and the internalopen area 650. - From the above description, methods of fabricating monitoring patterns overlapping an I/O pad array area according to example embodiments of the inventive concepts shown in
FIGS. 2A through 5B will be easily inferred. -
FIG. 7 is a schematic diagram of a semiconductor module including a semiconductor device including a process monitoring pattern overlapping an I/O pad array area according to example embodiments of the inventive concepts. Referring toFIG. 7 , asemiconductor module 700 according to example embodiments of the inventive concepts includes amodule substrate 710, a plurality ofsemiconductor devices 720 disposed on themodule substrate 710, andmodule contact terminals 730 formed in a line on one edge of themodule substrate 710 and electrically connected with thesemiconductor devices 720. Themodule substrate 710 may be a printed circuit board (PCB). Both surfaces of themodule substrate 710 may be used. In other words, thesemiconductor devices 720 may be disposed on the front side and the back side of themodule substrate 710. It is shown inFIG. 7 that eightsemiconductor devices 720 are disposed on the front side of themodule substrate 710, but this is merely an example. - The
semiconductor module 700 may further include a logic semiconductor device for controlling the semiconductor devices or the semiconductor packages. Thus, the number of thesemiconductor devices 720 constituting thesemiconductor module 700 shown inFIG. 7 is variable. At least one of thesemiconductor devices 720 may include a process monitoring pattern overlapping an I/O pad array area according to example embodiments of the inventive concepts. Themodule contact terminals 730 may be formed of a metal, and may have resistance to oxidation. Themodule contact terminals 730 may be set to vary according to the standard of thesemiconductor module 700. Thus, the number ofmodule contact terminals 730 shown in the drawing is not meaningful. -
FIG. 8 is a schematic block diagram of an electronic circuit board including a semiconductor device including a process monitoring pattern overlapping an I/O pad array area according to example embodiments of the inventive concepts. Referring toFIG. 8 , anelectronic circuit board 800 according to example embodiments of the inventive concepts includes amicroprocessor 820 disposed on acircuit board 810, a main storage circuit 830 and a supplementary storage circuit 840 communicating with themicroprocessor 820, an inputsignal processing circuit 850 sending an instruction to themicroprocessor 820, an outputsignal processing circuit 860 receiving an instruction from themicroprocessor 820, and a communicatingsignal processing circuit 870 exchanging electrical signals with other circuit boards. Arrows denote paths through which electrical signals can be transferred. Themicroprocessor 820 may receive and process a variety of electrical signals to output the processed results, and may control other components of theelectronic circuit board 810. Themicroprocessor 820 may be, for example, a central processing unit (CPU), a main control unit (MCU), etc. - The main storage circuit 830 may temporarily store data that is always or frequently required for pre- and post-processing data. The main storage circuit 830 requires a rapid response and thus may be a semiconductor memory. Specifically, the main storage circuit 830 may be a semiconductor memory referred to as cache, or may include a static RAM (SRAM), a DRAM, a resistive RAM (RRAM), and applied semiconductor memories, for example, a utilized RAM, a ferro-electric RAM, a fast cycle RAM, a phase changeable RAM, a magnetic RAM, and other semiconductor memories. The main storage circuit 830 may be volatile or non-volatile, and may include a RAM. In this example embodiment of the inventive concepts, the main storage circuit 830 may include at least one semiconductor device including a process monitoring pattern overlapping an I/O pad array area according to an example embodiment of the inventive concepts, or at least one
semiconductor module 700 including the semiconductor device. - The supplementary storage circuit 840 is a mass storage device, and may be a non-volatile semiconductor memory such as a flash memory, a hard disk drive (HDD) using a magnetic field, or a compact disk (CD) drive using light. The supplementary storage circuit 840 may be used to store a relatively large amount of data without requiring a higher speed than the main storage circuit 830. The supplementary storage circuit 840 may include a random access memory and/or non-random access memory such as a non-volatile storage device. The supplementary storage circuit 840 may include at least one semiconductor device including a process monitoring pattern overlapping an I/O pad array area according to an example embodiment of the inventive concepts, or at least one
semiconductor module 700 including the semiconductor device. The inputsignal processing circuit 850 may convert an external instruction into an electrical signal or transfer an electrical signal received from the outside to themicroprocessor 820. - The instruction or electrical signal received from the outside may be an operation instruction, an electrical signal to be processed, or data to be stored. The input
signal processing circuit 850 may be a terminal signal processing circuit that processes a signal transferred from a keyboard, a mouse, a touchpad, an image recognition device, or a variety of sensors, an image signal processing circuit that processes an image signal input from a scanner or a camera, various sensors or an input signal interface, or so on. The inputsignal processing circuit 850 may include at least one semiconductor device including a process monitoring pattern overlapping an I/O pad array area according to an example embodiment of the inventive concepts, or at least onesemiconductor module 700 including the semiconductor device. - The output
signal processing circuit 860 may be a component for transferring an electrical signal processed by themicroprocessor 820 to the outside. For example, the outputsignal processing circuit 860 may be a graphic card, an image processor, an optical transducer, a beam panel card, or an interface circuit having various functions. The outputsignal processing circuit 860 may include at least one semiconductor device including a process monitoring pattern overlapping an I/O pad array area according to an example embodiment of the inventive concepts, or at least onesemiconductor module 700 including the semiconductor device. - The communicating
signal processing circuit 870 is a component for directly exchanging electrical signals with another electronic system or another circuit board not through the inputsignal processing circuit 850 or the outputsignal processing circuit 860. For example, the communicatingsignal processing circuit 870 may be a modem, a local area network (LAN) card, various interface circuits, etc. of a personal computer (PC) system. The communicatingsignal processing circuit 870 may include at least one semiconductor device including a process monitoring pattern overlapping an I/O pad array area according to an example embodiment to the inventive concepts, or at least onesemiconductor module 700 including the semiconductor device. -
FIG. 9 is a schematic block diagram of an electronic system including a semiconductor device including a process monitoring pattern overlapping an I/O pad array area according to example embodiments of the inventive concepts, or a semiconductor module including the semiconductor device. Referring toFIG. 9 , anelectronic system 900 according to example embodiments of the inventive concepts includes acontrol unit 910, aninput unit 920, anoutput unit 930, and astorage unit 940, and may further include acommunication unit 950 and/or anoperation unit 960. Thecontrol unit 910 may control theelectronic system 900 and all the respective units. - The
control unit 910 may be considered a central processor or a central controller, and may include theelectronic circuit board 800 according to example embodiments of the inventive concepts. Also, thecontrol unit 910 may include at least one semiconductor device including a process monitoring pattern overlapping an I/O pad array area according to an example embodiment of the inventive concepts, or at least onesemiconductor module 700 including the semiconductor device. Theinput unit 920 may send an electrical instruction signal to thecontrol unit 910. Theinput unit 920 may be a keyboard, a keypad, a mouse, a touchpad, an image recognizer such as a scanner, or various input sensors. - The
input unit 920 may include at least one semiconductor device including a process monitoring pattern overlapping an I/O pad array area according to an example embodiment of the inventive concepts, or at least onesemiconductor module 700 including the semiconductor device. Theoutput unit 930 may receive the electrical instruction signal from thecontrol unit 910 and output a result processed by theelectronic system 900. Theoutput unit 930 may be a monitor, a printer, a beam projector, or various mechanical devices. Theoutput unit 930 may include at least one semiconductor device including a process monitoring pattern overlapping an I/O pad array area according to an example embodiment of the inventive concepts, or at least onesemiconductor module 700 including the semiconductor device. - The
storage unit 940 may be a component for temporarily or permanently storing an electrical signal that will be processed or has been processed by thecontrol unit 910. Thestorage unit 940 may be physically and electrically connected or combined with thecontrol unit 910. Thestorage unit 940 may be a semiconductor memory, a magnetic storage device such as a HDD, an optical storage device such as a CD, or a server having other data storage functions. Also, thestorage unit 940 may include at least one semiconductor device including a process monitoring pattern overlapping an I/O pad array area according to an example embodiment of the inventive concepts, or at least onesemiconductor module 700 including the semiconductor device. - The
communication unit 950 may receive the electrical instruction signal from thecontrol unit 910 and send or receive an instruction signal to or from another electronic system. Thecommunication unit 950 may be a wired transceiver device such as a modem and a LAN card, a wireless transceiver device such as a wireless broadband (WiBro) interface, an infrared port, etc. Also, thecommunication unit 950 may include at least one semiconductor device including a process monitoring pattern overlapping an I/O pad array area according to an example embodiment of the inventive concepts, or at least onesemiconductor module 700 including the semiconductor device. Theoperation unit 960 may perform a physical or mechanical operation according to an instruction of thecontrol unit 910. - For example, the
operation unit 960 may be a component that performs a mechanical operation, such as a plotter, an indicator, and an up/down operator. An electronic system according to an example embodiment of the inventive concepts may be a computer, a network server, a networking printer or scanner, a wireless controller, a terminal for mobile communication, an exchanger, or an electronic product performing other programmed operations. - The names, functions, etc. of components that are not indicated by reference numerals in the drawings can be readily understood from other drawings and the descriptions.
- As described above, in a semiconductor device according to example embodiments of the inventive concepts, a monitoring pattern is formed to overlap an I/O pad array area. Accordingly, reducing the width or area of a scribe lane may be possible. Also, an area on a wafer occupied by the semiconductor chip can be reduced, and thus the productivity of the semiconductor device can be improved.
- The foregoing is illustrative of embodiments and is not to be construed as limiting thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in embodiments without materially departing from the novel teachings and advantages. Accordingly, all such modifications are intended to be included within the scope of the inventive concepts as defined in the claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function, and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of various embodiments and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims.
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/861,984 US8673659B2 (en) | 2010-02-04 | 2013-04-12 | Method of fabricating semiconductor device including process monitoring pattern having overlapping input/output pad array area |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2010-0010515 | 2010-02-04 | ||
KR1020100010515A KR101585218B1 (en) | 2010-02-04 | 2010-02-04 | Semiconductor Device, Semiconductor Module, Electronic Circuit Board, and Electronic System Including a Process Monitoring Pattern Overlapping with Input/output Pad Area, and Method of Fabricating the Same |
US12/962,991 US8445907B2 (en) | 2010-02-04 | 2010-12-08 | Semiconductor device including process monitoring pattern having overlapping input/output pad array area |
US13/861,984 US8673659B2 (en) | 2010-02-04 | 2013-04-12 | Method of fabricating semiconductor device including process monitoring pattern having overlapping input/output pad array area |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/962,991 Division US8445907B2 (en) | 2010-02-04 | 2010-12-08 | Semiconductor device including process monitoring pattern having overlapping input/output pad array area |
Publications (2)
Publication Number | Publication Date |
---|---|
US20130273726A1 true US20130273726A1 (en) | 2013-10-17 |
US8673659B2 US8673659B2 (en) | 2014-03-18 |
Family
ID=44340899
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/962,991 Expired - Fee Related US8445907B2 (en) | 2010-02-04 | 2010-12-08 | Semiconductor device including process monitoring pattern having overlapping input/output pad array area |
US13/861,984 Expired - Fee Related US8673659B2 (en) | 2010-02-04 | 2013-04-12 | Method of fabricating semiconductor device including process monitoring pattern having overlapping input/output pad array area |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/962,991 Expired - Fee Related US8445907B2 (en) | 2010-02-04 | 2010-12-08 | Semiconductor device including process monitoring pattern having overlapping input/output pad array area |
Country Status (2)
Country | Link |
---|---|
US (2) | US8445907B2 (en) |
KR (1) | KR101585218B1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI715286B (en) * | 2019-11-13 | 2021-01-01 | 華邦電子股份有限公司 | Monitoring structure for critical dimension of lithography process |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7517762B2 (en) * | 1999-08-31 | 2009-04-14 | Samsung Electronics Co., Ltd. | Semiconductor device capable of preventing moisture-absorption of fuse area thereof and method for manufacturing the fuse area |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11219922A (en) * | 1998-02-03 | 1999-08-10 | Mitsubishi Electric Corp | Semiconductor device and manufacture of the same |
KR100343284B1 (en) * | 2000-06-23 | 2002-07-15 | 윤종용 | Bonding pad structure in semiconductor device and fabrication method thereof |
KR100859464B1 (en) * | 2000-12-29 | 2008-09-23 | 엘지디스플레이 주식회사 | Thin film transistor array panel of digital X-ray defector device and manufacturing method of the same |
KR20040058651A (en) | 2002-12-27 | 2004-07-05 | 삼성전자주식회사 | Wafer forming monitoring points |
KR100505894B1 (en) * | 2003-10-24 | 2005-08-01 | 매그나칩 반도체 유한회사 | Fabricating method of cmos image sensor protecting low temperature oxide delamination |
KR20060046876A (en) | 2004-11-12 | 2006-05-18 | 삼성전자주식회사 | Method forming oxide site for measuring a thickness of layer |
KR20080040811A (en) | 2006-11-03 | 2008-05-09 | 삼성전자주식회사 | Method for measuring material thickness in semiconductor memory device |
KR20090046993A (en) * | 2007-11-07 | 2009-05-12 | 주식회사 동부하이텍 | Semiconductor device and method for fabricating the same |
KR101385752B1 (en) * | 2008-10-24 | 2014-04-17 | 삼성전자주식회사 | A semiconductor device including a process monitoring pattern overlapped with an I/O pad |
-
2010
- 2010-02-04 KR KR1020100010515A patent/KR101585218B1/en not_active IP Right Cessation
- 2010-12-08 US US12/962,991 patent/US8445907B2/en not_active Expired - Fee Related
-
2013
- 2013-04-12 US US13/861,984 patent/US8673659B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7517762B2 (en) * | 1999-08-31 | 2009-04-14 | Samsung Electronics Co., Ltd. | Semiconductor device capable of preventing moisture-absorption of fuse area thereof and method for manufacturing the fuse area |
Also Published As
Publication number | Publication date |
---|---|
US20110187001A1 (en) | 2011-08-04 |
KR101585218B1 (en) | 2016-01-13 |
US8673659B2 (en) | 2014-03-18 |
US8445907B2 (en) | 2013-05-21 |
KR20110090622A (en) | 2011-08-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9899406B2 (en) | Vertical NAND flash memory device | |
US9564368B2 (en) | Semiconductor device and method of fabricating the same | |
US8552472B2 (en) | Integrated circuit devices including vertical channel transistors with shield lines interposed between bit lines and methods of fabricating the same | |
US8969215B2 (en) | Methods of fabricating semiconductor devices using double patterning technology | |
US9786552B2 (en) | Methods of forming fine patterns including pad portion and line portion | |
US7968447B2 (en) | Semiconductor device and methods of manufacturing the same | |
TWI685020B (en) | Semiconductor device including line patterns | |
US8507999B2 (en) | Semiconductor device, method of fabricating the same, and semiconductor module and electronic system including the semiconductor device | |
KR20080024969A (en) | Semiconductor memory device and method for forming thereof | |
WO2018236353A1 (en) | Embedded non-volatile memory based on ferroelectric field effect transistors | |
US9337151B2 (en) | Semiconductor device | |
US9378979B2 (en) | Methods of fabricating semiconductor devices and devices fabricated thereby | |
US9613972B1 (en) | Method of manufacturing semiconductor device | |
EP4020562A1 (en) | 3d-ferroelectric random (3d-fram) with buried trench capacitors | |
US10923407B2 (en) | Semiconductor device | |
US20110187004A1 (en) | Semiconductor devices including an interconnection pattern and methods of fabricating the same | |
US8673659B2 (en) | Method of fabricating semiconductor device including process monitoring pattern having overlapping input/output pad array area | |
TWI661557B (en) | Semiconductor device and method of fabricating the same | |
EP4020561A1 (en) | Metal replacement plate line process for 3d-ferroelectric random (3d-fram) | |
US10998266B2 (en) | Semiconductor devices including redistributed layer structures and methods of forming semiconductor devices including redistributed layer structures | |
US8183598B2 (en) | Semiconductor device, semiconductor module, and electronic apparatus including process monitoring pattern overlapping with I/O pad | |
US10056257B2 (en) | Methods for forming fine patterns using spacers | |
KR20090129258A (en) | Semiconductor memory device and method of fabricating the same | |
US11121136B2 (en) | Insulating structure and method of forming the same | |
KR20140023764A (en) | Semiconductor devices and method of manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551) Year of fee payment: 4 |
|
FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20220318 |