KR20140023764A - Semiconductor devices and method of manufacturing the same - Google Patents

Abstract

A method of manufacturing a semiconductor device is provided. Provided is a substrate that includes a cell array region, a peripheral circuit region, and an interface region between the cell array region and the peripheral circuit. A gate layer and an upper mask layer are successively formed on the substrate. By patterning the upper mask layer, the first upper mask patterns of the cell array region and the second upper mask patterns of the interface region are simultaneously formed. By using the first and second upper mask patterns, the word lines of the cell array region and the dummy patterns of the interface region are formed.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including dummy patterns and a method of manufacturing the same.

The semiconductor memory devices may be classified into volatile memory devices and nonvolatile memory devices. Volatile memory devices lose their stored data when their power supplies are interrupted. DRAM devices and SRAM devices may be included in the volatile memory devices. Nonvolatile memory devices retain their stored data even when their power supplies are interrupted. Phase change memory devices (PRAM devices), magnetic memory devices (MARM devices) and / or flash memory devices (flash memory devices), etc. may be included in the nonvolatile memory devices. The flash memory device may electrically write or erase data. The flash memory device may be classified into a NOR type flash memory device and a NAND type flash memory device. The NOR flash memory device is capable of high speed random access and can be widely used in a device requiring high speed operation. The NAND type flash memory device can be used as a large capacity storage device because of its excellent program and erase speed and easy integration.

As the semiconductor industry is highly developed, line widths and / or spacing of patterns for realizing nonvolatile memory devices are becoming smaller. As a result, the reliability of the nonvolatile memory device is deteriorated. As the semiconductor industry and / or the electronics industry develops, demands for high reliability as well as high reliability for nonvolatile memory devices are increasing.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device having excellent reliability and a manufacturing method thereof.

Another object of the present invention is to provide a semiconductor device optimized for high integration and a method of manufacturing the same.

A method of manufacturing a semiconductor device according to the present invention includes providing a substrate including a cell array region, a peripheral circuit region, and an interface region between the cell array region and the peripheral circuit region, a gate layer and an upper mask on the substrate. Sequentially forming a layer, patterning the upper mask layer to simultaneously form first upper mask patterns of a cell array region and second upper mask patterns of an interface region; And forming word lines on the cell array region and dummy patterns on the interface region using the first and second upper mask patterns.

According to an embodiment, the method of manufacturing a semiconductor device according to the present invention may further include forming a lower mask layer between the gate layer and the upper mask layer. Forming word lines on the cell array region and dummy patterns on the interface region using the first and second upper mask patterns may include first spacers on sidewalls of the first and second upper mask patterns, respectively. Forming mask patterns and second spacer mask patterns, and etching the lower mask layer using the first and second spacer mask patterns as an etch mask to form the first lower mask patterns of the cell array area and the second of the interface area. Forming the lower mask patterns, and etching the gate layer using the first and second lower mask patterns as an etch mask.

In example embodiments, the forming of the first and second spacer mask patterns may include forming a spacer layer on the first and second upper mask patterns, and forming the spacer layer on the first and second upper portions. Etching may be performed until the top surfaces of the mask patterns and the top surface of the lower mask layer are exposed, and the first and second upper mask patterns may be removed.

In example embodiments, the manufacturing method of the semiconductor device may further include forming pad patterns extending from the word lines on the interface region. In example embodiments, the forming of the pad patterns may include forming preliminary mask patterns exposing at least some of the first and second spacer mask patterns, and using the preliminary mask patterns as an etch mask. Etching to form third lower mask patterns, and etching the gate layer using the third lower mask patterns as an etch mask.

In example embodiments, the widths of the dummy patterns may be equal to the widths of the word lines and may be smaller than the widths of the pad patterns.

In example embodiments, the first upper mask patterns may have the same width as the second upper mask patterns.

According to another embodiment, the method of manufacturing a semiconductor device according to the present invention may further include forming a lower mask layer between the gate layer and the upper mask layer. Forming word lines on the cell array region and dummy patterns on the interface region using the first and second upper mask patterns may include first spacers on sidewalls of the first and second upper mask patterns, respectively. Forming mask patterns and second spacer mask patterns, exposing the lower mask layer by removing the second spacer mask patterns, exposing the first spacer mask patterns on the exposed lower mask layer; Forming preliminary mask patterns, etching the lower mask layer using the first spacer mask patterns and the first preliminary mask patterns as an etch mask, and forming first and second lower mask patterns; And etching the gate layer using the first and second lower mask patterns as an etching mask.

According to another embodiment, the method of manufacturing a semiconductor device according to the present invention may further include forming pad patterns extending from the word lines on the interface region. The forming of the pad patterns may include forming second preliminary mask patterns spaced apart from the first preliminary mask patterns on the exposed lower mask layer, and using the second preliminary mask patterns as an etch mask. Etching to form third lower mask patterns, and etching the gate layer using the third lower mask patterns as an etch mask.

A semiconductor device according to the present invention is provided on a substrate including a cell array region, a peripheral circuit region, an interface region between the cell array region and the peripheral circuit region, word lines on the cell array region, and provided on the interface region. Pad patterns connected to word lines, and dummy patterns provided on the interface area and spaced apart from the word lines and the pad patterns. The dummy patterns may have the same width as that of the word lines and have a width smaller than the width of the pad patterns. The dummy patterns may be electrically isolated.

According to embodiments of the present invention, as the line width distribution of patterns is improved, a semiconductor device having excellent reliability and optimized for high integration can be manufactured.

1 is a plan view of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along lines II ′ and II-II ′ of FIG. 1.
3 to 10 are cross-sectional views taken along lines II ′ and II-II ′ of FIG. 1 to illustrate a method of fabricating a semiconductor device according to example embodiments.
11 is a plan view of a semiconductor device according to another embodiment of the present invention.
12 is a cross-sectional view taken along line II ′ and II ′ of FIG. 11.
13 to 16 are cross-sectional views taken along lines II ′ and II-II ′ of FIG. 11 to illustrate a manufacturing method of a semiconductor device according to example embodiments of the inventive concepts.
17 is a schematic block diagram illustrating an example of an electronic device including a semiconductor device according to the inventive concept.
18 is a schematic block diagram illustrating an example of a memory card including a semiconductor device according to the inventive concept.

In order to fully understand the structure and effects of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below, but may be embodied in various forms and various modifications may be made. It will be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof.

In this specification, when an element is referred to as being on another element, it may be directly formed on another element, or a third element may be interposed therebetween. Further, in the drawings, the thickness of the components is exaggerated for an effective description of the technical content. The same reference numerals denote the same elements throughout the specification.

Embodiments described herein will be described with reference to cross-sectional views and / or plan views that are ideal illustrations of the present invention. In the drawings, the thicknesses of films and regions are exaggerated for effective explanation of technical content. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention. Although the terms first, second, third, etc. in the various embodiments of the present disclosure are used to describe various components, these components should not be limited by these terms. These terms have only been used to distinguish one component from another. The embodiments described and exemplified herein also include their complementary embodiments.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. The terms "comprises" and / or "comprising" used in the specification do not exclude the presence or addition of one or more other elements.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along lines II ′ and II-II ′ of FIG. 1.

1 and 2, the substrate 100 may include a first region a, a second region b, and a third region c. The first region a and the third region c may be spaced apart from each other, and the second region b may be disposed between the first region a and the third region c. The first area a may be a cell array area in which a plurality of memory cells are arranged. The third region c may be part of the peripheral circuit region. For example, the third region c may be a decoder region 103 in which decoders connected to word lines are arranged. The second region b may be an interface region that is a connection region for electrically connecting the conductive lines of the first region a and the wirings of the third region c to be described later. The substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

Device isolation patterns 101 may be disposed in the substrate. The device isolation patterns 101 may define active areas 102 in the first area a. The active regions 102 may be spaced apart from each other in a first direction. In addition, the active regions 102 may be in the form of lines extending in parallel along a second direction perpendicular to the first direction. The first and second directions may be parallel to the top surface of the substrate 100. The first direction may be the x-axis direction of FIG. 1, and the second direction may be the y-axis direction of FIG. 1. Although not shown in FIG. 1, device isolation patterns may be formed in the second region and the third region, and device isolation patterns formed in the third region may define active regions in which driving transistors are formed.

A plurality of word lines WL may be disposed on the substrate of the first region a. The word lines WL may extend in parallel in the first direction. The word lines WL may be spaced apart from each other along the second direction. The word lines WL may cross the active regions 102 extending parallel to the second direction.

The word lines WL may include gate patterns 200 and mask patterns 300. The gate patterns 200 may include a tunnel dielectric layer, a charge storage layer, a blocking insulating layer, and a conductive layer. The tunnel dielectric layer may be interposed between the active regions 102 and the charge storage layer, and the blocking insulating layer may be interposed between the charge storage layer and the conductive layer. The tunnel dielectric layer may be formed of a single layer or a multilayer. For example, the tunnel dielectric layer may include an oxide layer, a nitride layer, and / or an oxynitride layer. The charge storage layer may include at least one of a doped silicon film, a silicon nitride film, and a metal oxide film (eg, hafnium oxide film). The blocking insulating layer may include at least one of an oxide film, a nitride film, and a high dielectric film. The high dielectric film is preferably a dielectric film having a higher dielectric constant than the tunnel dielectric film. For example, the high dielectric film may include a metal oxide film such as a hafnium oxide film and an aluminum oxide film. The blocking dielectric layer may be formed of a single layer or a multilayer. The conductive layer may include at least one of doped silicon, conductive metal nitride, and metal silicide. The mask pattern 300 may include an oxide and / or silicon.

Each of the word lines WL may include extension parts WLe extending to the second region b. The extensions WLe may be positioned at the same level as the lines WL with respect to the top surface of the substrate 100. The extensions WLe may be spaced apart from each other. The extensions WLe may have different lengths in the first direction. For example, the lengths of the extensions WLe of the word lines WL may be continuously increased and / or decreased in the second direction. However, the present invention is not limited thereto. The extensions WLe may be implemented in various forms.

Dummy patterns 110 may be disposed on the substrate of the second region b. The dummy patterns 110 may extend side by side in the first direction. The dummy patterns 110 may be spaced apart from each other along the second direction. Although not illustrated in FIG. 1, the dummy patterns 110 may cross active regions formed in the second region b and extended side by side in the second direction. Pad patterns 120 may be disposed on the substrate of the second region b. The pad patterns 120 may be connected to extensions WLe of the word lines WL. The pad patterns 120 may electrically connect the word lines WL and wires extending from the third region c.

The dummy patterns 110 and the pad patterns 120 may include the gate patterns 200 and the mask patterns 300 in the same manner as the word lines WL. The width w2 of the dummy patterns 110 may be equal to the width w1 of the word lines WL and may be smaller than the width w3 of the pad patterns 120. For example, the width w2 of the dummy patterns 110 may be about 10 nm to about 100 nm.

Driving transistors (not shown) and wiring lines (not shown) electrically connected to the driving transistors may be disposed on the substrate of the third region c. The wiring lines may be electrically connected to the pad patterns 120 disposed in the second region b. That is, the wiring lines may electrically connect the driving transistors and the word lines WL to each other. The dummy patterns 110 may not be electrically connected to the wiring lines but may be in an electrically isolated state.

An interlayer insulating layer 700 may be formed on the first region a, the second region b, and the third region c. The interlayer insulating layer 700 may cover the word lines WL, the dummy patterns 110, and the pad patterns 120.

3 to 10 are cross-sectional views taken along lines II ′ and II-II ′ of FIG. 1 to illustrate a method of fabricating a semiconductor device according to example embodiments.

Referring to FIG. 3, a gate layer 210, a lower mask layer 310, and an upper mask layer 320 may be formed on the substrate 100. The gate layer 210 may include a tunnel dielectric layer, a charge storage layer, a blocking insulating layer, and a conductive layer. The tunnel dielectric layer may be interposed between the substrate 100 and the charge storage layer, and the blocking insulating layer may be interposed between the charge storage layer and the conductive layer. The tunnel dielectric layer may be formed by, for example, a thermal oxidation process. The charge storage layer, the blocking insulating layer, and the conductive layer may be formed using a deposition process such as atomic layer deposition (ALD), CVD, and / or sputtering. The lower mask layer 310 may include silicon and / or oxide. For example, the lower mask layer 310 may include polysilicon and PEOX. The upper mask layer 320 may include an amorphous carbon layer (ACL) and a silicon oxynitride layer. For example, the upper mask layer 320 may include SiON. The lower mask layer 310 and the upper mask layer 320 may be formed by a deposition process. The lower mask layer 310 and the upper mask layer 320 may have an etching selectivity.

Referring to FIG. 4, a photolithography and etching process is performed on the upper mask layer 320 in the first region a and the second region b, so that the first region on the first region a is formed. Upper mask patterns 330 and second upper mask patterns 340 on the second region b may be formed. For example, the width w5 of the second upper mask patterns 340 may be substantially the same as the width w4 of the first upper mask patterns 330. As the second upper mask patterns 340 are formed on the second region b, the mask pattern density on the second region b may become similar to the first region a. When the mask pattern density on the second region (b) is formed similar to the first region (a), the line width distribution of the mask patterns on the second region (b) may be reduced.

Referring to FIG. 5, a spacer layer 350 may be formed on the lower mask layer 310. The spacer layer 350 may cover the first upper mask patterns 330 and the second upper mask patterns 340. For example, the spacer layer 350 may include an oxide and may be formed by an atomic layer deposition method or CVD.

Referring to FIG. 6, the spacer layer 350 is etched to form first spacer mask patterns 430 on the first region a and second spacer mask patterns 440 on the second region b. This can be formed. The etching process may be performed until the top surfaces of the first upper mask patterns 330 and the second upper mask patterns 340 are exposed. During the etching process, an upper surface of the lower mask layer 310 may be exposed.

Referring to FIG. 7, the first upper mask patterns 330 and the second upper mask patterns 340 may be removed. For example, the first upper mask patterns 330 and the second upper mast patterns 340 may be removed by a wet etching process. Referring to FIG. 8, a preliminary mask layer 500 may be formed on the lower mask layer 310. The preliminary mask layer 500 may cover the first spacer mask patterns 430 and the second spacer mask patterns 440. For example, the preliminary mask layer 500 may include an oxide containing carbon.

Referring to FIG. 9, a patterning process may be performed on the preliminary mask layer 500 to form preliminary mask patterns 450 on the second region b. At least a portion of the first spacer mask patterns 430 and the second spacer mask patterns 440 may be exposed by the patterning process, and a portion of the lower mask layer 310 may be exposed.

Referring to FIG. 10, the lower mask layer 310 may be etched using the first and second spacer mask patterns 430 and 440 and the preliminary mask patterns 450 as an etch mask. The first lower mask patterns 630 on the first region a, the second lower mask patterns 640 and the third lower mask patterns 650 on the second region b by the etching process. This can be formed. The width w2 of the second lower mask patterns 640 may be substantially the same as the width w1 of the first lower mask patterns 630. It may be smaller than the width w3. For example, the width w2 of the second lower mask patterns 640 may be about 10 nm to about 100 nm.

Referring to FIG. 2 again, the gate layer 210 is etched using the first, second, and third lower mask patterns 630, 640, and 650 as an etch mask, thereby forming the first region a. Word lines WL on the top surface, dummy patterns 110 and pad patterns 120 on the second region b may be formed. The word lines WL, the dummy patterns 110, and the pad patterns 120 may include the gate patterns 200 and the mask patterns 300, respectively. An interlayer insulating layer 700 may be formed on the word lines WL, the dummy patterns 110, and the pad patterns 120. Forming the interlayer insulating layer 700 may include a planarization process. By forming the dummy patterns 110 on the second region b, thickness distribution of the interlayer insulating layer 700 by the planarization process may be improved.

FIG. 11 is a plan view illustrating a semiconductor device in accordance with another embodiment of the present invention, and FIG. 12 is a cross-sectional view taken along lines II ′ and II-II ′ of FIG. 11. Duplicate descriptions may be omitted for simplicity of explanation.

11 and 12, dummy patterns 150 may be disposed on the substrate 100 of the second region b. The dummy patterns 150 may extend in the second direction (eg, the y direction), and may be spaced apart from each other in the first direction (eg, the x direction). The width w6 of the dummy patterns 150 in the first direction may be greater than the width of the pad patterns 120 in the first direction. For example, the width w6 of the dummy patterns 150 in the first direction may be about 100 nm to about 120 nm. An interlayer insulating layer 700 may be formed on the first region a, the second region b, and the third region c. The interlayer insulating layer 700 may cover the word lines WL, the dummy patterns 150, and the pad patterns 120.

13 to 16 are cross-sectional views taken along lines II ′ and II-II ′ of FIG. 11 to illustrate a manufacturing method of a semiconductor device according to example embodiments of the inventive concepts. Duplicate descriptions may be omitted for simplicity of explanation.

Referring to FIG. 13, a photoresist PR may be provided on the resultant described with reference to FIG. 7. The photoresist may expose the second spacer mask patterns 440. Referring to FIG. 14, the second spacer mask patterns 440 exposed by the photoresist PR may be removed to expose the lower mask layer 310. After the second spacer mask patterns 440 are removed, the photoresist PR may be removed. The preliminary mask layer 500 may be formed on the lower mask layer 310. The preliminary mask layer 500 may cover the first spacer mask patterns 430. For example, the preliminary mask layer 500 may include an oxide containing carbon.

Referring to FIG. 15, a patterning process is performed on the preliminary mask layer 500 to form first preliminary mask patterns 460 and second preliminary mask patterns 470 on the second region b. Can be. The first spacer mask patterns 430 may be exposed by the patterning process, and a portion of the lower mask layer 310 may be exposed.

Referring to FIG. 16, the lower mask layer 310 may be etched using the first spacer mask patterns 430 and the first and second preliminary mask patterns 460 and 470 as an etch mask. The first lower mask patterns 630 on the first region a, the second lower mask patterns 660 and the third lower mask patterns 670 on the second region b are formed by the etching process. This can be formed.

Referring to FIG. 12 again, the gate layer 210 is etched using the first, second, and third lower mask patterns 630, 660, and 670 as an etch mask, thereby forming the first region a. Word lines WL on the top surface, dummy patterns 150 and pad patterns 120 on the second region b may be formed. The word lines WL, the dummy patterns 150, and the pad patterns 120 may include the gate patterns 200 and the mask patterns 300, respectively. An interlayer insulating layer 700 may be formed on the word lines WL, the dummy patterns 150, and the pad patterns 120. As the dummy patterns 150 are formed on the second region b, thickness distribution of the interlayer insulating layer 700 may be improved by a planarization process.

The pattern density of word lines on the second region may be lower than that of the first region. As the pattern density is lower, pattern defects such as breakage of the pattern and bridges between the patterns may increase. According to the inventive concept, the second upper mask patterns substantially the same as the first upper mask patterns of the first region may be formed on the second region. By forming the second upper mask patterns, since the pattern density on the second region is increased, the pattern line width distribution of the word lines on the second region may be improved. In addition, by forming dummy patterns on the second region, the thickness distribution of the interlayer insulating layer between the regions may be improved during the subsequent planarization process.

17 is a schematic block diagram illustrating an example of an electronic device including a semiconductor device according to the inventive concept.

Referring to FIG. 17, an electronic device 1100 according to the inventive concept may include a controller 1110, an input / output device 1120, an I / O, a memory device 1130, an interface 1140, and a bus 1150. , bus). The controller 1110, the input / output device 1120, the storage device 1130, and / or the interface 1140 may be coupled to each other via the bus 1150. The bus 1150 corresponds to a path through which data is moved.

The controller 1110 may include at least one of a microprocessor, a digital signal process, a microcontroller, and logic elements capable of performing similar functions. The input / output device 1120 may include a keypad, a keyboard, a display device, and the like. The storage device 1130 may store data and / or instructions and the like. The memory device 1130 may include at least one of semiconductor devices manufactured according to the inventive concept. Further, the storage device 1130 may further include other types of semiconductor memory devices (ex, a DRAM device and / or an SRAM device, etc.). The interface 1140 may perform functions to transmit data to or receive data from the communication network.

The electronic device 1100 can be a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital A music player, a digital music player, a memory card, or other electronic product.

18 is a schematic block diagram illustrating an example of a memory card including a semiconductor device according to the inventive concept.

Referring to FIG. 18, the memory card 1200 includes a memory device 1210. The memory device 1210 may include at least one of semiconductor devices manufactured according to the inventive concept. Further, the storage device 1210 may further include other types of semiconductor memory devices (ex, a DRAM device and / or an SRAM device, etc.). The memory card 1200 may include a memory controller 1220 that controls data exchange between a host 1230 and the memory device 1210.

The foregoing description of embodiments of the present invention provides illustrative examples for the description of the present invention. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention as defined by the appended claims. It is clear.

100: substrate 200: gate patterns
WL: word lines 300: mask patterns
110 and 150 dummy patterns 330 first upper mask patterns
120: pad patterns 340: second upper mask patterns
630: first lower mask patterns 430: first spacer mask patterns
640: second lower mask patterns 440: second spacer mask patterns
650: third lower mask patterns

Claims (10)

Providing a substrate comprising a cell array region, a peripheral circuit region, and an interface region between the cell array region and the peripheral circuit region;
Sequentially forming a gate layer and an upper mask layer on the substrate;
Patterning the upper mask layer to simultaneously form first upper mask patterns of a cell array region and second upper mask patterns of an interface region; And
Forming word lines on the cell array region and dummy patterns on the interface region using the first and second upper mask patterns. The method according to claim 1,
Forming a lower mask layer between the gate layer and the upper mask layer;
Forming word lines on the cell array region and dummy patterns on the interface region using the first and second upper mask patterns:
Forming first spacer mask patterns and second spacer mask patterns on sidewalls of the first and second upper mask patterns, respectively;
Etching the lower mask layer using the first and second spacer mask patterns as an etch mask to form first lower mask patterns in a cell array region and second lower mask patterns in an interface region; And
And etching the gate layer using the first and second lower mask patterns as an etch mask. The method according to claim 2,
Forming the first and second spacer mask patterns is:
Forming a spacer layer on the first and second upper mask patterns;
Etching the spacer layer until the top surfaces of the first and second upper mask patterns and the top surface of the lower mask layer are exposed; And
And removing the first and second upper mask patterns. The method according to claim 2,
Forming pad patterns extending from the word lines on the interface region;
Forming the pad patterns is:
Forming preliminary mask patterns exposing at least some of the first and second spacer mask patterns;
Etching the lower mask layer using the preliminary mask patterns as an etch mask to form third lower mask patterns; And
And etching the gate layer using the third lower mask patterns as an etch mask. The method of claim 4,
The width of the dummy patterns is the same as the width of the word lines, the method of manufacturing a semiconductor device smaller than the width of the pad patterns. The method according to claim 1,
The width of the first upper mask patterns and the width of the second upper mask patterns are the same. The method according to claim 1,
Forming a lower mask layer between the gate layer and the upper mask layer;
Forming word lines on the cell array region and dummy patterns on the interface region using the first and second upper mask patterns:
Forming first spacer mask patterns and second spacer mask patterns on sidewalls of the first and second upper mask patterns, respectively;
Removing the second spacer mask patterns to expose the lower mask layer;
Forming first preliminary mask patterns exposing the first spacer mask patterns on the exposed lower mask layer;
Etching the lower mask layer using the first spacer mask patterns and the first preliminary mask patterns as an etch mask to form first and second lower mask patterns; And
And etching the gate layer using the first and second lower mask patterns as an etch mask. The method of claim 7,
Forming pad patterns extending from the word lines on the interface region;
Forming the pad patterns is:
Forming second preliminary mask patterns spaced apart from the first preliminary mask patterns on the exposed lower mask layer;
Etching the lower mask layer using the second preliminary mask patterns as an etch mask to form third lower mask patterns; And
And etching the gate layer using the third lower mask patterns as an etch mask. A substrate comprising a cell array region, a peripheral circuit region, and an interface region between the cell array region and the peripheral circuit region;
Word lines on the cell array region;
Pad patterns provided on the interface region and connected to the word lines; And
Dummy patterns provided on the interface area and spaced apart from the word lines and the pad patterns,
And the dummy patterns are equal to the width of the word lines and have a width smaller than the width of the pad patterns. The method of claim 9,
And the dummy patterns are electrically isolated.

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