US20130187696A1 - Circuit for generating multi-phase non-overlapping clock signals - Google Patents
Circuit for generating multi-phase non-overlapping clock signals Download PDFInfo
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- the present invention relates generally to integrated circuits and, more particularly, to generating multi-phase, non-overlapping clock signals used in integrated circuits.
- Multi-phase clock signals are generally used as synchronized clock signals in circuits including cyclic analog-to-digital converters (ADCs). Multi-phase clock signals are generated by dividing the frequency of a reference clock signal. In addition to synchronization, multi-phase clock signals must meet other specific requirements of the digital signal processing circuits. One such requirement is the generation of non-overlapping clock signals. Non-overlapping clock signals are clock signals having active periods that do not overlap. FIG. 1 shows a timing diagram of two non-overlapping clock signals, Ph 1 and Ph 2 in which the active periods Ph 1 and Ph 2 do not overlap.
- FIG. 2 is a schematic diagram of a conventional circuit 200 for generating multi-phase, non-overlapping clock signals.
- the circuit 200 generates a set of four non-overlapping clock signals that are phase-shifted from each other and includes a shift register 202 that receives an input clock signal 204 and divides the frequency of the input clock signal 204 to generate four phase-shifted clock signals Q A , Q B , Q C and Q D .
- the number of phase-shifted clock signals corresponds to the number of non-overlapping clock signals required to be generated by the circuit 200 .
- the phase-shifted clock signals Q A , Q B , Q C and Q D are provided to corresponding circuit modules 206 a, 206 b, 206 c and 206 d (collectively referred to as circuit modules 206 ).
- Each circuit module 206 includes a NOT gate connected to a NOR gate.
- the circuit module 206 a includes NOT gate 208 a connected to NOR gate 210 a.
- the NOT gate 208 a receives the clock signal Q A , inverts it, and provides the inverted clock signal to an input of the NOR gate 210 a.
- the NOR gate 210 a also receives a feedback signal FB 4 and generates a first clock signal Ph 1 .
- the circuit modules 206 b - 206 d generate second, third and fourth clock signals, Ph 2 , Ph 3 and Ph 4 .
- the set of clock signals Ph 1 -Ph 4 are delayed using corresponding delay circuits 212 a - 212 d, which generally comprise strings of buffers.
- the delay circuits 212 a - 212 d introduce a predetermined time delay T d and generate corresponding feedback signals FB 1 , FB 2 , FB 3 , and FB 4 .
- the feedback signals FB 1 -FB 4 are provided to the circuit modules 206 a - 206 d in a cyclic order, i.e., the feedback signal generated using one clock signal is provided to a circuit module generating the next clock signal.
- feedback signals FB 1 , FB 2 , FB 3 and FB 4 are provided to the circuit modules 206 b, 206 c, 206 d and 206 a, respectively.
- the feedback signals FB 1 -FB 4 are provided as inputs to the respective NOR gates 210 b, 210 c, 210 d and 210 a to ensure that the clock signals Ph 1 -Ph 4 have non-overlapping active periods and adjacent clock signals (i.e., Ph 1 and Ph 2 , Ph 2 and Ph 3 , Ph 3 and Ph 4 , and Ph 4 and Ph 1 ) are separated by the predetermined time T d .
- the active periods of the clock signals Ph 1 and Ph 2 are separated by the predetermined time T d .
- the conventional circuit 200 introduces significant area overhead when transferred to an integrated circuit because it uses a separate circuit arrangement for generating each non-overlapping clock signal.
- the clock signal Ph 1 is generated using the circuit module 206 a and the delay circuit 212 a.
- the overhead increases proportionally with the number of non-overlapping clock signals generated.
- generation of each clock signal using a separate delay circuit introduces small variations in the delay time T d . These variations lead to time mismatches between the non-overlapping clock signals and lower the performance of a cyclic ADC or any other circuit that uses such clock signals.
- FIG. 1 is a timing diagram of two non-overlapping clock signals
- FIG. 2 is a schematic block diagram of a conventional circuit for generating multi-phase, non-overlapping clock signals
- FIG. 3 is a schematic block diagram of a circuit for generating multi-phase, non-overlapping clock signals in accordance with an embodiment of the present invention
- FIG. 4 is a timing diagram of four exemplary non-overlapping clock signals generated by the circuit of FIG. 3 ;
- FIG. 5 is a schematic block diagram of a circuit for generating multi-phase, non-overlapping clock signals in accordance with another embodiment of the present invention.
- FIG. 6 is a schematic block diagram of a circuit for generating multi-phase, non-overlapping clock signals in accordance with yet another embodiment of the present invention.
- FIG. 7 is a flow chart illustrating a method for generating multi-phase, non-overlapping clock signals in accordance with an embodiment of the present invention.
- a circuit for generating multi-phase, non-overlapping clock signals includes a shift register that generates first and second clock signals by dividing an input clock signal.
- the first and second clock signals are respectively received by first and second circuit modules that are connected to the shift register.
- the first circuit module receives a first feedback signal and generates a first interim signal using the first clock signal and the first feedback signal.
- the second circuit module receives the second feedback signal and generates a second interim signal.
- the first and second interim signals are non-overlapping by at least a predetermined minimum time difference.
- a multiplexer multiplexes the first and second interim signals to generate an output signal.
- a first delay circuit delays the output signal by a first predetermined time to generate a first delay signal.
- a second delay circuit delays the first delay signal by a second predetermined time to generate a second delay signal.
- a first de-multiplexer receives the second delay signal and generates the first and the second feedback signals.
- a second de-multiplexer receives the first delay signal and generates a set of multi-phase, non-overlapping clock signals.
- a circuit for generating multi-phase, non-overlapping clock signals includes a shift register that generates a plurality of clock signals by dividing the frequency of an input clock signal.
- the circuit also includes a plurality of circuit modules that receive a plurality of clock signals.
- the circuit modules also receive a plurality of feedback signals.
- Each circuit module generates a clock signal of a set of multi-phase, non-overlapping clock signals using the corresponding clock signal and feedback signal.
- the clock signals are generated by the plurality of circuit modules such that the non-overlapping period between the clock signals is of at least a predetermined minimum time.
- a multiplexer multiplexes the multi-phase, non-overlapping clock signals to generate an output signal.
- a first delay circuit delays the output signal by a first predetermined time to generate a first delay signal.
- a second delay circuit delays the first delay signal by a second predetermined time to generate a second delay signal.
- the second delay signal is de-multiplexed by a first de-multiplexer to generate the plurality of feedback signals.
- the first delay signal is de-multiplexed by a second de-multiplexer to generate another set of multi-phase, non-overlapping clock signals.
- a circuit for generating sets of multi-phase, non-overlapping clock signals includes a shift register that generates a plurality of clock signals by dividing an input clock signal.
- a plurality of circuit modules receive the plurality of clock signals and a plurality of feedback signals and generate a first, early set of multi-phase, non-overlapping clock signals.
- a plurality of first delay circuits are connected to the plurality of circuit modules and receive the first set of non-overlapping clock signals and generate a second set of multi-phase, non-overlapping clock signals that are offset from the first set of clock signals by a first predetermined time.
- a multiplexer is connected to the plurality of first delay circuits and multiplexes the second set of clock signals and generates an output signal.
- a second delay circuit generates a second delay signal by delaying the output signal by a second predetermined time.
- a de-multiplexer receives the second delay signal and generates the plurality of feedback signals.
- Various embodiments of the present invention provide a system and method for generating multi-phase, non-overlapping clock signals.
- the system of the present invention uses a single delay circuit to generate multiple non-overlapping clock signals as compared to multiple delay circuits required in prior-art systems.
- the use of a single delay circuit reduces area overhead and eliminates variations in the delay time that are otherwise introduced by conventional systems. Therefore, the multi-phase, non-overlapping clock signals generated by the present invention are reliable as compared to those generated by conventional systems and in turn, increase the reliability of circuits that use these signals.
- the circuit of the present invention is flexible and can be re-configured to generate multiple non-overlapping clock signals with different phases.
- FIG. 3 a schematic block diagram of a circuit 300 for generating multi-phase, non-overlapping clock signals in accordance with an embodiment of the present invention is shown.
- the circuit 300 generates two sets of four non-overlapping clock signals that are phase shifted from each other.
- the circuit 300 includes a shift register 302 that receives an input clock signal 304 and divides the frequency of the input clock signal 304 to generate four phase-shifted clock signals Q A , Q B , Q C and Q D .
- the number of phase-shifted clock signals corresponds to the number of non-overlapping clock signals that are required to be generated by the circuit 300 .
- Each circuit module 306 includes a NOT gate connected to a NOR gate.
- the circuit module 306 a includes NOT gate 308 a connected to NOR gate 310 a .
- the NOT gate 308 a receives the clock signal Q A , inverts it, and provides the inverted clock signal /Q A to an input of the NOR gate 310 a.
- the NOR gate 310 a also receives a feedback signal FB I and generates an early signal Ph 1e corresponding to a first non-overlapping clock signal Ph 1 .
- the circuit modules 306 b - 306 d generate early signals Ph 2 , Ph 3e and Ph 4e corresponding to the remaining non-overlapping clock signals Ph 2 , Ph 3 and Ph 4 .
- the early signals Ph 1e -Ph 4e represent the first set of non-overlapping clock signals.
- the clock signals Ph 1 -Ph 4 represent the second set of non-overlapping clock signals.
- the delay circuits 312 a - 312 d delay the corresponding early signals Ph 1e -Ph 4e by a predetermined time T e .
- the delay circuits 312 a - 312 d can be implemented as a string of buffers, as is known in the art.
- the delay circuits 312 a - 312 d also may include, for example, capacitors at intermediate stage outputs to increase delay and/or the buffers themselves may be weak (small W/L device ratios), also as is known in the art. It is preferred that each of the delay circuits has the same circuit structure so that they generate equivalent delays.
- FIG. 4 is a timing diagram showing four exemplary non-overlapping clock signals generated by the circuit 300 .
- the delay T e corresponds to the delay between the early signals Ph 1e -Ph 4e and the corresponding non-overlapping clock signals Ph 1 -Ph 4 .
- the delay T e is shown between early signals Ph 1e and Ph 3e and respective clock signals Ph 1 and Ph 3 .
- the non-overlapping clock signals Ph 1 -Ph 4 are multiplexed using a multiplexer 314 to generate an output signal PH_CLK.
- an OR gate is used to multiplex the non-overlapping clock signals Ph 1 -Ph 4 .
- the output signal PH_CLK is input to a delay circuit 316 that introduces a predetermined time delay T d in the output signal PH_CLK.
- the predetermined delay T d corresponds to the non-overlapping time between the clock signals Ph 1 , Ph 2 , Ph 3 and Ph 4 , as shown in FIG. 4 .
- the delay circuit 316 is similar to the delay circuits 312 in that it comprises a string of buffers and may or may not be modified as described above.
- the output of the delay circuit 316 is de-multiplexed using a de-multiplexer 318 .
- the de-multiplexer receives a select signal SEL from a counter 320 , which in a preferred embodiment is a modulo-N counter.
- the binary counter 320 receives the output signal PH_CLK as a clock signal and generates the select signal SEL.
- the de-multiplexer 318 generates four feedback signals FB 1 , FB 2 , FB 3 , and FB 4 .
- the feedback signals FB 1 -FB 4 are provided to corresponding ones of the circuit modules 306 a - 306 d .
- circuit 300 is shown to generate two sets of four non-overlapping clock signals, the invention should not be considered limited to generating four non-overlapping clock signals only, as it should be understood by those of skill in the art that the circuit can be extended to generate any number of non-overlapping clock signals (see, for example, FIG. 5 , discussed below).
- the circuit 300 differs from the conventional circuit 200 in that the second set of clock signals Ph 1 -Ph 4 are input to the mux 314 and then a single delay circuit 316 is used to generate the delayed clock signals that are used to generate the feedback signals FB 1 -FB 4 .
- Using the single delay circuit 316 saves the area used by the four delay circuits 212 a - 212 d of the conventional circuit 200 (less the area of the mux 314 , demux 318 , and modulo-N counter 320 ), and since each feedback signal is generated by the same circuitry, the delay values therebetween are not skewed.
- FIG. 5 a schematic block diagram of a circuit 500 for generating multi-phase, non-overlapping clock signals in accordance with another embodiment of the present invention is shown.
- the circuit 500 generates two sets of non-overlapping clock signals, each set including ‘n’ clock signals that are phase shifted from each other.
- the circuit 500 includes a shift register 502 that divides the frequency of an input clock signal 504 to generate n phase-shifted clock signals Q A , Q B to Q n .
- Circuit modules 506 a , 506 b to 506 n generate early signals Ph 1e , Ph 2e to Ph ne using corresponding clock signals Q A -Q n and corresponding feedback signals FB 1 , FB 2 to FB n .
- the early signals Ph 1e -Ph ne represent the first set of non-overlapping clock signals and provided to a multiplexer 508 , which in the embodiment shown is an OR gate, to generate an output signal PH_CLK.
- the output signal PH_CLK is delayed by a predetermined time T e with a first delay circuit 510 to generate a first delay signal 512 .
- the first delay signal 512 is delayed by a predetermined time T d with a second delay circuit 514 to generate a second delay signal 516 .
- the first delay signal 512 is de-multiplexed by a first de-multiplexer 518 to generate non-overlapping clock signals Ph 1 , Ph 2 to Ph n .
- the clock signals Ph 1 -Ph n represent the second set of non-overlapping clock signals.
- a first counter 520 receives the second delay signal 516 as a clock signal and generates a select signal SEL_ 1 for the first de-multiplexer 518 .
- a second de-multiplexer 522 receives the second delay signal 516 and generates the feedback signals FB 1 -FB n .
- a select signal SEL_ 2 for the second de-multiplexer 522 is generated by a second counter 526 .
- the second counter 526 receives the output signal PH_CLK as a clock signal.
- both the first and second delay circuits 510 and 514 are provided on the output side of the multiplexer 508 so all of the clock signals of the first set Ph 1e -Ph ne will travel essentially the same delay path.
- the first and second counters 520 and 526 comprise modulo-N counters.
- FIG. 6 a schematic block diagram of a circuit 600 for generating multi-phase, non-overlapping clock signals in accordance with yet another embodiment of the present invention is shown.
- the circuit 600 generates two sets of ‘n’ non-overlapping clock signals that are phase shifted from each other.
- the circuit 600 includes a shift register 602 that divides the frequency of an input clock signal 604 to generate two phase-shifted clock signals Q A and Q B .
- Circuit modules 606 a and 606 b receive the clock signals Q A and Q B , and feedback signals FB 1 and FB 2 , respectively, and generate corresponding interim signals 608 a and 608 b .
- the interim signals 608 a and 608 b are multiplexed, in the embodiment shown with OR gate 610 , to generate an output signal PH_CLK.
- the output signal PH_CLK is delayed with a first delay circuit 612 to generate a first delay signal 614 .
- the first delay circuit 612 introduces a delay of a predetermined time T e .
- the first delay signal 614 is provided to a second delay circuit 616 and delayed by a second predetermined time T d to generate a second delay signal 617 .
- the second predetermined time T d determines the non-overlapping time between the non-overlapping clock signals of each set.
- the second delay signal 617 is provided to a first de-multiplexer 618 to generate the feedback signals FB 1 and FB 2 .
- a frequency divider 619 generates and provides a select signal SEL_ 2 to the first de-multiplexer 618 .
- the frequency divider 619 divides the frequency of the first delay signal 614 (in one embodiment by half) to generate the select signal SEL_ 2 .
- the feedback signals FB 1 and FB 2 are supplied to the corresponding circuit modules 606 a and 606 b.
- the first delay signal 614 is de-multiplexed by a second de-multiplexer 620 to generate a first set of non-overlapping clock signals Ph 1 , Ph 2 to Ph n .
- a modulo-N counter 622 is used to generate a select signal SEL_ 1 for the second de-multiplexer 620 .
- the second delay signal 617 is provided as a clock signal to the modulo-N counter 622 .
- the modulo-N counter 622 generates count values from 0 to n ⁇ 1.
- the second de-multiplexer 620 receives the count values as SEL_ 1 signal and de-multiplexes the first delay signal 614 to generate the non-overlapping clock signals Ph 1 -Ph n .
- the modulo-N counter 622 can be set to any number N to generate the desired number of non-overlapping clock signals.
- the modulo-N counter 622 can be set to count from 0 to 3 to generate four non-overlapping clock signals or the modulo-N counter 622 can be set to count from 0 to 7 to generate eight non-overlapping clock signals.
- the circuit 600 is re-configurable and can be used to generate any number of non-overlapping clock signals.
- the circuit 600 also enables generation of early signals corresponding to non-overlapping clock signals Ph 1 -Ph n .
- a third de-multiplexer 624 de-multiplexes the output signal PH_CLK to generate early signals Ph 1e , Ph 2e to Ph ne based on the select signal SEL_ 1 .
- the early signals Ph 1e -Ph ne represent the second set of non-overlapping clock signals.
- the circuit 600 may also include a phase selection circuit 626 connected between the modulo-N counter 622 and the second and third de-multiplexers 620 and 624 .
- the phase selection circuit 626 selects particular values of the select signal SEL_ 1 and controls the generation of the non-overlapping clock signals Ph 1 -Ph n as well as early signals Ph 1e -Ph ne .
- the modulo-N counter 622 is programmed to generate count values 0 to 7
- the phase selection circuit 626 may select and provide count values of 0 and 2 to the second and third de-multiplexers 620 and 624 .
- the second de-multiplexer 620 generates two non-overlapping clock signals, i.e., Ph 1 and Ph 3
- the third de-multiplexer 624 generates two early signals, i.e., Ph 1e and Ph 3e .
- the non-overlapping time between Ph 1 and Ph 3 is Td.
- FIG. 7 a flow chart illustrating a method for generating multi-phase, non-overlapping clock signals in accordance with an embodiment of the present invention is shown.
- two phase-shifted clock signals, Q A and Q B are generated by the shift register 602 by dividing the frequency of the input clock signal 604 .
- the interim signals 608 a and 608 b are generated using the clock signals Q A and Q B , and feedback signals FB 1 and FB 2 .
- the interim signals 608 a and 608 b are non-overlapping by at least a predetermined minimum time difference.
- the interim signals are multiplexed by the OR gate 610 at step 706 .
- the output signal PH_CLK is generated and is delayed by the predetermined time, T e , to generate the first delay signal 614 .
- the first delay signal 614 is delayed by the predetermined time, T d , to generate the second delay signal 617 .
- the first de-multiplexer 618 de-multiplexes the second delay signal 617 to generate the feedback signals FB 1 and FB 2 .
- the select signal SEL_ 2 to the first de-multiplexer 618 is generated by the frequency divider 619 by dividing the frequency of the first delay signal 614 .
- the first delay signal 614 is de-multiplexed by the second de-multiplexer 620 to generate ‘n’ non-overlapping clock signals Ph 1 -Ph n .
- the non-overlapping clock signals Ph 1 -Ph n represent the first set of non-overlapping clock signals.
- the select signal SEL_ 1 to the second de-multiplexer 620 is generated by the modulo-N counter 622 using the second delay signal 617 .
- the output signal PH_CLK is de-multiplexed by the third de-multiplexer 624 to generate early signals Ph e1 -Ph en .
- the early signals Ph e1 -Ph en represent the second set of non-overlapping clock signals.
- the select signal SEL_ 1 is also provided to the third de-multiplexer 624 .
- a circuit such as the circuit 600 , can also be used to generate one set of non-overlapping clock signals (Ph 1 -Ph n ) without generating the early signals (Ph 1e -Ph ne ). In this case, the third de-multiplexer 624 is not required in the circuit 600 .
Abstract
Description
- The present invention relates generally to integrated circuits and, more particularly, to generating multi-phase, non-overlapping clock signals used in integrated circuits.
- Many digital signal processing circuits require synchronized clock signals for synchronizing the operations of internal circuits. Multi-phase clock signals are generally used as synchronized clock signals in circuits including cyclic analog-to-digital converters (ADCs). Multi-phase clock signals are generated by dividing the frequency of a reference clock signal. In addition to synchronization, multi-phase clock signals must meet other specific requirements of the digital signal processing circuits. One such requirement is the generation of non-overlapping clock signals. Non-overlapping clock signals are clock signals having active periods that do not overlap.
FIG. 1 shows a timing diagram of two non-overlapping clock signals, Ph1 and Ph2 in which the active periods Ph1 and Ph2 do not overlap. -
FIG. 2 is a schematic diagram of aconventional circuit 200 for generating multi-phase, non-overlapping clock signals. Thecircuit 200 generates a set of four non-overlapping clock signals that are phase-shifted from each other and includes ashift register 202 that receives aninput clock signal 204 and divides the frequency of theinput clock signal 204 to generate four phase-shifted clock signals QA, QB, QC and QD. The number of phase-shifted clock signals corresponds to the number of non-overlapping clock signals required to be generated by thecircuit 200. The phase-shifted clock signals QA, QB, QC and QD are provided tocorresponding circuit modules circuit module 206 a includesNOT gate 208 a connected toNOR gate 210 a. TheNOT gate 208 a receives the clock signal QA, inverts it, and provides the inverted clock signal to an input of theNOR gate 210 a. The NORgate 210 a also receives a feedback signal FB4 and generates a first clock signal Ph1. Similarly, thecircuit modules 206 b-206 d generate second, third and fourth clock signals, Ph2, Ph3 and Ph4. The set of clock signals Ph1-Ph4 are delayed using corresponding delay circuits 212 a-212 d, which generally comprise strings of buffers. The delay circuits 212 a-212 d introduce a predetermined time delay Td and generate corresponding feedback signals FB1, FB2, FB3, and FB4. The feedback signals FB1-FB4 are provided to the circuit modules 206 a-206 d in a cyclic order, i.e., the feedback signal generated using one clock signal is provided to a circuit module generating the next clock signal. Thus, feedback signals FB1, FB2, FB3 and FB4 are provided to thecircuit modules respective NOR gates FIG. 1 , the active periods of the clock signals Ph1 and Ph2 are separated by the predetermined time Td. - The
conventional circuit 200 introduces significant area overhead when transferred to an integrated circuit because it uses a separate circuit arrangement for generating each non-overlapping clock signal. For example, the clock signal Ph1 is generated using thecircuit module 206 a and thedelay circuit 212 a. The overhead increases proportionally with the number of non-overlapping clock signals generated. Also, generation of each clock signal using a separate delay circuit introduces small variations in the delay time Td. These variations lead to time mismatches between the non-overlapping clock signals and lower the performance of a cyclic ADC or any other circuit that uses such clock signals. - Therefore, there is a need for a circuit that generates multi-phase, non-overlapping clock signals and does not significantly increase area overhead and that overcomes the above-mentioned limitations.
- The following detailed description of the preferred embodiments of the present invention will be better understood when read in conjunction with the appended drawings. The present invention is illustrated by way of example, and not limited by the accompanying figures, in which like references indicate similar elements. It is to be understood that the drawings are not to scale and have been simplified for ease of understanding the invention.
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FIG. 1 is a timing diagram of two non-overlapping clock signals; -
FIG. 2 is a schematic block diagram of a conventional circuit for generating multi-phase, non-overlapping clock signals; -
FIG. 3 is a schematic block diagram of a circuit for generating multi-phase, non-overlapping clock signals in accordance with an embodiment of the present invention; -
FIG. 4 is a timing diagram of four exemplary non-overlapping clock signals generated by the circuit ofFIG. 3 ; -
FIG. 5 is a schematic block diagram of a circuit for generating multi-phase, non-overlapping clock signals in accordance with another embodiment of the present invention; -
FIG. 6 is a schematic block diagram of a circuit for generating multi-phase, non-overlapping clock signals in accordance with yet another embodiment of the present invention; and -
FIG. 7 is a flow chart illustrating a method for generating multi-phase, non-overlapping clock signals in accordance with an embodiment of the present invention. - The detailed description of the appended drawings is intended as a description of the currently preferred embodiments of the present invention, and is not intended to represent the only form in which the present invention may be practiced. It is to be understood that the same or equivalent functions may be accomplished by different embodiments that are intended to be encompassed within the spirit and scope of the present invention.
- In an embodiment of the present invention, a circuit for generating multi-phase, non-overlapping clock signals is provided. The circuit includes a shift register that generates first and second clock signals by dividing an input clock signal. The first and second clock signals are respectively received by first and second circuit modules that are connected to the shift register. The first circuit module receives a first feedback signal and generates a first interim signal using the first clock signal and the first feedback signal. The second circuit module receives the second feedback signal and generates a second interim signal. The first and second interim signals are non-overlapping by at least a predetermined minimum time difference. A multiplexer multiplexes the first and second interim signals to generate an output signal. A first delay circuit delays the output signal by a first predetermined time to generate a first delay signal. A second delay circuit delays the first delay signal by a second predetermined time to generate a second delay signal. A first de-multiplexer receives the second delay signal and generates the first and the second feedback signals. A second de-multiplexer receives the first delay signal and generates a set of multi-phase, non-overlapping clock signals.
- In another embodiment of the present invention, a circuit for generating multi-phase, non-overlapping clock signals is provided. The circuit includes a shift register that generates a plurality of clock signals by dividing the frequency of an input clock signal. The circuit also includes a plurality of circuit modules that receive a plurality of clock signals. The circuit modules also receive a plurality of feedback signals. Each circuit module generates a clock signal of a set of multi-phase, non-overlapping clock signals using the corresponding clock signal and feedback signal. The clock signals are generated by the plurality of circuit modules such that the non-overlapping period between the clock signals is of at least a predetermined minimum time. A multiplexer multiplexes the multi-phase, non-overlapping clock signals to generate an output signal. A first delay circuit delays the output signal by a first predetermined time to generate a first delay signal. A second delay circuit delays the first delay signal by a second predetermined time to generate a second delay signal. The second delay signal is de-multiplexed by a first de-multiplexer to generate the plurality of feedback signals. The first delay signal is de-multiplexed by a second de-multiplexer to generate another set of multi-phase, non-overlapping clock signals.
- In yet another embodiment of the present invention, a circuit for generating sets of multi-phase, non-overlapping clock signals is provided. The circuit includes a shift register that generates a plurality of clock signals by dividing an input clock signal. A plurality of circuit modules receive the plurality of clock signals and a plurality of feedback signals and generate a first, early set of multi-phase, non-overlapping clock signals. A plurality of first delay circuits are connected to the plurality of circuit modules and receive the first set of non-overlapping clock signals and generate a second set of multi-phase, non-overlapping clock signals that are offset from the first set of clock signals by a first predetermined time. A multiplexer is connected to the plurality of first delay circuits and multiplexes the second set of clock signals and generates an output signal. A second delay circuit generates a second delay signal by delaying the output signal by a second predetermined time. A de-multiplexer receives the second delay signal and generates the plurality of feedback signals.
- Various embodiments of the present invention provide a system and method for generating multi-phase, non-overlapping clock signals. The system of the present invention uses a single delay circuit to generate multiple non-overlapping clock signals as compared to multiple delay circuits required in prior-art systems. The use of a single delay circuit reduces area overhead and eliminates variations in the delay time that are otherwise introduced by conventional systems. Therefore, the multi-phase, non-overlapping clock signals generated by the present invention are reliable as compared to those generated by conventional systems and in turn, increase the reliability of circuits that use these signals. The circuit of the present invention is flexible and can be re-configured to generate multiple non-overlapping clock signals with different phases.
- Referring now to
FIG. 3 , a schematic block diagram of acircuit 300 for generating multi-phase, non-overlapping clock signals in accordance with an embodiment of the present invention is shown. Thecircuit 300 generates two sets of four non-overlapping clock signals that are phase shifted from each other. Thecircuit 300 includes ashift register 302 that receives aninput clock signal 304 and divides the frequency of theinput clock signal 304 to generate four phase-shifted clock signals QA, QB, QC and QD. The number of phase-shifted clock signals corresponds to the number of non-overlapping clock signals that are required to be generated by thecircuit 300. Clock signals QA, QB, QC and QD are provided tocorresponding circuit modules circuit module 306 a includesNOT gate 308 a connected to NORgate 310 a. TheNOT gate 308 a receives the clock signal QA, inverts it, and provides the inverted clock signal /QA to an input of the NORgate 310 a. The NORgate 310 a also receives a feedback signal FBI and generates an early signal Ph1e corresponding to a first non-overlapping clock signal Ph1. Similarly, thecircuit modules 306 b-306 d generate early signals Ph2, Ph3e and Ph4e corresponding to the remaining non-overlapping clock signals Ph2, Ph3 and Ph4. The early signals Ph1e-Ph4e represent the first set of non-overlapping clock signals. The early signals Ph1e-Ph4e and input to respective delay circuits 312 a-312 d to generate four non-overlapping clock signals Ph1-Ph4. The clock signals Ph1-Ph4 represent the second set of non-overlapping clock signals. The delay circuits 312 a-312 d delay the corresponding early signals Ph1e-Ph4e by a predetermined time Te. As a result, the first set (Ph1e-Ph4e) and the second set (Ph1-Ph4) of non-overlapping clock signals have a time difference of Te. The delay circuits 312 a-312 d can be implemented as a string of buffers, as is known in the art. The delay circuits 312 a-312 d also may include, for example, capacitors at intermediate stage outputs to increase delay and/or the buffers themselves may be weak (small W/L device ratios), also as is known in the art. It is preferred that each of the delay circuits has the same circuit structure so that they generate equivalent delays. -
FIG. 4 is a timing diagram showing four exemplary non-overlapping clock signals generated by thecircuit 300. The delay Te corresponds to the delay between the early signals Ph1e-Ph4e and the corresponding non-overlapping clock signals Ph1-Ph4. The delay Te is shown between early signals Ph1e and Ph3e and respective clock signals Ph1 and Ph3. The non-overlapping clock signals Ph1-Ph4 are multiplexed using amultiplexer 314 to generate an output signal PH_CLK. In one embodiment, an OR gate is used to multiplex the non-overlapping clock signals Ph1-Ph4. The output signal PH_CLK is input to adelay circuit 316 that introduces a predetermined time delay Td in the output signal PH_CLK. The predetermined delay Td corresponds to the non-overlapping time between the clock signals Ph1, Ph2, Ph3 and Ph4, as shown inFIG. 4 . Thedelay circuit 316 is similar to the delay circuits 312 in that it comprises a string of buffers and may or may not be modified as described above. - The output of the
delay circuit 316 is de-multiplexed using ade-multiplexer 318. The de-multiplexer receives a select signal SEL from acounter 320, which in a preferred embodiment is a modulo-N counter. Thebinary counter 320 receives the output signal PH_CLK as a clock signal and generates the select signal SEL. The de-multiplexer 318 generates four feedback signals FB1, FB2, FB3, and FB4. The feedback signals FB1-FB4 are provided to corresponding ones of the circuit modules 306 a-306 d. Although thecircuit 300 is shown to generate two sets of four non-overlapping clock signals, the invention should not be considered limited to generating four non-overlapping clock signals only, as it should be understood by those of skill in the art that the circuit can be extended to generate any number of non-overlapping clock signals (see, for example,FIG. 5 , discussed below). - The
circuit 300 differs from theconventional circuit 200 in that the second set of clock signals Ph1-Ph4 are input to themux 314 and then asingle delay circuit 316 is used to generate the delayed clock signals that are used to generate the feedback signals FB1-FB4. Using thesingle delay circuit 316 saves the area used by the four delay circuits 212 a-212 d of the conventional circuit 200 (less the area of themux 314,demux 318, and modulo-N counter 320), and since each feedback signal is generated by the same circuitry, the delay values therebetween are not skewed. - Referring now to
FIG. 5 , a schematic block diagram of acircuit 500 for generating multi-phase, non-overlapping clock signals in accordance with another embodiment of the present invention is shown. Thecircuit 500 generates two sets of non-overlapping clock signals, each set including ‘n’ clock signals that are phase shifted from each other. Thecircuit 500 includes ashift register 502 that divides the frequency of aninput clock signal 504 to generate n phase-shifted clock signals QA, QB to Qn. Circuit modules 506 a, 506 b to 506 n generate early signals Ph1e, Ph2e to Phne using corresponding clock signals QA-Qn and corresponding feedback signals FB1, FB2 to FBn. The early signals Ph1e-Phne represent the first set of non-overlapping clock signals and provided to amultiplexer 508, which in the embodiment shown is an OR gate, to generate an output signal PH_CLK. The output signal PH_CLK is delayed by a predetermined time Te with afirst delay circuit 510 to generate afirst delay signal 512. Thefirst delay signal 512 is delayed by a predetermined time Td with asecond delay circuit 514 to generate asecond delay signal 516. Thefirst delay signal 512 is de-multiplexed by afirst de-multiplexer 518 to generate non-overlapping clock signals Ph1, Ph2 to Phn. The clock signals Ph1-Phn represent the second set of non-overlapping clock signals. Afirst counter 520 receives thesecond delay signal 516 as a clock signal and generates a select signal SEL_1 for thefirst de-multiplexer 518. Asecond de-multiplexer 522 receives thesecond delay signal 516 and generates the feedback signals FB1-FBn. A select signal SEL_2 for thesecond de-multiplexer 522 is generated by asecond counter 526. Thesecond counter 526 receives the output signal PH_CLK as a clock signal. In this embodiment, both the first andsecond delay circuits multiplexer 508 so all of the clock signals of the first set Ph1e-Phne will travel essentially the same delay path. Also, in a preferred embodiment, the first andsecond counters - Referring now to
FIG. 6 , a schematic block diagram of acircuit 600 for generating multi-phase, non-overlapping clock signals in accordance with yet another embodiment of the present invention is shown. Thecircuit 600 generates two sets of ‘n’ non-overlapping clock signals that are phase shifted from each other. Thecircuit 600 includes ashift register 602 that divides the frequency of aninput clock signal 604 to generate two phase-shifted clock signals QA and QB. Circuit modules 606 a and 606 b receive the clock signals QA and QB, and feedback signals FB1 and FB2, respectively, and generate correspondinginterim signals interim signals gate 610, to generate an output signal PH_CLK. The output signal PH_CLK is delayed with afirst delay circuit 612 to generate afirst delay signal 614. Thefirst delay circuit 612 introduces a delay of a predetermined time Te. Thefirst delay signal 614 is provided to asecond delay circuit 616 and delayed by a second predetermined time Td to generate asecond delay signal 617. The second predetermined time Td determines the non-overlapping time between the non-overlapping clock signals of each set. - The
second delay signal 617 is provided to afirst de-multiplexer 618 to generate the feedback signals FB1 and FB2. Afrequency divider 619 generates and provides a select signal SEL_2 to thefirst de-multiplexer 618. Thefrequency divider 619 divides the frequency of the first delay signal 614 (in one embodiment by half) to generate the select signal SEL_2. The feedback signals FB1 and FB2 are supplied to thecorresponding circuit modules - The
first delay signal 614 is de-multiplexed by asecond de-multiplexer 620 to generate a first set of non-overlapping clock signals Ph1, Ph2 to Phn. A modulo-N counter 622 is used to generate a select signal SEL_1 for thesecond de-multiplexer 620. Thesecond delay signal 617 is provided as a clock signal to the modulo-N counter 622. The modulo-N counter 622 generates count values from 0 to n−1. Thesecond de-multiplexer 620 receives the count values as SEL_1 signal and de-multiplexes thefirst delay signal 614 to generate the non-overlapping clock signals Ph1-Phn. The modulo-N counter 622 can be set to any number N to generate the desired number of non-overlapping clock signals. For example, the modulo-N counter 622 can be set to count from 0 to 3 to generate four non-overlapping clock signals or the modulo-N counter 622 can be set to count from 0 to 7 to generate eight non-overlapping clock signals. - The
circuit 600 is re-configurable and can be used to generate any number of non-overlapping clock signals. Thecircuit 600 also enables generation of early signals corresponding to non-overlapping clock signals Ph1-Phn. Athird de-multiplexer 624 de-multiplexes the output signal PH_CLK to generate early signals Ph1e, Ph2e to Phne based on the select signal SEL_1. The early signals Ph1e-Phne represent the second set of non-overlapping clock signals. - The
circuit 600 may also include aphase selection circuit 626 connected between the modulo-N counter 622 and the second andthird de-multiplexers phase selection circuit 626 selects particular values of the select signal SEL_1 and controls the generation of the non-overlapping clock signals Ph1-Phn as well as early signals Ph1e-Phne. For example, if the modulo-N counter 622 is programmed to generatecount values 0 to 7, thephase selection circuit 626 may select and provide count values of 0 and 2 to the second andthird de-multiplexers second de-multiplexer 620 generates two non-overlapping clock signals, i.e., Ph1 and Ph3, and thethird de-multiplexer 624 generates two early signals, i.e., Ph1e and Ph3e. The non-overlapping time between Ph1 and Ph3 is Td. - Referring now to
FIG. 7 , a flow chart illustrating a method for generating multi-phase, non-overlapping clock signals in accordance with an embodiment of the present invention is shown. Various steps of the flow chart will be explained in conjunction withFIG. 6 . Atstep 702, two phase-shifted clock signals, QA and QB, are generated by theshift register 602 by dividing the frequency of theinput clock signal 604. Atstep 704, theinterim signals interim signals OR gate 610 atstep 706. Atstep 708, the output signal PH_CLK is generated and is delayed by the predetermined time, Te, to generate thefirst delay signal 614. Atstep 710, thefirst delay signal 614 is delayed by the predetermined time, Td, to generate thesecond delay signal 617. Atstep 712, thefirst de-multiplexer 618 de-multiplexes thesecond delay signal 617 to generate the feedback signals FB1 and FB2. The select signal SEL_2 to thefirst de-multiplexer 618 is generated by thefrequency divider 619 by dividing the frequency of thefirst delay signal 614. Atstep 714, thefirst delay signal 614 is de-multiplexed by thesecond de-multiplexer 620 to generate ‘n’ non-overlapping clock signals Ph1-Phn. The non-overlapping clock signals Ph1-Phn represent the first set of non-overlapping clock signals. The select signal SEL_1 to thesecond de-multiplexer 620 is generated by the modulo-N counter 622 using thesecond delay signal 617. At 716, the output signal PH_CLK is de-multiplexed by thethird de-multiplexer 624 to generate early signals Phe1-Phen. The early signals Phe1-Phen represent the second set of non-overlapping clock signals. The select signal SEL_1 is also provided to thethird de-multiplexer 624. - It will be apparent to those skilled in the art that many circuits require multi-phase, non-overlapping signals and their corresponding early signals for operation. For example, switched capacitor based circuits use early signals to implement bottom plate sampling to avoid signal dependent charge injection. In other words, early signals are required for designing parasitic insensitive switched capacitor circuits. A circuit, such as the
circuit 600, can also be used to generate one set of non-overlapping clock signals (Ph1-Phn) without generating the early signals (Ph1e-Phne). In this case, thethird de-multiplexer 624 is not required in thecircuit 600. - While various embodiments of the present invention have been illustrated and described, it will be clear that the present invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the present invention, as described in the claims.
Claims (19)
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US20130057326A1 (en) * | 2011-09-06 | 2013-03-07 | Elpida Memory, Inc. | Semiconductor device using multi-phase clock signal and information processing system including the same |
WO2017100078A1 (en) * | 2015-12-08 | 2017-06-15 | Rambus Inc. | Low power signaling interface |
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US8736309B2 (en) * | 2012-05-24 | 2014-05-27 | Freescale Semiconductor, Inc. | Non-overlapping clock generator circuit and method |
CN105336368B (en) * | 2014-07-18 | 2022-11-18 | 兆易创新科技集团股份有限公司 | Non-overlapping four-phase clock generation circuit |
US9537475B1 (en) * | 2016-01-06 | 2017-01-03 | Rambus Inc. | Phase interpolator device using dynamic stop and phase code update and method therefor |
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JP2959372B2 (en) | 1993-12-03 | 1999-10-06 | 日本電気株式会社 | Clock generation circuit |
US5692164A (en) | 1994-03-23 | 1997-11-25 | Intel Corporation | Method and apparatus for generating four phase non-over lapping clock pulses for a charge pump |
US20060038596A1 (en) * | 2004-08-18 | 2006-02-23 | Binan Wang | Delay locked loop circuitry and method for optimizing delay timing in mixed signal systems |
US7649957B2 (en) | 2006-03-22 | 2010-01-19 | Freescale Semiconductor, Inc. | Non-overlapping multi-stage clock generator system |
US8141024B2 (en) * | 2008-09-04 | 2012-03-20 | Synopsys, Inc. | Temporally-assisted resource sharing in electronic systems |
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US20130057326A1 (en) * | 2011-09-06 | 2013-03-07 | Elpida Memory, Inc. | Semiconductor device using multi-phase clock signal and information processing system including the same |
US8643413B2 (en) * | 2011-09-06 | 2014-02-04 | Yoshimitsu Yanagawa | Semiconductor device using multi-phase clock signal and information processing system including the same |
US20140132317A1 (en) * | 2011-09-06 | 2014-05-15 | Yoshimitsu Yanagawa | Semiconductor device using multi-phase clock signal and information processing system including the same |
US8860476B2 (en) * | 2011-09-06 | 2014-10-14 | Ps4 Luxco S.A.R.L. | Semiconductor device using multi-phase clock signal and information processing system including the same |
WO2017100078A1 (en) * | 2015-12-08 | 2017-06-15 | Rambus Inc. | Low power signaling interface |
US10622032B2 (en) | 2015-12-08 | 2020-04-14 | Rambus Inc. | Low power signaling interface |
US11450356B2 (en) | 2015-12-08 | 2022-09-20 | Rambus Inc. | Synchronous signaling interface with over-clocked timing reference |
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