US20130134508A1 - Semiconductor device with side-junction and method for fabricating the same - Google Patents
Semiconductor device with side-junction and method for fabricating the same Download PDFInfo
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- US20130134508A1 US20130134508A1 US13/725,498 US201213725498A US2013134508A1 US 20130134508 A1 US20130134508 A1 US 20130134508A1 US 201213725498 A US201213725498 A US 201213725498A US 2013134508 A1 US2013134508 A1 US 2013134508A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
Definitions
- Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device including a side-junction, and a method for fabricating the semiconductor device.
- each buried bit line BBL may be adjacent to two cells.
- a One-Side-Contact (OSC) process may be performed for forming a contact in an active region while insulating another active region.
- OSC process will be simply referred to as a sidewall contact process.
- each active region includes a body isolated by a trench and a pillar formed over the body.
- a buried bit line BBL fills a trench between bodies, and a word line (or a vertical gate) is disposed adjacent to the sidewall of a pillar and extended in a direction crossing a buried bit line BBL.
- the word line forms a channel in a vertical direction.
- a portion of a sidewall of the body is exposed to couple an active region with a buried bit line BBL.
- a junction is formed by implanting or diffusing a dopant into the exposed portion of the sidewall of the body.
- the buried bit line BBL and the body are electrically coupled through the junction. Since the junction is formed on just one sidewall of the body, the junction is referred to as a One-Side Junction (OSJ).
- OSJ One-Side Junction
- FIGS. 1A to 1C are cross-sectional views illustrating a conventional method for forming a semiconductor device by using a sidewall contact process.
- a plurality of bodies 103 isolated by trenches 102 are formed over a substrate 101 .
- a hard mask pattern 104 is formed over the bodies 103 .
- the hard mask pattern 104 functions as an etch barrier during the formation of active regions.
- the doped polysilicon layer 108 is planarized and etched back.
- the doped polysilicon layer pattern which is obtained from the planarization and etch-back processes gap-fills a portion of each trench 102 to the degree that the doped polysilicon layer pattern has a height to at least contact the sidewall.
- an annealing process 109 is performed.
- the dopant doping the doped polysilicon layer pattern is diffused into the sidewall of the body 103 exposed by the sidewall so as to form a sidewall junction 110 .
- a floating body 111 may be generated to increase a potential and cause a concern with respect to the operation of a cell transistor, such as a threshold voltage drop.
- An exemplary embodiment of the present invention is directed to a semiconductor device which prevents a floating body from being generated due to excessive diffusion of a sidewall junction, and a method for fabricating the semiconductor device.
- a method for fabricating a semiconductor device includes: forming a plurality of bodies that are each isolated from another by a trench and each include a diffusion barrier region with a sidewall exposed to the trench; forming a doped layer gap-filling the trench; forming a sidewall junction at the exposed sidewall of the diffusion barrier region by annealing the doped layer; and forming a conductive line coupled with the sidewall junction to fill the trench.
- a method for fabricating a semiconductor device includes: forming a diffusion barrier layer by performing an ion implantation process onto a substrate; forming a plurality of bodies that are each isolated from another by a trench and each include a diffusion barrier region of the diffusion barrier layer with a sidewall of the diffusion barrier region being exposed to the trench by etching the substrate to a depth below the diffusion barrier region; forming an insulation layer through which a sidewall contact is formed to expose the sidewall of the diffusion barrier region; forming a doped layer gap-filling the trench; forming a sidewall junction at the exposed sidewall of the diffusion barrier region by annealing the doped layer; and forming a buried bit line coupled with the sidewall junction to fill the trench.
- a semiconductor device a plurality of bodies that are each isolated from another by a trench and each include a diffusion barrier region with a sidewall exposed to the trench; an insulation layer through which a sidewall contact is formed to expose the exposed sidewall of the diffusion barrier region; a sidewall junction formed at the exposed sidewall of the diffusion barrier region; a buried bit line coupled with the sidewall junction and arranged to fill the trench; a plurality of pillars formed over the plurality of the bodies, respectively; and a vertical word line extending along a sidewall of each of the pillars in a direction crossing the buried bit line.
- FIGS. 1A to 1C are cross-sectional views illustrating a conventional method for forming a semiconductor device by using a sidewall contact process.
- FIG. 2 is a cross-sectional view illustrating a semiconductor device in accordance with an exemplary embodiment of the present invention.
- FIGS. 3A to 3G are cross-sectional views describing a method for forming the semiconductor device shown in FIG. 2 .
- FIGS. 4A to 4K are cross-sectional views illustrating a method of forming a sidewall contact in accordance with an exemplary embodiment of the present invention.
- FIGS. 5A to 5E are cross-sectional views illustrating a semiconductor device fabrication method after the formation of buried bit lines.
- first layer is referred to as being “on” a second layer or “on” a substrate, it not only refers to a case where the first layer is formed directly on the second layer or the substrate but also a case where a third layer exists between the first layer and the second layer or the substrate.
- FIG. 2 is a cross-sectional view illustrating a semiconductor device in accordance with an exemplary embodiment of the present invention.
- a plurality of bodies 201 each include a diffusion barrier region 23 A of a diffusion barrier layer and a sidewall exposing the diffusion barrier region 23 A. Then, through an insulation layer (for example, 29 A and 27 A), a sidewall contact exposing a portion of a sidewall and covering the bodies 201 is formed. A sidewall junction 38 is formed in the inside of the diffusion barrier region 23 A of the exposed portion of the sidewall. Subsequently, a conductive line coupled with the sidewall junction 38 is formed between the plurality of the bodies 201 .
- the conductive line includes a buried bit line 39 .
- the buried bit line 39 may be a metal bit line formed of a metal layer.
- the plurality of the bodies 201 isolated by trenches 26 are formed over a substrate 21 .
- the substrate 21 includes a silicon substrate.
- the plurality of the bodies 201 are formed by etching the substrate 21 .
- the plurality of the bodies 201 may include silicon bodies as well.
- the plurality of the bodies 201 are extended from the surface of the substrate 21 in a vertical direction, Each of the plurality of the bodies 201 is a region where a channel region, a source region and a drain region of a vertical transistor is formed.
- Each body 201 includes two sidewalls.
- the body 201 is referred to as an active body.
- a hard mask pattern 24 is formed in the upper portion of the body 201 .
- the hard mask pattern 24 functions as an etch barrier when the body 201 is formed.
- the hard mask pattern 24 includes a dielectric material layer such as an oxide layer and a nitride layer. According to an example, a nitride layer such as a silicon nitride layer is used as the hard mask pattern 24 .
- An insulation layer (for example, 29 A and 27 A) is formed on both sidewalls of the body 201 , the surface of a trench 26 between bodies 201 , and the surface of the hard mask pattern 24 .
- the insulation layer according to an example includes a liner oxide layer pattern 27 A and a liner nitride layer pattern 29 A.
- the liner oxide layer pattern 27 A is formed on both sidewalls of the body 201 and the surface of the trench 26 .
- the liner nitride layer pattern 29 A is formed on the surface of a portion of the liner oxide layer pattern 27 A.
- a sidewall contact (‘ 35 ’ in FIG. 4K ) is formed by removing a portion of the insulation layer ( 29 A and 27 A).
- the sidewall contact 35 is a one-side contact which selectively exposes a portion of just one sidewall of the body 201 .
- the sidewall contact 35 includes a linear opening which has a shape of line extended along the sidewall of the body 201 .
- the above-described insulation layer ( 29 A and 27 A) provides the sidewall contact 35 which exposes a portion of the sidewall of the body 201 .
- a method for forming the sidewall contact 35 will be described later on with reference to FIGS. 4A to 4K .
- a sidewall junction 38 is formed in the inside of the diffusion barrier region 23 A. With the diffusion barrier region 23 A, the sidewall junction 38 is prevented from being excessively diffused.
- the diffusion barrier region 23 A includes an interstitial impurity such as carbon.
- the sidewall junction 38 may include phosphorus (P).
- FIGS. 3A to 3G are cross-sectional views describing a method for forming the semiconductor device shown in FIG. 2 .
- a first impurity is ion-implanted into a substrate 21 .
- the substrate 21 includes a silicon substrate.
- a first impurity is implanted into a region reserved for a junction through ion implantation 22 to form a diffusion barrier layer 23 .
- the ion implantation is performed using carbon as the first impurity. Since the substrate 21 is a silicon substrate, carbon becomes an interstitial impurity within the substrate 21 .
- the dopant for doping a doped polysilicon layer to be formed later in the semiconductor device fabrication process is phosphorus (P)
- the phosphorus (P) is diffused through interstitial sites.
- carbon is already implanted and diffused into the interstitial sites in, for example, the diffusion barrier layer 23 , the excessive diffusion of the phosphorus (P) may be prevented. Meanwhile, carbon may have substantially no effect on the conductivity of a sidewall junction.
- the diffusion barrier region 23 becomes silicon carbide (SiC).
- a hard mask pattern 24 is formed over the substrate 21 .
- the hard mask pattern 24 is formed by forming a hard mask layer and then etching the hard mask layer using a photoresist pattern 25 as an each barrier.
- the photoresist pattern 25 is a line-and-space pattern and it may be also called a buried bit line (BBL) mask.
- the hard mask pattern 24 may be formed of an oxide layer, a nitride layer, or stacked layers of the two. According to an example, a nitride layer such as a silicon nitride is used as the hard mask pattern 24 .
- the photoresist pattern 25 is stripped and a plurality of trenches 26 are formed by using the hard mask pattern 24 as an etch barrier and etching the substrate 21 to a desired depth. Due to the plurality of the trenches 26 , a plurality of bodies 201 are formed over the substrate 21 . The plurality of the bodies 201 are extended from the surface of the substrate 21 in a vertical direction. Each body 201 has two sidewalls. In a vertical cell structure, a body 201 is an active region where a channel region, a source region, and a drain region of a transistor are formed.
- the sidewalls of the body 201 may have a vertical profile as shown.
- the etch process for forming the plurality of bodies 201 and the plurality of the trenches 26 may be a dry etch process using plasma.
- each of the plurality of the bodies 201 has a sidewall which exposes a diffusion barrier region 23 A. Since the substrate 21 is a silicon substrate, the plurality of the bodies 201 may be referred to as silicon bodies.
- a sidewall contact 35 is formed to expose a portion of a sidewall of a body 201 , that is, a portion of the diffusion barrier region 23 A.
- the sidewall contact 35 is formed of an insulation layer that includes a liner oxide layer pattern 27 A and a liner nitride layer pattern 29 A.
- the liner oxide layer pattern 27 A is formed on both sidewalls of the body 201 and the surface of the substrate 21 .
- the liner nitride layer pattern 29 A is formed on the surface of a portion of the liner oxide layer pattern 27 A.
- the sidewall contact 35 is formed by removing a portion of the insulation layer.
- the sidewall contact 35 is a one-side contact which selectively exposes a portion of a sidewall of the body 201 .
- the sidewall contact 35 includes a linear opening which is formed in the shape of line.
- the sidewall contact 35 exposes a portion of a sidewall of the body 201 (for example, the diffusion barrier region 23 A) at a region reserved for a junction through the insulation layer.
- a method for forming the sidewall contact 5 will be described in detail later with reference to FIGS. 4A to 4K .
- a doped layer is formed to gap-fill the plurality of the trenches 26 between the plurality of the bodies 201 .
- the doped layer includes an impurity for forming a junction implanted therein.
- the doped layer may include a doped polysilicon layer 36 .
- the doped polysilicon layer 36 has excellent step coverage, it may gap-fill the plurality of the trenches 26 without voids. Therefore, the doped polysilicon layer 36 used in forming a junction has excellent dose uniformity, where the doped polysilicon layer 36 is doped with a dopant for forming a junction.
- the dopant for the doped polysilicon layer 36 may be an N-type impurity such as phosphorus (P).
- the doped polysilicon layer 36 may be formed through a Chemical Vapor Deposition (CVD) method.
- the dopant doping the doped polysilicon layer 36 includes a dose ranging from approximately 1 ⁇ 10 15 to approximately 1 ⁇ 10 17 atoms/cm 2 .
- the doped polysilicon layer 36 is illustrated as an example, another material doped with an impurity for forming a junction may be used according to another example. For instance, an oxide layer such as phosphor silicate glass (PSG) may be used.
- PSG phosphor silicate glass
- the doped polysilicon layer 36 is planarized and etched back.
- the doped polysilicon layer 36 acquired after the planarization and etch-back processes is referred to as a doped polysilicon layer pattern 36 A, hereafter.
- the doped polysilicon layer pattern 36 A is formed to gap-fill a portion of each trench 26 , where the doped polysilicon layer pattern 36 A has a sufficient height to cover the opening on a sidewall of the body 201 for the sidewall contact 35 .
- the dopant may be prevented from being diffused into the regions other than the sidewall contact during a subsequent annealing process when the planarization and etch-back processes are performed and the height of the doped polysilicon layer pattern 36 A is decreased.
- an annealing process 37 is performed.
- the dopant doping the doped polysilicon layer pattern 36 A is diffused into the diffusion barrier region 23 A which is exposed by the sidewall contact 35 so as to form a sidewall junction 38 .
- the sidewall junction 38 becomes an N-type junction.
- the annealing process 37 may be a furnace annealing process, a rapid thermal annealing process or a combination of both.
- the annealing process 37 may be performed at a temperature ranging from approximately 750° to approximately 1200° C.
- the sidewall junction 38 has a doping concentration of approximately at least 1 ⁇ 10 20 atoms/cm 3 .
- the sidewall junction 38 is formed by forming the doped polysilicon layer pattern 36 A and performing a thermal diffusion through the annealing process 37 , the depth of the sidewall junction 38 may be controlled to be shallow and the concentration of the dopant may be controlled easily.
- the carbon implanted into the diffusion barrier region 23 A may suppress the dopant (for example, N-type impurity such as phosphorus) of the sidewall junction 38 from being diffused excessively during the annealing process 37 . As a result, generation of floating bodies may be prevented/reduced.
- a body-tied structure Such a structure that suppresses the excessive diffusion of the sidewall junction 38 is referred to as a body-tied structure.
- the doped polysilicon layer pattern 36 A is removed.
- the doped polysilicon layer pattern 36 A may be removed through a wet etch process or a dry etch process.
- chemical compounds based on hydrogen bromide (HBr) or chlorine (Cl 2 ) are used, where oxygen (O 2 ) nitrogen (N 2 ), helium (He) or argon (Ar) are added.
- HBr hydrogen bromide
- Cl 2 chlorine
- He helium
- Ar argon
- a cleaning solution having a high selectivity between a nitride layer and an oxygen layer is used.
- a conductive line electrically connected to the sidewall junction 38 for example, a buried bit line 39 , is formed as follows.
- a bit line conductive layer (for example, 39) is formed over the substrate structure to gap-fill the plurality of the trenches 26 .
- the bit line conductive layer may be a metal layer such as a titanium nitride layer (TiN), a tungsten (W) layer, or stacked layers of both.
- TiN titanium nitride layer
- W tungsten
- stacked layers of both When the bit line conductive layer is a metal layer, an Ohmic contact is needed between the sidewall junction 38 and the metal layer.
- the sidewall junction 38 may be formed of silicon and the Ohmic contact may include a metal silicide such as titanium silicide.
- a planarization process and an etch-back process are sequentially performed to remove a portion of the bit line conductive layer.
- the buried bit line 39 electrically connected to the sidewall junction 38 is formed.
- the buried bit line 39 is a metallic bit line formed of the metal layer.
- FIGS. 4A to 4K are cross-sectional views illustrating a method of forming the sidewall contact in accordance with an exemplary embodiment of the present invention.
- the drawings illustrate how the sidewall contact is formed after the process of FIG. 3C .
- a liner oxide layer 27 is formed as an insulation layer over the substrate structure including the plurality of the bodies 201 .
- the liner oxide layer 27 may include an oxide layer such as a silicon oxide layer.
- a first gap-fill layer 2 gap-filling the plurality of the trenches 26 is formed.
- the first gap fill layer 28 may be polysilicon layer or amorphous silicon.
- the first gap-fill layer 28 is planarized until the surface of the hard mask pattern 24 is exposed.
- the planarization of the first gap-fill layer 28 may be performed through a Chemical Mechanical Polishing (CMP) process.
- CMP Chemical Mechanical Polishing
- an etch-back process is performed.
- the first gap-fill layer 28 acquired after the etch-back process is referred to as a first gap-fill layer pattern 28 A.
- the first gap-fill layer pattern 28 A forms a part of a first recess R 1 .
- the liner oxide layer 27 over the hard mask pattern 24 may be polished, where the liner oxide layer pattern 27 A may remain covering both sidewalls of each trench 26 and the hard mask pattern 24 .
- the liner oxide layer pattern 27 A covers the bottom of the trench 26 as well.
- the liner oxide layer pattern 27 A is thinned by performing a wet etch process.
- a liner nitride layer 29 is formed of an insulation layer over the resulting substrate structure including the first gap-fill layer pattern 28 A.
- the liner nitride layer 29 may be a nitride layer such as a silicon nitride layer.
- the liner nitride layer 29 is etched. As a result, a liner nitride layer pattern 29 A is formed. Subsequently, the first gap-fill layer pattern 28 A is recessed to a desired depth by using the liner nitride layer pattern 29 A as an etch barrier. As a result, a second recess R 2 is formed. The first gap-fill layer pattern forming a part of the second recess R 2 is referred to as a first gap-fill layer pattern 28 B forming a second recess.
- a metal nitride layer for forming spacers 30 is conformally formed over the resulting substrate structure including the second recess R 2 .
- spacers 30 are formed by performing a spacer etch process on the metal nitride layer.
- the spacers 30 are formed on both sidewalls of each body 201 , that is, on both sidewalls of the second recess R 2 .
- the spacers 30 may be formed of titanium nitride (TiN).
- a second gap-fill layer 31 gap-filling the second recess R 2 with the spacers 30 formed therein is formed.
- the second gap-fill layer 31 may be an oxide layer or a spin-on dielectric (SOD) layer.
- the second gap-fill layer 31 is planarized and etched back.
- the second gap-fill layer 31 acquired after the planarization and etch-back processes is referred to as a second gap-fill layer pattern 31 A.
- etch barrier 32 is formed over the resulting substrate structure including the second gap-fill layer pattern 31 A.
- the etch barrier 32 may be an undoped polysilicon layer.
- the tilt ion implantation process 33 is a process of ion-implanting a dopant at a desired slanted angle.
- the dopant is ion-implanted into a portion of the etch barrier 32 .
- the tilt ion implantation process 33 is performed at a desired angle, which ranges from approximately 5° to approximately 30°.
- a shadow is formed by the hard mask pattern 24 in implanting ion beams.
- the dopant ion-implanted is a P-type dopant, e.g., boron, and a dopant source for ion-implanting boron is BF 2 .
- a portion of the etch barrier 32 adjacent to the left side of the hard mask pattern 24 remains undoped.
- a portion of the etch barrier 32 formed over the hard mask pattern 24 and a portion adjacent to the right side of the hard mask pattern 24 is referred to as a doped etch barrier 32 A.
- the other portion of the etch barrier layer 32 which is not doped with the dopant is referred to as an undoped etch barrier 32 B.
- the undoped etch barrier 328 is removed.
- the polysilicon layer which is used as the etch barrier, has different etch rates according to whether or not it is doped with the dopant.
- the undoped polysilicon layer into which the dopant is not ion implanted is wet-etched rapidly. Therefore, the undoped polysilicon layer is selectively etched using a chemical having a high selectivity which is capable of wet-etching, for example, the undoped polysilicon layer but not the doped polysilicon layer.
- the undoped etch barrier 32 B is removed through the wet-etch process or a wet cleaning process.
- a spacer referred to as a first spacer 30 A remains.
- a cleaning process is performed to expose a portion of a sidewall of each body 201 .
- the cleaning process may be a wet cleaning process.
- the wet cleaning process may be performed using hydrogen fluoride (HF) or a buffered oxide etchant (BOE).
- HF hydrogen fluoride
- BOE buffered oxide etchant
- the hard mask pattern 24 , the liner oxide layer pattern 27 A, and the liner nitride layer pattern 29 A are collectively referred to as an ‘insulation layer.’
- the insulation layer provides the sidewall contact 35 which exposes a portion of a sidewall of the body 201 .
- the first spacer 30 A and the doped etch barrier 32 A are removed.
- the doped etch barrier 32 A is removed, the first gap-fill layer pattern 28 B forming the second recess R 2 , is simultaneously removed as well.
- FIGS. 5A to 5E are cross-sectional views illustrating a semiconductor device fabrication method after the formation of buried bit lines.
- FIGS. 5A to 5E present cross-sectional views obtained by cutting the semiconductor device along lines B-B′ and C-C′ shown in FIG. 3G which run perpendicular to the page of FIG. 3 .
- a first inter-layer dielectric layer 41 is formed.
- the first inter-layer dielectric layer 41 is planarized until the surface of the hard mask pattern 24 is exposed.
- word line trenches 42 are formed.
- a photoresist layer pattern which is not illustrated in the drawing, is used to form the word line trenches 42 .
- the first inter-layer dielectric layer 41 is etched to a desired depth by using the photoresist pattern as an etch barrier.
- the hard mask pattern 24 and the bodies 201 are etched to a desired depth, too.
- body pattern 201 B and pillars 201 A are formed.
- the body pattern 201 B and the pillars 201 A become active regions.
- the body pattern 201 B is a portion where the sidewall junction 38 is formed, and it is formed in the shape of line extended in the same direction as the buried bit line 39 is laid.
- the pillars 201 A are extended in a vertical direction over the body pattern 201 B.
- the pillars 201 A are formed on a cell basis.
- the remaining thickness R 1 of the first inter-layer dielectric layer 41 functions as an isolation layer between the buried bit line 39 and the vertical word line.
- a word line conductive layer 44 is formed to gap-fill the word line trenches (refer to the reference numeral ‘ 42 ’ of FIG. 5B ). Subsequently, a planarization process and an etch-back process are performed so that the word line conductive layer 44 remains at a desired height to gap-fill a portion of each word line trench 42 . A gate insulation layer 43 is formed before the word line conductive layer 44 is formed.
- spacers 45 are formed by depositing a nitride layer and then performing an etch-back process on the nitride layer.
- the word line conductive layer 44 is etched by using the spacers 45 that are etched to form a spacer pattern.
- vertical word lines 44 A each of which is adjacent to the sidewalls of a corresponding pillar 201 A is formed.
- the vertical word lines 44 A also function as vertical gates, too.
- vertical word lines 44 A coupling adjacent vertical gates may be formed.
- the vertical word lines 44 A are formed in a direction crossing the buried bit lines 39 .
- a second inter-layer dielectric layer 46 is formed over the resulting substrate structure including the vertical word lines 44 A.
- each pillar 201 A is exposed by performing a storage node contact etch process. Subsequently, storage node contact plugs (SNC) 48 are formed. Before the storage node contact plugs 48 are formed, drains 47 may be formed by performing an ion-implantation. As a result, the drains 47 , the sidewall junctions 38 , and the vertical word lines 44 A constitute a vertical channel transistor. The vertical word lines 44 A form vertical channels between the drains 47 and the sidewall junctions 38 . The sidewall junctions 38 become the source for vertical transistors.
- SNC storage node contact plugs
- Storage nodes 49 are formed over the storage node contact plugs 48 .
- the storage nodes 49 may have a cylindrical shape. According to another exemplary embodiment of the present invention, the storage nodes 49 may have a pillar shape or a concave shape. Subsequently, a dielectric layer and an upper electrode are formed.
- Exemplary embodiments of the present invention may prevent a floating body from being generated by forming a diffusion barrier region in advance in a region where a sidewall junction is to be formed and suppressing excessive diffusion of the sidewall junction.
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Abstract
A method for fabricating a semiconductor device includes forming a plurality of bodies that are each isolated from another by a trench and each include a diffusion barrier region with a sidewall exposed to the trench, forming a doped layer gap-filling the trench, forming a sidewall junction at the exposed sidewall of the diffusion barrier region by annealing the doped layer, and forming a conductive line coupled with the sidewall junction to fill the trench.
Description
- The present application claims priority of Korean Patent Application No. 10-2010-0065264, filed on Jul. 7, 2010, which is incorporated herein by reference in its entirety.
- Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device including a side-junction, and a method for fabricating the semiconductor device.
- When cells having a vertical transistor structure employ buried bit lines (BBL), each buried bit line BBL may be adjacent to two cells. For a cell to be driven by a buried bit line BBL, a One-Side-Contact (OSC) process may be performed for forming a contact in an active region while insulating another active region. Hereafter, the OSC process will be simply referred to as a sidewall contact process. In a cell of a vertical transistor structure formed by using the sidewall contact process, each active region includes a body isolated by a trench and a pillar formed over the body. A buried bit line BBL fills a trench between bodies, and a word line (or a vertical gate) is disposed adjacent to the sidewall of a pillar and extended in a direction crossing a buried bit line BBL. The word line forms a channel in a vertical direction.
- According to the sidewall contact process, a portion of a sidewall of the body is exposed to couple an active region with a buried bit line BBL. Then, a junction is formed by implanting or diffusing a dopant into the exposed portion of the sidewall of the body. The buried bit line BBL and the body are electrically coupled through the junction. Since the junction is formed on just one sidewall of the body, the junction is referred to as a One-Side Junction (OSJ).
- When a diffusion barrier is formed between the buried bit line BBL and the side junction, agglomeration may be caused. To address such a concern, a method of forming a one-side junction by directly forming a doped polysilicon layer without forming a diffusion barrier has been researched.
-
FIGS. 1A to 1C are cross-sectional views illustrating a conventional method for forming a semiconductor device by using a sidewall contact process. - Referring to
FIG. 1A , a plurality ofbodies 103 isolated bytrenches 102 are formed over asubstrate 101. Ahard mask pattern 104 is formed over thebodies 103. Thehard mask pattern 104 functions as an etch barrier during the formation of active regions. - An insulation layer is formed on both sidewalls of each
body 103, the surface of thesubstrate 101 between thebodies 103, and the surface of thehard mask pattern 104. The insulation layer includes aliner oxide layer 105 and aliner nitride layer 106. - A
sidewall contact 107 is formed by removing a portion of the insulation layer. Thesidewall contact 107 is a one-side contact which exposes a portion of just one sidewall of abody 103. - Referring to
FIG. 1B , a dopedpolysilicon layer 108 is formed over the substrate structure to gap-fill sidewall contacts 107 and thetrenches 102. Here, the dopedpolysilicon layer 108 is doped with a dopant for forming a sidewall contact. For example, the dopant doping the dopedpolysilicon layer 108 may be an N-type impurity, such as phosphorus (P). - Referring to
FIG. 1C , the dopedpolysilicon layer 108 is planarized and etched back. As a result, the doped polysilicon layer pattern which is obtained from the planarization and etch-back processes gap-fills a portion of eachtrench 102 to the degree that the doped polysilicon layer pattern has a height to at least contact the sidewall. - Subsequently, an
annealing process 109 is performed. Here, the dopant doping the doped polysilicon layer pattern is diffused into the sidewall of thebody 103 exposed by the sidewall so as to form asidewall junction 110. - However, when the dopant is excessively diffused during the process of forming the doped polysilicon layer pattern, a floating
body 111 may be generated to increase a potential and cause a concern with respect to the operation of a cell transistor, such as a threshold voltage drop. - An exemplary embodiment of the present invention is directed to a semiconductor device which prevents a floating body from being generated due to excessive diffusion of a sidewall junction, and a method for fabricating the semiconductor device.
- In accordance with an exemplary embodiment of the present invention, a method for fabricating a semiconductor device includes: forming a plurality of bodies that are each isolated from another by a trench and each include a diffusion barrier region with a sidewall exposed to the trench; forming a doped layer gap-filling the trench; forming a sidewall junction at the exposed sidewall of the diffusion barrier region by annealing the doped layer; and forming a conductive line coupled with the sidewall junction to fill the trench.
- In accordance with another exemplary embodiment of the present invention, a method for fabricating a semiconductor device includes: forming a diffusion barrier layer by performing an ion implantation process onto a substrate; forming a plurality of bodies that are each isolated from another by a trench and each include a diffusion barrier region of the diffusion barrier layer with a sidewall of the diffusion barrier region being exposed to the trench by etching the substrate to a depth below the diffusion barrier region; forming an insulation layer through which a sidewall contact is formed to expose the sidewall of the diffusion barrier region; forming a doped layer gap-filling the trench; forming a sidewall junction at the exposed sidewall of the diffusion barrier region by annealing the doped layer; and forming a buried bit line coupled with the sidewall junction to fill the trench.
- In accordance with yet another exemplary embodiment of the present invention, a semiconductor device: a plurality of bodies that are each isolated from another by a trench and each include a diffusion barrier region with a sidewall exposed to the trench; an insulation layer through which a sidewall contact is formed to expose the exposed sidewall of the diffusion barrier region; a sidewall junction formed at the exposed sidewall of the diffusion barrier region; a buried bit line coupled with the sidewall junction and arranged to fill the trench; a plurality of pillars formed over the plurality of the bodies, respectively; and a vertical word line extending along a sidewall of each of the pillars in a direction crossing the buried bit line.
-
FIGS. 1A to 1C are cross-sectional views illustrating a conventional method for forming a semiconductor device by using a sidewall contact process. -
FIG. 2 is a cross-sectional view illustrating a semiconductor device in accordance with an exemplary embodiment of the present invention. -
FIGS. 3A to 3G are cross-sectional views describing a method for forming the semiconductor device shown inFIG. 2 . -
FIGS. 4A to 4K are cross-sectional views illustrating a method of forming a sidewall contact in accordance with an exemplary embodiment of the present invention. -
FIGS. 5A to 5E are cross-sectional views illustrating a semiconductor device fabrication method after the formation of buried bit lines. - Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.
- The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being “on” a second layer or “on” a substrate, it not only refers to a case where the first layer is formed directly on the second layer or the substrate but also a case where a third layer exists between the first layer and the second layer or the substrate.
-
FIG. 2 is a cross-sectional view illustrating a semiconductor device in accordance with an exemplary embodiment of the present invention. - Referring to
FIG. 2 , a plurality ofbodies 201 each include adiffusion barrier region 23A of a diffusion barrier layer and a sidewall exposing thediffusion barrier region 23A. Then, through an insulation layer (for example, 29A and 27A), a sidewall contact exposing a portion of a sidewall and covering thebodies 201 is formed. Asidewall junction 38 is formed in the inside of thediffusion barrier region 23A of the exposed portion of the sidewall. Subsequently, a conductive line coupled with thesidewall junction 38 is formed between the plurality of thebodies 201. The conductive line includes a buriedbit line 39. Theburied bit line 39 may be a metal bit line formed of a metal layer. - Here, the plurality of the
bodies 201 isolated bytrenches 26 are formed over asubstrate 21. According to an example, thesubstrate 21 includes a silicon substrate. The plurality of thebodies 201 are formed by etching thesubstrate 21. When thesubstrate 21 includes a silicon substrate, the plurality of thebodies 201 may include silicon bodies as well. The plurality of thebodies 201 are extended from the surface of thesubstrate 21 in a vertical direction, Each of the plurality of thebodies 201 is a region where a channel region, a source region and a drain region of a vertical transistor is formed. Eachbody 201 includes two sidewalls. Thebody 201 is referred to as an active body. - A
hard mask pattern 24 is formed in the upper portion of thebody 201. Thehard mask pattern 24 functions as an etch barrier when thebody 201 is formed. Thehard mask pattern 24 includes a dielectric material layer such as an oxide layer and a nitride layer. According to an example, a nitride layer such as a silicon nitride layer is used as thehard mask pattern 24. - An insulation layer (for example, 29A and 27A) is formed on both sidewalls of the
body 201, the surface of atrench 26 betweenbodies 201, and the surface of thehard mask pattern 24. The insulation layer according to an example includes a lineroxide layer pattern 27A and a linernitride layer pattern 29A. The lineroxide layer pattern 27A is formed on both sidewalls of thebody 201 and the surface of thetrench 26. The linernitride layer pattern 29A is formed on the surface of a portion of the lineroxide layer pattern 27A. - A sidewall contact (‘35’ in
FIG. 4K ) is formed by removing a portion of the insulation layer (29A and 27A). Thesidewall contact 35 is a one-side contact which selectively exposes a portion of just one sidewall of thebody 201. Thesidewall contact 35 includes a linear opening which has a shape of line extended along the sidewall of thebody 201. - The above-described insulation layer (29A and 27A) provides the
sidewall contact 35 which exposes a portion of the sidewall of thebody 201. A method for forming thesidewall contact 35 will be described later on with reference toFIGS. 4A to 4K . - Referring to
FIG. 2 , asidewall junction 38 is formed in the inside of thediffusion barrier region 23A. With thediffusion barrier region 23A, thesidewall junction 38 is prevented from being excessively diffused. - The
diffusion barrier region 23A includes an interstitial impurity such as carbon. Thesidewall junction 38 may include phosphorus (P). -
FIGS. 3A to 3G are cross-sectional views describing a method for forming the semiconductor device shown inFIG. 2 . - Referring to
FIG. 3A , a first impurity is ion-implanted into asubstrate 21. Thesubstrate 21 includes a silicon substrate. A first impurity is implanted into a region reserved for a junction throughion implantation 22 to form adiffusion barrier layer 23. - The ion implantation is performed using carbon as the first impurity. Since the
substrate 21 is a silicon substrate, carbon becomes an interstitial impurity within thesubstrate 21. When the dopant for doping a doped polysilicon layer to be formed later in the semiconductor device fabrication process is phosphorus (P), the phosphorus (P) is diffused through interstitial sites. Here, if carbon is already implanted and diffused into the interstitial sites in, for example, thediffusion barrier layer 23, the excessive diffusion of the phosphorus (P) may be prevented. Meanwhile, carbon may have substantially no effect on the conductivity of a sidewall junction. - When carbon is on-implanted, the
diffusion barrier region 23 becomes silicon carbide (SiC). - Referring to
FIG. 3B , ahard mask pattern 24 is formed over thesubstrate 21. Here, thehard mask pattern 24 is formed by forming a hard mask layer and then etching the hard mask layer using a photoresist pattern 25 as an each barrier. The photoresist pattern 25 is a line-and-space pattern and it may be also called a buried bit line (BBL) mask. Thehard mask pattern 24 may be formed of an oxide layer, a nitride layer, or stacked layers of the two. According to an example, a nitride layer such as a silicon nitride is used as thehard mask pattern 24. - Referring to
FIG. 3C , the photoresist pattern 25 is stripped and a plurality oftrenches 26 are formed by using thehard mask pattern 24 as an etch barrier and etching thesubstrate 21 to a desired depth. Due to the plurality of thetrenches 26, a plurality ofbodies 201 are formed over thesubstrate 21. The plurality of thebodies 201 are extended from the surface of thesubstrate 21 in a vertical direction. Eachbody 201 has two sidewalls. In a vertical cell structure, abody 201 is an active region where a channel region, a source region, and a drain region of a transistor are formed. - The sidewalls of the
body 201 may have a vertical profile as shown. The etch process for forming the plurality ofbodies 201 and the plurality of thetrenches 26 may be a dry etch process using plasma. - As described above, when the plurality of the
bodies 201 are formed by etching thesubstrate 21, each of the plurality of thebodies 201 has a sidewall which exposes adiffusion barrier region 23A. Since thesubstrate 21 is a silicon substrate, the plurality of thebodies 201 may be referred to as silicon bodies. - Referring to
FIG. 3D , asidewall contact 35 is formed to expose a portion of a sidewall of abody 201, that is, a portion of thediffusion barrier region 23A. - The
sidewall contact 35 is formed of an insulation layer that includes a lineroxide layer pattern 27A and a linernitride layer pattern 29A. The lineroxide layer pattern 27A is formed on both sidewalls of thebody 201 and the surface of thesubstrate 21. The linernitride layer pattern 29A is formed on the surface of a portion of the lineroxide layer pattern 27A. Thesidewall contact 35 is formed by removing a portion of the insulation layer. Thesidewall contact 35 is a one-side contact which selectively exposes a portion of a sidewall of thebody 201. Thesidewall contact 35 includes a linear opening which is formed in the shape of line. - The
sidewall contact 35 exposes a portion of a sidewall of the body 201 (for example, thediffusion barrier region 23A) at a region reserved for a junction through the insulation layer. A method for forming the sidewall contact 5 will be described in detail later with reference toFIGS. 4A to 4K . - Referring to
FIG. 3E , a doped layer is formed to gap-fill the plurality of thetrenches 26 between the plurality of thebodies 201. The doped layer includes an impurity for forming a junction implanted therein. The doped layer may include a dopedpolysilicon layer 36. When the dopedpolysilicon layer 36 has excellent step coverage, it may gap-fill the plurality of thetrenches 26 without voids. Therefore, the dopedpolysilicon layer 36 used in forming a junction has excellent dose uniformity, where the dopedpolysilicon layer 36 is doped with a dopant for forming a junction. The dopant for the dopedpolysilicon layer 36 may be an N-type impurity such as phosphorus (P). The dopedpolysilicon layer 36 may be formed through a Chemical Vapor Deposition (CVD) method. The dopant doping the dopedpolysilicon layer 36 includes a dose ranging from approximately 1×1015 to approximately 1×1017 atoms/cm2. While the dopedpolysilicon layer 36 is illustrated as an example, another material doped with an impurity for forming a junction may be used according to another example. For instance, an oxide layer such as phosphor silicate glass (PSG) may be used. - Referring to
FIG. 3F , the dopedpolysilicon layer 36 is planarized and etched back. The dopedpolysilicon layer 36 acquired after the planarization and etch-back processes is referred to as a dopedpolysilicon layer pattern 36A, hereafter. As a result, the dopedpolysilicon layer pattern 36A is formed to gap-fill a portion of eachtrench 26, where the dopedpolysilicon layer pattern 36A has a sufficient height to cover the opening on a sidewall of thebody 201 for thesidewall contact 35. As described above, the dopant may be prevented from being diffused into the regions other than the sidewall contact during a subsequent annealing process when the planarization and etch-back processes are performed and the height of the dopedpolysilicon layer pattern 36A is decreased. - Subsequently, an annealing process 37 is performed. Here, the dopant doping the doped
polysilicon layer pattern 36A is diffused into thediffusion barrier region 23A which is exposed by thesidewall contact 35 so as to form asidewall junction 38. When the dopant doping the dopedpolysilicon layer pattern 36A is an N-type impurity, thesidewall junction 38 becomes an N-type junction. - The annealing process 37 may be a furnace annealing process, a rapid thermal annealing process or a combination of both. The annealing process 37 may be performed at a temperature ranging from approximately 750° to approximately 1200° C. According to an example, the
sidewall junction 38 has a doping concentration of approximately at least 1×1020 atoms/cm3. - As described above, since the
sidewall junction 38 is formed by forming the dopedpolysilicon layer pattern 36A and performing a thermal diffusion through the annealing process 37, the depth of thesidewall junction 38 may be controlled to be shallow and the concentration of the dopant may be controlled easily. - The carbon implanted into the
diffusion barrier region 23A may suppress the dopant (for example, N-type impurity such as phosphorus) of thesidewall junction 38 from being diffused excessively during the annealing process 37. As a result, generation of floating bodies may be prevented/reduced. Such a structure that suppresses the excessive diffusion of thesidewall junction 38 is referred to as a body-tied structure. - Referring to
FIG. 3G , the dopedpolysilicon layer pattern 36A is removed. Here, the dopedpolysilicon layer pattern 36A may be removed through a wet etch process or a dry etch process. In case of the dry etch process, chemical compounds based on hydrogen bromide (HBr) or chlorine (Cl2) are used, where oxygen (O2) nitrogen (N2), helium (He) or argon (Ar) are added. In case of the wet etch process, a cleaning solution having a high selectivity between a nitride layer and an oxygen layer is used. - Subsequently, a conductive line electrically connected to the
sidewall junction 38, for example, a buriedbit line 39, is formed as follows. - First, a bit line conductive layer (for example, 39) is formed over the substrate structure to gap-fill the plurality of the
trenches 26. The bit line conductive layer may be a metal layer such as a titanium nitride layer (TiN), a tungsten (W) layer, or stacked layers of both. When the bit line conductive layer is a metal layer, an Ohmic contact is needed between thesidewall junction 38 and the metal layer. Here, thesidewall junction 38 may be formed of silicon and the Ohmic contact may include a metal silicide such as titanium silicide. - Subsequently, a planarization process and an etch-back process are sequentially performed to remove a portion of the bit line conductive layer. As a result of the planarization process and the etch-back process, the buried
bit line 39 electrically connected to thesidewall junction 38 is formed. The buriedbit line 39 is a metallic bit line formed of the metal layer. -
FIGS. 4A to 4K are cross-sectional views illustrating a method of forming the sidewall contact in accordance with an exemplary embodiment of the present invention. The drawings illustrate how the sidewall contact is formed after the process ofFIG. 3C . - Referring to
FIG. 4A , aliner oxide layer 27 is formed as an insulation layer over the substrate structure including the plurality of thebodies 201. Theliner oxide layer 27 may include an oxide layer such as a silicon oxide layer. - A first gap-
fill layer 2 gap-filling the plurality of thetrenches 26 is formed. The firstgap fill layer 28 may be polysilicon layer or amorphous silicon. - Referring to
FIG. 4B , the first gap-fill layer 28 is planarized until the surface of thehard mask pattern 24 is exposed. The planarization of the first gap-fill layer 28 may be performed through a Chemical Mechanical Polishing (CMP) process. Subsequently, an etch-back process is performed. The first gap-fill layer 28 acquired after the etch-back process is referred to as a first gap-fill layer pattern 28A. After the etch-back process, the first gap-fill layer pattern 28A forms a part of a first recess R1. During the CMP process, theliner oxide layer 27 over thehard mask pattern 24 may be polished, where the lineroxide layer pattern 27A may remain covering both sidewalls of eachtrench 26 and thehard mask pattern 24. The lineroxide layer pattern 27A covers the bottom of thetrench 26 as well. - Subsequently, the liner
oxide layer pattern 27A is thinned by performing a wet etch process. - Referring to
FIG. 4C , aliner nitride layer 29 is formed of an insulation layer over the resulting substrate structure including the first gap-fill layer pattern 28A. Theliner nitride layer 29 may be a nitride layer such as a silicon nitride layer. - Referring to
FIG. 4D , theliner nitride layer 29 is etched. As a result, a linernitride layer pattern 29A is formed. Subsequently, the first gap-fill layer pattern 28A is recessed to a desired depth by using the linernitride layer pattern 29A as an etch barrier. As a result, a second recess R2 is formed. The first gap-fill layer pattern forming a part of the second recess R2 is referred to as a first gap-fill layer pattern 28B forming a second recess. - Referring to
FIG. 4E , a metal nitride layer for formingspacers 30 is conformally formed over the resulting substrate structure including the second recess R2. Subsequently, spacers 30 are formed by performing a spacer etch process on the metal nitride layer. Thespacers 30 are formed on both sidewalls of eachbody 201, that is, on both sidewalls of the second recess R2. Thespacers 30 may be formed of titanium nitride (TiN). - A second gap-
fill layer 31 gap-filling the second recess R2 with thespacers 30 formed therein is formed. The second gap-fill layer 31 may be an oxide layer or a spin-on dielectric (SOD) layer. - Referring to
FIG. 4F , the second gap-fill layer 31 is planarized and etched back. The second gap-fill layer 31 acquired after the planarization and etch-back processes is referred to as a second gap-fill layer pattern 31A. - Subsequently, an
etch barrier 32 is formed over the resulting substrate structure including the second gap-fill layer pattern 31A. Theetch barrier 32 may be an undoped polysilicon layer. - Referring to
FIG. 4G , a tiltion implantation process 33 is performed. The tiltion implantation process 33 is a process of ion-implanting a dopant at a desired slanted angle. The dopant is ion-implanted into a portion of theetch barrier 32. - The tilt
ion implantation process 33 is performed at a desired angle, which ranges from approximately 5° to approximately 30°. Here, a shadow is formed by thehard mask pattern 24 in implanting ion beams. As a result, although a portion of theetch barrier 32 becomes doped, the remainder of the etch barriers remains undoped, According to an example the dopant ion-implanted is a P-type dopant, e.g., boron, and a dopant source for ion-implanting boron is BF2. As a result, a portion of theetch barrier 32 adjacent to the left side of thehard mask pattern 24 remains undoped. - Due to the tilt
ion implantation process 33 of the dopant, a portion of theetch barrier 32 formed over thehard mask pattern 24 and a portion adjacent to the right side of thehard mask pattern 24 is referred to as adoped etch barrier 32A. The other portion of theetch barrier layer 32 which is not doped with the dopant is referred to as anundoped etch barrier 32B. - Referring to
FIG. 4H , the undoped etch barrier 328 is removed. Here, the polysilicon layer, which is used as the etch barrier, has different etch rates according to whether or not it is doped with the dopant. In particular, the undoped polysilicon layer into which the dopant is not ion implanted is wet-etched rapidly. Therefore, the undoped polysilicon layer is selectively etched using a chemical having a high selectivity which is capable of wet-etching, for example, the undoped polysilicon layer but not the doped polysilicon layer. Theundoped etch barrier 32B is removed through the wet-etch process or a wet cleaning process. - After the
undoped etch barrier 32B is removed, only the dopedetch barrier 32A remains. - Referring to
FIG. 4I , just one of thespacers 30 is removed through a wet-etch process. Accordingly, a spacer referred to as afirst spacer 30A remains. - Referring to
FIG. 43 , a cleaning process is performed to expose a portion of a sidewall of eachbody 201. - The cleaning process may be a wet cleaning process. The wet cleaning process may be performed using hydrogen fluoride (HF) or a buffered oxide etchant (BOE). With the wet cleaning process, a portion of the liner
oxide layer pattern 27A is removed so as to form asidewall contact 35. When thesidewall contact 35 is formed, the second gap-fill layer pattern 31A is removed as well. - As described above, the
hard mask pattern 24, the lineroxide layer pattern 27A, and the linernitride layer pattern 29A are collectively referred to as an ‘insulation layer.’ Here, the insulation layer provides thesidewall contact 35 which exposes a portion of a sidewall of thebody 201. - Referring to
FIG. 4K , thefirst spacer 30A and the dopedetch barrier 32A are removed. When the dopedetch barrier 32A is removed, the first gap-fill layer pattern 28B forming the second recess R2, is simultaneously removed as well. -
FIGS. 5A to 5E are cross-sectional views illustrating a semiconductor device fabrication method after the formation of buried bit lines.FIGS. 5A to 5E present cross-sectional views obtained by cutting the semiconductor device along lines B-B′ and C-C′ shown inFIG. 3G which run perpendicular to the page ofFIG. 3 . - Referring to
FIG. 5A , a firstinter-layer dielectric layer 41 is formed. The firstinter-layer dielectric layer 41 is planarized until the surface of thehard mask pattern 24 is exposed. - Referring to
FIG. 55 word line trenches 42 are formed. A photoresist layer pattern, which is not illustrated in the drawing, is used to form theword line trenches 42. After forming the photoresist pattern, the firstinter-layer dielectric layer 41 is etched to a desired depth by using the photoresist pattern as an etch barrier. When the firstinter-layer dielectric layer 41 is etched, thehard mask pattern 24 and thebodies 201 are etched to a desired depth, too. As a result of the etch process,body pattern 201B andpillars 201A are formed. Thebody pattern 201B and thepillars 201A become active regions. Thebody pattern 201B is a portion where thesidewall junction 38 is formed, and it is formed in the shape of line extended in the same direction as the buriedbit line 39 is laid. Thepillars 201A are extended in a vertical direction over thebody pattern 201B. Thepillars 201A are formed on a cell basis. The remaining thickness R1 of the firstinter-layer dielectric layer 41 functions as an isolation layer between the buriedbit line 39 and the vertical word line. - Referring to
FIG. 5C , a word lineconductive layer 44 is formed to gap-fill the word line trenches (refer to the reference numeral ‘42’ ofFIG. 5B ). Subsequently, a planarization process and an etch-back process are performed so that the word lineconductive layer 44 remains at a desired height to gap-fill a portion of eachword line trench 42. Agate insulation layer 43 is formed before the word lineconductive layer 44 is formed. - Referring to
FIG. 5D ,spacers 45 are formed by depositing a nitride layer and then performing an etch-back process on the nitride layer. The word lineconductive layer 44 is etched by using thespacers 45 that are etched to form a spacer pattern. As a result,vertical word lines 44A each of which is adjacent to the sidewalls of acorresponding pillar 201A is formed. Here, thevertical word lines 44A also function as vertical gates, too. According to another exemplary embodiment of the present invention, after the circular vertical gates that each surround acorresponding pillar 201A are formed,vertical word lines 44A coupling adjacent vertical gates may be formed. Thevertical word lines 44A are formed in a direction crossing the buried bit lines 39. - Referring to
FIG. 5E , a secondinter-layer dielectric layer 46 is formed over the resulting substrate structure including thevertical word lines 44A. - The upper portion of each
pillar 201A is exposed by performing a storage node contact etch process. Subsequently, storage node contact plugs (SNC) 48 are formed. Before the storage node contact plugs 48 are formed, drains 47 may be formed by performing an ion-implantation. As a result, thedrains 47, thesidewall junctions 38, and thevertical word lines 44A constitute a vertical channel transistor. Thevertical word lines 44A form vertical channels between thedrains 47 and thesidewall junctions 38. Thesidewall junctions 38 become the source for vertical transistors. -
Storage nodes 49 are formed over the storage node contact plugs 48. Thestorage nodes 49 may have a cylindrical shape. According to another exemplary embodiment of the present invention, thestorage nodes 49 may have a pillar shape or a concave shape. Subsequently, a dielectric layer and an upper electrode are formed. - Exemplary embodiments of the present invention may prevent a floating body from being generated by forming a diffusion barrier region in advance in a region where a sidewall junction is to be formed and suppressing excessive diffusion of the sidewall junction.
- While the present invention has been described with respect to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.
Claims (5)
1-17. (canceled)
18. A semiconductor device, comprising:
a plurality of bodies that are each isolated from another by a trench and each include a diffusion barrier region with a sidewall exposed to the trench;
an insulation layer through which a sidewall contact is formed to expose the exposed sidewall of the diffusion barrier region;
a sidewall junction formed at the exposed sidewall of the diffusion barrier region;
a buried bit line coupled with the sidewall junction and filled a portion of the trench;
a plurality of pillars formed over the plurality of the bodies, respectively; and
a vertical word line extending along a sidewall of each of the pillars in a direction crossing the buried bit line.
19. The semiconductor device of claim 18 , wherein the diffusion barrier region comprises an interstitial impurity.
20. The semiconductor device of claim 18 , wherein the diffusion barrier region is doped with carbon.
21. The semiconductor device of claim 18 , wherein the sidewall junction is doped with phosphorus (P).
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US13/725,498 US20130134508A1 (en) | 2010-07-07 | 2012-12-21 | Semiconductor device with side-junction and method for fabricating the same |
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KR1020100065264A KR101062889B1 (en) | 2010-07-07 | 2010-07-07 | Semiconductor device with side-junction and method for manufacturing the same |
KR10-2010-0065264 | 2010-07-07 | ||
US12/939,677 US8354342B2 (en) | 2010-07-07 | 2010-11-04 | Semiconductor device with side-junction and method for fabricating the same |
US13/725,498 US20130134508A1 (en) | 2010-07-07 | 2012-12-21 | Semiconductor device with side-junction and method for fabricating the same |
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US12/939,677 Division US8354342B2 (en) | 2010-07-07 | 2010-11-04 | Semiconductor device with side-junction and method for fabricating the same |
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US12/939,677 Active 2030-12-17 US8354342B2 (en) | 2010-07-07 | 2010-11-04 | Semiconductor device with side-junction and method for fabricating the same |
US13/725,498 Abandoned US20130134508A1 (en) | 2010-07-07 | 2012-12-21 | Semiconductor device with side-junction and method for fabricating the same |
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US (2) | US8354342B2 (en) |
KR (1) | KR101062889B1 (en) |
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KR20120063756A (en) * | 2010-12-08 | 2012-06-18 | 에스케이하이닉스 주식회사 | Method for manufacturing semiconductor device with side-contact |
KR20120063820A (en) * | 2010-12-08 | 2012-06-18 | 에스케이하이닉스 주식회사 | Method for manufacturing side-contact in semiconductor device |
KR101202690B1 (en) * | 2010-12-09 | 2012-11-19 | 에스케이하이닉스 주식회사 | Methof for forming side contact in semiconductor device |
KR101213931B1 (en) * | 2010-12-14 | 2012-12-18 | 에스케이하이닉스 주식회사 | Vertical type semiconductor and method of the same |
KR101185994B1 (en) * | 2011-02-15 | 2012-09-25 | 에스케이하이닉스 주식회사 | Method of opening one-side contact in vertical transistor and method of fabricating the one-side junction region using the same |
KR20120097663A (en) * | 2011-02-25 | 2012-09-05 | 에스케이하이닉스 주식회사 | Method for manufacturing buried bit line in semiconductor device |
US9401363B2 (en) | 2011-08-23 | 2016-07-26 | Micron Technology, Inc. | Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices |
KR20130047410A (en) * | 2011-10-31 | 2013-05-08 | 에스케이하이닉스 주식회사 | Semiconductor device and method for fabricating the same |
US8901631B2 (en) * | 2013-03-11 | 2014-12-02 | Nanya Technology Corporation | Vertical transistor in semiconductor device and method for fabricating the same |
US9166001B2 (en) | 2014-02-11 | 2015-10-20 | Taiwan Semiconductor Manufacturing Company Limited | Vertical structure and method of forming semiconductor device |
US9793407B2 (en) * | 2015-12-15 | 2017-10-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin field effect transistor |
KR102563924B1 (en) * | 2016-08-05 | 2023-08-04 | 삼성전자 주식회사 | Vertical type memory device |
CN110391299B (en) * | 2018-04-23 | 2023-07-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
US10580888B1 (en) * | 2018-08-08 | 2020-03-03 | Infineon Technologies Austria Ag | Oxygen inserted Si-layers for reduced contact implant outdiffusion in vertical power devices |
US11164791B2 (en) | 2019-02-25 | 2021-11-02 | International Business Machines Corporation | Contact formation for stacked vertical transport field-effect transistors |
US11069679B2 (en) | 2019-04-26 | 2021-07-20 | International Business Machines Corporation | Reducing gate resistance in stacked vertical transport field effect transistors |
US11018138B2 (en) * | 2019-10-25 | 2021-05-25 | Applied Materials, Inc. | Methods for forming dynamic random-access devices by implanting a drain through a spacer opening at the bottom of angled structures |
CN114068545B (en) * | 2020-08-05 | 2024-09-20 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
CN113035868B (en) * | 2021-02-25 | 2022-05-31 | 长鑫存储技术有限公司 | Semiconductor structure forming method and semiconductor structure |
US11848360B2 (en) * | 2021-06-17 | 2023-12-19 | Micron Technology, Inc. | Integrated assemblies and methods of forming integrated assemblies |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090244954A1 (en) * | 2008-03-26 | 2009-10-01 | Cannon Ethan H | Structure and method for improving storage latch susceptibility to single event upsets |
Family Cites Families (5)
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DE19911149C1 (en) | 1999-03-12 | 2000-05-18 | Siemens Ag | IC structure, e.g. a DRAM cell array, has a buried conductive structure with two different conductivity portions separated by a diffusion barrier |
US6593612B2 (en) | 2000-12-05 | 2003-07-15 | Infineon Technologies Ag | Structure and method for forming a body contact for vertical transistor cells |
US6621112B2 (en) | 2000-12-06 | 2003-09-16 | Infineon Technologies Ag | DRAM with vertical transistor and trench capacitor memory cells and methods of fabrication |
US6605504B1 (en) | 2002-06-28 | 2003-08-12 | Infineon Technologies Ag | Method of manufacturing circuit with buried strap including a liner |
US7355230B2 (en) * | 2004-11-30 | 2008-04-08 | Infineon Technologies Ag | Transistor array for semiconductor memory devices and method for fabricating a vertical channel transistor array |
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2010
- 2010-07-07 KR KR1020100065264A patent/KR101062889B1/en active IP Right Grant
- 2010-11-04 US US12/939,677 patent/US8354342B2/en active Active
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US20090244954A1 (en) * | 2008-03-26 | 2009-10-01 | Cannon Ethan H | Structure and method for improving storage latch susceptibility to single event upsets |
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TW201203457A (en) | 2012-01-16 |
KR101062889B1 (en) | 2011-09-07 |
US8354342B2 (en) | 2013-01-15 |
CN102315162A (en) | 2012-01-11 |
CN102315162B (en) | 2015-04-29 |
US20120007258A1 (en) | 2012-01-12 |
TWI524468B (en) | 2016-03-01 |
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