US20130095414A1 - Lithography Mask and Method of Forming a Lithography Mask - Google Patents

Lithography Mask and Method of Forming a Lithography Mask Download PDF

Info

Publication number
US20130095414A1
US20130095414A1 US13/324,755 US201113324755A US2013095414A1 US 20130095414 A1 US20130095414 A1 US 20130095414A1 US 201113324755 A US201113324755 A US 201113324755A US 2013095414 A1 US2013095414 A1 US 2013095414A1
Authority
US
United States
Prior art keywords
layer
percentage
molybdenum
silicon
lithography mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US13/324,755
Other versions
US8921014B2 (en
Inventor
Chue-San Yoo
Chun-Lang Chen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to US13/324,755 priority Critical patent/US8921014B2/en
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YOO, CHUE-SAN, CHEN, CHUN-LANG
Publication of US20130095414A1 publication Critical patent/US20130095414A1/en
Priority to US14/558,097 priority patent/US9513542B2/en
Application granted granted Critical
Publication of US8921014B2 publication Critical patent/US8921014B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/54—Absorbers, e.g. of opaque materials
    • G03F1/58—Absorbers, e.g. of opaque materials having two or more different absorber layers, e.g. stacked multilayer absorbers
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/54—Absorbers, e.g. of opaque materials
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/80—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials

Definitions

  • multiple lithography steps are generally used to form a semiconductor chip. These steps typically include forming a photoresist over a substrate that is to be formed into the semiconductor chip, exposing the photoresist to a pattern of light generally controlled by a mask, developing the pattern in the photoresist to expose the underlying substrate, and etching the pattern in the underlying substrate.
  • the pattern etched in the underlying substrate may be a basis for some feature formation, such as an ion impurity implantation such as for doping source and drain regions, a formation of a structure like a gate patterning, or a pattern for a conductive material such as in a metallization layer.
  • critical dimensions of features typically must be precise. If dimensions of features are just a small amount more than corresponding critical dimensions, the features can overlay other features. Accordingly, it is advantageous to form features with precise dimensions that are true to a design.
  • lithography steps are typically used to form these features, and at the source of the lithography steps is the mask. If the mask is not able to precisely form a pattern in a photoresist, the subsequently formed feature may not meet its critical dimension requirement. Some causes for a mask not being able to precisely form a pattern may be that the pattern formed in the mask itself is not precise, such as caused by a slight, unintended etching of material holding the pattern in the mask during the cleaning of the mask while being formed. This slight etch may widen the pattern in the mask beyond a critical dimension. Further, various physical characteristics of the mask, such a reflectivity percentage, a refractive index, and a coefficient of extinction, may cause an exposure through the mask to be improperly focused or allow spurious light to be incident on the photoresist.
  • FIG. 1 illustrates a first layered structure used in forming a mask according to an embodiment
  • FIG. 2 illustrates a second layered structure used in forming a mask according to an embodiment
  • FIG. 3 illustrates a third layered structure used in forming a mask according to an embodiment
  • FIG. 4 illustrates a fourth layered structure used in forming a mask according to an embodiment
  • FIGS. 5 through 11 illustrate a method for forming a binary mask according to an embodiment.
  • Embodiments will be described with respect to a specific context, namely a method for forming a mask and/or reticle for use in a lithography process, such as in semiconductor processing.
  • Embodiments contemplate forming a binary mask for use in the lithography process, particularly at technology nodes of 20 nanometer (nm) and 28 nm.
  • Other embodiments may also be applied to other lithography processes, other types of masks, for example a phase shift mask, and any technology node.
  • FIG. 1 illustrates a first layered structure 10 used in forming a mask according to an embodiment.
  • the layered structure 10 includes a substrate 12 , a molybdenum silicon nitride (Mo x Si y N z ) layer 14 , and a hardmask 16 .
  • the substrate 12 is an acceptable transparent material, such as quartz, low thermal expansive (LTE) glass, or the like.
  • the Mo x Si y N z layer 14 is a low reflectivity layer having, for example, an atomic weight percentage of molybdenum (x) between approximately 1 and 2 percent, an atomic weight percentage of silicon (y) between approximately 50 and 55 percent, and an atomic weight percentage of nitrogen (z) between approximately 40 and 50 percent.
  • the Mo x Si y N z layer 14 is a shielding layer having, for example, an atomic weight percentage of molybdenum (x) between approximately 4 and 5 percent, an atomic weight percentage of silicon (y) between approximately 45 and 50 percent, and an atomic weight percentage of nitrogen (z) between approximately 40 and 50 percent.
  • the hardmask 16 is an acceptable material, such as a metal like chromium, tantalum, an oxide or nitride of a metal like chromium oxide, tantalum nitride, tantalum oxide, the like, or a combination thereof.
  • the Mo x Si y N z layer 14 is formed on a surface of the substrate 12 by, for example, a sputter deposition. In other embodiments, other physical vapor deposition (PVD) processes or the like may be used. A person having ordinary skill in the art will readily understand the appropriate parameters, gases, etc. used in forming the Mo x Si y N z layer 14 with a desired concentration or percentage of particular elements.
  • the Mo x Si y N z layer 14 can be formed with any thickness, and in some embodiments, the thickness is between 40 nm and 75 nm.
  • the hardmask 16 can be formed on a surface of the Mo x Si y N z layer 14 opposite the surface of the substrate 12 by PVD, atomic layer deposition (ALD), the like, or a combination thereof, with a thickness of, for example, 5 nm to 20 nm.
  • FIG. 2 is a second layered structure 20 used in forming a mask according to an embodiment.
  • a shielding layer 22 such as Mo 0.04-0.05 Si 0.45-0.50 N 0.40-0.50 , is formed over the surface of the substrate 12
  • a low reflectivity layer 24 such as Mo 0.01-0.02 Si 0.50-0.55 N 0.40-0.50 , is formed over a surface of the shielding layer 22 .
  • the hardmask 16 is formed over a surface of the low reflectivity layer 24 .
  • the shielding layer 22 can have a thickness, for example, between 35 nm and 55 nm
  • the low reflectivity layer 24 can have a thickness, for example, between 5 nm and 20 nm.
  • the layers may be formed in situ by varying parameters of the deposition process used.
  • FIG. 3 is a third layered structure 28 used in forming a mask according to an embodiment.
  • the third layered structure 28 is similar to the second layered structure 20 of FIG. 2 except the positions of the shielding layer 22 and the low reflectivity layer 24 are switched.
  • FIG. 4 is a fourth layered structure 30 used in forming a mask according to an embodiment.
  • a first low reflectivity layer 32 is over the substrate 12 , and a shielding layer 34 is over the first low reflectivity layer 32 .
  • a second low reflectivity layer 36 is over the shielding layer 34 , and the hardmask 16 is over the second low reflectivity layer 36 .
  • Each of the first low reflectivity layer 32 and the second low reflectivity layer 36 is, in this embodiment, Mo 0.01-0.02 Si 0.50-0.55 N 0.40-0.50 , and each may have a thickness between approximately 5 nm and 20 nm.
  • the shielding layer 34 is, in this embodiment, Mo 0.04-0.05 Si 0.45-0.50 N 0.40-0.50 and may have a thickness between approximately 30 nm and 55 nm.
  • FIGS. 5 through 11 illustrate a method for forming a binary mask according to an embodiment. It should be noted that the order of steps discussed herein is as an example, and the steps may be performed in any logical order.
  • a layered structure such as any of layered structures 10 , 20 , 28 , and 30 , has a photoresist 42 , such as a chemically amplified resist (CAR), formed thereon, such as by coating.
  • Layer(s) 40 represents, for example, the Mo x Si y N z layer 14 in the layered structure 10 ; shielding layer 22 and the low reflectivity layer 24 in the layered structures 20 and 28 ; or the first low reflectivity layer 32 , the shielding layer 34 , and the second low reflectivity layer 36 in the layered structure 30 .
  • the photoresist 42 is exposed, such as by an electronic (e-beam) exposure, with a pattern 44 .
  • the structure is baked, such as at a temperature between approximately 90° C. and 130° C.
  • the photoresist 42 is developed to form openings according to the pattern 44 through the photoresist 42 using, for example, a mixture of tetramethylammonium hydroxide (TMAH) and water.
  • TMAH tetramethylammonium hydroxide
  • the hardmask 16 is etched to form openings through the hardmask 16 in the form of the pattern 44 .
  • the etching may be by a plasma etch using chlorine (Cl 2 ) and oxygen (O 2 ), although other acceptable etching techniques may be used.
  • the photoresist 42 is removed, such as by using an acceptable strip process.
  • FIG. 1 the photoresist 42 is removed, such as by using an acceptable strip process.
  • layer(s) 40 is etched, such as using a plasma with sulfur hexafluoride (SF 6 ) and O 2 , to form openings through the layer(s) 40 in the form of the pattern 44 , thereby transferring the pattern 44 into the layer(s) 40 .
  • layer(s) 40 may have layers of different compositions of Mo x Si y N z , and all of the present layers can be etched in a single etch step based on the same elements being in the layers although the respective compositions may be different. In such embodiments, no extra by-product is generally produced by the etching due to the presence of two or more layers.
  • the hardmask 16 is removed using an acceptable strip process. It should be noted that after various etching and/or removing steps, components may be cleaned, such as with a sulfuric-peroxide mixture (SPM) or jet-spray with deionized water.
  • SPM sulfuric-peroxide mixture
  • the composition of molybdenum and silicon e.g., x and y, respectively, the percentage of reflectivity of the layer can be tuned.
  • Table 1 summarizes various characteristics of Mo x Si y N z layers as discussed herein in various embodiments when a light having a wavelength at 193 nanometers is used in conjunction with a mask with the Mo x Si y N z layer, for example, during semiconductor processing.
  • Embodiments may achieve advantages.
  • First, embodiments may have a reduced stress during processing because the various layers may have more similar coefficients of thermal expansion (CTE).
  • Embodiments may also have better cleaning durability than conventional masks.
  • embodiments may have a critical dimension loss of approximately 0.1 nm per clean with a SPM clean or less than 0.1 nm per clean with a jet-spray clean with deionized water. These critical dimension losses are improvements of approximately 3 to 4 times over some conventional techniques.
  • embodiments may vary the composition of a layer to adjust and tune the reflectivity, the refractive index (n), and the extinction coefficient (k) of the layer.
  • a first embodiment is a lithography mask comprising a transparent substrate and a first molybdenum silicon nitride (Mo x Si y N z ) layer.
  • the first Mo x Si y N z layer is over the transparent substrate.
  • a percentage of molybdenum (x) of the first Mo x Si y N z layer is between 1 and 2.
  • a percentage of silicon (y) of the first Mo x Si y N z layer is between 50 and 55.
  • a percentage of nitride (z) of the first Mo x Si y N z layer is between 40 and 50.
  • the first Mo x Si y N z layer has an opening therethrough.
  • Another embodiment is a lithography mask comprising a substrate and a molybdenum-containing layer over a surface of the substrate.
  • the molybdenum-containing layer comprises a first portion with a first percentage of molybdenum and a second portion with a second percentage of molybdenum. The first percentage and the second percentage are different.
  • Another embodiment is a lithography mask comprising a substrate and a molybdenum silicon nitride (MoSiN) structure on a surface of the substrate.
  • the MoSiN structure comprises a first Mo 0.01-0.02 Si 0.50-0.55 N 0.40-0.50 layer.
  • the MoSiN structure has an opening exposing the surface of the substrate.
  • a further embodiment is a method for forming a lithography mask.
  • the method comprises forming a molybdenum-containing layer over a transparent substrate and forming a first opening through the molybdenum-containing layer.
  • the molybdenum-containing layer comprises a first portion with a first percentage of molybdenum and a second portion with a second percentage of molybdenum. The first percentage being different from the second percentage.
  • a yet further embodiment is a method for forming a lithography mask.
  • the method comprises forming a first molybdenum silicon nitride (Mo x Si y N z ) layer over a transparent substrate and forming a first opening through the first Mo x Si y N z layer.
  • a percentage of molybdenum (x) of the first Mo x Si y N z layer is between 1 and 2.
  • a percentage of silicon (y) of the first Mo x Si y N z layer is between 50 and 55.
  • a percentage of nitride (z) of the first Mo x Si y N z layer is between 40 and 50.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)

Abstract

A first embodiment is a lithography mask comprising a transparent substrate and a first molybdenum silicon nitride (MoxSiyNz) layer. The first MoxSiyNz layer is over the transparent substrate. A percentage of molybdenum (x) of the first MoxSiyNz layer is between 1 and 2. A percentage of silicon (y) of the first MoxSiyNz layer is between 50 and 55. A percentage of nitride (z) of the first MoxSiyNz layer is between 40 and 50. The first MoxSiyNz layer has an opening therethrough.

Description

  • This application claims the benefit of U.S. Provisional Application No. 61/547,468, filed on Oct. 14, 2011, entitled “Lithography Mask and Method of Forming a Lithography Mask,” which application is hereby incorporated herein by reference in its entirety.
    • BACKGROUND
  • In semiconductor processing, multiple lithography steps are generally used to form a semiconductor chip. These steps typically include forming a photoresist over a substrate that is to be formed into the semiconductor chip, exposing the photoresist to a pattern of light generally controlled by a mask, developing the pattern in the photoresist to expose the underlying substrate, and etching the pattern in the underlying substrate. The pattern etched in the underlying substrate may be a basis for some feature formation, such as an ion impurity implantation such as for doping source and drain regions, a formation of a structure like a gate patterning, or a pattern for a conductive material such as in a metallization layer.
  • Advances in semiconductor processing have generally allowed for continued reduction of minimum feature sizes for semiconductor chips; however, each reduction in size typically is accompanied with its own challenges. As minimum feature size decreases, overlay concerns are typically intensified. Minimum feature size reduction allows for a greater density of features in a given area, which in turn increases the likelihood that an improperly overlaid feature can render the chip useless.
  • To help avoid improper overlaying of features, critical dimensions of features typically must be precise. If dimensions of features are just a small amount more than corresponding critical dimensions, the features can overlay other features. Accordingly, it is advantageous to form features with precise dimensions that are true to a design.
  • As previously noted, lithography steps are typically used to form these features, and at the source of the lithography steps is the mask. If the mask is not able to precisely form a pattern in a photoresist, the subsequently formed feature may not meet its critical dimension requirement. Some causes for a mask not being able to precisely form a pattern may be that the pattern formed in the mask itself is not precise, such as caused by a slight, unintended etching of material holding the pattern in the mask during the cleaning of the mask while being formed. This slight etch may widen the pattern in the mask beyond a critical dimension. Further, various physical characteristics of the mask, such a reflectivity percentage, a refractive index, and a coefficient of extinction, may cause an exposure through the mask to be improperly focused or allow spurious light to be incident on the photoresist.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • For a more complete understanding of the present embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
  • FIG. 1 illustrates a first layered structure used in forming a mask according to an embodiment;
  • FIG. 2 illustrates a second layered structure used in forming a mask according to an embodiment;
  • FIG. 3 illustrates a third layered structure used in forming a mask according to an embodiment;
  • FIG. 4 illustrates a fourth layered structure used in forming a mask according to an embodiment; and
  • FIGS. 5 through 11 illustrate a method for forming a binary mask according to an embodiment.
    •  DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
  • The making and using of the present embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosed subject matter, and do not limit the scope of the different embodiments.
  • Embodiments will be described with respect to a specific context, namely a method for forming a mask and/or reticle for use in a lithography process, such as in semiconductor processing. Embodiments contemplate forming a binary mask for use in the lithography process, particularly at technology nodes of 20 nanometer (nm) and 28 nm. Other embodiments may also be applied to other lithography processes, other types of masks, for example a phase shift mask, and any technology node.
  • FIG. 1 illustrates a first layered structure 10 used in forming a mask according to an embodiment. The layered structure 10 includes a substrate 12, a molybdenum silicon nitride (MoxSiyNz) layer 14, and a hardmask 16. The substrate 12 is an acceptable transparent material, such as quartz, low thermal expansive (LTE) glass, or the like. In an embodiment, the MoxSiyNz layer 14 is a low reflectivity layer having, for example, an atomic weight percentage of molybdenum (x) between approximately 1 and 2 percent, an atomic weight percentage of silicon (y) between approximately 50 and 55 percent, and an atomic weight percentage of nitrogen (z) between approximately 40 and 50 percent. In another embodiment, the MoxSiyNz layer 14 is a shielding layer having, for example, an atomic weight percentage of molybdenum (x) between approximately 4 and 5 percent, an atomic weight percentage of silicon (y) between approximately 45 and 50 percent, and an atomic weight percentage of nitrogen (z) between approximately 40 and 50 percent. The hardmask 16 is an acceptable material, such as a metal like chromium, tantalum, an oxide or nitride of a metal like chromium oxide, tantalum nitride, tantalum oxide, the like, or a combination thereof.
  • The MoxSiyNz layer 14 is formed on a surface of the substrate 12 by, for example, a sputter deposition. In other embodiments, other physical vapor deposition (PVD) processes or the like may be used. A person having ordinary skill in the art will readily understand the appropriate parameters, gases, etc. used in forming the MoxSiyNz layer 14 with a desired concentration or percentage of particular elements. The MoxSiyNz layer 14 can be formed with any thickness, and in some embodiments, the thickness is between 40 nm and 75 nm. The hardmask 16 can be formed on a surface of the MoxSiyNz layer 14 opposite the surface of the substrate 12 by PVD, atomic layer deposition (ALD), the like, or a combination thereof, with a thickness of, for example, 5 nm to 20 nm.
  • FIG. 2 is a second layered structure 20 used in forming a mask according to an embodiment. A shielding layer 22, such as Mo0.04-0.05Si0.45-0.50N0.40-0.50, is formed over the surface of the substrate 12, and a low reflectivity layer 24, such as Mo0.01-0.02Si0.50-0.55N0.40-0.50, is formed over a surface of the shielding layer 22. The hardmask 16 is formed over a surface of the low reflectivity layer 24. The shielding layer 22 can have a thickness, for example, between 35 nm and 55 nm, and the low reflectivity layer 24 can have a thickness, for example, between 5 nm and 20 nm. When layers formed of the same elements but different compositions are used, the layers may be formed in situ by varying parameters of the deposition process used.
  • FIG. 3 is a third layered structure 28 used in forming a mask according to an embodiment. The third layered structure 28 is similar to the second layered structure 20 of FIG. 2 except the positions of the shielding layer 22 and the low reflectivity layer 24 are switched.
  • FIG. 4 is a fourth layered structure 30 used in forming a mask according to an embodiment. A first low reflectivity layer 32 is over the substrate 12, and a shielding layer 34 is over the first low reflectivity layer 32. A second low reflectivity layer 36 is over the shielding layer 34, and the hardmask 16 is over the second low reflectivity layer 36. Each of the first low reflectivity layer 32 and the second low reflectivity layer 36 is, in this embodiment, Mo0.01-0.02Si0.50-0.55N0.40-0.50, and each may have a thickness between approximately 5 nm and 20 nm.
  • The shielding layer 34 is, in this embodiment, Mo0.04-0.05Si0.45-0.50N0.40-0.50 and may have a thickness between approximately 30 nm and 55 nm.
  • Other embodiments contemplate various combinations and numbers of a low reflectivity layer(s) and/or shielding layer(s) comprising MoxSiyNz. A person having ordinary skill in the art will readily understand these modifications.
  • FIGS. 5 through 11 illustrate a method for forming a binary mask according to an embodiment. It should be noted that the order of steps discussed herein is as an example, and the steps may be performed in any logical order.
  • In FIG. 5, a layered structure, such as any of layered structures 10, 20, 28, and 30, has a photoresist 42, such as a chemically amplified resist (CAR), formed thereon, such as by coating. Layer(s) 40 represents, for example, the MoxSiyNz layer 14 in the layered structure 10; shielding layer 22 and the low reflectivity layer 24 in the layered structures 20 and 28; or the first low reflectivity layer 32, the shielding layer 34, and the second low reflectivity layer 36 in the layered structure 30. In FIG. 5, the photoresist 42 is exposed, such as by an electronic (e-beam) exposure, with a pattern 44.
  • In FIG. 6, the structure is baked, such as at a temperature between approximately 90° C. and 130° C. In FIG. 7, the photoresist 42 is developed to form openings according to the pattern 44 through the photoresist 42 using, for example, a mixture of tetramethylammonium hydroxide (TMAH) and water. In FIG. 8, the hardmask 16 is etched to form openings through the hardmask 16 in the form of the pattern 44. The etching may be by a plasma etch using chlorine (Cl2) and oxygen (O2), although other acceptable etching techniques may be used. In FIG. 9, the photoresist 42 is removed, such as by using an acceptable strip process. In FIG. 10, layer(s) 40 is etched, such as using a plasma with sulfur hexafluoride (SF6) and O2, to form openings through the layer(s) 40 in the form of the pattern 44, thereby transferring the pattern 44 into the layer(s) 40. It should be noted that layer(s) 40 may have layers of different compositions of MoxSiyNz, and all of the present layers can be etched in a single etch step based on the same elements being in the layers although the respective compositions may be different. In such embodiments, no extra by-product is generally produced by the etching due to the presence of two or more layers. In FIG. 11, the hardmask 16 is removed using an acceptable strip process. It should be noted that after various etching and/or removing steps, components may be cleaned, such as with a sulfuric-peroxide mixture (SPM) or jet-spray with deionized water.
  • A correlation exists between the percentages of silicon and molybdenum in a MoxSiyNz layer and the reflectivity of the layer. The percentage of reflectivity can be expressed by R=0.058x+0.0011y. By adjusting the composition of molybdenum and silicon, e.g., x and y, respectively, the percentage of reflectivity of the layer can be tuned. The following Table 1 summarizes various characteristics of MoxSiyNz layers as discussed herein in various embodiments when a light having a wavelength at 193 nanometers is used in conjunction with a mask with the MoxSiyNz layer, for example, during semiconductor processing.
  • TABLE 1
    Refractive Extinction Reflectivity
    Film Mo (%) Si (%) N (%) Index (n) Coefficient (k) (%)
    Shielding layer 4-5 45-50 40-50 2.2-2.4 0.55-0.60 34
    Low reflectivity layer 1-2 50-55 40-50 2.5-2.6 0.60-0.65 12
  • Embodiments may achieve advantages. First, embodiments may have a reduced stress during processing because the various layers may have more similar coefficients of thermal expansion (CTE). Embodiments may also have better cleaning durability than conventional masks. For example, embodiments may have a critical dimension loss of approximately 0.1 nm per clean with a SPM clean or less than 0.1 nm per clean with a jet-spray clean with deionized water. These critical dimension losses are improvements of approximately 3 to 4 times over some conventional techniques. Further, as shown in Table 1, embodiments may vary the composition of a layer to adjust and tune the reflectivity, the refractive index (n), and the extinction coefficient (k) of the layer.
  • A first embodiment is a lithography mask comprising a transparent substrate and a first molybdenum silicon nitride (MoxSiyNz) layer. The first MoxSiyNz layer is over the transparent substrate. A percentage of molybdenum (x) of the first MoxSiyNz layer is between 1 and 2. A percentage of silicon (y) of the first MoxSiyNz layer is between 50 and 55. A percentage of nitride (z) of the first MoxSiyNz layer is between 40 and 50. The first MoxSiyNz layer has an opening therethrough.
  • Another embodiment is a lithography mask comprising a substrate and a molybdenum-containing layer over a surface of the substrate. The molybdenum-containing layer comprises a first portion with a first percentage of molybdenum and a second portion with a second percentage of molybdenum. The first percentage and the second percentage are different.
  • Another embodiment is a lithography mask comprising a substrate and a molybdenum silicon nitride (MoSiN) structure on a surface of the substrate. The MoSiN structure comprises a first Mo0.01-0.02Si0.50-0.55N0.40-0.50 layer. The MoSiN structure has an opening exposing the surface of the substrate.
  • A further embodiment is a method for forming a lithography mask. The method comprises forming a molybdenum-containing layer over a transparent substrate and forming a first opening through the molybdenum-containing layer. The molybdenum-containing layer comprises a first portion with a first percentage of molybdenum and a second portion with a second percentage of molybdenum. The first percentage being different from the second percentage.
  • A yet further embodiment is a method for forming a lithography mask. The method comprises forming a first molybdenum silicon nitride (MoxSiyNz) layer over a transparent substrate and forming a first opening through the first MoxSiyNz layer. A percentage of molybdenum (x) of the first MoxSiyNz layer is between 1 and 2. A percentage of silicon (y) of the first MoxSiyNz layer is between 50 and 55. A percentage of nitride (z) of the first MoxSiyNz layer is between 40 and 50.
  • Although the present embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims (20)

What is claimed is:
1. A lithography mask comprising:
a transparent substrate; and
a first molybdenum silicon nitride (MoxSiyNz) layer over the transparent substrate, a percentage of molybdenum (x) of the first MoxSiyNz layer being between 1 and 2, a percentage of silicon (y) of the first MoxSiyNz layer being between 50 and 55, and a percentage of nitrogen (z) of the first MoxSiyNz layer being between 40 and 50, the first MoxSiyNz layer having an opening therethrough.
2. The lithography mask of claim 1 further comprising a second molybdenum silicon nitride (MoxSiyNz) layer, the first MoxSiyNz layer being disposed between the transparent substrate and the second MoxSiyNz layer, a percentage of molybdenum (x) of the second MoxSiyNz layer being between 4 and 5, a percentage of silicon (y) of the second MoxSiyNz layer being between 45 and 50, and a percentage of nitrogen (z) of the second MoxSiyNz layer being between 40 and 50, the opening being through the second MoxSiyNz layer.
3. The lithography mask of claim 1 further comprising a second molybdenum silicon nitride (MoxSiyNz) layer disposed between the transparent substrate and the first MoxSiyNz layer, a percentage of molybdenum (x) of the second MoxSiyNz layer being between 4 and 5, a percentage of silicon (y) of the second MoxSiyNz layer being between 45 and 50, and a percentage of nitrogen (z) of the second MoxSiyNz layer being between 40 and 50, the opening being through the second MoxSiyNz layer.
4. The lithography mask of claim 1 further comprising:
a second molybdenum silicon nitride (MoxSiyNz) layer, the first MoxSiyNz layer being disposed between the transparent substrate and the second MoxSiyNz layer, a percentage of molybdenum (x) of the second MoxSiyNz layer being between 4 and 5, a percentage of silicon (y) of the second MoxSiyNz layer being between 45 and 50, and a percentage of nitrogen (z) of the second MoxSiyNz layer being between 40 and 50; and
a third molybdenum silicon nitride (MoxSiyNz) layer, the second MoxSiyNz layer being disposed between the first MoxSiyNz layer and the third MoxSiyNz layer, a percentage of molybdenum (x) of the third MoxSiyNz layer being between 1 and 2, a percentage of silicon (y) of the third MoxSiyNz layer being between 50 and 55, and a percentage of nitrogen (z) of the third MoxSiyNz layer being between 40 and 50, the opening being through the second MoxSiyNz layer and the third MoxSiyNz layer.
5. The lithography mask of claim 1, wherein the transparent substrate comprises quartz.
6. The lithography mask of claim 1 further comprising a hardmask, the first MoxSiyNz layer being disposed between the hardmask and the transparent substrate.
7. A lithography mask comprising:
a substrate; and
a molybdenum-containing layer over a surface of the substrate, the molybdenum-containing layer comprising a first portion with a first percentage of molybdenum and a second portion with a second percentage of molybdenum, wherein the first percentage and the second percentage are different.
8. The lithography mask of claim 7, wherein the molybdenum-containing layer has an opening exposing the surface of the substrate.
9. The lithography mask of claim 7, wherein the first percentage of molybdenum is greater than the second percentage of molybdenum, the first portion being over the second portion.
10. The lithography mask of claim 9, wherein the first portion comprises Mo0.04-0.05Si0.45-0.50N0.40-0.50, and the second portion comprises Mo0.01-0.02Si0.50-0.55N0.40-0.50.
11. The lithography mask of claim 7, wherein the second percentage of molybdenum is greater than the first percentage of molybdenum, the first portion being over the second portion.
12. The lithography mask of claim 11, wherein the second portion comprises Mo0.04-0.05Si0.45-0.50N0.40-0.50, and the first portion comprises Mo0.01-0.02Si0.50-0.55N0.40-0.50.
13. The lithography mask of claim 7, wherein the molybdenum-containing layer further comprises silicon and nitrogen.
14. The lithography mask of claim 7, wherein the molybdenum-containing layer comprises a third portion with a third percentage of molybdenum, the first portion being over the second portion, the second portion being over the third portion, the second percentage of molybdenum being greater than each of the first percentage of molybdenum and the second percentage of molybdenum.
15. The lithography mask of claim 14, wherein the first portion comprises Mo0.01-0.02Si0.50-0.55N0.40-0.50, the second portion comprises Mo0.04-0.05Si0.45-0.50N0.40-0.50, and the third portion comprises Mo0.01-0.02Si0.50-0.55N0.40-0.50.
16. A method for forming a lithography mask, the method comprising:
forming a molybdenum-containing layer over a transparent substrate, the molybdenum-containing layer comprising a first portion with a first percentage of molybdenum and a second portion with a second percentage of molybdenum, the first percentage being different from the second percentage; and
forming a first opening through the molybdenum-containing layer.
17. The method of claim 16, wherein the molybdenum-containing layer further comprises silicon and nitrogen, the first portion comprising:
the first percentage of molybdenum being between 1 and 2,
a first percentage of silicon being between 50 and 55, and
a first percentage of nitrogen being between 40 and 50,
the second portion comprising:
the second percentage of molybdenum being between 4 and 5,
a second percentage of silicon being between 45 and 50, and
a second percentage of nitrogen being between 40 and 50, and
the first portion being over the second portion.
18. The method of claim 16, wherein the molybdenum-containing layer further comprises silicon and nitrogen, the first portion comprising:
the first percentage of molybdenum being between 4 and 5,
a first percentage of silicon being between 45 and 50, and
a first percentage of nitrogen being between 40 and 50,
the second portion comprising:
the second percentage of molybdenum being between 1 and 2,
a second percentage of silicon being between 50 and 55, and
a second percentage of nitrogen being between 40 and 50, and
the first portion being over the second portion.
19. The method of claim 16, wherein the molybdenum-containing layer further comprises silicon and nitrogen, the molybdenum-containing layer further comprising a third portion, the first portion comprising:
the first percentage of molybdenum being between 1 and 2,
a first percentage of silicon being between 50 and 55, and
a first percentage of nitrogen being between 40 and 50,
the second portion comprising:
the second percentage of molybdenum being between 4 and 5,
a second percentage of silicon being between 45 and 50, and
a second percentage of nitrogen being between 40 and 50,
the third portion comprising:
a third percentage of molybdenum being between 1 and 2,
a third percentage of silicon being between 50 and 55, and
a third percentage of nitrogen being between 40 and 50, and
the first portion being over the second portion, the second portion being over the third portion.
20. The method of claim 16, wherein the molybdenum-containing layer further comprises silicon and nitrogen.
US13/324,755 2011-10-14 2011-12-13 Lithography mask and method of forming a lithography mask Active 2032-11-10 US8921014B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US13/324,755 US8921014B2 (en) 2011-10-14 2011-12-13 Lithography mask and method of forming a lithography mask
US14/558,097 US9513542B2 (en) 2011-10-14 2014-12-02 Lithography mask and method of forming a lithography mask

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201161547468P 2011-10-14 2011-10-14
US13/324,755 US8921014B2 (en) 2011-10-14 2011-12-13 Lithography mask and method of forming a lithography mask

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14/558,097 Division US9513542B2 (en) 2011-10-14 2014-12-02 Lithography mask and method of forming a lithography mask

Publications (2)

Publication Number Publication Date
US20130095414A1 true US20130095414A1 (en) 2013-04-18
US8921014B2 US8921014B2 (en) 2014-12-30

Family

ID=48086204

Family Applications (2)

Application Number Title Priority Date Filing Date
US13/324,755 Active 2032-11-10 US8921014B2 (en) 2011-10-14 2011-12-13 Lithography mask and method of forming a lithography mask
US14/558,097 Active 2032-02-21 US9513542B2 (en) 2011-10-14 2014-12-02 Lithography mask and method of forming a lithography mask

Family Applications After (1)

Application Number Title Priority Date Filing Date
US14/558,097 Active 2032-02-21 US9513542B2 (en) 2011-10-14 2014-12-02 Lithography mask and method of forming a lithography mask

Country Status (1)

Country Link
US (2) US8921014B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140030448A1 (en) * 2012-07-30 2014-01-30 Air Products And Chemicals, Inc. Non-oxygen containing silicon-based films and methods of forming the same
CN105842981A (en) * 2016-05-03 2016-08-10 岭南师范学院 Preparation method of low-cost precision chip mold lithography mask
KR20190002334A (en) * 2017-06-29 2019-01-08 신에쓰 가가꾸 고교 가부시끼가이샤 Photomask blank, and photomask
JP2022118976A (en) * 2021-02-03 2022-08-16 アルバック成膜株式会社 Mask blank and photomask

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100092874A1 (en) * 2008-06-25 2010-04-15 Hoya Corporation Phase shift mask blank, phase shift mask, and method for manufacturing phase shift mask blank
US20110287346A1 (en) * 2010-05-19 2011-11-24 Hoya Corporation Mask blank manufacturing method, transfer mask manufacturing method, mask blank, and transfer mask

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6569580B2 (en) 2001-03-13 2003-05-27 Diverging Technologies, Inc. Binary and phase-shift photomasks

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100092874A1 (en) * 2008-06-25 2010-04-15 Hoya Corporation Phase shift mask blank, phase shift mask, and method for manufacturing phase shift mask blank
US20110287346A1 (en) * 2010-05-19 2011-11-24 Hoya Corporation Mask blank manufacturing method, transfer mask manufacturing method, mask blank, and transfer mask

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140030448A1 (en) * 2012-07-30 2014-01-30 Air Products And Chemicals, Inc. Non-oxygen containing silicon-based films and methods of forming the same
US9243324B2 (en) * 2012-07-30 2016-01-26 Air Products And Chemicals, Inc. Methods of forming non-oxygen containing silicon-based films
CN105842981A (en) * 2016-05-03 2016-08-10 岭南师范学院 Preparation method of low-cost precision chip mold lithography mask
KR20190002334A (en) * 2017-06-29 2019-01-08 신에쓰 가가꾸 고교 가부시끼가이샤 Photomask blank, and photomask
JP2019012132A (en) * 2017-06-29 2019-01-24 信越化学工業株式会社 Photomask Blank and Photomask
KR102293214B1 (en) 2017-06-29 2021-08-24 신에쓰 가가꾸 고교 가부시끼가이샤 Photomask blank, and photomask
JP2022118976A (en) * 2021-02-03 2022-08-16 アルバック成膜株式会社 Mask blank and photomask

Also Published As

Publication number Publication date
US20150132685A1 (en) 2015-05-14
US8921014B2 (en) 2014-12-30
US9513542B2 (en) 2016-12-06

Similar Documents

Publication Publication Date Title
US7540970B2 (en) Methods of fabricating a semiconductor device
KR102217760B1 (en) Halftone phase shift mask blank and halftone phase shift mask
US8778807B2 (en) Method of reducing delamination in the fabrication of small-pitch devices
US8071261B2 (en) Lithography masks and methods of manufacture thereof
JP6716629B2 (en) Phase inversion blank mask and manufacturing method thereof
KR102195696B1 (en) Halftone phase shift photomask blank
CN107430328B (en) Photomask blank, method for manufacturing photomask, and method for forming mask pattern
KR102260135B1 (en) Photomask blank
US9513542B2 (en) Lithography mask and method of forming a lithography mask
JP6477159B2 (en) Halftone phase shift mask blank and method of manufacturing halftone phase shift mask blank
JP2009063638A (en) Method of manufacturing photomask and method of manufacturing semiconductor device
KR102493632B1 (en) Phase shift-type photomask blank and phase shift-type photomask
US9057961B2 (en) Systems and methods for lithography masks
KR20170016107A (en) Method for fabricating semiconductor device
US20010055843A1 (en) Method for fabricating semiconductor device
KR100945919B1 (en) Method for fabricating photomask in semiconductor device
KR20070113604A (en) Method for forming micro pattern of semiconductor device
US11500293B2 (en) Patterning material film stack with hard mask layer configured to support selective deposition on patterned resist layer
JP2022009498A (en) Photomask and its manufacturing method
US10126643B2 (en) Anti-ESD photomask and method of forming the same
US8524608B1 (en) Method for fabricating a patterned structure of a semiconductor device
TWI785552B (en) Manufacturing method of photomask
JP2000131825A (en) Photomask for semiconductor device and its production
WO2022191042A1 (en) Phase-shift mask blank, phase-shift mask, method of manufacturing phase-shift mask, and method of modifying phase-shift mask
TW202347013A (en) Phase shift mask and method for manufacturing phase shift mask

Legal Events

Date Code Title Description
AS Assignment

Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YOO, CHUE-SAN;CHEN, CHUN-LANG;SIGNING DATES FROM 20111130 TO 20111206;REEL/FRAME:027384/0809

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551)

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8