US20130078794A1 - Charge trap type non-volatile memory device and method for fabricating the same - Google Patents
Charge trap type non-volatile memory device and method for fabricating the same Download PDFInfo
- Publication number
- US20130078794A1 US20130078794A1 US13/682,276 US201213682276A US2013078794A1 US 20130078794 A1 US20130078794 A1 US 20130078794A1 US 201213682276 A US201213682276 A US 201213682276A US 2013078794 A1 US2013078794 A1 US 2013078794A1
- Authority
- US
- United States
- Prior art keywords
- layer
- charge trap
- charge
- nitride
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 title claims abstract description 54
- 150000004767 nitrides Chemical class 0.000 claims abstract description 42
- 238000009413 insulation Methods 0.000 claims abstract description 39
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 38
- 229920005591 polysilicon Polymers 0.000 claims abstract description 38
- 230000004888 barrier function Effects 0.000 claims abstract description 32
- 125000006850 spacer group Chemical group 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 230000003647 oxidation Effects 0.000 claims description 31
- 238000007254 oxidation reaction Methods 0.000 claims description 31
- 230000008569 process Effects 0.000 claims description 28
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 13
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 11
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 238000009279 wet oxidation reaction Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 186
- 239000007789 gas Substances 0.000 description 8
- 239000012535 impurity Substances 0.000 description 6
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 241000293849 Cordylanthus Species 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 230000014759 maintenance of location Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910003468 tantalcarbide Inorganic materials 0.000 description 3
- -1 tantalum carbide nitride Chemical class 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000001272 nitrous oxide Substances 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 238000007669 thermal treatment Methods 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 229910003855 HfAlO Inorganic materials 0.000 description 1
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 1
- ODUCDPQEXGNKDN-UHFFFAOYSA-N Nitrogen oxide(NO) Natural products O=N ODUCDPQEXGNKDN-UHFFFAOYSA-N 0.000 description 1
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000005516 deep trap Effects 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000002365 multiple layer Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
Definitions
- the present disclosure relates to a semiconductor device and a method for fabricating the same, and more particularly, to a charge trap type non-volatile memory device and a method for fabricating the same.
- a non-volatile memory device refers to a memory device which can maintain stored data intact even when a power supply is cut off.
- a memory device which stores data by storing or erasing charges in a floating gate is referred to as a floating gate type non-volatile memory device.
- a typical floating gate type non-volatile memory device includes a tunnel insulation layer, a floating gate, a charge barrier layer, and a control gate formed over a substrate.
- a typical floating gate type non-volatile memory device stores data by injecting or emitting charges in the floating gate.
- a typical method presents a charge trap type non-volatile memory device as a type of non-volatile memory device.
- a charge trap type non-volatile memory device is described in detail with a drawing.
- FIG. 1 illustrates a cross-sectional view of a typical charge trap type non-volatile memory device.
- the charge trap type non-volatile memory device includes a tunnel insulation layer 110 , a charge trap layer 120 , a charge barrier layer 130 , a gate electrode 140 , and a hard mask pattern 150 formed over a substrate 100 .
- the tunnel insulation layer 110 is formed as an energy barrier layer for charge tunneling.
- the tunnel insulation layer 110 may include an oxide-based layer.
- the charge trap layer 120 stores charges which tunneled through the tunnel insulation layer 110 .
- the charge trap layer 120 substantially functions as a data storing unit.
- the charge trap layer 120 may include a nitride-based layer.
- the charge barrier layer 130 is formed to prevent charges from passing through the charge trap layer 120 and moving upward.
- nitride-based spacers 160 are formed over sidewalls of the hard mask pattern 150 and the gate electrode 140 to prevent oxidation of the gate electrode 140 during a subsequent process.
- Reference denotation ‘A’ represents a charge trap structure A which includes the tunnel insulation layer 110 , the charge trap layer 120 , the charge barrier layer 130 , the gate electrode 140 , the hard mask pattern 150 , and the nitride-based spacers 160 .
- An oxide-based spacer 170 is formed over the charge trap structure A.
- the typical charge trap type non-volatile memory device having the above described structure stores or erases charges in a deep level trap site in the charge trap layer 120 .
- the stored charges may not be lost even when the tunnel insulation layer 110 is formed to a small thickness.
- the typical charge trap type non-volatile memory device may be operated at a low operation voltage.
- the integration scale of a semiconductor device may be improved compared to a floating gate type non-volatile memory device.
- the typical charge trap type non-volatile memory device may have limitations as follows.
- the charge trap layer 120 including a nitride-based layer there may be a large density difference in a trap site depending on the composition of silicon (Si) and nitrogen (N) of the nitride-based layer. Thus, charges stored in the charge trap layer 120 may not be dispersed evenly.
- an oxidation process is performed on the substrate structure including the charge trap structure A to form the oxide-based spacer 170 .
- the oxide-based spacer 170 is formed so that the tunnel insulation layer 110 and the charge trap layer 120 may be reinforced and prevented from getting damaged.
- charges may be lost through a portion of the sidewall of the charge trap layer 120 , as represented with reference denotation ‘B’, because an interface between the charge trap layer 120 and the oxide-based spacer 170 is not stabilized even after the oxide-based spacer 170 is formed over the sidewalls of the charge trap layer 120 .
- One or more embodiments disclosed in the present application are directed to providing a memory device having a charge trap layer which includes a polysilicon thin layer and a nitride-based layer and a method for fabricating the same.
- a charge trap type non-volatile memory device including: a tunnel insulation layer formed over a substrate; a charge trap layer formed over the tunnel insulation layer, the charge trap layer including a charge trap polysilicon thin layer and a charge trap nitride-based layer; a charge barrier layer formed over the charge trap layer; a gate electrode formed over the charge barrier layer; and an oxide-based spacer formed over sidewalls of the charge trap layer and provided to isolate the charge trap layer.
- a method for fabricating a charge trap type non-volatile memory device including: forming a tunnel insulation layer over a substrate; forming a charge trap layer over the tunnel insulation layer, the charge trap layer including a charge trap polysilicon thin layer and a charge trap nitride-based layer; forming a charge barrier layer over the charge trap layer; forming a gate electrode conductive layer over the charge barrier layer; etching the gate electrode conductive layer, the charge barrier layer, the charge trap layer, and the tunnel insulation layer to form a charge trap structure; and forming an oxide-based spacer over sidewalls of the etched charge trap layer.
- FIG. 1 illustrates a cross-sectional view of a typical charge trap type non-volatile memory device.
- FIGS. 2A to 2G show cross-sectional views illustrating a method of fabricating a charge trap type non-volatile memory device in accordance with one embodiment.
- One or more embodiments of the present disclosure relate to a charge trap type non-volatile memory device which includes a charge trap layer having a polysilicon thin layer and a nitride-based layer.
- the charge trap type non-volatile memory device may improve the operation rate of charge storage and erasure by dispersedly storing charges in the polysilicon thin layer and the nitride-based layer.
- the charge trap type non-volatile memory device may prevent loss of charges by effectively isolating the charge trap layer using an oxide-based layer formed to enclose sidewalls of the charge trap layer. Therefore, data retention and reliability of the memory device may be enhanced.
- FIGS. 2A to 2G show cross-sectional views illustrating a method of fabricating a charge trap type non-volatile memory device in accordance with one embodiment.
- a tunnel insulation layer 210 is formed over a substrate 200 .
- the tunnel insulation layer 210 is formed as an energy barrier layer for charge tunneling.
- the tunnel insulation layer 210 may include an oxide-based layer formed by a radical oxidation process.
- the radical oxidation process may be performed at a temperature ranging from approximately 750° C. to approximately 950° C.
- the occurrence of undesirable formation in the tunnel insulation layer 210 may be minimized by including nitrogen during the oxidation process.
- the tunnel insulation layer 210 may be formed to a thickness ranging from approximately 40 ⁇ to approximately 60 ⁇ .
- an annealing process may be performed using nitrous oxide (N 2 O) gas or nitrogen oxide (NO) gas.
- a charge trap polysilicon thin layer 220 A is formed over the tunnel insulation layer 210 .
- the charge trap polysilicon thin layer 220 A may be formed to a thickness ranging from approximately 10 ⁇ to approximately 30 ⁇ .
- the charge trap polysilicon thin layer 220 A may be formed using the process shown below.
- An amorphous silicon layer is formed to a certain thickness over the tunnel insulation layer 210 .
- the amorphous silicon layer may be formed to a thickness ranging from approximately 50 ⁇ to approximately 100 ⁇ .
- the amorphous silicon layer may be formed at a temperature ranging from approximately 480° C. to approximately 550° C. using silane (SiH 4 ) gas or disilane (Si 2 H 6 ) gas in a high-temperature low-pressure batch type furnace.
- an amorphous silicon layer, not doped with impurities may be formed using a single wafer type chamber, or an amorphous silicon layer, doped with impurities, may be formed using phosphine (PH 3 ) gas.
- the rate of charge storage and erasure of the memory device may be controlled by controlling the impurity doping concentration level.
- the amorphous silicon layer is crystallized and oxidized using an oxidation process.
- the amorphous silicon layer is crystallized to form a polysilicon layer and, at substantially the same time, oxidized to form an oxide layer.
- An upper portion is oxidized without oxidizing a bottom portion by controlling the oxidation process. As a result, a thin layer structure which includes the non-oxidized remaining polysilicon thin layer in the bottom portion and the oxide layer in the upper portion may be formed.
- the remaining polysilicon thin layer may be formed to a thickness ranging from approximately 10 ⁇ to approximately 30 ⁇ .
- the oxidation process of the amorphous silicon layer may be performed at a temperature ranging from approximately 700° C. to approximately 1,000° C. using a high-temperature low-pressure oxidation method. Also, the oxidation process may be performed using a wet, dry, or radical oxidation method.
- a wet etch process is performed to remove the oxide layer using the remaining polysilicon thin layer as an etch stop layer.
- the wet etch process may be performed using hydrogen fluoride (HF) or buffer oxide etchant (BOE), and thus, the remaining polysilicon thin layer may be formed to have a thickness ranging from approximately 10 ⁇ to approximately 30 ⁇ over the tunnel insulation layer 210 . Consequently, the charge trap polysilicon thin layer 220 A having a uniform thickness is formed.
- a charge trap nitride-based layer 220 B is formed over the charge trap polysilicon thin layer 220 A.
- a charge trap layer 220 including the charge trap polysilicon thin layer 220 A and the charge trap nitride-based layer 220 B is formed.
- the charge trap nitride-based layer 220 B may be formed using a low pressure chemical vapor deposition (LPCVD) method or a plasma enhanced chemical vapor deposition (PECVD) method at a temperature ranging from approximately 300° C. to approximately 650° C.
- LPCVD low pressure chemical vapor deposition
- PECVD plasma enhanced chemical vapor deposition
- the charge trap nitride-based layer 220 B may be formed to have a ratio of silicon (Si) to nitrogen (N) ranging approximately 1:1.30-1.36 and a thickness ranging from approximately 30 ⁇ to approximately 70 ⁇ .
- the process may be controlled in a manner that an interfacial oxide layer is not formed between the charge trap nitride-based layer 220 B and the charge trap polysilicon thin layer 220 A.
- the charge trap nitride-based layer 220 B may include a stack structure which includes a first nitride-based layer and a second nitride-based layer, wherein the second nitride-based layer has a different nitrogen ratio from that of the first nitride-based layer.
- the first nitride-based layer may be formed over charge trap polysilicon thin layer 220 A, and the second nitride-based layer having a higher nitrogen content than the first nitride-based layer may be formed over the first nitride-based layer.
- the second nitride-based layer may be formed to have a ratio of Si to N ranging approximately 1:1.33-2.0 and a thickness ranging from approximately 10 ⁇ to approximately 30 ⁇ .
- the charge trap type non-volatile memory device in accordance with one or more embodiments dispersedly stores charges in the charge trap polysilicon thin layer 220 A and the charge trap nitride-based layer 220 B as described above.
- the charge trap type non-volatile memory device may stably store and erase charges compared to a typical method.
- the rate of charge storage and erasure may be improved in the charge trap type non-volatile memory device in accordance with one or more embodiments.
- a charge barrier layer 230 is formed over the charge trap layer 220 .
- the charge barrier layer 230 is a type of barrier layer which is formed to prevent charges from passing through the charge trap layer 220 and moving upward.
- the charge barrier layer 230 may include a high-k dielectric layer formed to a thickness ranging from approximately 50 ⁇ to approximately 250 ⁇ , wherein k stands for a constant.
- the charge barrier layer 230 may include a stack structure which includes one of LaHfO, DyScO and HfAlO compounds and an aluminum oxide (Al 2 O 3 ) layer.
- the charge barrier layer 230 may be formed using an atomic layer deposition (ALD) method, chemical vapor deposition (CVD) method, or plasma vapor deposition (PVD) method.
- ALD atomic layer deposition
- CVD chemical vapor deposition
- PVD plasma vapor deposition
- a thermal treatment process is performed on the substrate structure to crystallize or induce phase change in the charge barrier layer 230 .
- the dielectric constant of the charge barrier layer 230 may be increased and the charge barrier layer 230 may be further densified.
- the thermal treatment process may be performed at a temperature ranging from approximately 800° C. to approximately 1,100° C. in a nitrogen (N 2 ) gas ambience or a mixture of N 2 gas and oxygen (O 2 ) gas ambience.
- a gate electrode conductive layer 240 is formed over the charge barrier layer 230 .
- the gate electrode conductive layer 240 may include a stack structure of metal and polysilicon.
- the gate electrode conductive layer 240 may be formed by forming a tantalum (Ta)-based or titanium (Ti)-based metal, e.g., titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide nitride (TaCN), oxidized tantalum carbonitride (TaCNO), Ti/TiN, Ti/TaN or tantalumcarbide (TaC), and a polysilicon layer doped with N-type impurities, e.g., phosphorus (P).
- the polysilicon layer may be doped at a concentration level ranging from approximately 3 ⁇ 10 20 atoms/cc to approximately 1 ⁇ 10 21 atoms/cc to form an N-type gate electrode.
- Tungsten silicide may be additionally formed over the polysilicon layer or a combination of tungsten (W) and tungsten nitride (WNx) may be additionally formed over the polysilicon layer to improve resistance of a subsequent gate electrode.
- a hard mask layer 250 is formed over the gate electrode conductive layer 240 .
- the hard mask layer 250 may include silicon oxynitride (SiON) or silicon nitride (SiN).
- a photoresist pattern (not shown) is formed over the hard mask layer 250 to form a gate electrode.
- the hard mask layer 250 and the gate electrode conductive layer 240 are etched using the photoresist pattern to form a hard mask pattern 250 A and a gate electrode 240 A.
- a spacer insulation layer 260 is formed over the substrate structure to prevent abnormal oxidation of the gate electrode 240 A during a subsequent oxidation process.
- the spacer insulation layer 260 may include a nitride-based layer formed to a thickness ranging from approximately 50 ⁇ to approximately 100 ⁇ using a CVD method.
- a spacer etch is performed on the spacer insulation layer 260 ( FIG. 2E ) to form a spacer 260 A over sidewalls of the hard mask pattern 250 A and the gate electrode 240 A.
- the charge barrier layer 230 , the charge trap layer 220 , and the tunnel insulation layer 210 are etched using the hard mask pattern 250 A and the spacer 260 A as an etch barrier to form a charge barrier pattern 230 A, a first charge trap pattern 220 ′, and an etched tunnel insulation layer 210 A.
- Reference denotations 220 AA and 220 BA represent a charge trap polysilicon thin pattern 220 AA and a charge trap nitride-based pattern 220 BA, respectively.
- a charge trap structure C is formed.
- the etch process is performed in a manner that the etched tunnel insulation layer 210 A remains with a thickness ranging from approximately 10 ⁇ to approximately 30 ⁇ . As a result, damage on the substrate 200 may be minimized and an undercut problem, where the tunnel insulation layer 210 around the charge trap structure C is excessively etched, may be prevented.
- an oxidation process is performed on the substrate structure to oxidize edge portions of the first charge trap pattern 220 ′ and form an oxide-based spacer 270 over the substrate structure.
- Reference denotation 220 ′′ represents a second charge trap pattern 220 ′′.
- the oxide-based spacer 270 is formed in a bird's beak shape as shown with reference denotation ‘D’.
- the oxide-based spacer 270 is formed in a manner to enclose sidewalls of the second charge trap pattern 220 ′′ and thus isolating the second charge trap pattern 220 ′′.
- Reference denotations 220 AB and 220 BB represent an oxidized charge trap polysilicon thin pattern 220 AB and an oxidized charge trap nitride-based pattern 220 BB, respectively.
- Formation of the bird's beak shape of the oxide-based spacer 270 may be achieved because the charge trap polysilicon thin pattern 220 AA is more easily oxidized than other layers. In other words, during the oxidation process, oxidation starts from edge portions of the charge trap polysilicon thin pattern 220 AA and forms the bird's beak shaped oxide-based spacer 270 developing into the charge trap polysilicon thin pattern 220 AA, thus forming the oxidized charge trap polysilicon thin pattern 220 AB.
- Reference denotation C′ represents an oxidized charge trap structure C′.
- the oxidation process may be performed using a radical oxidation method at a temperature ranging from approximately 700° C. to approximately 950° C. so that all layers including Si may be oxidized.
- the oxide-based spacer 270 may be formed to a thickness ranging from approximately 10 ⁇ to approximately 30 ⁇ . As a result, oxidation of the substrate 200 may be minimized, and changes in impurity concentration levels and the depths of source/drain regions may be minimized.
- an additional oxide-based layer may be formed using a CVD method after forming the oxide-based spacer 270 using the oxidation process.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
There is provided a charge trap type non-volatile memory device and a method for fabricating the same, the charge trap type non-volatile memory device including: a tunnel insulation layer formed over a substrate; a charge trap layer formed over the tunnel insulation layer, the charge trap layer including a charge trap polysilicon thin layer and a charge trap nitride-based layer; a charge barrier layer formed over the charge trap layer; a gate electrode formed over the charge barrier layer; and an oxide-based spacer formed over sidewalls of the charge trap layer and provided to isolate the charge trap layer.
Description
- The present application is a Divisional of patent application Ser. No. 13/448,046, filed on Apr. 16, 2012, which also is a Divisional of patent application Ser. No. 12/432,060, filed on Apr. 29, 2009, which claims priority from Korean patent application number 10-2008-0074139, filed on Jul. 29, 2008, and the disclosure of which is hereby incorporated by reference herein its entirety.
- The present disclosure relates to a semiconductor device and a method for fabricating the same, and more particularly, to a charge trap type non-volatile memory device and a method for fabricating the same.
- A non-volatile memory device refers to a memory device which can maintain stored data intact even when a power supply is cut off. In particular, a memory device which stores data by storing or erasing charges in a floating gate is referred to as a floating gate type non-volatile memory device.
- A typical floating gate type non-volatile memory device includes a tunnel insulation layer, a floating gate, a charge barrier layer, and a control gate formed over a substrate. A typical floating gate type non-volatile memory device stores data by injecting or emitting charges in the floating gate.
- However, there is a limitation as to achieving a large integration scale in a floating gate type non-volatile memory device because as the thickness of a tunnel insulation layer becomes greater, a higher operation voltage may be needed, causing its peripheral circuitry to become complicated.
- Therefore, a typical method presents a charge trap type non-volatile memory device as a type of non-volatile memory device. Herein, a charge trap type non-volatile memory device is described in detail with a drawing.
-
FIG. 1 illustrates a cross-sectional view of a typical charge trap type non-volatile memory device. The charge trap type non-volatile memory device includes atunnel insulation layer 110, acharge trap layer 120, acharge barrier layer 130, agate electrode 140, and ahard mask pattern 150 formed over asubstrate 100. - The
tunnel insulation layer 110 is formed as an energy barrier layer for charge tunneling. Thetunnel insulation layer 110 may include an oxide-based layer. - The
charge trap layer 120 stores charges which tunneled through thetunnel insulation layer 110. Thus, thecharge trap layer 120 substantially functions as a data storing unit. Thecharge trap layer 120 may include a nitride-based layer. - The
charge barrier layer 130 is formed to prevent charges from passing through thecharge trap layer 120 and moving upward. - At this time, nitride-based
spacers 160 are formed over sidewalls of thehard mask pattern 150 and thegate electrode 140 to prevent oxidation of thegate electrode 140 during a subsequent process. - Reference denotation ‘A’ represents a charge trap structure A which includes the
tunnel insulation layer 110, thecharge trap layer 120, thecharge barrier layer 130, thegate electrode 140, thehard mask pattern 150, and the nitride-basedspacers 160. An oxide-basedspacer 170 is formed over the charge trap structure A. - The typical charge trap type non-volatile memory device having the above described structure stores or erases charges in a deep level trap site in the
charge trap layer 120. Thus, the stored charges may not be lost even when thetunnel insulation layer 110 is formed to a small thickness. Also, the typical charge trap type non-volatile memory device may be operated at a low operation voltage. Furthermore, the integration scale of a semiconductor device may be improved compared to a floating gate type non-volatile memory device. - However, the typical charge trap type non-volatile memory device may have limitations as follows. For the
charge trap layer 120 including a nitride-based layer, there may be a large density difference in a trap site depending on the composition of silicon (Si) and nitrogen (N) of the nitride-based layer. Thus, charges stored in thecharge trap layer 120 may not be dispersed evenly. - In particular, storage and erasure of charges may not be performed smoothly because the trap site is concentrated on an interface between the
charge barrier layer 130 and thecharge trap layer 120 and the interface state is unstable. Such limitation may deteriorate data retention and endurance of the memory device. - Furthermore, sidewalls of the
tunnel insulation layer 110 and thecharge trap layer 120 are not protected by the nitride-basedspacers 160. Therefore, the sidewalls of thetunnel insulation layer 110 and thecharge trap layer 120 may be exposed and damaged during a subsequent process. - In the typical method, an oxidation process is performed on the substrate structure including the charge trap structure A to form the oxide-based
spacer 170. The oxide-basedspacer 170 is formed so that thetunnel insulation layer 110 and thecharge trap layer 120 may be reinforced and prevented from getting damaged. - However, there are limitations as to preventing damage by forming the oxide-based
spacer 170 on the sidewalls of the layers that constitute the charge trap structure A due to structural characteristics of the charge trap structure A configured in a multiple-layer stack structure. As a result, damage in thecharge trap layer 120 may induce loss of data stored in the memory device, i.e., charges, and thus, deteriorate data retention of the memory device. - On the other hand, if the oxidation process is performed for a longer period of time in order to sufficiently reinforce the damaged sidewalls, there may arise other limitations such as oxidation of the
substrate 100 or change in the impurity concentration level and depth in source/drain regions. - Furthermore, charges may be lost through a portion of the sidewall of the
charge trap layer 120, as represented with reference denotation ‘B’, because an interface between thecharge trap layer 120 and the oxide-basedspacer 170 is not stabilized even after the oxide-basedspacer 170 is formed over the sidewalls of thecharge trap layer 120. - One or more embodiments disclosed in the present application are directed to providing a memory device having a charge trap layer which includes a polysilicon thin layer and a nitride-based layer and a method for fabricating the same.
- In accordance with one or more embodiments, there is provided a charge trap type non-volatile memory device, including: a tunnel insulation layer formed over a substrate; a charge trap layer formed over the tunnel insulation layer, the charge trap layer including a charge trap polysilicon thin layer and a charge trap nitride-based layer; a charge barrier layer formed over the charge trap layer; a gate electrode formed over the charge barrier layer; and an oxide-based spacer formed over sidewalls of the charge trap layer and provided to isolate the charge trap layer.
- In accordance with one or more embodiments, there is provided a method for fabricating a charge trap type non-volatile memory device, including: forming a tunnel insulation layer over a substrate; forming a charge trap layer over the tunnel insulation layer, the charge trap layer including a charge trap polysilicon thin layer and a charge trap nitride-based layer; forming a charge barrier layer over the charge trap layer; forming a gate electrode conductive layer over the charge barrier layer; etching the gate electrode conductive layer, the charge barrier layer, the charge trap layer, and the tunnel insulation layer to form a charge trap structure; and forming an oxide-based spacer over sidewalls of the etched charge trap layer.
-
FIG. 1 illustrates a cross-sectional view of a typical charge trap type non-volatile memory device. -
FIGS. 2A to 2G show cross-sectional views illustrating a method of fabricating a charge trap type non-volatile memory device in accordance with one embodiment. - Other objects and advantages of the present disclosure can be understood by the following description, and will become apparent with reference to one or more embodiments.
- One or more embodiments of the present disclosure relate to a charge trap type non-volatile memory device which includes a charge trap layer having a polysilicon thin layer and a nitride-based layer. The charge trap type non-volatile memory device may improve the operation rate of charge storage and erasure by dispersedly storing charges in the polysilicon thin layer and the nitride-based layer. Furthermore, the charge trap type non-volatile memory device may prevent loss of charges by effectively isolating the charge trap layer using an oxide-based layer formed to enclose sidewalls of the charge trap layer. Therefore, data retention and reliability of the memory device may be enhanced.
- Hereafter, one or more of various embodiments of the present disclosure will be described in detail. Regarding the drawings, the illustrated thickness and spacing distance may be exaggerated for convenience. In the description of the present invention, any portions irrelevant to the substance of the present disclosure may be omitted. Furthermore, the same or like reference numerals through out the various embodiments of the present invention represent the same or like elements in different drawings. It will be understood that when a layer is referred to as being “on/under” another layer or substrate, it can be directly on/under the other layer or substrate, or intervening layers may also be present. In addition, when a layer is referred to as being ‘between’ two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
-
FIGS. 2A to 2G show cross-sectional views illustrating a method of fabricating a charge trap type non-volatile memory device in accordance with one embodiment. - Referring to
FIG. 2A , atunnel insulation layer 210 is formed over asubstrate 200. Thetunnel insulation layer 210 is formed as an energy barrier layer for charge tunneling. Thetunnel insulation layer 210 may include an oxide-based layer formed by a radical oxidation process. - The radical oxidation process may be performed at a temperature ranging from approximately 750° C. to approximately 950° C. The occurrence of undesirable formation in the
tunnel insulation layer 210 may be minimized by including nitrogen during the oxidation process. For instance, thetunnel insulation layer 210 may be formed to a thickness ranging from approximately 40 Å to approximately 60 Å. Also, an annealing process may be performed using nitrous oxide (N2O) gas or nitrogen oxide (NO) gas. - A charge trap polysilicon
thin layer 220A is formed over thetunnel insulation layer 210. For instance, the charge trap polysiliconthin layer 220A may be formed to a thickness ranging from approximately 10 Å to approximately 30 Å. However, if it is difficult to form the charge trap polysiliconthin layer 220A to the above described thickness due to limitations arising during the process, the charge trap polysiliconthin layer 220A may be formed using the process shown below. - An amorphous silicon layer is formed to a certain thickness over the
tunnel insulation layer 210. For instance, the amorphous silicon layer may be formed to a thickness ranging from approximately 50 Å to approximately 100 Å. - The amorphous silicon layer may be formed at a temperature ranging from approximately 480° C. to approximately 550° C. using silane (SiH4) gas or disilane (Si2H6) gas in a high-temperature low-pressure batch type furnace.
- Otherwise, an amorphous silicon layer, not doped with impurities, may be formed using a single wafer type chamber, or an amorphous silicon layer, doped with impurities, may be formed using phosphine (PH3) gas. At this time, the rate of charge storage and erasure of the memory device may be controlled by controlling the impurity doping concentration level.
- The amorphous silicon layer is crystallized and oxidized using an oxidation process. The amorphous silicon layer is crystallized to form a polysilicon layer and, at substantially the same time, oxidized to form an oxide layer. An upper portion is oxidized without oxidizing a bottom portion by controlling the oxidation process. As a result, a thin layer structure which includes the non-oxidized remaining polysilicon thin layer in the bottom portion and the oxide layer in the upper portion may be formed.
- Therefore, it may be possible to form an oxide layer having a uniform thickness by performing an oxidation process to crystallize and form the oxide layer at substantially the same time, and thus forming a remaining polysilicon thin layer with a uniform thickness. For instance, the remaining polysilicon thin layer may be formed to a thickness ranging from approximately 10 Å to approximately 30 Å.
- The oxidation process of the amorphous silicon layer may be performed at a temperature ranging from approximately 700° C. to approximately 1,000° C. using a high-temperature low-pressure oxidation method. Also, the oxidation process may be performed using a wet, dry, or radical oxidation method.
- A wet etch process is performed to remove the oxide layer using the remaining polysilicon thin layer as an etch stop layer. For instance, the wet etch process may be performed using hydrogen fluoride (HF) or buffer oxide etchant (BOE), and thus, the remaining polysilicon thin layer may be formed to have a thickness ranging from approximately 10 Å to approximately 30 Å over the
tunnel insulation layer 210. Consequently, the charge trap polysiliconthin layer 220A having a uniform thickness is formed. - Referring to
FIG. 2B , a charge trap nitride-basedlayer 220B is formed over the charge trap polysiliconthin layer 220A. Thus, acharge trap layer 220 including the charge trap polysiliconthin layer 220A and the charge trap nitride-basedlayer 220B is formed. - For instance, the charge trap nitride-based
layer 220B may be formed using a low pressure chemical vapor deposition (LPCVD) method or a plasma enhanced chemical vapor deposition (PECVD) method at a temperature ranging from approximately 300° C. to approximately 650° C. - At this time, the charge trap nitride-based
layer 220B may be formed to have a ratio of silicon (Si) to nitrogen (N) ranging approximately 1:1.30-1.36 and a thickness ranging from approximately 30 Å to approximately 70 Å. At this time, the process may be controlled in a manner that an interfacial oxide layer is not formed between the charge trap nitride-basedlayer 220B and the charge trap polysiliconthin layer 220A. - Furthermore, the charge trap nitride-based
layer 220B may include a stack structure which includes a first nitride-based layer and a second nitride-based layer, wherein the second nitride-based layer has a different nitrogen ratio from that of the first nitride-based layer. For instance, the first nitride-based layer may be formed over charge trap polysiliconthin layer 220A, and the second nitride-based layer having a higher nitrogen content than the first nitride-based layer may be formed over the first nitride-based layer. As a result, charges stored in thecharge trap layer 220 may be prevented from leaking out and thus the functions of a subsequent charge barrier layer may be supplemented. For instance, the second nitride-based layer may be formed to have a ratio of Si to N ranging approximately 1:1.33-2.0 and a thickness ranging from approximately 10 Å to approximately 30 Å. - The charge trap type non-volatile memory device in accordance with one or more embodiments dispersedly stores charges in the charge trap polysilicon
thin layer 220A and the charge trap nitride-basedlayer 220B as described above. As a result, the charge trap type non-volatile memory device may stably store and erase charges compared to a typical method. Furthermore, the rate of charge storage and erasure may be improved in the charge trap type non-volatile memory device in accordance with one or more embodiments. - Referring to
FIG. 2C , acharge barrier layer 230 is formed over thecharge trap layer 220. Thecharge barrier layer 230 is a type of barrier layer which is formed to prevent charges from passing through thecharge trap layer 220 and moving upward. For instance, thecharge barrier layer 230 may include a high-k dielectric layer formed to a thickness ranging from approximately 50 Å to approximately 250 Å, wherein k stands for a constant. - In particular, the
charge barrier layer 230 may include a stack structure which includes one of LaHfO, DyScO and HfAlO compounds and an aluminum oxide (Al2O3) layer. Also, thecharge barrier layer 230 may be formed using an atomic layer deposition (ALD) method, chemical vapor deposition (CVD) method, or plasma vapor deposition (PVD) method. - A thermal treatment process is performed on the substrate structure to crystallize or induce phase change in the
charge barrier layer 230. As a result, the dielectric constant of thecharge barrier layer 230 may be increased and thecharge barrier layer 230 may be further densified. The thermal treatment process may be performed at a temperature ranging from approximately 800° C. to approximately 1,100° C. in a nitrogen (N2) gas ambience or a mixture of N2 gas and oxygen (O2) gas ambience. - A gate electrode
conductive layer 240 is formed over thecharge barrier layer 230. For instance, the gate electrodeconductive layer 240 may include a stack structure of metal and polysilicon. In particular, the gate electrodeconductive layer 240 may be formed by forming a tantalum (Ta)-based or titanium (Ti)-based metal, e.g., titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide nitride (TaCN), oxidized tantalum carbonitride (TaCNO), Ti/TiN, Ti/TaN or tantalumcarbide (TaC), and a polysilicon layer doped with N-type impurities, e.g., phosphorus (P). For instance, the polysilicon layer may be doped at a concentration level ranging from approximately 3×1020 atoms/cc to approximately 1×1021 atoms/cc to form an N-type gate electrode. - Tungsten silicide (WSix) may be additionally formed over the polysilicon layer or a combination of tungsten (W) and tungsten nitride (WNx) may be additionally formed over the polysilicon layer to improve resistance of a subsequent gate electrode.
- A
hard mask layer 250 is formed over the gate electrodeconductive layer 240. For instance, thehard mask layer 250 may include silicon oxynitride (SiON) or silicon nitride (SiN). - Referring to
FIG. 2D , a photoresist pattern (not shown) is formed over thehard mask layer 250 to form a gate electrode. Thehard mask layer 250 and the gate electrodeconductive layer 240 are etched using the photoresist pattern to form ahard mask pattern 250A and agate electrode 240A. - Referring to
FIG. 2E , aspacer insulation layer 260 is formed over the substrate structure to prevent abnormal oxidation of thegate electrode 240A during a subsequent oxidation process. For instance, thespacer insulation layer 260 may include a nitride-based layer formed to a thickness ranging from approximately 50 Å to approximately 100 Å using a CVD method. - Referring to
FIG. 2F , a spacer etch is performed on the spacer insulation layer 260 (FIG. 2E ) to form aspacer 260A over sidewalls of thehard mask pattern 250A and thegate electrode 240A. Thecharge barrier layer 230, thecharge trap layer 220, and thetunnel insulation layer 210 are etched using thehard mask pattern 250A and thespacer 260A as an etch barrier to form acharge barrier pattern 230A, a firstcharge trap pattern 220′, and an etchedtunnel insulation layer 210A. Reference denotations 220AA and 220BA represent a charge trap polysilicon thin pattern 220AA and a charge trap nitride-based pattern 220BA, respectively. Thus, a charge trap structure C is formed. - The etch process is performed in a manner that the etched
tunnel insulation layer 210A remains with a thickness ranging from approximately 10 Å to approximately 30 Å. As a result, damage on thesubstrate 200 may be minimized and an undercut problem, where thetunnel insulation layer 210 around the charge trap structure C is excessively etched, may be prevented. - Referring to
FIG. 2G , an oxidation process is performed on the substrate structure to oxidize edge portions of the firstcharge trap pattern 220′ and form an oxide-basedspacer 270 over the substrate structure.Reference denotation 220″ represents a secondcharge trap pattern 220″. - The oxide-based
spacer 270 is formed in a bird's beak shape as shown with reference denotation ‘D’. The oxide-basedspacer 270 is formed in a manner to enclose sidewalls of the secondcharge trap pattern 220″ and thus isolating the secondcharge trap pattern 220″. Reference denotations 220AB and 220BB represent an oxidized charge trap polysilicon thin pattern 220AB and an oxidized charge trap nitride-based pattern 220BB, respectively. - Formation of the bird's beak shape of the oxide-based
spacer 270 may be achieved because the charge trap polysilicon thin pattern 220AA is more easily oxidized than other layers. In other words, during the oxidation process, oxidation starts from edge portions of the charge trap polysilicon thin pattern 220AA and forms the bird's beak shaped oxide-basedspacer 270 developing into the charge trap polysilicon thin pattern 220AA, thus forming the oxidized charge trap polysilicon thin pattern 220AB. - In particular, the oxide-based
spacer 270 formed over edge portions of the oxidized charge trap polysilicon thin pattern 220AB accelerates oxidation of sidewalls of the charge trap nitride-based pattern 220BA to form the oxidized charge trap nitride-based pattern 220BB. - Therefore, the thickness of the oxide-based
spacer 270 enclosing the sidewalls of the secondcharge trap pattern 220″ becomes greater than that of the typical method. Consequently, loss of stored charges may be prevented by substantially isolating the secondcharge trap pattern 220″. Reference denotation C′ represents an oxidized charge trap structure C′. - For instance, the oxidation process may be performed using a radical oxidation method at a temperature ranging from approximately 700° C. to approximately 950° C. so that all layers including Si may be oxidized. Also, the oxide-based
spacer 270 may be formed to a thickness ranging from approximately 10 Å to approximately 30 Å. As a result, oxidation of thesubstrate 200 may be minimized, and changes in impurity concentration levels and the depths of source/drain regions may be minimized. - Although not illustrated, an additional oxide-based layer may be formed using a CVD method after forming the oxide-based
spacer 270 using the oxidation process. - While one or more embodiments have been described, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope defined in the following claims.
Claims (5)
1. A method of fabricating a charge trap type non-volatile memory device, comprising:
forming a tunnel insulation layer over a substrate;
forming a charge trap layer over the tunnel insulation layer, the charge trap layer including a charge trap polysilicon thin layer and a charge trap nitride-based layer;
forming a charge barrier layer over the charge trap layer;
forming a gate electrode conductive layer over the charge barrier layer;
etching the gate electrode conductive layer, the charge barrier layer, the charge trap layer, and the tunnel insulation layer to form a charge trap structure; and
forming an oxide-based spacer over sidewalls of the etched charge trap layer, wherein forming the charge trap structure comprises:
etching the gate electrode conductive layer to form a gate electrode;
forming a nitride-based spacer over sidewalls of the gate electrode;
etching the charge barrier layer, the charge trap layer, and the tunnel insulation layer using the nitride-based spacer, wherein the tunnel insulation layer is partially etched so that the substrate is not exposed; and
performing an oxidation process over the substrate structure to form an oxide-based spacer over sidewalls of the etched charge trap layer.
2. The method of claim 1 , wherein the performing the oxidation process comprises using a radical oxidation method.
3. The method of claim 1 , wherein forming the charge trap polysilicon thin layer comprises:
forming an amorphous silicon layer over the tunnel insulation layer;
crystallizing and oxidizing the amorphous silicon layer using an oxidation process; and
removing an oxide-based layer formed after performing the oxidation process to form the charge trap polysilicon thin layer having a uniform thickness.
4. The method of claim 3 , wherein the oxidizing the amorphous silicon layer comprises performing one of a wet oxidation method, a dry oxidation method, and a radical oxidation method.
5. The method of claim 1 , wherein forming the charge trap nitride-based layer comprises:
forming a first nitride-based layer over the charge trap polysilicon thin layer; and
forming a second nitride-based layer over the first nitride-based layer, the second nitride-based layer having a higher nitrogen content than the first nitride-based layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/682,276 US20130078794A1 (en) | 2008-07-29 | 2012-11-20 | Charge trap type non-volatile memory device and method for fabricating the same |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2008-0074139 | 2008-07-29 | ||
KR1020080074139A KR101060618B1 (en) | 2008-07-29 | 2008-07-29 | Charge trap type nonvolatile memory device and manufacturing method thereof |
US12/432,060 US8178918B2 (en) | 2008-07-29 | 2009-04-29 | Charge trap type non-volatile memory device and method for fabricating the same |
US13/448,046 US8426280B2 (en) | 2008-07-29 | 2012-04-16 | Charge trap type non-volatile memory device and method for fabricating the same |
US13/682,276 US20130078794A1 (en) | 2008-07-29 | 2012-11-20 | Charge trap type non-volatile memory device and method for fabricating the same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/448,046 Division US8426280B2 (en) | 2008-07-29 | 2012-04-16 | Charge trap type non-volatile memory device and method for fabricating the same |
Publications (1)
Publication Number | Publication Date |
---|---|
US20130078794A1 true US20130078794A1 (en) | 2013-03-28 |
Family
ID=41607436
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/432,060 Active 2029-11-24 US8178918B2 (en) | 2008-07-29 | 2009-04-29 | Charge trap type non-volatile memory device and method for fabricating the same |
US13/448,046 Active US8426280B2 (en) | 2008-07-29 | 2012-04-16 | Charge trap type non-volatile memory device and method for fabricating the same |
US13/682,276 Abandoned US20130078794A1 (en) | 2008-07-29 | 2012-11-20 | Charge trap type non-volatile memory device and method for fabricating the same |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/432,060 Active 2029-11-24 US8178918B2 (en) | 2008-07-29 | 2009-04-29 | Charge trap type non-volatile memory device and method for fabricating the same |
US13/448,046 Active US8426280B2 (en) | 2008-07-29 | 2012-04-16 | Charge trap type non-volatile memory device and method for fabricating the same |
Country Status (2)
Country | Link |
---|---|
US (3) | US8178918B2 (en) |
KR (1) | KR101060618B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8803223B2 (en) * | 2012-09-11 | 2014-08-12 | Macronix International Co., Ltd. | SONOS device and method for fabricating the same |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7915126B2 (en) * | 2007-02-14 | 2011-03-29 | Micron Technology, Inc. | Methods of forming non-volatile memory cells, and methods of forming NAND cell unit string gates |
KR101486745B1 (en) * | 2008-11-05 | 2015-02-06 | 삼성전자주식회사 | Nonvolatile memory device without gate spacer and method for manufacturing the same |
TW201123304A (en) * | 2009-12-21 | 2011-07-01 | Univ Nat Taiwan Science Tech | Semiconductor device and damascene structure |
US8951896B2 (en) | 2013-06-28 | 2015-02-10 | International Business Machines Corporation | High linearity SOI wafer for low-distortion circuit applications |
US10365936B2 (en) * | 2014-02-27 | 2019-07-30 | Red Hat Israel, Ltd. | Idle processor management by guest in virtualized systems |
KR102263315B1 (en) * | 2014-08-06 | 2021-06-15 | 삼성전자주식회사 | Semiconductor device and manufacturing method of semiconductor device |
KR101601101B1 (en) * | 2014-10-27 | 2016-03-08 | 서강대학교산학협력단 | A memory device using charge trap and manufacturing method thereof |
KR102629466B1 (en) * | 2016-09-21 | 2024-01-26 | 에스케이하이닉스 주식회사 | Manufacturing method of semiconductor device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040004243A1 (en) * | 2002-07-03 | 2004-01-08 | Rudeck Paul J. | Programmable memory devices comprising tungsten |
US20040171236A1 (en) * | 2002-08-23 | 2004-09-02 | Toppoly Electronics Corp. | Method for reducing surface roughness of polysilicon films for liquid crystal displays |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100695423B1 (en) | 2005-06-14 | 2007-03-15 | 주식회사 하이닉스반도체 | Semiconductor device and method for fabrication of the same |
KR100791333B1 (en) * | 2006-01-17 | 2008-01-07 | 삼성전자주식회사 | Method for fabricating nonvolatible memory device and nonvolatible memory device fabricated thereby |
KR100827201B1 (en) | 2006-09-29 | 2008-05-02 | 주식회사 하이닉스반도체 | Non-volatile memory device and fabrication method thereof |
KR100807220B1 (en) | 2007-02-01 | 2008-02-28 | 삼성전자주식회사 | Method of manufacturing non-volatile memory device |
US8809932B2 (en) * | 2007-03-26 | 2014-08-19 | Samsung Electronics Co., Ltd. | Semiconductor memory device, method of fabricating the same, and devices employing the semiconductor memory device |
-
2008
- 2008-07-29 KR KR1020080074139A patent/KR101060618B1/en not_active IP Right Cessation
-
2009
- 2009-04-29 US US12/432,060 patent/US8178918B2/en active Active
-
2012
- 2012-04-16 US US13/448,046 patent/US8426280B2/en active Active
- 2012-11-20 US US13/682,276 patent/US20130078794A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040004243A1 (en) * | 2002-07-03 | 2004-01-08 | Rudeck Paul J. | Programmable memory devices comprising tungsten |
US20040171236A1 (en) * | 2002-08-23 | 2004-09-02 | Toppoly Electronics Corp. | Method for reducing surface roughness of polysilicon films for liquid crystal displays |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8803223B2 (en) * | 2012-09-11 | 2014-08-12 | Macronix International Co., Ltd. | SONOS device and method for fabricating the same |
US9384989B2 (en) | 2012-09-11 | 2016-07-05 | Macronix International Co., Ltd. | Sonos device and method for fabricating the same |
Also Published As
Publication number | Publication date |
---|---|
US8178918B2 (en) | 2012-05-15 |
US8426280B2 (en) | 2013-04-23 |
KR101060618B1 (en) | 2011-08-31 |
US20120202329A1 (en) | 2012-08-09 |
US20100025752A1 (en) | 2010-02-04 |
KR20100012632A (en) | 2010-02-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8426280B2 (en) | Charge trap type non-volatile memory device and method for fabricating the same | |
US9991112B2 (en) | Method for forming dielectric film and method for fabricating semiconductor device | |
US20080272424A1 (en) | Nonvolatile Memory Device Having Fast Erase Speed And Improved Retention Characteristics And Method For Fabricating The Same | |
US7981786B2 (en) | Method of fabricating non-volatile memory device having charge trapping layer | |
US9018708B2 (en) | Semiconductor device and method for fabricating the same | |
JP5425378B2 (en) | Manufacturing method of semiconductor device | |
KR20080036679A (en) | Method of forming a non-volatile memory device | |
US9514946B2 (en) | Semiconductor memory incorporating insulating layers of progressively decreasing band gaps and method of manufacturing the same | |
US20220278214A1 (en) | Semiconductor devices with liners and related methods | |
US11935926B2 (en) | Semiconductor device and method for fabricating the same | |
US11557594B2 (en) | Method of manufacturing semiconductor device having buried word line | |
US20090140322A1 (en) | Semiconductor Memory Device and Method of Manufacturing the Same | |
KR100757323B1 (en) | Charge trap type non volatile memory device and method of manufacturing the same | |
US7824992B2 (en) | Method of fabricating non-volatile memory device | |
US20020001932A1 (en) | Method for forming a gate for semiconductor devices | |
KR20080015554A (en) | Method of manufacturing a non-volatile memory device | |
US11056576B1 (en) | Method of manufacturing semiconductor device | |
US7306993B2 (en) | Method for fabricating semiconductor device with recessed channel | |
KR100885797B1 (en) | Nonvolatile memory device and method of manufacturing nonvolatile memory device | |
JP2010027967A (en) | Method for manufacturing non-volatile semiconductor storage device | |
US20100163963A1 (en) | Nonvolatile memory device and method of fabricating the same | |
KR20080077769A (en) | Method for fabricating flash memory device | |
JP2008098420A (en) | Semiconductor memory and its manufacturing method | |
KR20100041426A (en) | Method of manufacturing a semiconductor device | |
JP2008108848A (en) | Semiconductor memory device and its manufacturing method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:DONG, CHA-DEOK;REEL/FRAME:029331/0820 Effective date: 20090409 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO PAY ISSUE FEE |