US20130015452A1 - Array substrate and method for manufacturing the array substrate - Google Patents
Array substrate and method for manufacturing the array substrate Download PDFInfo
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- US20130015452A1 US20130015452A1 US13/616,150 US201213616150A US2013015452A1 US 20130015452 A1 US20130015452 A1 US 20130015452A1 US 201213616150 A US201213616150 A US 201213616150A US 2013015452 A1 US2013015452 A1 US 2013015452A1
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- 239000000758 substrate Substances 0.000 title claims abstract description 108
- 238000000034 method Methods 0.000 title description 48
- 238000004519 manufacturing process Methods 0.000 title description 39
- 238000009413 insulation Methods 0.000 claims abstract description 52
- 239000004065 semiconductor Substances 0.000 claims abstract description 34
- 239000010409 thin film Substances 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 description 90
- 239000002184 metal Substances 0.000 description 90
- 238000005530 etching Methods 0.000 description 81
- 239000007789 gas Substances 0.000 description 73
- 229910018503 SF6 Inorganic materials 0.000 description 52
- 230000008569 process Effects 0.000 description 34
- 238000001312 dry etching Methods 0.000 description 30
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 29
- 229960000909 sulfur hexafluoride Drugs 0.000 description 29
- 239000000203 mixture Substances 0.000 description 27
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 23
- WRQGPGZATPOHHX-UHFFFAOYSA-N ethyl 2-oxohexanoate Chemical compound CCCCC(=O)C(=O)OCC WRQGPGZATPOHHX-UHFFFAOYSA-N 0.000 description 23
- 229920002120 photoresistant polymer Polymers 0.000 description 22
- 239000000460 chlorine Substances 0.000 description 18
- 229910052801 chlorine Inorganic materials 0.000 description 18
- 238000000926 separation method Methods 0.000 description 18
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 15
- 239000001307 helium Substances 0.000 description 15
- 229910052734 helium Inorganic materials 0.000 description 15
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 15
- 239000010936 titanium Substances 0.000 description 14
- 238000002161 passivation Methods 0.000 description 13
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 12
- 239000010949 copper Substances 0.000 description 12
- 229910052719 titanium Inorganic materials 0.000 description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 11
- 238000000151 deposition Methods 0.000 description 11
- 239000001301 oxygen Substances 0.000 description 11
- 229910052760 oxygen Inorganic materials 0.000 description 11
- 238000001039 wet etching Methods 0.000 description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 10
- 238000004140 cleaning Methods 0.000 description 10
- 229910052802 copper Inorganic materials 0.000 description 10
- 230000008021 deposition Effects 0.000 description 10
- 239000000463 material Substances 0.000 description 10
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 9
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 8
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 8
- -1 SiNx Chemical compound 0.000 description 7
- 239000007788 liquid Substances 0.000 description 7
- 150000001875 compounds Chemical class 0.000 description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 5
- 239000011651 chromium Substances 0.000 description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 229910052779 Neodymium Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- XROWMBWRMNHXMF-UHFFFAOYSA-J titanium tetrafluoride Chemical compound [F-].[F-].[F-].[F-].[Ti+4] XROWMBWRMNHXMF-UHFFFAOYSA-J 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000003252 repetitive effect Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
An array substrate including: a gate electrode and a gate insulation layer disposed on a base substrate, the gate insulation layer having a first thickness in a first region and a second thickness in a second region, the first thickness being greater than the second thickness; a semiconductor pattern disposed on the gate insulation layer in the first region, an end portion of the semiconductor pattern having a stepped portion with respect to the gate insulation layer; an ohmic contact pattern disposed on the semiconductor pattern, an end portion of the ohmic contact pattern opposite to a channel portion being aligned with the end portion of the semiconductor pattern; and source and drain electrodes disposed on the ohmic contact pattern, the source and drain electrodes spaced apart from each other and including first and second thin-film transistor patterns.
Description
- This application is a divisional of U.S. patent application Ser. No. 12/777,347, filed on May 11, 2010, which claims priority to Korean Patent Application No. 2009-0050842, filed on Jun. 9, 2009, and all the benefits accruing therefrom under 35 U.S.C. §119, the content of which in its entirety is herein incorporated by reference.
- 1. Field of the Invention
- Exemplary embodiments relate to an array substrate and a method for manufacturing the array substrate. More particularly, exemplary embodiments relate to an array substrate for a liquid crystal display (“LCD”) device and a method for manufacturing the array substrate.
- 2. Description of the Related Art
- Generally, a LCD device includes an array substrate on which switching elements are formed to operate each pixel area, an opposite substrate facing the array substrate and a liquid crystal layer disposed between the array substrate and the opposite substrate. The LCD panel applies a voltage to the liquid crystal layer and controls the transmissivity of light from a backlight assembly, which is typically disposed under the opposite substrate, to display an image.
- The array substrate includes a thin-film transistor (“TFT”), which functions as the switching element, and is manufactured using patterns formed in a plurality of photolithographic processes. Generally, a specific mask is used in each photolithographic process, thus numerous masks may be used. However, a four-mask process using four masks has been recently used for manufacturing the array substrate. Because the process uses only four masks, the process is simpler and has lower costs than processes that use a larger number of masks. In the four-mask process, first a metal layer for a data line is etched in a first etching process to form a data line, then the metal layer for the data line and a channel layer formed under the metal layer for the data line are etched in a second etching process to form a source electrode, a drain electrode and a channel portion. The first etching process is a wet etching process and the second etching process includes wet and dry etching processes.
- In order to manufacture a large, high resolution LCD device, copper, which has low resistivity, is used for the metal layer for a gate line and/or the metal layer for the data line. In addition, titanium and copper are used at the same time to decrease the resistance of the line.
- However, pure titanium easily oxidizes to form a surface oxide layer that is substantially inert to etching gases. Thus a metal layer including titanium is not reactive with and thus not readily etched by an etching gas. Accordingly, the dry etching process may be difficult to perform on a metal layer including titanium.
- Exemplary embodiments provide an array substrate capable of improving the reliability of a manufacturing process in a dry etching process.
- Exemplary embodiments provide a method for manufacturing the array substrate.
- In an array substrate according to an embodiment, an array substrate includes a gate electrode disposed on a base substrate; a gate insulation layer disposed on the base substrate on which the gate electrode is disposed, the gate insulation layer having a first thickness in a first region and a second thickness in a second region; the first thickness is being greater than the second thickness; a semiconductor pattern disposed on the gate insulation layer in the first region; an end portion of the semiconductor pattern having a stepped portion with respect to the gate insulation layer; an ohmic contact pattern disposed on the semiconductor pattern, an end portion of the ohmic contact pattern opposite to a channel portion being aligned with the end portion of the semiconductor pattern; and source and drain electrodes disposed on the ohmic contact pattern, the source and drain electrodes spaced apart from each other and including first and second thin film transistor (“TFT”) patterns, wherein an end portions of the first and second thin film transistor patterns have a stepped portion with respect to each other.
- The array substrate may include a gate line disposed on the base substrate; a data line disposed on the base substrate on which the gate line is disposed, wherein a first line pattern and a data line pattern form a stepped portion with respect to each other and the first line pattern and the data line pattern cross the gate line; and a pixel electrode electrically contacts the drain electrode.
- An end portion of the second TFT pattern may be aligned with an end portion of the ohmic contact pattern, and the end portion of the second TFT pattern and an end portion of the first TFT pattern may have a stepped portion with respect to each other.
- A first distance between portions of the second TFT pattern corresponding to the source and drain electrodes may be greater than a second distance between portions of the first TFT pattern corresponding to the source and drain electrodes.
- A method for manufacturing an array substrate according to an embodiment includes, sequentially disposing first and second metal layers on a base substrate, on which a gate line, a gate electrode and a channel layer are disposed; sequentially etching the second and first metal layers to form a metal line pattern, the metal line pattern including first and second line patterns and a first electrode pattern, the first electrode pattern including first and second element patterns; partially etching the second element pattern to form a second electrode pattern, the second electrode pattern including the first element pattern and a partially etched second element pattern; partially etching the second line pattern to form a data line, the data line including the first line pattern and a partially etched second line pattern; converting an oxide layer to a fluoride layer by contacting the oxide layer with a reactive gas, the reactive gas including a fluoride containing compound, the oxide layer being naturally formed on the first element pattern when forming the second electrode pattern; etching the fluoride layer and an exposed portion of the first element pattern to form a source electrode electrically connected to the data line and a drain electrode spaced apart from the source electrode; and disposing a pixel electrode, the pixel electrode electrically contacting the drain electrode.
- The first metal layer may include titanium, and the second metal layer may include copper.
- The width of the first element pattern may be greater than a width of the partially etched second element pattern. A distance between the source and drain electrodes of the etched first element pattern may be about 2 micrometers to about 3 micrometers.
- The reactive gas may include at least one gas selected from a group consisting of carbon tetrafluoride, sulfur hexafluoride, a mixture of sulfur hexafluoride and helium, a mixture of sulfur hexafluoride and nitrogen, a mixture of sulfur hexafluoride and oxygen and a mixture of sulfur hexafluoride, oxygen and helium.
- The first and second electrode patterns and the data line may be formed via wet etching, and the source and drain electrodes may be formed via dry etching.
- An embodiment of a method for manufacturing an array substrate may include disposing a gate insulation layer on the base substrate on which the gate line and the gate electrode are formed are disposed, and disposing a photoresist layer on the second metal layer.
- Forming the first electrode pattern may further include forming an exposed area through the photoresist layer using a mask to form a source photo pattern; and etching the first and second element patterns in a region exposed by the source photo pattern to form the first electrode pattern having a width, which is less than a width of the source photo pattern.
- A method for manufacturing an array substrate according to an embodiment includes, etching the channel layer to form a sub-channel pattern having a width, which is substantially the same as a width of the source photo pattern; and removing the source photo pattern to form a remaining photo pattern, wherein an end portion of the remaining photo pattern being is aligned with an end portion of the first electrode pattern, and the remaining photo pattern has a separate portion corresponding to a separation region between the source and drain electrodes.
- Forming the source and drain electrodes may further include etching the first element pattern using the remaining photo pattern as a mask to form the source and drain electrodes, wherein a separation distance between portions of the first element pattern after the etching is less than a separation distance between portions of the second element pattern after the etching, etching the sub-channel pattern using the remaining photo pattern as a mask to form a channel pattern including a channel portion, and etching the gate insulation layer in a region exposed by the remaining photo pattern and the sub-channel pattern to form an etched gate insulation layer.
- Etched portions of the etched gate insulation layer may have a stepped portion with respect to each other.
- The source and drain electrodes and the channel pattern may be formed at the same time, an etching gas may include chlorine and fluorine, and an etching component may include chloride ions.
- A reaction rate of the sub-channel pattern and an etching gas and a reaction rate of the gate insulation layer and the etching gas may be greater than a reaction rate of the first element pattern and the etching gas.
- An etching gas may include metal and channel etching gases, the metal etching gas etching the first element pattern and includes chlorine, the channel etching gas etching the sub-channel pattern and including chlorine and fluorine, an etching component of the etching gas may include chloride ions.
- The chloride ions of the metal etching gas may etch the sub-channel pattern, and a reaction rate of the sub-channel pattern and the metal etching gas may be greater than a reaction rate of the first element pattern and the metal etching gas.
- A reaction rate of the gate insulation layer and the etching gas may be greater than a reaction rate of the first element pattern and the etching gas.
- According to some exemplary embodiments, a dry etching process is conducted normally since an oxide layer of the first element pattern may be converted to a fluoride layer, which may be easily vaporized. Accordingly, the reliability of the manufacturing process may be improved.
- The above and other features, aspects and advantages of this disclosure will become more apparent by describing in further detail exemplary embodiments thereof with reference to the accompanying drawings, in which:
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FIG. 1 is a top plan view illustrating an exemplary embodiment of an array substrate; -
FIG. 2 is a cross-sectional view taken along line I-I′ ofFIG. 1 ; -
FIG. 3 is a cross-sectional view illustrating an exemplary embodiment of a method of manufacturing a gate pattern of the array substrate ofFIG. 2 ; -
FIGS. 4 to 10 are cross-sectional views illustrating an exemplary embodiment of a method of manufacturing a source pattern and a channel portion of the array substrate ofFIG. 2 ; -
FIG. 11 is a cross-sectional view illustrating an exemplary embodiment of a method of manufacturing a passivation layer of the array substrate ofFIG. 2 ; -
FIG. 12 is an enlarged cross-sectional view illustrating a channel portion ofFIG. 2 ; -
FIG. 13 is an enlarged cross-sectional view illustrating a portion ‘A’ ofFIG. 2 ; -
FIG. 14 is a top plan view illustrating an exemplary embodiment of an apparatus for manufacturing the array substrate ofFIG. 2 ; -
FIG. 15 is a cross-sectional view illustrating an exemplary embodiment of a dry etching chamber ofFIG. 14 ; -
FIG. 16 is a cross-sectional view illustrating another exemplary embodiment of a method of manufacturing a source pattern of the array substrate; and -
FIG. 17 is a cross-sectional view illustrating an exemplary embodiment of a method of manufacturing a channel portion of the array substrate ofFIG. 16 . - The present invention is described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the present invention are shown. The present invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Like reference numerals refer to like elements throughout. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.
- It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
- It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
- Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
- The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
- Exemplary embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized exemplary embodiments (and intermediate structures) of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, exemplary embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
- Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
- Hereinafter, the present invention will be explained in further detail with reference to the accompanying drawings.
-
FIG. 1 is a top plan view illustrating an exemplary embodiment of an array substrate.FIG. 2 is a cross-sectional view taken along line I-I′ ofFIG. 1 . - Referring to
FIGS. 1 and 2 , anarray substrate 100 includes agate line 122, adata line 153, a switching element SW and apixel electrode 180. - For example, in one exemplary embodiment the
gate line 122 extends in a first direction D1 of thebase substrate 110, and a plurality of the gate lines 122 is arranged substantially in parallel in a second direction D2, which is different from the first direction D1. In one exemplary embodiment, the first direction D1 and the second direction D2 may be substantially perpendicular to each other. - The
data line 153 extends in the second direction D2 and a plurality of thedata lines 153 is arranged substantially in parallel in the first direction. Thedata line 153 intersects thegate line 122, e.g. thedata line 153 crosses over thegate line 122 and thedata line 153 and thegate line 122 are vertically aligned at the intersection therebetween. - The switching element SW includes a
gate electrode 124, asource electrode 157 and adrain electrode 158. Thegate electrode 124 is electrically connected to thegate line 122. Thesource electrode 157 is electrically connected to thedata line 153. Thedrain electrode 158 is spaced apart from thesource electrode 157. An end portion of thedrain electrode 158 makes contact with thepixel electrode 180 through acontact hole 172 so that the switching element SW is electrically connected to thepixel electrode 180. - The
array substrate 100 further includes agate insulation layer 130, achannel pattern 140 and apassivation layer 170. - The
gate insulation layer 130 is disposed on abase substrate 110 and on thegate line 122 and thegate electrode 124, which are also disposed on thebase substrate 110. - The
channel pattern 140 is disposed on thegate insulation layer 130, which is disposed on thegate electrode 124, and overlaps with thegate electrode 124. Thechannel pattern 140 is disposed between thegate insulation layer 130 and a metal layer for forming thedata line 153. In one exemplary embodiment, the metal layer for the data line is patterned to provide thesource electrode 157, thedrain electrode 158 and thedata line 153. A channel portion CH is disposed between the source and drainelectrodes - The
data line 153 and the source and drainelectrodes data line 153. - The
passivation layer 170 is disposed on abase substrate 110, on which thedata line 153 and the source anddrain electrode contact hole 172 partially exposing thedrain electrode 158. -
FIG. 3 is a cross-sectional view illustrating an exemplary embodiment of a method of manufacturing the gate pattern of the array substrate ofFIG. 2 .FIGS. 4 to 10 are cross-sectional views illustrating an exemplary embodiment of a method of manufacturing the source pattern and the channel portion of the array substrate ofFIG. 2 .FIG. 11 is a cross-sectional view illustrating an exemplary embodiment of a method of manufacturing the passivation layer of the array substrate ofFIG. 2 . Hereinafter, an embodiment of a method for manufacturing the array substrate will be explained in further detail. - Referring to
FIG. 3 , agate pattern 120 is disposed on thebase substrate 110. Thegate pattern 120 includes thegate line 122 and thegate electrode 124. - For example, in one exemplary embodiment a gate metal layer (not shown) may be disposed on the
base substrate 110, a gate photo pattern (not shown) may be disposed on the gate metal layer using a first mask (not shown), and the gate metal layer may be etched using the gate photo pattern as an etch stop layer, to form thegate pattern 120. In an exemplary embodiment the gate metal layer may be wet etched. - The
base substrate 110 may be a transparent-insulating substrate, such as a glass substrate or other material having similar characteristics. The gate metal layer may include a metal, such as aluminum (Al), molybdenum (Mo), neodymium (Nd), chromium (Cr), tantalum (Ta), titanium (Ti), tungsten (W), copper (Cu), silver (Ag), an alloy thereof, or the like or a combination thereof. In an exemplary embodiment, the gate metal layer may consist essentially of a metal such as aluminum, molybdenum, neodymium, chromium, tantalum, titanium, tungsten, copper, silver, an alloy thereof, or the like or a combination thereof. In another exemplary embodiment, the gate metal layer may consist of a metal such as aluminum, molybdenum, neodymium, chromium, tantalum, titanium, tungsten, copper, silver, an alloy thereof or a combination thereof. Alternative exemplary embodiments include configurations wherein the gate metal layer may have a multilayer structure including greater than or equal to two metal layers wherein at least two of the metal layers have different physical characteristics. - Referring to
FIGS. 2 , 3 and 4, thegate insulation layer 130, achannel layer 140 a and the metal layer for thedata line 150 a are sequentially disposed on thebase substrate 110 on which thegate pattern 120 is disposed. For example, in one exemplary embodiment thegate insulation layer 130 and thechannel layer 140 a may be formed via a plasma-enhanced chemical vapor deposition (“PECVD”) process. - In an embodiment, the
gate insulation layer 130 may include silicon nitride (e.g., SiNx, 0<x<1) and silicon oxide (e.g., SiOy, 0<y<1). In another embodiment thegate insulation layer 130 may comprise silicon nitride (e.g., SiNx, wherein x is greater than 0 and less than or equal to about 1.3), silicon oxide (e.g., SiOy, wherein y is greater than 0 and less than or equal to about 2), or the like or a combination thereof. Thechannel layer 140 a includes asemiconductor layer 142 a and anohmic contact layer 144 a. Thesemiconductor layer 142 a may be disposed on thegate insulation layer 130 and may include amorphous silicon (“a-Si”) or the like. Theohmic contact layer 144 a is disposed on thesemiconductor layer 142 a and may include an n-doped amorphous silicon (“n+ a-Si”), or the like, and thus may include amorphous silicon, which has been doped with n-type impurities at a high density. - Then, the metal layer for the
data line 150 a is disposed on thechannel layer 140 a. The metal layer for thedata line 150 a includes afirst metal layer 151 a and asecond metal layer 152 a, which may be disposed sequentially. In one exemplary embodiment, the metal layer for thedata line 150 a may be disposed via a sputtering process. In one exemplary embodiment, thefirst metal layer 151 a may include titanium (Ti) and the second metal layer may include copper (Cu). In an exemplary embodiment, thefirst metal layer 151 a may consist essentially of titanium or the like and the second metal layer may consist essentially of copper or the like. In another exemplary embodiment, thefirst metal layer 151 a may consist of titanium and the second metal layer may consist of copper. In an exemplary embodiment thefirst metal layer 151 a is disposed before thesecond metal layer 152 a is disposed; for example, copper may be deposited after titanium is deposited. - Referring
FIGS. 2 , 4 and 5, a photoresist pattern layer (not shown) is formed via coating photoresist materials on the metal layer for thedata line 150 a, and asource photo pattern 160 is formed via patterning the photoresist layer using a second mask. - For example, in one exemplary embodiment the photoresist layer may include a negative-type photoresist material. In an exemplary embodiment wherein a negative-type photoresist is used, a portion of the negative-type photoresist material on which light is irradiated is cured and remains, and a portion of the negative-type photoresist material on which light is not irradiated is removed. Alternative exemplary embodiments include configurations wherein the photoresist layer may include a positive-type photoresist material. In an exemplary embodiment wherein a positive-type photoresist is used, a portion of the positive-type photoresist material on which the light is not irradiated is cured and remains, and a portion of the positive-type photoresist material on which the light is irradiated is removed. According to type and/or other characteristics of the photoresist layer, the second mask MASK may be designed without further undue experimentation by one of skill in the art. The photoresist layer according to the present exemplary embodiment includes the negative photoresist material.
- The second mask MASK may be a slit mask and include first, second and third light-transmitting
portions portion 20 and a diffractingportion 30. Thesource photo pattern 160 includes a first thick portion TH1 and a second thick portion TH2. - The first, second and third light-transmitting
portions portion 12 corresponding to an area of thebase substrate 110 on which thedata line 153 ofFIG. 1 may be disposed, a second light-transmittingportion 14 corresponding to an area of thebase substrate 110 on which thesource electrode 157 may be disposed and a third light-transmittingportion 16 corresponding to an area of thebase substrate 110 on which thedrain electrode 158 may be disposed. The first thickness portion TH1 is disposed on the portion of the metal layer for thedata line 150 a corresponding to the first, second and third light-transmittingportions diffraction portion 30 corresponds to an area on which the channel portion CH ofFIG. 1 may be disposed. The second thick portion TH2 is disposed on the portion of the metal layer for thedata line 150 a corresponding to thediffraction portion 30. The second thick portion TH2 has a second thickness THb. The second thickness THb may be less than the first thickness THa. - In one exemplary embodiment, the mask may be a half-tone mask and include a transflective portion. A half-tone (e.g., transflective) portion may be disposed at the
diffraction portion 30 in the exemplary embodiment wherein the half-tone mask is used. Referring toFIGS. 2 , 5 and 6, thefirst metal layer 151 a and thesecond metal layer 152 a are sequentially etched using thesource photo pattern 160 as an etch stop layer. - For example, a
first electrode pattern 150 b connected to themetal line pattern 153 a and themetal line pattern 153 a itself are formed via etching the metal layer for thedata line 150 a. - The
metal line pattern 153 a includes afirst line pattern 154 and asecond line pattern 155 a, and thefirst electrode pattern 150 b includes afirst element pattern 151 b and asecond element pattern 152 b. - The metal layer for the
data line 150 a may be patterned, for example, in one exemplary embodiment, by wet etching. Thus, the width of themetal line pattern 153 a and that of thefirst electrode pattern 150 b may be narrower than that of thesource photo pattern 160. - Referring to
FIGS. 2 , 6 and 7, asub-channel pattern 140 b, which includes asub-semiconductor pattern 142 b and asub-ohmic pattern 144 b, is formed via etching a portion of achannel layer 140 a, which is not covered with thesource photo pattern 160, using thesource photo pattern 160. Thesub-channel pattern 140 b remains under themetal line pattern 153 a and thefirst electrode pattern 150 b. Thegate insulation layer 130 is exposed on an area of thebase substrate 110, which does not correspond to thesource photo pattern 160. Thechannel layer 140 a may be formed, for example, in one exemplary embodiment, by dry etching. Thus, the width of thesub-channel pattern 140 b may be substantially the same as the width of thesource photo pattern 160. - Referring to
FIGS. 2 , 7 and 8, a remainingphoto pattern 162 is formed via removing the second thickness portion TH2 of thesource photo pattern 160. An end portion of the remainingphoto pattern 162 is substantially aligned with an end portion of thefirst electrode pattern 150 b, and the remainingphoto pattern 162 has a separate portion corresponding to a separation region between the source and drainelectrodes - The remaining
photo pattern 162 includes a third thickness portion TH3. A portion of the first thickness portion TH1 is removed corresponding to the second thickness THb of the second thickness portion TH2 is removed to form the third thick portion TH3. A portion of thesecond element pattern 152 b corresponding to the channel portion CH is exposed by the third thickness portion TH3 of the remainingphoto pattern 162. The third thickness portion TH3 has a third thickness THc, which may be less than the first thickness THa of the first thickness portion TH1. - Referring to
FIGS. 2 , 8 and 9, the exposedsecond element pattern 152 b is partially etched using the remainingphoto pattern 162 as the etch stop layer to form a first thin-film transistor (“TFT”)pattern 152. Accordingly, asecond electrode pattern 150 c, which includes thefirst TFT pattern 152 and thefirst element pattern 151 b, is formed. - The
second line pattern 155 a is partially etched using the remainingphoto pattern 162 as the etch stop layer to form adata line pattern 155. Accordingly, thedata line 153, including thedata line pattern 155 and thefirst line pattern 154, is formed. - In an exemplary embodiment, since the
second element pattern 152 b is wet etched, the width of thefirst TFT pattern 152, which is included in thesecond electrode pattern 150 c, may be narrower than the width of the remainingphoto pattern 162. - Then, an oxide layer of the
first element pattern 151 b may be converted to a fluoride layer using a reactive gas, which includes a fluoride containing compound. For example, as thesecond electrode pattern 150 c is disposed, or after thesecond electrode pattern 150 c is disposed, a surface of thefirst element pattern 151 b may be oxidized. In an exemplary embodiment, the oxidized surface of thefirst element pattern 151 b may be converted to the fluoride layer by contacting the oxide layer with the fluoride containing compound. The fluoride layer may have a significant vapor pressure, thus may be readily vaporized, thereby, facilitating removal of the fluoride layer. - For example, in one exemplary embodiment the reactive gas may include the fluoride containing compound in a highly activated state. In an exemplary embodiment, the reactive gas may break the combination of the
first element pattern 151 b and the oxide component, and replace the oxygen of the oxide layer with fluoride from the reactive gas, thereby forming the fluoride layer on thefirst element pattern 151 b. In an exemplary embodiment, the fluoride layer may include, for example, titanium fluoride. - While not wanting to be bound by theory, it is understood that the boiling point of the fluoride layer, which may comprise titanium fluoride, may be between about 50° C. and about 100° C., specifically about 75° C., thus the titanium fluoride may be easily vaporized. In an exemplary embodiment, after vaporization the
first element pattern 151 b does not substantially include an oxide layer or a fluoride layer. Accordingly, thefirst element pattern 151 b may be normally etched without interference from a layer such as an oxide layer. - The reactive gas may include, for example, carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), a mixture of sulfur hexafluoride and helium (SF6/He), a mixture of sulfur hexafluoride and nitrogen (SF6/N2), a mixture of sulfur hexafluoride and oxygen (SF6/O2), a mixture of sulfur hexafluoride, oxygen and helium (SF6/O2/He), or the like or a combination thereof. In an exemplary embodiment, the reactive gas may consist essentially of carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), a mixture of sulfur hexafluoride and helium (SF6/He), a mixture of sulfur hexafluoride and nitrogen (SF6/N2), a mixture of sulfur hexafluoride and oxygen (SF6/O2), a mixture of sulfur hexafluoride, oxygen and helium (SF6/O2/He), or the like or a combination thereof. In another embodiment, the reactive gas may consist of carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), a mixture of sulfur hexafluoride and helium (SF6/He), a mixture of sulfur hexafluoride and nitrogen (SF6/N2), a mixture of sulfur hexafluoride and oxygen (SF6/O2), a mixture of sulfur hexafluoride, oxygen and helium (SF6/O2/He) or a combination thereof.
- For example, in an exemplary embodiment wherein the reactive gas is a mixture of sulfur hexafluoride and helium (SF6/He), the internal pressure of a dry etching chamber providing the reactive gas may be about 60 millitorr (mT) to about 400 mT, specifically about 100 mT to about 300 mT, more specifically about 200 mT. In an exemplary embodiment, a mole ratio of sulfur hexafluoride to helium may be about 1:0 to about 1:5, specifically about 1:1 to about 1:4, more specifically about 1:2 to about 1:3.
- Referring to
FIGS. 2 , 9 and 10, the remaining exposed portion of thefirst element pattern 151 b is etched using the remainingphoto pattern 162 as the etch stop layer. For example, in one exemplary embodiment thefirst element pattern 151 b is dry etched to form thesecond TFT pattern 151 and the source and drainelectrodes - Accordingly, the source and drain
electrodes second TFT patterns - In an exemplary embodiment, the
second TFT pattern 151 may have a width substantially the same as the remainingphoto pattern 162. - The
source electrode 157 is electrically connected to thedata line 153, and thedrain electrode 158 is spaced apart from thesource electrode 157. A separation distance of the portions of thesecond TFT pattern 151 corresponding to the source and drainelectrodes - The portion of the
first element pattern 151 b exposed by the remainingphoto pattern 162 may be dry etched using an etching gas. The etching gas may include a chlorine-based gas and may include chlorine. For example, in one exemplary embodiment an etching component of the etching gas may include chloride ions (Cl−). In another embodiment, the etching gas may include a mixture of sulfur hexafluoride and chlorine (e.g., SF6 and Cl2). - In an embodiment, the exposed portion of the
sub-channel pattern 140 b, disposed and in an area, which is wider than the remainingphoto pattern 162, and the portion of thesub-channel pattern 140 b corresponding to the channel portion CH may be etched by the etching gas with thefirst element pattern 151 b to form thechannel pattern 140. - For example, in one exemplary embodiment the portion of the
sub-ohmic pattern 144 b exposed during the forming the source and drainelectrodes sub-ohmic pattern 144 b exposed in the area wider than the remainingphoto pattern 162 is also removed. - In such an exemplary embodiment, since a reaction rate of the
sub-channel pattern 140 b with the etching gas may be faster than the reaction rate of thefirst element pattern 151 b with the etching gas, the thickness of the etchedsub-channel pattern 140 b may be greater than the thickness of the etchedfirst element pattern 151 b. - Additionally, since the
gate insulation layer 130 is exposed on an area of thebase substrate 110, which does not correspond to the area in which thesub-channel pattern 140 b is disposed, the exposed portion of thegate insulation layer 130 may be etched by the etching gas along with thefirst element pattern 151 b and thesub-channel pattern 140 b. - In such an exemplary embodiment, the
sub-channel pattern 140 b is first etched in an area corresponding to thesub-channel pattern 140 b, except for an area corresponding to the source and drainelectrodes gate insulation layer 130 is etched, so that the etched portions of thegate insulation layer 130 may have a stepped portion with respect to each other. Similarly, the reaction rate of thegate insulation layer 130 with the etching gas may be greater than the reaction rate of thefirst element pattern 151 b with the etching gas. Accordingly, the thickness of the etchedgate insulation layer 130 etched by the etching gas may be greater than the thickness of the etchedfirst element pattern 151 b etched by the etching gas. - Accordingly, the
semiconductor pattern 142, which is included in thechannel pattern 140, is exposed to form the channel portion CH. The etched portions of thegate insulation layer 130 may be stepped with respect to each other as illustrated inFIG. 13 , and the width of thechannel pattern 140 may be reduced. - Additionally, the remaining
photo pattern 162 is partially removed and the thickness of the remaining photo pattern may be less than the third thickness THc. - Referring to
FIGS. 7 and 8 again, thechannel layer 140 a is etched to form thesub-channel pattern 140 b and thesource photo pattern 160 is etched to form the remainingphoto pattern 162. According to the above-mentioned processes, thesub-ohmic pattern 144 b may be entirely removed from thesub-semiconductor pattern 142 b after etching thesub-ohmic pattern 144 b. - In the present exemplary embodiment, the
source photo pattern 160 is etched to form the remainingphoto pattern 162 after thechannel layer 140 a is etched to form thesub-channel pattern 140 b. Alternative exemplary embodiments include configurations wherein thechannel layer 140 a may be etched after etching thesource photo pattern 160. - Referring to
FIG. 10 again, the width of thesemiconductor pattern 142 of thechannel pattern 140 is less than the width of thesub-semiconductor pattern 142 b of thesub-channel pattern 140 b. - Accordingly, the
ohmic contact pattern 144, which is included in thechannel pattern 140, may be entirely removed, and the width of thesemiconductor pattern 142 is reduced so that electrical characteristics of the switching element SW may be improved. - As illustrated in
FIGS. 8 to 10 , converting the oxide layer to the fluoride layer and forming the source and drainelectrodes - Subsequently, a cleaning process may be performed. In the cleaning process, the
base substrate 110, on which the channel portion CH is disposed, is taken out of the dry etching chamber, and chlorine ions, which are a component of the etching gas, are removed. - In the cleaning process, the chlorine ions may be removed from the
base substrate 110 by dissolving the chloride ions in water. A dipping method including a step in which thebase substrate 110 is put in and taken out of a cleaning container containing the water may be used as the cleaning process. Alternative exemplary embodiments include methods wherein the cleaning process may include a spraying method including a step in which the water is sprayed on thebase substrate 110 at high pressure. In addition, the above-mentioned cleaning methods may be used in combination and at the same time. The impurities, including the chloride ions, may be partially removed from thebase substrate 110 in the cleaning process. - The water may have a temperature between about 50° C. and about 80° C., specifically about 65° C. to increase a rate at which the chlorine ions are dissolved in the water.
- Then, the remaining
photo pattern 162 is removed from thebase substrate 110. For example, in one exemplary embodiment the remainingphoto pattern 162 may be removed by disposing thebase substrate 110, including the remainingphoto pattern 162, into a strip container containing a strip liquid and dissolving the remainingphoto pattern 162 into the strip liquid. Alternative exemplary embodiments include configurations wherein the remainingphoto pattern 162 may be removed from thebase substrate 110 via an ashing process. -
FIG. 11 is a cross-sectional view illustrating an exemplary embodiment of a method of manufacturing the passivation layer of the array substrate ofFIG. 2 . - Referring to
FIGS. 2 , 10 and 11, thepassivation layer 170 is disposed so as to cover thedata line 153, thesource electrode 157 and thedrain electrode 158 on thebase substrate 110 from which the remainingphoto pattern 162 is removed. Thepassivation layer 170 may include, for example, silicon nitride, silicon oxide, or the like or a combination thereof. - In one exemplary embodiment the
passivation layer 170 on thedrain electrode 158 may be etched using a third mask (not shown) to form acontact hole 172 exposing thedrain electrode 158. - Referring to
FIGS. 2 and 11 again, a transparent electrode layer (not shown) is disposed on thebase substrate 110 on which thepassivation layer 170 and thecontact hole 172 are disposed. - Then, the transparent electrode layer is patterned using a fourth mask (not shown) to form a
pixel electrode 180. Thepixel electrode 180 makes electrical contact with thedrain electrode 158 through thecontact hole 172, and thus the switching element SW is electrically connected to thepixel electrode 180. Thepixel electrode 180 may include a transparent conductive material. Thepixel electrode 180 may include, for example, indium zinc oxide (“IZO”), indium tin oxide (“ITO”), or the like or a combination thereof. -
FIG. 12 is an enlarged cross-sectional view illustrating an exemplary embodiment of the channel portion ofFIG. 2 .FIG. 13 is an enlarged cross-sectional view illustrating a portion A ofFIG. 2 . - Referring to
FIGS. 2 and 12 , a first separation distance dl, which is defined between a portion of asecond TFT pattern 151 corresponding to thesource electrode 157 adjacent to the channel portion CH and a portion of thesecond TFT pattern 151 corresponding to thedrain electrode 158, is smaller than a second separation distance d2, which is defined between a portion of afirst TFT pattern 152 corresponding to thesource electrode 157 and a portion of thefirst TFT pattern 152 corresponding to thedrain electrode 158. - The
channel pattern 140 includes theohmic contact pattern 144, corresponding to thesecond TFT pattern 151, and thesemiconductor pattern 142, corresponding to theohmic contact pattern 144 and the channel portion CH. - In one exemplary embodiment the
semiconductor pattern 142 is disposed on thegate insulation layer 130. Thegate insulation layer 130 has a stepped portion, and thesemiconductor pattern 142 is disposed on an upper portion of thegate insulation layer 130. - Except for the channel portion CH, the
ohmic contact pattern 144 is disposed on thesemiconductor pattern 142. In one exemplary embodiment, an end portion of theohmic contact pattern 144 is aligned with an end portion of thesemiconductor pattern 142. Accordingly, thechannel pattern 140 may include thesemiconductor pattern 142 corresponding to the channel portion CH. - In such an exemplary embodiment, the end portion of the
second TFT pattern 151 disposed on theohmic contact pattern 144 is aligned with the end portion of theohmic contact pattern 144. The end portion of thefirst TFT pattern 152, which is disposed on thesecond TFT pattern 151, and thesecond TFT pattern 151 may form a stepped portion with respect to each other. - In a four-part process according to the present exemplary embodiment, the second and
first TFT patterns second metal layers - Although only the first and
second TFT patterns FIG. 12 , thefirst line pattern 154 and thedata line pattern 155 inFIG. 9 may have a stepped portion with respect to each other. - Referring to
FIGS. 2 , 12 and 13, the etched portions of thegate insulation layer 130 in the portion A form a stepped portion. Thechannel pattern 140 having a stepped portion with thegate insulation layer 130 is disposed on thegate insulation layer 130. Thesecond TFT pattern 151 is disposed on thechannel pattern 140, and the end portion of the second TFT pattern is disposed in alignment with the end portion of thechannel pattern 140. Thefirst TFT pattern 152 is disposed on thesecond TFT pattern 151, and thefirst TFT pattern 152 has a stepped portion with respect to thesecond TFT pattern 151. - In one exemplary embodiment the separation distance of the portions of the
second TFT pattern 151 corresponding to the source and drainelectrodes -
FIG. 14 . is a schematic plan view illustrating an exemplary embodiment of the apparatus for manufacturing the array substrate ofFIG. 2 .FIG. 15 is a schematic cross-sectional view illustrating an exemplary embodiment of the dry etching chamber ofFIG. 14 . - Referring
FIGS. 2 , 3 to 11 and 14, anapparatus 200 for manufacturing the array substrate includes atransfer robot 210, adeposition chamber 220, awet etching chamber 230, adry etching chamber 240, aprotection chamber 250 and arotation unit 280. - The
rotation unit 280 rotates a plurality ofchambers 220 to 250 to perform a manufacturing process. - A deposition method in the
deposition chamber 220 may include, for example, a chemical vapor deposition (“CVD”) method, a sputtering process or the like. The CVD method may include a plasma enhanced chemical vapor deposition (“PECVD”) process. - In the
deposition chamber 220 the gate metal layer (not shown), thegate insulation layer 130, thechannel layer 140 a, the metal layer for thedata line 150 a, thepassivation layer 170 and the transparent electrode layer (not shown) may be disposed by PECVD or the like. - Although not shown in
FIG. 14 , theapparatus 200 for manufacturing the array substrate may further include an exposing apparatus, which disposes a photoresist layer and exposes the photoresist layer using the first to fourth masks. The exposing process may be performed before thebase substrate 110 moves from thedeposition chamber 220 to thewet etching chamber 230 and/or thedry etching chamber 240. - The
protection chamber 250 may be, for example, a cleaning chamber, in which thebase substrate 110 is cleaned, a heating chamber, in which thebase substrate 110 is heated or a cooling chamber, in which thebase substrate 110 is cooled. - In one exemplary embodiment the
base substrate 110 manufactured in the previous manufacturing process may be disposed in thedeposition chamber 220 from the exterior by thetransfer robot 210, and the gate metal layer may be disposed in thedeposition chamber 220. - The
base substrate 110 on which the gate metal layer is disposed may be moved to thewet etching chamber 230 by thetransfer robot 210, and thegate pattern 120 may be disposed by wet etching. - The
base substrate 110, on which thegate pattern 120 is disposed, may be moved to thedeposition chamber 220 by thetransfer robot 210, and in thedeposition chamber 220, thegate insulation layer 130, thechannel layer 140 a and the metal layer for the data line may be sequentially disposed on the base substrate on which thegate pattern 120 is disposed. - Then, in the
wet etching chamber 230, the first andsecond metal layers base substrate 110, on which thegate insulation layer 130, thechannel pattern 140 and the metal layer for thedata line 150 a are disposed, are entirely etched, to form thefirst element pattern 151 b. Then, in thewet etching chamber 230, thesecond metal layer 152 a of thebase substrate 110, on which thegate insulation layer 130, thechannel pattern 140 and the metal layer for thedata line 150 a are disposed, is etched to form thesecond electrode pattern 150 c and thedata line 153. - Then, the
first element pattern 151 b and thesub-channel pattern 140 b are etched in thedry etching chamber 240. In an exemplary embodiment, thegate insulation layer 130 may also be etched. - In an exemplary embodiment, in the
dry etching chamber 240 an oxide layer of thefirst element pattern 151 b may be removed by contacting thefirst element pattern 151 b with the reactive gas, which may include carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), a mixture of sulfur hexafluoride and helium (SF6/He), a mixture of sulfur hexafluoride and nitrogen (SF6/N2), a mixture of sulfur hexafluoride and oxygen (SF6/O2), a mixture of sulfur hexafluoride, oxygen and helium (SF6/O2/He), or the like or a combination thereof. - Additionally, in the
dry etching chamber 240, thefirst element pattern 151 b and thesub-channel pattern 140 b may be etched by contacting with the etching gas, which may include a mixture of sulfur hexafluoride and chlorine (SF6, Cl2). - In the
protection chamber 250, a cleaning process is performed to remove chloride ions, which result from the etching gas, from thebase substrate 110 on which the channel portion CH is disposed. - Then, in the
deposition chamber 220, thepassivation layer 170 is disposed to cover thedata line 153 and the source and drainelectrodes base substrate 110, and thepassivation layer 170 is etched in thedry etching chamber 240 to form thecontact hole 172. - Then, in the
deposition chamber 220, a transparent electrode layer is disposed to cover thepassivation layer 170, and the transparent electrode layer is etched to form thepixel electrode 180 in the wet and/ordry etching chambers - Referring to
FIGS. 14 and 15 , thedry etching chamber 240 includes afirst substrate 243 and asecond substrate 245. - The
base substrate 110 corresponding to each step is disposed on thefirst substrate 243. - The
dry etching chamber 240 receives the reactive gas and the etching gas from outside and forms plasma between thesecond substrate 245, which is connected to a voltage supply V, and thefirst substrate 243, which is grounded. - Accordingly, in the
dry etching chamber 240, a process for removing an oxide layer of thefirst element pattern 151 b and a process for dry etching thefirst element pattern 151 b and thesub-channel pattern 140 b may be performed using the plasma. - While not wanting to be bound by theory, it is understood that the oxide layer on the
first element pattern 151 b chemically reacts with the reactive gas, and thefirst element pattern 151 b and thesub-channel pattern 140 b chemically react with the etching gas. Accordingly, the voltage supply V provides a low voltage of about 40 V to about 60 V, specifically about 45 V to about 55 V, more specifically about 50 V to perform the manufacturing process for thearray substrate 100. - In an embodiment, since the oxide layer of the
first element pattern 151 b (e.g., the TFT pattern) may be converted to the fluoride layer using the reactive gas, which includes the fluoride containing compound, thefirst element pattern 151 b may be etched without interference from an oxide and the reliability of manufacturing process may be improved. - Additionally, the portion of the
first element pattern 151 b and thesub-channel pattern 140 b, which are disposed on an area which is wider than an area of the remainingphoto pattern 162, are dry-etched at the same time, so that the width of thechannel pattern 140 of the switching element SW may be reduced, and the separation distance of the source and drainelectrodes -
FIG. 16 is a cross-sectional view illustrating another exemplary embodiment of a method of manufacturing a source pattern of an array substrate.FIG. 17 is a cross-sectional view illustrating an exemplary embodiment of a method of manufacturing a channel portion of the array substrate ofFIG. 16 . - A method for manufacturing an array substrate according to the present exemplary embodiment is substantially the same as the method according to the previous exemplary embodiment except that the
first element pattern 151 b and thesub-channel pattern 140 b ofFIG. 9 are first etched by a metal etching gas as illustrated inFIG. 16 , and thesub-channel pattern 140 b is etched by a channel etching gas as illustrated inFIG. 17 . Accordingly, the same reference numerals will be used to refer to the same or like elements as those described in the previous exemplary embodiment and any further repetitive explanation concerning the above elements will be omitted. - Referring to
FIGS. 2 , 9 and 16, the exposedsecond electrode pattern 150 c is dry-etched using the remainingphoto pattern 162 as an etch stop layer to form the source and drainelectrodes - The
source electrode 157 is electrically connected to thedata line 153, and thedrain electrode 158 is spaced apart from thesource electrode 157. A separation distance of the source and drainelectrodes - In an embodiment, an oxide layer disposed on a surface of the
first element pattern 151 b may be converted to the fluoride layer. Since the fluoride layer may be easily vaporized, thefirst element pattern 151 b may be etched without interference from the oxide layer. - When the
first element pattern 151 b is etched by the metal etching liquid, the portion of thesub-channel pattern 140 b on an area larger than the remainingphoto pattern 162 is partially etched, and thus adummy channel pattern 240 may be formed. - The
dummy channel pattern 240 may include a dummyohmic pattern 244 and adummy semiconductor pattern 242. The sub-ohmic pattern, except in an area corresponding to a separation region between the source and drainelectrodes photo pattern 162, thereby forming the dummyohmic pattern 244. In addition, the sub-semiconductor pattern, except in the area corresponding to the separation region between the source and drainelectrodes sub-semiconductor pattern 142 b, thereby forming the dummyohmic pattern 244. - Since a reaction rate of the
sub-channel pattern 140 b with the metal etching liquid is faster than the reaction rate of thefirst element pattern 151 b with the metal etching liquid, the thickness of thesub-channel pattern 140 b etched by the metal etching liquid may be greater than the thickness of thefirst element pattern 151 b etched by the metal etching liquid. In addition, since thegate insulation layer 130 is exposed in an area of thebase substrate 110, except in an area in which thesub-channel pattern 140 b is disposed, the exposed portion of thegate insulation layer 130 may also be etched with thefirst element pattern 151 b and thesub-channel pattern 140 b. In such an exemplary embodiment, the reaction rate of thegate insulation layer 130 with the metal etching gas may be faster than the reaction rate of thefirst element pattern 151 b with the metal etching gas. Accordingly, the thickness of thegate insulation layer 130 etched by the metal etching gas may be greater than the thickness of thefirst element pattern 151 b etched by the metal etching gas. - The
first element pattern 151 b (e.g., the TFT pattern) exposed by the remainingphoto pattern 162 may be dry-etched using the metal etching gas. The metal etching gas may be a chlorine-based gas and may include chlorine. For example, in one exemplary embodiment an etching component of the metal etching gas may be chloride ions (Cl−). In an embodiment, the metal etching gas may be a gas mixture including chlorine (Cl2), boron trichloride (BCl3), or the like or a combination thereof. For example, the metal etching gas may include a mixture of chlorine and helium (Cl2/He), a mixture of chlorine and argon (Cl2/Ar), chlorine (Cl2), or the like or a combination thereof. - For example, in the exemplary embodiment wherein a mixture of chlorine and helium (Cl2/He) is used as the metal etching gas, the internal pressure of the dry etching chamber when the metal etching gas is provided to the dry etching chamber may be about 60 mT to about 200 mT, specifically about 80 mT to about 180 mT, more specifically about 100 mT to about 160 mT. In an exemplary embodiment, a mole ratio of chlorine (Cl2) and helium (He) may be about 1:0 to about 1:5, specifically about 1:1 to about 1:4, more specifically about 1:2 to about 1:3.
- By disposing the source and drain
electrodes ohmic pattern 244 may be exposed through a separation region between the source and drainelectrodes first element pattern 151 b may remain in the separation region between the source and drainelectrodes - Referring to
FIGS. 2 , 16 and 17, the dummyohmic pattern 244, exposed using the remainingphoto pattern 162 and the source and drainelectrodes first element pattern 151 b, and thus thechannel pattern 140 may be formed. In such an exemplary embodiment, the dummyohmic pattern 244 may be dry-etched using the channel etching gas. - For example, the portion of the dummy
ohmic pattern 244 exposed through the separation region between the source and drainelectrodes dummy semiconductor pattern 242, exposed because it extends beyond an area of the remainingphoto pattern 162, may be removed, and the remaining portion of thefirst element pattern 151 b may be removed. - In such an exemplary embodiment, the portion of the dummy
ohmic pattern 244 and thedummy semiconductor pattern 242 disposed beyond an area of the remainingphoto pattern 162 are dry-etched at the same time. Thus the width of thechannel pattern 140 may be narrower than the width of thesub-channel pattern 140 b, because the portion of thedummy semiconductor pattern 242 exposed because it extends beyond the area of the remainingphoto pattern 162 may be entirely removed. Accordingly, electrical characteristics of the switching element SW may be improved. - The portion of the
gate insulation layer 130 exposed on the area of thebase substrate 110, except an area on which thesub-channel pattern 140 b is disposed, may be additionally etched by the channel etching gas. Accordingly, the etched portions of thegate insulation layer 130 may form a stepped portion. - In an exemplary embodiment, the remaining
photo pattern 162 is partially removed and the thickness of the remainingphoto pattern 162 may be less than the third thickness THc. Accordingly, thesemiconductor pattern 142 of thechannel pattern 140 is exposed, and the channel portion CH is formed. - An apparatus for manufacturing the array substrate according to the present exemplary embodiment is substantially the same as that the apparatus according to the previous exemplary embodiment except for the type of gas used in the dry etching chamber. Accordingly, the same reference numerals will be used to refer to the same or like parts as those described in the previous exemplary embodiment, and any further repetitive explanation concerning the above elements will be omitted.
- In the
dry etching chamber 240, when thefirst element pattern 151 b and thesub-channel pattern 140 b of thebase substrate 110, on which thechannel layer 140 a and the metal layer for thedata line 150 a are disposed, are etched, the metal etching gas and the dry etching gas may be used. - In the process of manufacturing the array substrate according to an exemplary embodiment, the
first element pattern 151 b may be etched independently from thesub-channel pattern 140 b in regions corresponding to the separation region between the source and drainelectrodes first element pattern 151 b and thesub-channel pattern 140 b may be more precisely etched, and the reliability of manufacturing process may be improved. - According to an exemplary embodiment, an oxide layer of a first element pattern may be converted with a reactive gas to a fluoride layer, which may be easily vaporized. The reactive gas may include a fluoride containing compound. Accordingly, the first element pattern may be etched without interference from an oxide, and the reliability of manufacturing process may be improved.
- Additionally, by dry etching the first element pattern and a sub-channel pattern, which are wider than an area of a remaining photo pattern, at the same time, the width of a channel pattern of a switching element may be decreased. Because the separation distance of source and drain electrodes of the switching element is decreased, electrical characteristics of the switching element may be improved.
- Additionally, by etching the first element pattern and the sub-channel pattern independently, since the first element pattern and the sub-channel pattern may be more precisely etched, the reliability of manufacturing process may be improved.
- The foregoing is illustrative and is not to be construed as limiting thereof. Although a few exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible without materially departing from the novel teachings and advantages, features and aspects of the foregoing exemplary embodiments. Accordingly, all such modifications are intended to be included within the scope of the present invention as defined in the claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of the present invention and is not to be construed as limited to the specific exemplary embodiments disclosed, and that modifications to the disclosed exemplary embodiments, as well as other exemplary embodiments, are intended to be included within the scope of the appended claims. The present invention is defined by the following claims, with equivalents of the claims to be included therein.
Claims (4)
1. An array substrate comprising:
a gate electrode disposed on a base substrate;
a gate insulation layer disposed on the base substrate on which the gate electrode is disposed, the gate insulation layer having a first thickness in a first region and a second thickness in a second region, the first thickness being greater than the second thickness;
a semiconductor pattern disposed on the gate insulation layer in the first region, an end portion of the semiconductor pattern having a stepped portion with respect to the gate insulation layer;
an ohmic contact pattern disposed on the semiconductor pattern, an end portion of the ohmic contact pattern, which is disposed substantially opposite to a channel portion of the ohmic contact region, being aligned with the end portion of the semiconductor pattern; and
source and drain electrodes disposed on the ohmic contact pattern, the source and drain electrodes being spaced apart from each other and including first and second thin-film transistor patterns, wherein end portions of the first and second thin film transistor patterns have a stepped portion with respect to each other.
2. The array substrate of claim 1 , further comprising:
a gate line disposed on the base substrate;
a data line disposed on the base substrate on which the gate line is disposed, wherein a first line pattern and a data line pattern form a stepped portion with respect to each other and the first line pattern and the data line pattern cross the gate line; and
a pixel electrode which electrically contacts the drain electrode.
3. The array substrate of claim 2 , wherein an end portion of the second thin film transistor pattern is aligned with an end portion of the ohmic contact pattern, and the end portion of the second thin film transistor pattern and an end portion of the first thin film transistor pattern have a stepped portion with respect to each other.
4. The array substrate of claim 3 , wherein a first distance between portions of the second thin film transistor pattern corresponding to the source and drain electrodes is greater than a second distance between portions of the first thin film transistor pattern corresponding to the source and drain electrodes.
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US13/616,150 US20130015452A1 (en) | 2009-06-09 | 2012-09-14 | Array substrate and method for manufacturing the array substrate |
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KR1020090050842A KR101571803B1 (en) | 2009-06-09 | 2009-06-09 | Array substrate and method of manufacturing the array substrate |
KR10-2009-0050842 | 2009-06-09 | ||
US12/777,347 US8298877B2 (en) | 2009-06-09 | 2010-05-11 | Array substrate and method for manufacturing the array substrate |
US13/616,150 US20130015452A1 (en) | 2009-06-09 | 2012-09-14 | Array substrate and method for manufacturing the array substrate |
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US13/616,150 Abandoned US20130015452A1 (en) | 2009-06-09 | 2012-09-14 | Array substrate and method for manufacturing the array substrate |
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KR101582946B1 (en) * | 2009-12-04 | 2016-01-08 | 삼성디스플레이 주식회사 | Thin film transistor substrate and the method therrof |
JP6004308B2 (en) * | 2011-08-12 | 2016-10-05 | Nltテクノロジー株式会社 | Thin film device |
US20130043559A1 (en) * | 2011-08-17 | 2013-02-21 | International Business Machines Corporation | Trench formation in substrate |
CN103048840B (en) * | 2012-11-12 | 2015-04-01 | 京东方科技集团股份有限公司 | Array substrate, manufacture method of array substrate, liquid crystal display panel and display device |
KR102130110B1 (en) * | 2013-10-21 | 2020-07-06 | 삼성디스플레이 주식회사 | Display panel and method of manufacturing the same |
WO2019182264A1 (en) | 2018-03-23 | 2019-09-26 | 홍잉 | Vertical nanowire semiconductor device and manufacturing method therefor |
WO2019182261A1 (en) | 2018-03-23 | 2019-09-26 | 홍잉 | Method for manufacturing single-grained nanowire and method for manufacturing semiconductor device employing same single-grained nanowire |
KR101993313B1 (en) * | 2019-04-15 | 2019-06-26 | 한국생산기술연구원 | Flexible filter element using liquid metal and method of preparing the same |
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US6104042A (en) * | 1999-06-10 | 2000-08-15 | Chi Mei Optoelectronics Corp. | Thin film transistor with a multi-metal structure a method of manufacturing the same |
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US20040056251A1 (en) * | 2002-07-19 | 2004-03-25 | Dong-Gyu Kim | Thin film transistor array panel and manufacturing method thereof |
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US6319861B1 (en) * | 2000-05-02 | 2001-11-20 | United Microelectronics Corp. | Method of improving deposition |
KR100720433B1 (en) | 2000-08-30 | 2007-05-22 | 엘지.필립스 엘시디 주식회사 | Method for manufacturing liquid crystal display device |
US7134199B2 (en) * | 2002-06-13 | 2006-11-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fluxless bumping process |
KR101267080B1 (en) | 2006-08-30 | 2013-05-23 | 엘지디스플레이 주식회사 | Thin film transistor device for liquid crystal display and fabricating method thereof |
KR101425635B1 (en) | 2006-11-29 | 2014-08-06 | 삼성디스플레이 주식회사 | Method of manufacturing of oxide thin film transistor array substrate and oxide thin film transistor array substrate |
KR101253497B1 (en) * | 2008-06-02 | 2013-04-11 | 엘지디스플레이 주식회사 | Method of fabricating array substrate for liquid crystal display device |
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US6900854B1 (en) * | 1998-11-26 | 2005-05-31 | Samsung Electronics Co., Ltd. | Thin film transistor array panel for a liquid crystal display |
US6104042A (en) * | 1999-06-10 | 2000-08-15 | Chi Mei Optoelectronics Corp. | Thin film transistor with a multi-metal structure a method of manufacturing the same |
US20020005540A1 (en) * | 1999-12-30 | 2002-01-17 | Kim Dong Hee | Thin film transistor and fabricating method thereof |
US20040056251A1 (en) * | 2002-07-19 | 2004-03-25 | Dong-Gyu Kim | Thin film transistor array panel and manufacturing method thereof |
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US8298877B2 (en) | 2012-10-30 |
US20100308334A1 (en) | 2010-12-09 |
KR101571803B1 (en) | 2015-11-26 |
KR20100132167A (en) | 2010-12-17 |
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