KR101425635B1 - Method of manufacturing of oxide thin film transistor array substrate and oxide thin film transistor array substrate - Google Patents

Method of manufacturing of oxide thin film transistor array substrate and oxide thin film transistor array substrate Download PDF

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KR101425635B1
KR101425635B1 KR20070119287A KR20070119287A KR101425635B1 KR 101425635 B1 KR101425635 B1 KR 101425635B1 KR 20070119287 A KR20070119287 A KR 20070119287A KR 20070119287 A KR20070119287 A KR 20070119287A KR 101425635 B1 KR101425635 B1 KR 101425635B1
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alloy
region
oxide semiconductor
film
pattern
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KR20070119287A
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KR20080048936A (en
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이제훈
양동주
인태형
김도현
홍선영
정승재
정창오
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삼성디스플레이 주식회사
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Abstract

A method of manufacturing an oxide thin film transistor substrate is provided. A method of manufacturing an oxide thin film transistor substrate includes forming a gate wiring on an insulating substrate, forming a laminated structure of an oxide semiconductor pattern and a data wiring on the gate wiring, wherein the oxide semiconductor pattern is divided into a first region and a second region And the data line is formed on the second region so that the thickness of the first region is thinner than the thickness of the second region.
Oxide thin film transistor, oxide semiconductor, etching, work function, channel thickness

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of manufacturing an oxide thin film transistor substrate,

The present invention relates to a method for manufacturing an oxide thin film transistor substrate and an oxide thin film transistor substrate manufactured thereby, and more particularly, to a method for manufacturing an oxide thin film transistor having high charge mobility and high on / off current ratio and a substrate.

As the size and quality of the liquid crystal display device continue to increase, it is required to improve the electrical characteristics of the thin film transistor driving the liquid crystal. In the case of a conventional thin film transistor, hydrogenated amorphous silicon (a-Si: H) is used as a semiconductor film in which a channel is formed.

In the case of hydrogenated amorphous silicon, there is a problem that the charge mobility and on / off current ratio are relatively low. In addition, the optical band gap of hydrogenated amorphous silicon is about 1.8 eV, a leakage photocurrent is generated from the backlight unit and a residual image due to an increase in dangling bond is generated, thereby deteriorating the characteristics of the thin film transistor have.

SUMMARY OF THE INVENTION The present invention provides a method of manufacturing an oxide thin film transistor substrate having an oxide thin film transistor having excellent characteristics.

It is another object of the present invention to provide an oxide thin film transistor substrate having an oxide thin film transistor having excellent characteristics.

The technical objects of the present invention are not limited to the above-mentioned technical problems, and other technical subjects not mentioned can be clearly understood by those skilled in the art from the following description.

According to another aspect of the present invention, there is provided a method of fabricating an oxide thin film transistor substrate, comprising: forming a gate wiring on an insulating substrate; forming a stacked structure of an oxide semiconductor film pattern and a data wiring on the gate wiring; Wherein the oxide semiconductor film pattern is divided into a first region and a second region so that the thickness of the first region is thinner than the thickness of the second region and the data line is formed on the second region According to another aspect of the present invention, there is provided an oxide thin film transistor substrate including gate lines formed on an insulating substrate, oxide semiconductor patterns formed on the gate lines, An oxide semiconductor pattern that is divided into a first region, a second region, the first region being thinner than the second region, The first comprises a data line formed on the second region.

The details of other embodiments are included in the detailed description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. To fully disclose the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

Although elements such as first, second, etc. are used to describe various elements, components, regions, wires, layers and / or sections, these elements, components, regions, wires, layers and / It is of course not limited. These terms are only used to distinguish one element, element, region, line, layer or sections from another element, element, region, line, layer or sections. Therefore, the first element, the first element, the first region, the first wiring, the first layer or the first section, which will be described below, can be applied to the second element, the second element, , A second wire, a second layer or a second section.

The terms spatially relative, "below", "beneath", "lower", "above", "upper" May be used to readily describe a device or a relationship of components to other devices or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. For example, when inverting an element shown in the figures, an element described as "below" or "beneath" of another element may be placed "above" another element. Thus, the exemplary term "below" can include both downward and upward directions. The elements can also be oriented in different directions, so that spatially relative terms can be interpreted according to orientation.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

The embodiments described herein will be described with reference to cross-sectional views that are ideal schematic views of the present invention. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are generated according to the manufacturing process. For example, the etched area shown at right angles may be rounded or may have a shape with a certain curvature. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

Hereinafter, an oxide thin film transistor substrate according to an embodiment of the present invention will be described with reference to the accompanying drawings.

First, the structure of an oxide thin film transistor substrate according to an embodiment of the present invention will be described with reference to FIGS. 1A to 1B. FIG. FIG. 1A is a layout diagram of an oxide thin film transistor substrate according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view of the oxide thin film transistor substrate taken along line B-B 'of FIG. 1A.

A gate line 22 is formed on the substrate 10 in a lateral direction and a gate electrode 26 of an oxide thin film transistor formed in a protrusion shape connected to the gate line 22 is formed. These gate lines 22 and gate electrodes 26 are referred to as gate wirings.

A storage electrode line 28 extending in the transverse direction is formed substantially parallel to the gate line 22 across the pixel region on the substrate 10 and connected to the storage electrode line 28 to form a wide width The storage electrode 27 is formed. The storage electrode 27 overlaps the drain electrode extension 67 connected to the pixel electrode 82, which will be described later, to form a storage capacitor for improving the charge storage ability of the pixel. The storage electrode 27 and the storage electrode line 28 are referred to as a storage wiring.

The gate wirings 22 and 26 and the storage wirings 27 and 28 may be formed of a metal of aluminum series such as aluminum (Al) and aluminum alloy, a series metal such as silver (Ag) and silver alloy, Such as molybdenum metal, chromium (Cr), titanium (Ti), and tantalum (Ta), such as copper, molybdenum and molybdenum alloys. However, the present invention is not limited thereto, and the gate wirings 22 and 26 and the storage wirings 27 and 28 may be made of various metals and conductors.

A gate insulating film 30 made of silicon nitride (SiNx) or the like is formed on the gate wirings 22, 26 and the storage wirings 27, 28. On the gate insulating film 30, oxide semiconductor patterns 42 and 44 made of an oxide including at least one of O and Zn, In, Ga, or Sn are formed. For example, as the oxide semiconductor patterns 42 and 44, mixed oxides such as InZnO, InGaO, InSnO, ZnSnO, GaSnO, GaZnO, and GaInZnO may be used. The oxide semiconductor patterns 42 and 44 have an effective mobility of about 2 to 100 times larger than that of hydrogenated amorphous silicon and have on / off current ratios of 10 5 to 10 8 , Lt; / RTI > Also, in the case of the oxide semiconductors 42 and 44, since the band gap is about 3.0 to 3.5 eV, no leakage photocurrent is generated with respect to visible light. Accordingly, instantaneous afterglow of the oxide thin film transistor can be prevented, and it is not necessary to form a light shielding film under the oxide thin film transistor, so that the aperture ratio of the liquid crystal display device can be increased. In order to improve the characteristics of the oxide semiconductor, Group 3, Group 4, Group 5 or Group 5 elements or transition elements on the periodic table may be further included. In the case of an oxide thin film transistor, pattern shapes of oxide semiconductor patterns and data lines are generally different from each other. However, in the case of applying the four-mask process, the oxide semiconductor patterns 42 and 44 are patterned in substantially the same shape as the data lines 62, 65, 66, and 67 to be described later except for the channel region of the oxide thin film transistor . This is because the oxide semiconductor patterns 42 and 44 and the data lines 62, 65, 66, and 67 are patterned by using one etching mask. Although FIGS. 1A and 1B illustrate the structure manufactured by the four-mask process, the present invention is not limited thereto. For example, when a four-mask process and a five-mask process are applied It is obvious to those skilled in the art to apply the core idea of the present invention. Data wirings 62, 65, 66, and 67 are formed on the oxide semiconductor patterns 42 and 44 and the gate insulating film 30. The data lines 62, 65, 66 and 67 are formed in the vertical direction and intersect the gate line 22 to form a data line 62 defining a pixel and a data line 62 branched from the data line 62 The source electrode 65 extended to the upper portion of the oxide semiconductor pattern 44 and the source electrode 65 are separated from the source electrode 65 and face the source electrode 65 about the channel portion of the gate electrode 26 or the oxide thin film transistor A drain electrode 66 formed on the oxide semiconductor pattern 44 and a drain electrode extension 67 extending from the drain electrode 66 and overlapping the storage electrode 27.

The data lines 62, 65, 66, and 67 may be formed of a material that directly contacts the oxide semiconductor patterns 42 and 44 to form an ohmic contact. When the data lines 62, 65, 66, and 67 are made of a material having a lower work function than the material of the oxide semiconductor patterns 42 and 44, ohmic contacts can be formed between the two layers. Therefore, when the work function of the material constituting the oxide semiconductor patterns 42 and 44 is about 5 eV or more, for example, about 5.1 to 5.3 eV, the data lines 62, 65, 66, It can be formed of a material which becomes 5.3 eV or less. The difference between the work function values of the data wirings 62, 65, 66, 67 and the oxide semiconductor patterns 42, 44 is as small as about 1.5 eV or less, which is more suitable for improving contact resistance characteristics. In order to make ohmic contact with the oxide semiconductor patterns 42 and 44, the data lines 62, 65, 66, and 67 are formed of Ni, Co, Ti, Ag, Cu, , Nb, Au, Fe, Se, Ta, or the like. An alloy including at least one element selected from Ti, Zr, W, Ta, Nb, Pt, Hf, O and N is also applicable to the metal.

Table 1 below is a table showing the work function of the metal material used as the data lines 62, 65, 66, and 67.

[Table 1]

metal Ni Co Ti Ag Cu Mo The work function (eV) 5.01 5.0 4.7 4.73 4.7 4.5 metal Al Be Nb Au Fe Se The work function (eV) 4.08 5.0 4.3 5.1 4.5 5.11

On the other hand, when the oxide semiconductor is in direct contact with a metal such as Al, Cu or Ag, the characteristics of the oxide thin film transistor employing these metals as the data lines 62, 65, 66, and 67 by mutual reaction or diffusion and / The ohmic contact characteristics with ITO or IZO generally used as electrodes can be deteriorated. Therefore, the data lines 62, 65, 66, and 67 can be formed in a double-layer structure or a triple-layer structure.

When an alloy containing Nd, Sc, C, Ni, B, Zr, Lu, Cu, Ag or the like is applied to Al or Al to the data lines 62, 65, 66 and 67, / Or a multi-layered film in which a heterogeneous film is laminated on the bottom can be applied. (Al alloy), Al (Al alloy), Al (Al alloy), Ti (Ti alloy) / Al Ti (Al alloy) / Ti (Ti alloy), Ta (Ta alloy) / Al (Al alloy) / Ta (Co alloy) / Al Ta alloy, Ta alloy, Al alloy, Al alloy, Ti alloy, Ti alloy, Ta alloy, A triple film such as Co (Co alloy) / Al (Al alloy) / Co (Co alloy), Mo (Mo alloy) / Al (Al alloy) / Mo (Mo alloy) Mo, W, Nb, Zr, V, O, N, etc. may be added to the materials indicated by the alloy.

On the other hand, when Cu or a Cu alloy is applied to the data lines 62, 65, 66, and 67, the ohmic contact characteristics between the data lines 62, 65, 66, A double film may be used in which a film containing Mo, Ti or Ta is applied between the Cu or Cu alloy film and the oxide semiconductor patterns 42 and 44 as the first, second, and third semiconductor layers 62, 65, 66, and 67. For example, a double film such as Mo (Mo alloy) / Cu, Ti (Ti alloy) / Cu, TiN (TiN alloy) / Cu, Ta (Ta alloy) / Cu, TiOx / Cu and the like can be applied.

The source electrode 65 overlaps at least a portion of the gate electrode 26 and the drain electrode 66 overlaps at least a portion of the gate electrode 26 so as to face the source electrode 65 about the channel portion of the oxide thin film transistor do.

The drain electrode extension 67 overlaps with the storage electrode 27 to form a storage capacitor with the storage electrode 27 and the gate insulating film 30 interposed therebetween. A storage capacitor connected to the drain electrode through the pixel electrode and formed in the same step as the drain electrode and formed using the counter electrode (not shown) and the storage electrode 27 formed on the storage electrode 27 And the storage capacitor may be formed by overlapping the pixel electrode and the storage electrode 27. [

On the other hand, the oxide semiconductor patterns 42 and 44 have substantially the same shape as the data lines 62, 65, 66, and 67 except for the channel portion of the oxide thin film transistor. That is, the source electrode 65 and the drain electrode 66 are separated from each other in the channel portion of the oxide thin film transistor, and the oxide semiconductor pattern 44 for the oxide thin film transistor is connected without being broken here to form a channel of the oxide thin film transistor .

A protective film 70 is formed on the data wirings 62, 65, 66, 67 and the oxide semiconductor pattern 44 exposed thereby. The protective film 70 may be formed of an inorganic film or an organic film and may have a bilayer structure of a lower inorganic film and an upper organic film to protect the oxide semiconductor pattern 44.

A contact hole 77 for exposing the drain electrode extension 67 is formed in the protection film 70.

On the protective film 70, a pixel electrode 82 is formed along the shape of the pixel. The pixel electrode 82 is electrically connected to the drain electrode extension 67 through the contact hole 77. Here, the pixel electrode 82 may be a transparent conductor such as ITO or IZO, or a reflective conductor such as aluminum.

The factors affecting the electrical characteristics of the oxide thin film transistor will be described with reference to FIGS. 2A to 2C.

FIG. 2A is an enlarged view of the area A in FIG. 1B, and shows the thickness (hereinafter referred to as a) and the thickness (hereinafter referred to as 'b') of the first area A and the second area B, respectively. In the oxide thin film transistor, appropriate thicknesses of the first region (A) and the second region (B) are required.

2B shows the electrical characteristics of the oxide thin film transistor under each condition while changing 'b' to 700 Å and changing only 'a'. Referring to FIG. 2B, when 'a' gradually decreases and the thickness of the channel layer is less than about 160 ANGSTROM, the IV characteristics of the oxide thin film transistor deteriorate due to uniformity, surface effect, and the like, .

FIG. 2C shows the electrical characteristics of the oxide thin film transistor under each condition while fixing 'a' and changing only 'b'. 2C, the first group g1 is a case where b is 1600 to 1700 Å, the second group g2 is a case where b is 1400 Å to 1500 Å, the third group g3 is a case where b is 1300 Å to 1400 Å, The fourth group g4 is a case in which b is in a range of 1100 Å to 1200 Å, the fifth group g5 is in a range of 1000 Å to 1100 Å, the sixth group g1 is in a range of 900 Å to 1000 Å, and the seventh group g7 ) Is a case where b is 800 ANGSTROM to 900 ANGSTROM. As can be seen from FIG. 2C, when the b value is increased, the threshold voltage value of the oxide thin film transistor gradually becomes a negative value. Therefore, in order to obtain a threshold voltage higher than -20 V required for driving the display device, b must have a value of 1300 ANGSTROM or less.

2B and 2C, a may be greater than about 160 ANGSTROM and less than about 1300 ANGSTROM since b is greater than a, the minimum value of a is 160 ANGSTROM and the maximum value of b is 1300 ANGSTROM. Thus, b may be greater than about 160 ANGSTROM and less than about 1300 ANGSTROM. This result of the oxide thin film transistor is considered to be due to the physical properties of the oxide layer. Therefore, according to the oxide thin film transistor substrate according to an embodiment of the present invention, the ratio of b / a may be less than 1, and may be at least 0.123 or more. In this case, the leakage current of the oxide thin film transistor can be reduced. Further, the current value at the time of turning on the oxide thin film transistor increases, and the oxide thin film transistor can have an appropriate threshold voltage.

Hereinafter, various embodiments of a method for manufacturing an oxide thin film transistor having such a suitable b / a ratio will be described with reference to FIGS. 3 to 8. FIG. FIGS. 3 to 8 are process sectional views sequentially illustrating a method of manufacturing the oxide thin film transistor substrate illustrated in FIG. 1B.

3, a multilayered metal film for gate wiring (not shown) is deposited on the insulating substrate 10 and patterned to form the gate line 22, the gate electrode 26, and the storage electrode 27, . At this time, the storage electrode 27 may not be formed according to the driving method. The gate line 22, the gate electrode 26 and the storage electrode 27 may be formed of a double film structure in which a lower film of aluminum or an aluminum alloy and an upper film of a molybdenum or molybdenum alloy are stacked. 3, a gate insulating film 30 is formed on the substrate 10, the gate wirings 22 and 26, and the storage wirings 27 and 28 by, for example, plasma enhanced chemical vapor deposition (CVD) , PECVD) or reactive sputtering.

The oxide semiconductor film 40 and the conductive film 60 for a data wiring are deposited on the gate insulating film 30 by using RF (radio frequency) sputtering or DC (direct current) sputtering, for example. In this case, when an oxide thin film transistor is manufactured using the four-mask process, the oxide semiconductor film 40 and the data wiring conductive film 60 can be continuously deposited. Therefore, in the deposition step of the oxide semiconductor film 40, It is possible to maintain a state in which the vacuum is not broken between the conductive films 60 and the deposition steps. By continuously depositing the oxide semiconductor film 40 and the data wiring conductive film 60 in one vacuum chamber without breaking the vacuum, it is possible to prevent the oxide semiconductor film 40 from being affected by oxygen in the atmosphere, So that the characteristics of the oxide thin film transistor can be further improved.

Subsequently, a photosensitive film is coated on the conductive film 60 for data wiring. The photoresist film is irradiated with light through a mask and then developed to form a photoresist pattern 114. The photoresist pattern 114 includes an exposed region C for exposing the data wiring conductive film 60 and a first thickness region A and a second thickness region B overlapping the data wiring conductive film 60 do. The first thickness region A is located between the channel portion of the oxide thin film transistor, that is, between the source electrode (65 in FIG. 1B) and the drain electrode (66 in FIG. The second thickness region (B) is located on both sides of the first thickness region (A). The first thickness region (A) is thinner than the second thickness region (B). At this time, the ratio of the thickness of the first thickness region A to the thickness of the second thickness region B may differ depending on processing conditions in an etching process to be described later.

As described above, there are various methods of varying the thickness of the photoresist layer depending on the position, and a slit, a lattice pattern, or a mask using a semitransparent film can be used to adjust the light transmittance. In addition, by using a photoresist film made of a material capable of reflowing, the photoresist film is exposed by a conventional mask, which is divided into a portion through which light is completely transparent and a portion through which light can not be completely transmitted, The first thickness region A having such a small thickness can be formed by letting a part of the photoresist film flow down.

Referring to FIG. 4, the data wiring conductive film 60 and the oxide semiconductor film 40 are etched using the photoresist pattern 114 as an etching mask. As a result of the etching, the conductive film patterns 62 and 64 and the oxide semiconductor film patterns 42 and 43 thereunder are left under the first and second thickness regions A and B, The film 60 and the oxide semiconductor film 40 are both removed and the gate insulating film 30 under the oxide film is exposed. 1B), except that the source electrode (65 in FIG. 1B) and the drain electrode (66 in FIG. 1B) of the remaining conductive film patterns 62 and 64 are connected without being separated. 66, and 67, respectively.

A method of etching the data wiring conductive film 60 and the oxide semiconductor film 40 by using the photoresist pattern 114 as an etching mask may be applied to a variety of etching methods depending on the kind of materials constituting the material and the limiting parameters of the etching process .

The data wiring conductive film 60 is formed of a double or triple film including an Mo or Mo alloy film and an Al or Al alloy film and the oxide semiconductor film 40 is formed of at least one element of Ga, The following various etching methods may be used.

According to one method, the data wiring conductive film 60 and the oxide semiconductor film 40 can be continuously wet-etched continuously using the mixed etching solution of one condition shown in Table 2 below. By continuously etching the conductive film for data wiring 60 and the oxide semiconductor film 40 in a batch manner, the manufacturing process of the oxide thin film transistor can be simplified.

According to another method, the data wiring conductive film 60 can be wet-etched and the oxide semiconductor film 40 can be dry-etched. Etching gas mixed with Ar or He may be used as the fluorine-based etching gas when the oxide semiconductor film 40 is dry-etched. CHF 3 , CF 4, and the like may be used as the fluorine-based gas. It is also possible to perform the dry etching of the oxide semiconductor film 40 using a gas containing C, H, O, or the like.

According to another method, the conductive film for data wiring 60 may be dry-etched using a fluorine-based etching gas, a chlorine-based etching gas, or a mixture gas thereof, and the oxide semiconductor film 40 may be wet-etched. When the conductive pattern 60 for data wiring is dry-etched, finer patterning can be performed due to the characteristics of anisotropic etching. Examples of fluorine-based etching gases include SF 6 , CF 4 , XeF 2 , BrF 2 , and ClF 2 , and chlorine-based etching gases include Cl 2 , BCl 3 , and HCl. For example, a mixed gas of Cl 2 and O 2 can be used for the Mo film, and a dry etching can be performed for the Al film using the mixed gas of SF 6 and Cl 2. The wet etching of the oxide semiconductor film 40 may be performed using an etchant in which deionized water is mixed with hydrofluoric acid, sulfuric acid, hydrochloric acid, or a combination thereof, or a mixed etchant under the conditions shown in Table 2 below.

According to another method, both the conductive film for data wiring 60 and the oxide semiconductor film 40 can be dry-etched.

Among the above methods, a method in which the conductive film for data wiring 60 and the oxide semiconductor film 40 are successively etched under the same etching condition is effective in terms of simplification of the manufacturing process. It is also possible that a method of advancing the etching of the data wiring conductive film 60 by wet etching so that the oxide semiconductor film 40 is not damaged by dry etching may be more effective.

[Table 2]

division One 3 2 Etching method Wet etching Wet etching Dry etching Furtherance Phosphoric acid (60 to 80 wt%)
Nitric acid (3 to 15 wt%)
Acetic acid (3 to 20 wt%)
Pure water (0 to 10 wt%)
Other additives
Ethylene glycol
(0.1 to 30 wt%)
HNO3 (0.1 to 20 wt%)
H2SO4 (0.01 to 5 wt%)
Pure water
Other additives.
O2, Cl2
(O2 / Cl2
= 0.1 to 10 (sccm / sccm)
Conductive film for data wiring
(Mo, Al, Cu, Ti, Ta)
Etching rate
60 ~ 150 A / sec 0.5 to 2 Å / sec 900 to 5400
Å / min
The oxide semiconductor film
(Ga, In, Zn, Sn, O)
Etching rate
10 ~ 30 Å / sec 10 ~ 30 Å / sec 30 ~ 300 Å / sec
Etch selectivity of the conductive film for data wiring to the oxide semiconductor film 2: 1 to 15: 1 0.017: 1 to 0.2: 1 3: 1 to 18: 1

The data wiring conductive film 60 is formed to include a film made of Mo, Ti, Ta, or an alloy film thereof and a film made of a Cu or Cu alloy film, and the oxide semiconductor film 40 is formed of Ga, In, or Zn In the case of an oxide semiconductor film containing at least one element and O, the following various etching methods can be used.

According to one method, the data wiring conductive film 60 and the oxide semiconductor film 40 are formed using a mixed etching solution of H 2 O 2 , HF (1 to 2%) and additives, phosphoric acid, nitric acid (1 to 5 wt% Sulfuric acid and an additive, or a mixed etchant of the one condition in Table 2 above. By continuously etching the conductive film for data wiring 60 and the oxide semiconductor film 40 in a batch manner, the manufacturing process of the oxide thin film transistor can be simplified. This method can be more effectively applied to the case of the conductive film 60 for a data wiring composed of a double film of Mo (Mo alloy) / Cu (Cu alloy).

According to another method, the data wiring conductive film 60 can be wet-etched and the oxide semiconductive film 40 can be dry-etched.

According to another method, when the data wiring conductive film 60 is a double film of Ti (Ti alloy) / Cu (Cu alloy) or a double film of Ta (Ta alloy) / Cu (Cu alloy) Alloy) film may be advantageous from the viewpoint of process stability by performing wet etching using an etchant containing no H 2 O 2 and dry etching the underlying Ti (Ti alloy) film or Ta (Ta alloy) film. The dry etching of Ti (Ti alloy) film or Ta (Ta alloy) film can be performed using Cl 2 , O 2 , and SF 6 as the main etching gas. In this case, the lower oxide semiconductor film 40 can be used either dry or wet etching.

5, a photoresist pattern 114 'for removing the first thickness region A of the photoresist pattern 114 by etch-back to expose the conductive film pattern 64 on the channel portion, . The remaining photoresist film on the exposed surface of the conductive film pattern 64 can be removed by an ashing process.

Next, as shown in FIG. 6, the conductive film pattern 64 exposed by the etch-back removing step is removed by wet etching, dry etching, or wet etching and dry etching. In this case, the wet etching selectivity ratio of the conductive film pattern 64 to the oxide semiconductor film 40 is preferably 2: 1 to 15: 1, and the dry etching selectivity is preferably at least 3: 1 or more Do.

The wet etching can be carried out using the mixed etching solution of the condition 1 in Table 2 above. Wet etching may also be performed using an etchant in which deionized water is mixed with hydrofluoric acid, sulfuric acid, hydrochloric acid, and combinations thereof. The dry etching can be performed by using the mixed etching gas of the two conditions shown in Table 2, or by using various dry etching methods mentioned above. When the conductive film pattern 64 is made of a double film of Ti (Ti alloy) / Cu (Cu alloy) or a double film of Ta (Ta alloy) / Cu (Cu alloy), the above- You may.

When the conductive film pattern 64 is etched, a portion of the oxide semiconductor film pattern 44 in the channel portion is etched according to the selection ratio at the time of etching, so that the b / a ratio has a value of less than 1. In this way, the data lines 62, 65, 66, and 67 are completed while the source electrode 65 and the drain electrode 66 are separated.

Then, the photoresist pattern 114 'is removed as shown in FIG. 7 to complete the data lines 62, 65, 66, and 67.

8, a protective film 70 is formed on the resultant structure, and the protective film 70 is etched to form a contact hole 77 for exposing the drain electrode extension 67. Next, as shown in FIG. In this case, if the protective film 70 is a photosensitive material, the contact hole 77 pattern is formed using a photolithography method, and if the protective film 70 is not a photosensitive material, the contact hole 77 pattern is formed through an additional photoresist mask process .

Finally, as shown in FIG. 1B, a transparent conductor such as ITO, IZO, or the like is deposited and photolithographically etched to form a pixel electrode 82 connected to the drain electrode extension 67.

FIGS. 3 to 8 illustrate a method using a four-mask process, but a five-mask process may be used to fabricate an oxide thin film transistor according to embodiments of the present invention.

In the case of applying the five-mask process, only the oxide semiconductor film 40 is first deposited, and then the oxide semiconductor film pattern 43 is etched. The etch can be etched using the etchant of Condition 1 or 2 of Table 2 above.

A conductive film 60 for a data line is formed on the entire surface of the substrate on which the oxide semiconductor film pattern 43 is formed and is etched to form a conductive film pattern 64. Thereafter, the conductive film pattern 64 of the channel portion is removed by a wet etching, a dry etching, or a wet etching and a dry etching. At this time, it is preferable that the wet etching selectivity ratio of the conductive film pattern 64 to the oxide semiconductor film pattern 43 is 2: 1 to 15: 1, and the dry etching selectivity is at least 3: 1 proper.

A part of the oxide semiconductor film pattern 44 of the channel portion is etched according to the selectivity ratio at the time of etching so that the b / a ratio has a value less than 1. In this way, the data lines 62, 65, 66, and 67 are completed while the source electrode 65 and the drain electrode 66 are separated.

The subsequent process is substantially the same as the four-mask process, so a detailed description thereof will be omitted.

The method of manufacturing an oxide thin film transistor substrate according to the present invention may include a color filter on array (COA) structure for forming a color filter on an oxide thin film transistor array or a color filter on array (AOC) for forming a color filter before forming an oxide thin film transistor array. (Array on Color filter) structure.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

1A is a layout diagram of an oxide thin film transistor substrate according to an embodiment of the present invention.

FIG. 1B is a cross-sectional view of the oxide thin film transistor substrate of FIG. 1A taken along line B-B '.

FIG. 2A is an enlarged view of the area A of FIG. 1B.

2B is an electrical characteristic diagram of an oxide thin film transistor according to an embodiment of the present invention.

2C is another electrical characteristic diagram of an oxide thin film transistor according to an embodiment of the present invention.

FIGS. 3 to 8 are cross-sectional views sequentially illustrating a method of manufacturing the oxide thin film transistor substrate illustrated in FIG. 1B.

Description of the Related Art

10: substrate 22: gate wiring

26: gate electrode 27: storage electrode

28: storage electrode line 30: gate insulating film

40: oxide semiconductor film 42, 44: oxide semiconductor film pattern

60: conductive film for data wiring 62: data line

64: conductive film pattern 65: source electrode

66: drain electrode 67: drain electrode extension part

70: Shielding film 77: Contact hole

82: pixel electrode 114: photosensitive film pattern

Claims (21)

  1. A gate wiring is formed on an insulating substrate,
    An oxide semiconductor film pattern is formed on the gate wiring, the oxide semiconductor film pattern being composed of a first region which is not in direct contact with the following data line and a second region which is thicker than the first region and which is in direct contact with the data line,
    And forming a data line directly above the second region of the oxide semiconductor film pattern to form a laminate structure of the oxide semiconductor film pattern and the data line.
  2. The method according to claim 1,
    Wherein the thickness of the first region and the thickness ratio of the second region are 0.123 or more and less than 1, respectively.
  3. 3. The method of claim 2,
    Wherein the first region has a thickness of from 160 ANGSTROM to less than 1300 ANGSTROM
  4. The method of claim 3, wherein
    The formation of the laminated structure of the oxide semiconductor film pattern and the data wiring is performed,
    An oxide semiconductor film and a conductive film for data wiring are formed on the gate wiring,
    Forming an etch mask pattern having a first thickness region corresponding to the first region, a second thickness region corresponding to the second region and thicker than the first thickness region, and an exposed region for exposing the conductive film for data wiring,
    Etching the conductive film for data wiring and the oxide semiconductor film exposed by the exposed region of the etching mask pattern,
    Removing the first thickness region of the etch mask pattern,
    And etching the conductive film for data wiring exposed by the removal.
  5. 5. The method of claim 4,
    Wherein the forming of the oxide semiconductor film and the conductive film for data wiring is continuously performed by using sputtering in one vacuum chamber.
  6. 6. The method of claim 5,
    Wherein the conductive film for data wiring includes at least one element selected from the group consisting of Al, Cu, Ti, Ta, and Mo,
    Wherein the oxide semiconductor film contains at least one element selected from the group consisting of Ga, In, Zn, and Sn and O.
  7. The method according to claim 6,
    Wherein the etching of the conductive film for data wiring and the oxide semiconductor film exposed by the exposed region of the etching mask pattern is performed continuously under the same etching conditions.
  8. 8. The method of claim 7,
    Wherein the conductive film for data wiring is etched by wet etching.
  9. 9. The method of manufacturing an oxide thin film transistor substrate according to claim 8, wherein the conductive film for data wiring is a multiple film consisting of a multilayer of a film containing Mo and a film containing Al or a film containing Mo and a film containing Cu.
  10. The method according to claim 6,
    Wherein the conductive film for data wiring comprises a lower film including Ti or Ta and an upper film including Cu,
    Wherein the etching of the conductive film for data wiring includes etching the upper film by wet etching and etching the lower film by dry etching.
  11. 3. The method of claim 2,
    The formation of the laminated structure of the oxide semiconductor pattern and the data wiring is performed,
    An oxide semiconductor film pattern is formed on the gate wiring,
    Forming a conductive film for a data wiring on the oxide semiconductor film pattern,
    The conductive film for data wiring is etched to form a conductive film pattern,
    And removing the conductive film pattern on the first region.
  12. 3. The method of claim 2,
    Wherein the work function of the data line is about 5.3 eV or less.
  13. 3. The method of claim 2,
    And the band gap of the oxide semiconductor film pattern is 3.2 to 3.4 eV.
  14. 14. The method of claim 13,
    Wherein a difference between a work function value of the data line and the oxide semiconductor film pattern is about 1.5 eV or less.
  15. The method according to claim 1,
    The data line may be formed of one selected from the group consisting of Mo (Mo alloy) / Al (Al alloy), Ti (Ti alloy) / Al (Al alloy), Ta (Ta alloy) / Al (Al alloy) ), Cu (Co alloy) / Al (Al alloy), Mo (Mo alloy) / Cu, Ti (Ti alloy) / Cu, TiN (TiN alloy) / Cu, Ta (Ti alloy) / Ti (Al alloy) / Ti (Al alloy) / Ta (Ta alloy) / Al (Ni alloy) / Al (Al alloy) / Ni (Ni alloy), Co (Co alloy) / Al (Al alloy) / TiN, Ta (Ta alloy) / Al And a triple layer of any one of Co (Co alloy) and Mo (Mo alloy) / Al (Al alloy) / Mo (Mo alloy).
  16. A gate wiring formed on an insulating substrate;
    An oxide semiconductor pattern formed on the gate wiring and composed of a first region that is not in direct contact with the data line and a second region that is thicker than the first region and that is in direct contact with the data line; And a data line formed directly on a second region of the oxide semiconductor film pattern.
  17. 17. The method of claim 16,
    Wherein the thickness of the first region and the thickness ratio of the second region are 0.123 or more and less than 1, respectively.
  18. 18. The method of claim 17,
    Wherein the first region has a thickness of from 160 ANGSTROM to 1300 ANGSTROM.
  19. 18. The method of claim 17, wherein the data line includes at least one element selected from Al, Cu, Ti, Ta, and Mo,
    Wherein the oxide semiconductor pattern includes at least one element selected from the group consisting of Ga, In, Zn, and Sn and O.
  20. The method according to claim 1,
    Wherein the data line is made of a material having a work function smaller than that of the material constituting the oxide semiconductor pattern.
  21. 17. The method of claim 16,
    Wherein the data line is made of a material having a work function smaller than that of the material constituting the oxide semiconductor pattern.
KR20070119287A 2006-11-29 2007-11-21 Method of manufacturing of oxide thin film transistor array substrate and oxide thin film transistor array substrate KR101425635B1 (en)

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US11/947,725 US7772021B2 (en) 2006-11-29 2007-11-29 Flat panel displays comprising a thin-film transistor having a semiconductive oxide in its channel and methods of fabricating the same for use in flat panel displays
US12/774,255 US7960730B2 (en) 2006-11-29 2010-05-05 Flat panel displays comprising a thin-film transistor having a semiconductive oxide in its channel and methods of fabricating the same for use in flat panel displays

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