US20120257438A1 - Contemporaneous margin verification and memory access for memory cells in cross point memory arrays - Google Patents
Contemporaneous margin verification and memory access for memory cells in cross point memory arrays Download PDFInfo
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- US20120257438A1 US20120257438A1 US13/530,009 US201213530009A US2012257438A1 US 20120257438 A1 US20120257438 A1 US 20120257438A1 US 201213530009 A US201213530009 A US 201213530009A US 2012257438 A1 US2012257438 A1 US 2012257438A1
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- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5685—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using storage elements comprising metal oxide memory material, e.g. perovskites
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0033—Disturbance prevention or evaluation; Refreshing of disturbed memory data
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0061—Timing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
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- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3431—Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
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- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
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- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
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- G11C2211/5634—Reference cells
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- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5646—Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page"
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- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
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- G11C2213/71—Three dimensional array
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- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
Definitions
- FIG. 2E depicts a schematic view of another example of a second memory structure during a second phase of read margin determination for the array depicted in FIG. 2D ;
- the remaining row conductors 155 and column conductors 157 are unselected and may be electrically coupled with some nominal voltage potential such as ground, or may be allowed to float.
- V 2 is applied to only one of the terminals of each of the un-selected memory cells 236 u
- a potential difference e.g., 2V
- a first current I 1 is approximately the sum of the leakage currents I L and the current I R (e.g., I 1 ⁇ I R +I L ).
- a current mirror (not shown) or an I/V converter (not shown) may be placed electrically in series with the selected column conductor 157 (e.g., at a node 226 ) to provide a signal that is the current or voltage equivalent of the first current I 1 . That signal may be used to charge the capacitor 234 from a reference level to a first voltage level during the first cycle.
- the direction of current flow in FIG. 2D will depend on the magnitude and polarity of the voltages V 1 and V 2 .
- V Bias voltage potential applied by voltage source V Bias rises from 0V at a time t 0 to a voltage V 4 at a time t 1 .
- the rise in voltage over tine for V Bias need not be linear.
- the terminals electrically coupled with the row conductors 155 are floating, the application of V Bias to the selected column conductor 157 creates a potential difference across those cells and generates leakage currents I L in cells 236 u and 236 ′ and a reference current I REF in reference cell 230 ′.
- a second current I 2 is the sum of the total leakage current I L+ and the reference current I REF (e.g., I 2 ⁇ I L+ +I REF ).
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Abstract
Circuitry for restoring data values in re-writable non-volatile memory is disclosed. An integrated circuit includes a memory access circuit and a sensing circuit configured to sense a data signal during a read operation to at least one two-terminal non-volatile cross-point memory array. Each memory array includes a plurality of two-terminal memory elements. A plurality of the memory arrays can be fabricated over the substrate and vertically stacked on one another. Further, the integrated circuit can include a margin manager circuit configured to manage a read margin for the two-terminal memory elements substantially during the read operation, thereby providing for contemporaneous read and margin determination operations. Stored data read from the two-terminal memory elements may have a value of the stored data restored (e.g., re-written to the same cell or another cell) if the value is not associated with a read margin (e.g., a hard programmed or hard erased state).
Description
- This application is a continuation of pending U.S. patent application Ser. No. 13/181,438, filed Jul. 12, 2011, which is a continuation of U.S. patent application Ser. No. 12/927,247, filed Nov. 9, 2010, now issued as U.S. Pat. No. 7,978,501, which is a division of U.S. patent application Ser. No. 12/284,227, filed Sep. 19, 2008, now issued as U.S. Pat. No. 7,830,701, all of which are herein incorporated by reference in their entirety for all purposes. This application is also related to U.S. patent application Ser. No. 11/095,026, filed Mar. 30, 2005, published as U.S. Pub. No. 20060171200, and to U.S. patent application Ser. No. 11/583,676, filed Oct. 19, 2006, now issued as U.S. Pat. No. 7,372,753, all of which are herein incorporated by reference in their entirety for all purposes.
- The present invention relates generally to memory technology. More specifically, the present invention relates to data retention in non-volatile memory.
- Non-volatile memory is a type of data storage device in which stored data is retained in the absence of power. That is, data that was previously written to the non-volatile memory remains stored in the memory without substantial degradation of the value of the stored data after electrical power is removed from the non-volatile memory. However, some forms of non-volatile memory may be susceptible to degradation of the value of stored data due to several factors including passage of time, disturbs caused by successive read operations to a non-volatile memory cell, disturbs caused by half-select voltages applied to non-volatile memory cells, just to name a few. For example, disturbances in a non-volatile two-terminal cross-point memory array can degrade the margins, such as read margins, associated with non-volatile two-terminal memory cells positioned in the array, thereby leading to corrupted data or incorrect data being read from the array. Margins often describe the tolerance for a memory cell to provide accurate data (e.g., data representing values for a logic “0” or a logic “1”) during, for example, a read operation when the memory cells are exposed to memory disturb effects caused by the application of a read voltage across the two terminals of the memory cell. Generally, data retention is the ability of the memory to retain stored data without corruption of the stored data due to any number of effects including but not limited to the aforementioned passage of time or disturbs to the memory cells caused by applied voltages.
- To maintain appropriate read margins in environments that degrade memory cells, some conventional approaches test whether a specific memory cell can deliver voltages and/or currents that satisfy margin requirements during a margin test operation. Usually, the margin test operation is performed as a separate process that consumes memory support circuitry resources during the margin testing, typically at the expense of other memory device processes. Further, conventional approaches typically require dedicated sense amplifiers and reference cells to determine the read margins. Thus, the drawbacks to conventional approaches usually include an increased amount of circuitry and/or delayed memory operations (e.g., reading and writing) due to the margin testing. As one example, for memory cells that store data as a resistance value where a logic “0” is a high resistance (e.g., 10 MΩ) and a logic “1” is a low resistance (e.g., 100 kΩ)), for a constant value of a read voltage (e.g., 3 V), a low read current will flow through a memory cell storing the high resistance logic “0” and a high read current will flow thorough a memory cell storing the low resistance logic “1”. Accordingly, circuitry, such as a sense amp, can determine the value of stored data in a memory cell by sensing the magnitude of read current flowing through the memory cell during a read operation. However, if the resistance values for logic “0” and logic “1” drift in value and/or are corrupted by disturbs, then the magnitude of the read currents will also be affected and the sense amp may not be able to accurately determine the value of the stored data. Consequently, incorrect data values may be obtained during read operations to the memory due to corrupted data.
- There are continuing efforts to improve data retention in non-volatile memory.
- The invention and its various embodiments are more fully appreciated in connection with the following detailed description taken in conjunction with the accompanying drawings, in which:
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FIG. 1 depicts an integrated circuit including a margin manager circuit for managing margins for re-writable memory cells disposed in a single layer or in multiple layers of memory; -
FIG. 2 depicts a portion of an integrated circuit including a margin manager circuit; -
FIG. 2A depicts a schematic view of at least a portion of a memory array including a plurality of memory cells and optionally, at least one reference cell; -
FIG. 2B depicts a schematic view of one example of a first memory structure during a first phase of a data operation for the array depicted inFIG. 2A ; -
FIG. 2C depicts a schematic view of one example of a second memory structure during a second phase of the data operation for the array depicted inFIG. 2A ; -
FIG. 2D depicts a schematic view of another example of a first memory structure during a first phase of a data operation to an array including a plurality of reference cells; -
FIG. 2E depicts a schematic view of another example of a second memory structure during a second phase of read margin determination for the array depicted inFIG. 2D ; -
FIG. 3 is a diagram depicting charge and discharge rates as applied to read margin management; -
FIG. 4 is a diagram depicting the generation of signal samples for determining margins; -
FIG. 5 is a timing diagram depicting the sampling of signals; -
FIG. 6 depicts a cross-sectional view of an example of an integrated circuit implementing a margin manager; -
FIG. 7 depicts a block diagram of a memory access circuit implementing a representative margin manager to reduce effects of memory disturbs in association with read margins; -
FIG. 8 is a timing diagram depicting management of margins for multi-level cells; and -
FIG. 9 depicts an exemplary state table for the timing diagram shown inFIG. 8 . - Like reference numerals refer to corresponding parts throughout the several views of the drawings and the drawings are not necessarily to scale.
- Various embodiments or examples of the invention may be implemented in numerous ways, including as a system, a process, an apparatus, or a series of program instructions on a computer readable medium such as a computer readable storage medium or a computer network where the program instructions are sent over optical, electronic, or wireless communication links. In general, operations of disclosed processes may be performed in an arbitrary order, unless otherwise provided in the claims.
- A detailed description of one or more examples is provided below along with accompanying figures. The detailed description is provided in connection with such examples, but is not limited to any particular example. The scope is limited only by the claims, and numerous alternatives, modifications, and equivalents are encompassed. Numerous specific details are set forth in the following description in order to provide a thorough understanding. These details are provided as examples and the described techniques may be practiced according to the claims without some or all of the accompanying details. For clarity, technical material that is known in the technical fields related to the examples has not been described in detail to avoid unnecessarily obscuring the description.
- U.S. patent application Ser. No. 11/095,026, filed Mar. 30, 2005, published as U.S. Pub. No. 20060171200, and entitled “Memory Using Mixed Valence Conductive Oxides,” is hereby incorporated by reference in its entirety for all purposes and describes non-volatile third dimensional memory elements that may be arranged in a two-terminal, cross-point memory array. In at least some embodiments, a two-terminal memory element can be configured to change conductivity when exposed to an appropriate voltage drop across the two terminals of the memory element. The memory element can include an electrolytic tunnel barrier and a mixed valence conductive oxide. Application of a write voltage of appropriate magnitude and polarity across the two terminals of the memory is operative to generate an electrical field within the mixed valence conductive oxide that is strong enough to move oxygen ions out of the mixed valence conductive oxide and into the electrolytic tunnel barrier. When certain mixed valence conductive oxides (e.g., praseodymium-calcium-manganese-oxygen (PCMO) perovskites and lanthanum-nickel-oxygen (LNO) perovskites) change valence, their conductivity changes. Additionally, oxygen accumulation in certain electrolytic tunnel barriers (e.g., yttrium stabilized zirconia (YSZ) can also change conductivity. If a portion of the mixed valence conductive oxide near the electrolytic tunnel barrier becomes less conductive, the tunnel barrier width effectively increases. If the electrolytic tunnel barrier becomes less conductive, the tunnel barrier height effectively increases. Both mechanisms can be reversible if the excess oxygen from the electrolytic tunnel barrier flows back into the mixed valence conductive oxide. A memory can be designed to exploit tunnel barrier height modification, tunnel barrier width modification, or both.
- Both the electrolytic tunnel barrier and the mixed valence conductive oxide do not need to operate in a silicon substrate, and, therefore, can be fabricated above circuitry formed on the substrate, such as memory access circuits for performing data operations on the cross-point array(s) and/or circuitry being used for other purposes. Further, a two-terminal memory element can be arranged as a cross point such that one terminal is electrically coupled with an X-direction line (or an “X-line”) and the other terminal is electrically coupled with a Y-direction line (or a “Y-line”). A third dimensional memory can include multiple memory elements vertically stacked upon one another, sometimes sharing X-direction and Y-direction lines in a layer of memory, and sometimes having isolated lines. When a first write voltage VW1, is applied across the memory element (e.g., by applying ½ VW1 to the X-direction line and ½-VW1 to the Y-direction line), the memory element can switch to a low resistive state. When a second write voltage, VW2, is applied across the memory element (e.g., by applying ½ VW2 to the X-direction line and ½-VW2 to the Y-direction line), the memory element can switch to a high resistive state. Memory elements using electrolytic tunnel barriers and mixed valence conductive oxides can have VW1 opposite in polarity from VW2.
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FIG. 1 depicts anintegrated circuit 100 including a margin manager circuit for managing margins for re-writable memory cells disposed in asingle layer 151 or in multiple layers ofmemory 150, according to various embodiments of the invention. In this example, integratedcircuit 100 is shown to include eithermultiple layers 150 of memory (e.g., layers 152 a, 152 b, . . . 152 n) or asingle layer 151 ofmemory 152 formed on a base layer 154 (e.g., a silicon wafer). In at least some embodiments, eachlayer 152 of memory can be associated with across point array 153 that includes conductive array lines (155, 157) arranged in different directions (e.g., substantially orthogonal to one another) to accessmemory elements 156, which can be two-terminal memory cells. For example,conductors 155 can be X-direction array lines (e.g., row conductors) andconductors 157 can be Y-direction array lines (e.g., column conductors). In some embodiments, a two-terminal memory cell can have a programmable resistivity operative to store data as a plurality of conductivity profiles.Base layer 154 can include a bulk semiconductor substrate upon which circuitry, such as memory access circuits, can be formed. In at least some embodiments,base layer 154 can be configured asbase layer 154 a upon which circuitry including but not limited to amargin manager circuit 160, asensing circuit 170 and amemory access circuit 180 are formed.Memory access circuit 180 can be configured to perform various memory access operations, such as write operations, read operations, and restore operations in association with re-writable memory cells.Margin manager circuit 160 is electrically coupled with areference signal 161 from a reference memory cell and adata signal 163 a from a memory cell selected for a read operation.Sensing circuit 170 can be configured to receive adata signal 163 a viapath 173 during a memory access operation, such as a read operation, to determine the state of the data stored in the selected memory cell.Sensing circuit 170 can also be configured to receive thereference signal 161 viapath 173. Thepath 173 can be a single interconnect structure or can be a bus structure that supports multiple interconnects. In at least some embodiments, the data signal 163 a (e.g., a read current) can be indicative of the value of stored data in the selected memory cell (e.g., one of the plurality of conductivity profiles).Margin manager circuit 160 can be configured to manage a margin, such as a read margin, for a memory cell. In at least some embodiments,margin manager circuit 160 can be configured to manage the read margin as a function of time. - As shown,
margin manager circuit 160 can include amargin detector 162 andmargin restoration circuit 164.Margin detector 162 can be configured to detect viapath 171 whether the re-writable memory cell is associated with a specified level of read margin for a value (e.g., a logic value) representative of a state of stored data. Responsive to the detection of a non-specified level of read margin bymargin detector 162,margin restoration circuit 164 can be configured to re-write a state into re-writable memory cell to restore the read margin to the specific level of read margin. In at least some embodiments,margin manager circuit 160 can be configured to contemporaneously detect read margins requiring restorations and to read data from the re-writable memory cells, and can be further configured to restore the read margin at any time after a read operation has been initiated by, for example,memory access circuit 180.Margin restoration circuit 164 can communicate at least one control signal viapath 175 to activatememory access circuit 180, the control signal optionally including the value to be written in the memory cell in order to restore the read margin. In at least some embodiments,margin manager circuit 160 can be configured to control sensing circuit 170 (e.g., via path 173) to determine the read margin and to read the value of the stored data out from the re-writable memory cell. - In view of the foregoing, the structures and/functionalities of
integrated circuit 100 can provide for contemporaneous (or substantially contemporaneous) margin detection and read operation. By combining margin detection and read operation processes,margin manager circuit 160 can thereby facilitate a reduction of memory accesses that otherwise might be performed for a dedicated margin testing operation. Further,multiplicative sensing circuits 170 need not be implemented to perform margin testing operations sincemanager circuit 160 can controlsensing circuit 170 to both determine the read margin and read data values of the stored data. - As used herein, the term “specified level” can refer, at least in some embodiments, to a threshold (or a range) that specifies a margin, such as a read margin, whereby a memory cell being associated with a read margin can be consider as having a sufficient margin if the memory cell surpasses a specified level. A threshold (or a range) can be expressed in terms of parameter values or magnitudes of the data signal, such as voltages, currents, resistances, etc. When a memory cell is associated with a specified level of read margin, the memory cell can be described as being in a “hard” state. That is, it is either sufficiently programmed or sufficiently erased to provide data signals that can accurately convey the state of stored data in the memory cell. By contrast, if the memory cell is not associated with specified level of read margin (or is associated with a different range), then the memory cell can be described as being in a “soft state.” That is, the memory cell is not sufficiently programmed or not sufficiently erased. Thus, the data signal may not provide an accurate representation of the state of stored data in the memory cell, as sensed by sensing
circuit 170. In at least some embodiments, a specified level of read margin can refer to a specific resistance value as a threshold, or a range of resistance values that represent either a programmed state or an erased state, whereas another range of resistance values can be indicative of not having a specified level of read margin for either a programmed state or an erased state. - In at least some embodiments,
margin manager 160 can be configured to determine whether a value of resistance (e.g., as indicated by a data signal) is associated with a first range of resistances that specify a read margin. For example, the first range of resistances can indicate a hard state for a state stored in the memory cell, whereby the stored state is solidly programmed or erased. Thus, a hard state can be either a “hard programmed state” if a data signal specifies a value indicating a programmed value (e.g., such as “0”), or a “hard erased state” if the data signal specifies a value indicating an erased value (e.g., such as “1”). Generally, hard states can be relatively immune to read failure due to disturb-related effects or other extraneous factors. But note thatmargin manager 160 can be configured to determine whether the value of resistance is associated with a second range of resistances for the read margin. Further to the example, consider that the second range of resistances can indicate a soft state for a state stored in the memory cell, whereby the stored state is weakly programmed or erased. Thus, a soft state can be a “soft programmed state” if the data signal specifies a programmed value (e.g., such as “0”) for the second range of resistances, or a “soft erased state” if the data signal specifies an erased value (e.g., such as “1”) for the same range of resistances. Generally, the soft programmed state and soft erased state can be relatively susceptible to read failure due to disturb-related effects or other extraneous factors.Margin restoration circuit 164 can be configured to change an association for the re-writable memory cell to the first range of resistances (e.g., to a hard state) from the second range of resistances (e.g., from a soft state), thereby restoring the read margin to a specified level of read margin. As used herein, the term “state” can refer, at least in some embodiments and contexts, to the datum or data stored in a memory cell. For example, a state can be a logic value of “0” or “1” for a single bit of data or can include logic values for data, such as “00”, “01”, “10”, and “11” for a memory cell that stores multi-bit data, that is two or more bits of data. As used herein, the term “value” can refer, at least in some embodiments and contexts, to a quantity or amount of some parameter, such as a value of resistance that represents the presumed state of stored data in a memory cell. The states of “0” and “1” can be represented by values (e.g., magnitudes of currents) that correspond to, and are sensed as, “0” and “1”, by circuitry, such as thesensing circuit 170, for example. However, disturb effects can cause a value to degrade thereby causing the value to represent the wrong state. For example, consider the case in which a programmed cell (e.g., having a logic value of “0”) experiences disturb-related effects and the read margin becomes insufficient. Thus, the value of the programmed cell may represent an incorrect state (i.e., the value might incorrectly indicate that the memory cell includes a logic value of “1”, which is incorrect and contrary to the logic “0” state that actually was programmed. In essence, degradation can lead to data corruption if steps are not taken to maintain read margins within acceptable levels. -
FIG. 2 illustrates a portion of an integrated circuit including a margin manager circuit, according to various embodiments of the invention. In this example,portion 200 of an integrated circuit is shown to include amargin manager 201, at least onereference memory cell 230 and a memory cell 236 (e.g., selected for a read operation) positioned in one or more layers ofmemory 290, asense amplifier 250, and amemory access circuit 280 configured to perform read and write operations, as well as any other type of memory access operations. In at least some embodiments,reference memory cell 230 can be configured to generate a reference signal representing a reference current. The reference current can be generated by applying a voltage of a predetermined magnitude and polarity across terminals (235, 237) of thereference memory cell 230. For example, the applied voltage can be the read voltage that is applied across the selectedmemory cell 236 during a read operation. In some embodiments, the reference current may be included with other currents such as leakage currents and/or half-select currents generated by other memory cells during data operations. As one example, the leakage currents may be generated by the same group of memory cells during a data operation, such as a group of un-selected memory cells positioned on the same column or row as a selected memory cell during a read operation. Thus,reference memory cell 230 can be modeled as a reference current source 232 (or a sink, in some cases). Similarly,memory cell 236 can be configured to generate a signal representing a current, which can be combined with other currents such as leakage currents (e.g., leakage currents identical to those generated by the above mentioned group of memory cells) and/or half-select currents generated by other memory cells during data operations. Those currents may compensate for the extraneous currents associated with the reference current. Thus,memory cell 236 can be modeled as a current sink 238 (or a source, in some cases). U.S. patent application Ser. No. 11/583,676, filed Oct. 19, 2006 and entitled “Two-Cycle Sensing In A Two-Terminal Memory Array Having Leakage Current”, now U.S. Pat. No. 7,372,753, and already incorporated herein by reference, describes circuitry and methods for sensing the value of stored data in a memory cell (e.g., as a read current) using leakage current subtraction in one embodiment to subtract leakage currents generated by un-selected memory cells that are on the same row or column as the selected memory cell. Sensing occurs in two cycles, where in one cycle, the sensed current is a total current comprised of the read current plus the leakage currents (e.g., from a first memory structure including the selected memory cell and un-selected memory cells) and in a second cycle, the sensed current comprises the leakage currents (e.g., from a second memory structure including the reference memory cell and un-selected memory cells). The currents sensed during the two cycles are subtracted to generate a data signal that is compared with a reference signal generated by a reference cell. A comparison circuit outputs a value indicative of the data stored in the selected memory cell. For example, the data signal and reference signal may be currents that are converted into voltages by I/V converters. The voltages from the I/V converters are compared to each other and if the voltage for the data signal is greater than the voltage for the reference signal, then the comparison circuit outputs a first voltage indicative of a first logic value (e.g., a logic “0”). On the other hand, if the voltage for the data signal is less than the voltage for the reference signal, then the comparison circuit outputs a second voltage indicative of a second logic value (e.g., a logic “1”). Currents generated by the reference cell and currents flowing in the row and/or column lines of the selected memory cell can be sensed by current mirror circuits that are electrically in series with the reference cell and the row and/or column lines. - In regard to the aforementioned first and second memory structures, the selected memory cell and the un-selected memory cells can be positioned on the same row or column of a two-terminal cross-point memory array. As one example, for the first memory structure, the selected memory cell can have one of its terminals electrically coupled with a selected row conductive array line and the other terminal electrically coupled with a selected column conductive array line. The un-selected memory cells can have one of their terminals electrically coupled with the same column conductive array line as the selected memory cell and the other of their terminals electrically coupled with a different row conductive array line.
- As another example, for the second memory structure, the un-selected memory cells can have their terminals electrically coupled as described in the above example; however, the second memory structure may include the reference memory cell. The terminals of the un-selected memory cells that are electrically coupled with the same column conductive array line as the selected memory cell and one of the terminals of the reference memory cell may be electrically coupled with the same voltage potential (e.g., a bias voltage that may be initially 0V and rise to a voltage of about 100 mV to about 200 mV). The other terminal of the reference memory cell may be electrically coupled with another voltage potential, such as a reference voltage or may be allowed to float, for example. In some applications, the reference voltage may be a read voltage potential or some other reference level voltage.
- Reference is now made to
FIG. 2A where thecross-point array 153 is depicted in schematic form. For purposes of illustration, thearray 153 includes four rows oriented in arow direction 221 r (r0, r1, r2, r3) that is aligned with an X-axis of coordinatesystem 221 and four columns oriented in acolumn direction 221 c (c0, c1, c2, c3) that is aligned with a Y-axis of 221. There are 16memory cells 236 positioned at a cross-point of one of therow conductors 155 with one of thecolumn conductors 157. One terminal of eachmemory cell 236 is connected to only one of therow conductors 155 and the other terminal of eachmemory cell 236 is connected to only one of thecolumn conductors 157. Thearray 153 may include at least onereference cell 230 with its terminal (235, 237) electrically coupled withconductive lines reference cell 230 may be positioned external to thearray 153 or may be positioned in a row or column of thearray 153 as will be described in greater detail below. - Turning now to
FIG. 2B , during a first phase of a data operation (e.g., a read margin determination) afirst memory structure 295 includes a selected memory cell denoted as 236′ positioned in row r2 and column c2. Other un-selected memory cells in the same column c2 as the selectedmemory cell 236′ are denoted as 236 u. Eachun-selected memory cell 236 u has one terminal electrically coupled with thesame column conductor 157 as the selectedmemory cell 236′ and the other terminal electrically coupled with arow conductor 155 that is different than therow conductor 155 for selectedmemory cell 236′. During the first phase, voltage potentials V1 and V2 are applied to the row andcolumn conductors 155 and 157 (shown in heavy line) for r2 and c2 such that the selectedmemory cell 236′ is selected for a data operation (e.g., read margin determination) and a current IR (e.g., a read current) flows through thememory cell 236′. As one example, the voltage potentials may be a read voltage with V1 applying +2V to selectedrow conductor 155 and V2 applying −2V to selectedcolumn conductor 157, such that a potential difference across selectedmemory cell 236′ is approximately 4V. The remainingrow conductors 155 andcolumn conductors 157 are unselected and may be electrically coupled with some nominal voltage potential such as ground, or may be allowed to float. In that V2 is applied to only one of the terminals of each of theun-selected memory cells 236 u, a potential difference (e.g., 2V) is applied across theun-selected memory cells 236 u and generates a leakage current IL that flows through eachcell 236 u. A first current I1 is approximately the sum of the leakage currents IL and the current IR (e.g., I1≈IR+IL). A current mirror (not shown) or a current-to-voltage converter (I/V converter) (not shown) may be placed electrically in series with the selected column conductor 157 (e.g., at a node 224) to provide a signal that is the current or voltage equivalent of the first current I1. That signal may be used to charge thecapacitor 234 from a reference level to a first voltage level during the first cycle. One skilled in the art will appreciate that the direction of current flow inFIG. 2B will depend on the magnitude and polarity of the voltages V1 and V2. - Moving now to
FIG. 2C , during a second phase of the data operation asecond memory structure 296 includes theun-selected memory cells 236 u and areference cell 230 selected for the data operation. As one example of how thereference cell 230 can be selected for the data operation, terminal 235 is electrically coupled with aconductive line 222 and terminal 237 is electrically coupled with aconductive line 223.Conductive line 223 is electrically coupled with selectedcolumn conductor 157 and a voltage source VBias. Conductive line 222 is electrically coupled with a voltage source VREF. The selectedrow conductor 155 is electrically coupled with a voltage source V3 such that leakage currents IL flow throughcells reference cell 230 also generates a reference current IREF. A second current I2 is the sum of the total leakage current IL+ and the reference current IREF (e.g., I2≈IL+IREF). During the second phase, the second current I2 can be used to discharge thecapacitor 234 to a second voltage. A current mirror (not shown) or an I/V converter (not shown) may be placed electrically in series with the selected column conductor 157 (e.g., at a node 225) to provide a signal that is the current or voltage equivalent of the second current I2. The voltage source V3 may apply a potential such as a read voltage potential (e.g., 2V) to therow conductors 155. The voltage source VBias may apply a substantially constant voltage potential. On the other hand, the voltage source VBias may apply a voltage potential V that rises over time T from some lower voltage value (e.g., ≈0V or ground potential) to a higher voltage value (e.g. in a range from about 100 mV to about 200 mV) as depicted by a graph where the voltage potential applied by voltage source VBias rises from 0V at a time t0 to a voltage V4 at a time t1. The rise in voltage over time for VBias need not be linear as depicted inFIG. 2C . The voltage source VREF may apply a potential that is substantially equal to that of voltage source V3, some other voltage such as ground potential, or theterminal 235 of thereference cell 230 may be allowed to float. - Referring now to
FIGS. 2D and 2E , in an alternate embodiment, a two-terminal cross-point array can include a plurality ofreference cells 230 positioned in one or more rows or one or more columns of the array. InFIG. 2D , anarray 253 includes a fifth row denoted as r4 having a plurality ofreference cells 230 with eachreference cell 230 having oneterminal 235 in electrical communication with asingle row conductor 155 and theother terminal 237 in electrical communication with asingle column conductor 157. As was described above in reference toFIG. 2B , during a first phase of a data operation (e.g., a read margin determination), afirst memory structure 297 includes a selected memory cell denoted as 236′ positioned in row r2 and column c2. Other un-selected memory cells in the same column c2 as the selectedmemory cell 236′ are denoted as 236 u. Additionally, column c2 includes a reference cell denoted as 230′ that is affected by the data operation to the selected memory cell as 236′. Eachun-selected memory cell 236 u and thereference cell 230′, has one terminal electrically coupled with thesame column conductor 157 as the selectedmemory cell 236′ and the other terminal electrically coupled with arow conductor 155 that is different than therow conductor 155 for selectedmemory cell 236′. During the first phase, voltage potentials V1 and V2 are applied to the row andcolumn conductors 155 and 157 (shown in heavy line) for r2 and c2 such that the selectedmemory cell 236′ is selected for a data operation and a current IR flows through thememory cell 236′. As was described above, V1 and V2 may be +2V and −2V respectively. The remainingrow conductors 155 andcolumn conductors 157 are unselected and may be electrically coupled with some nominal voltage potential such as ground, or may be allowed to float. In that V2 is applied to only one of the terminals of each of theun-selected memory cells 236 u and thereference cell 230′, a potential difference (e.g., ≈2V) is applied across theun-selected memory cells 236 u and thereference cell 230′. As a result, a leakage current IL flows throughcells capacitor 234 from a reference level to a first voltage level during the first cycle. One skilled in the art will appreciate that the direction of current flow inFIG. 2D will depend on the magnitude and polarity of the voltages V1 and V2. - Moving now to
FIG. 2E , during a second phase of the data operation asecond memory structure 298 includes theun-selected memory cells 236 u and thereference cell 230. Preferably,row conductors 155 are allowed to float. A voltage source VBias is electrically coupled with the selectedcolumn conductor 157. Voltage source VBias may apply a substantially constant voltage potential or, as was described above in reference toFIG. 2C , the voltage source VBias may apply a voltage potential V that rises over time T from some lower voltage value to a higher voltage value as depicted by the graph inFIG. 2C , where the voltage potential applied by voltage source VBias rises from 0V at a time t0 to a voltage V4 at a time t1. The rise in voltage over tine for VBias need not be linear. Although the terminals electrically coupled with therow conductors 155 are floating, the application of VBias to the selectedcolumn conductor 157 creates a potential difference across those cells and generates leakage currents IL incells reference cell 230′. A second current I2 is the sum of the total leakage current IL+ and the reference current IREF (e.g., I2≈I L++IREF). During the second phase, the second current I2 can be used to discharge thecapacitor 234 to a second voltage. A current mirror (not shown) or an I/V converter (not shown) may be placed electrically in series with the selected column conductor 157 (e.g., at a node 228) to provide a signal that is the current or voltage equivalent of the second current I2. - Referring again to
FIG. 2 ,margin manager 201 can include amargin detector 202 and a margin restoration circuit 270. Further,margin manager 201 can include acapacitive element 234 coupled withsense amplifier 250, aswitch 240 coupled with areference memory cell 230 and thecapacitive element 234, and aswitch 242 coupled with thememory cell 236 and thecapacitive element 234.Margin manager 201 can be configured to determine a rate at which a current flows fromcapacitive element 234, whereby the rate specifies whether the read margin formemory cell 236 is associated with a specified level of read margin. Thus, specified levels of read margin can be expressed as a function of time, such as capacitor discharge rates, andmargin manager 201 can be configured to detect various capacitor discharge rates and determine whether any of the various capacitor discharge rates are indicative of one or more specified levels of read margin. - Further to
FIG. 2 ,margin detector 202 can include asampling controller 210, asampler 212, and amargin determinator 218. In operation,sampling controller 210 can be configured to activateswitch 240 during a first phase (e.g., of a read operation) to chargecapacitive element 234 and to activateswitch 242 during a second phase (e.g., of the read operation) to dischargecapacitive element 234. In the first phase,reference memory cell 230 provides a reference signal viaswitch 240 tocapacitive element 234, whereasmemory cell 236 provides a signal viaswitch 242 tocapacitive element 234 during a second phase.Sampler 212 can be configured to activatesense amplifier 250 multiple times during, for example, a read operation to perform contemporaneous reads and margin determinations. In at least some embodiments,margin determinator 218 can be configured to sense differences between a reference current fromreference memory cell 230 and a current frommemory cell 236, wherebymargin determinator 218 can determine read margins based on the differences in currents (e.g., as perceived or detected, based on the charge and discharge rates of capacitive element 234).Capacitive element 234 can be at least one capacitor, an inherent and/or parasitic capacitance of at least one or more of the array lines (e.g., 155 and/or 157), at least onememory cell 236, at least onereference memory cell 230, or any other structure capable of storing charge. For example, thememory cell 236 and its associated electrodes can be used as thecapacitive element 234 with the electrodes operative as the plates of the capacitor and the electrolytic tunnel barrier in contact with a conductive metal oxide (CMO) material or a mixed valence conductive oxide operative as the dielectric of the capacitor. In that a structure for thereference memory cell 230 can be substantially identical to that of thememory cells 236, thereference memory cell 230 can also be used as thecapacitive element 234. In some embodiments, at least onereference memory cell 230 can be used to generate the reference signal (e.g., a reference current) and at least one otherreference memory cell 230 can be used as thecapacitive element 234. If a plurality of thereference memory cells 230 or a plurality of thememory cells 236 are used as thecapacitive element 234, then they can be connected in parallel, in series, or in series/parallel combination to obtain the desired value of capacitance. - In operation,
margin manager 201 can be activated in response to an access tomemory layers 290, such as during a read operation. Once a read operation is active,margin manager 201 can be configured to receive a reference signal in association withreference memory cell 230. During one phase,sampling controller 210 can activateswitch 240 to chargecapacitive element 234 using the reference signal, such as a reference current IREF. During another phase,sampling controller 210 can activateswitch 242 to accesscapacitive element 234 bycoupling memory cell 236 tocapacitive element 234. In this phase,sampler 212 can be configured to sample a signal, such as a read current IRead, associated withmemory cell 236 at multiple points in time to generate signal samples, according to various embodiments.Sampler 212 activatessense amplifier 250 at the multiple points to generate the signal samples ascapacitive element 234 is discharging. In at least one embodiment,sense amplifier 250 includes asingle sense amplifier 250 to generate the signal samples. Thesingle sense amplifier 250 can be electrically coupled with a single conductive array line such as a column line or a row line. Themargin manger 201 and/or thesampling controller 210 can determine which phase occurs first in time. -
Sampler 212 is configured to sample the signal coextensive (and/or substantially coextensive) with the sampling of a value (e.g., a logic value) representative of the stored data inmemory cell 236 during a period of time. In at least some embodiments,sampler 212 can include astate sampler 214 and amargin sampler 216.State sampler 214 can be configured sample the signal associated withmemory cell 236 at a specific point (or multiple points) in time at whichsense amplifier 250 can sense the value of the stored data inmemory cell 236. Therefore,state sampler 214 can sample the value of data stored inmemory cell 236 viapath 252 to determine a “read sample” as part of a read operation, whereby the read sample represents the read data (e.g., as sensed by sense amplifier 250). In one embodiment, the specific point (or multiple points) in time at whichsense amplifier 250 senses the value of the stored data is determined as a function of the rate at whichcapacitive element 234 is charged.Margin sampler 216 can be configured to sample the signal viapath 252 to determine “margin samples” at one or more times either prior to or subsequent to, or both (e.g., both before and after) the specific point (or multiple points) in time at whichstate sampler 214 samples the signal to read the value of the stored data. -
Margin determinator 218 can be configured to interpret the signal samples generated bysampler 212 viapath 243 to determine whethermemory cell 236 is associated with a specified level of read margin for the value representative of the stored data. A signal sample can either be a read sample or a margin sample, or both.Margin determinator 218 can detect that the value representative of the stored data changes to another value during a period of time specified as thesampler 212 generates signal samples at multiple points in time. For example, ifmargin determinator 218 detects that the value representative of the stored data changes to another value during the period of time the signal samples are generated, thenmargin determinator 218 can identify thatmemory cell 236 does not have the specified level of read margin. In some embodiments,margin determinator 218 can determine magnitudes (or approximations thereof) for the signal samples, and then analyze whether the magnitudes for the signal samples are associated with a range of magnitudes for the specified level of read margin. For example,margin determinator 218 can determine that at least one of the magnitudes for the signal samples is not associated with the range of magnitudes. Since one or more magnitudes are not associated with the specified level of read margin,margin determinator 218 can determine thatmemory cell 236 does not have sufficient read margin (e.g.,memory cell 236 is associated with either soft programmed or soft erased states). - Margin restoration circuit 270 can be configured to restore an association between
memory cell 236 and a specified level of read margin. For example, margin restoration circuit 270 can causememory access circuit 280 to generate a write operation to write (or re-write) the value of the stored data intomemory cell 236 to ensure that a sufficient read margin is restored tomemory cell 236. Margin restoration circuit 270 can be configured to restore the read margin to a specified level of read margin at any time, such as during the read operation or at any time subsequent thereto. In at least some embodiments,margin detector 202 can store data representing the magnitudes of the signal samples (e.g., 1,1,1, or 0,1,1) via path 260 in a sample repository, which, in some cases, can be part of memory layers 290. For example, a portion of the memory cells in one or more of the layers of memory can be used as data storage space for the sample repository. Margin restoration circuit 270 can be configured to retrieve the stored data viapath 262 from a portion of a cross point array, such as in memory layers 290. - In at least some embodiments, read margins can be characterized by rates at which a current is discharged from a capacitor, whereby the rates can be graphically represented as different profiles. A determination whether a
memory cell 236 has sufficient read margin (i.e., a specified level of read margin) can be made by comparing a profile for a rate at which the capacitor is discharged (subsequent to charging the capacitor with a current from the memory cell 236). Then,margin determinator 218 can determine whether the rate is associated with a group of rates that is indicative of a specified level of read margin. In some embodiments, margin restoration circuit 270 can be configured to restore a resistance value to the memory cell, whereby the restored resistance value provides for rates at which the current is discharged from the capacitor that are associated with the group of rates. - Note that
reference memory cell 230 can be positioned within or without the one or more layers ofmemory 290 that includememory cell 236. In at least some embodiments,margin manager 201 can operate on every read access, or can be configured to operate during specific predetermined read operations (or can operate to perform random contemporaneous reads and margin determinations). In some cases,margin manager 201 can operate at the expiration of any time interval that is sufficient to detect and restore specified levels of margin. Although only onesense amp 250 is depicted inFIG. 2 ,portion 200 can include a plurality of sense amps (not shown) operative to provide page mode reads from a plurality of selectedmemory cells 236 during a read operation. The circuitry for theswitches capacitive element 234 can be replicated for determining read margins for n-bits of data (e.g., one or more bytes of data). Page mode reads can also be effectuated by a usingsingle sense amp 250,switch 240, andcapacitive element 234; however, theswitch 242 is modified to selectively switch among a plurality of selectedmemory cells 236. For example, modifiedswitch 242 can be activated bymargin manager 201 to selectively switch from a first selectedmemory cell 236 to a second selectedmemory cell 236, and so on, to an “n-th” selectedmemory cell 236. As one example, theswitch 242 can be configured to switch among eightmemory cells 236 to effectuate a page mode read for a byte of data. For each selectedmemory cell 236, theswitches memory cell 236 to be determined as was described above. After the read margin for the currently selectedmemory cell 236 is determined, theswitch 242 is activated to switch to thenext memory cell 236 so that its read margin can be determined. Theswitch 242 is repeatedly activated until switched to the “n-th” selected memory cell 236 (e.g., the eighth cell for a byte of data). -
FIG. 3 is a diagram 300 depicting charge and discharge rates as applied to read margin management, according to various embodiments of the invention. In this example, agraph 302 and agraph 330 respectively depict rates of charging a capacitive element during one phase and discharging the capacitive element during a subsequent phase. As shown ingraph 302, the rate of charging a capacitive element is depicted asrelationship 310 as expressed in volts over a time period (“Tch”) 304, as determined from a time point (“T0”) 306 to time point (“T1”) 308. A reference cell can be accessed to supply the current that charges a capacitor according tograph 302. Time point (“Tsw”) 312 can represent a point in time at which there is a switch from one phase to a subsequent phase. As shown ingraph 330, the rate of discharging the capacitive element is depicted asrelationship 350 as expressed in volts over the same time period (“Tch”) 304, as determined from a time point (“Tsw”) 312 to time point (“T2”) 311, which is aligned withtime point 308 for purposes of illustration. In at least one embodiment, time point (“Tsw”) 312 represents a point in time when a sense amplifier switches to a margin sampling mode from a mode during which a reference cell is accessed. As shown,relationship 350 intersects 0 volts at time point (“T2”) 311. In at least one embodiment, a sampler circuit can be configured to sample a signal atpoint 352 to determine the value of data (i.e., read data) being read out of a memory cell. Note, too, that a programmed state is associated withvalues 344 above 0 volts, whereas an erased state is associated withvalues 346 below 0 volts, both sets ofvalues FIG. 3 , a first line and a second line respectively represent a specifiedlevel 340 of read margin for a programmed state (e.g., “0”) and a second specifiedlevel 342 of read margin for an erased state (e.g., “1”). Thus, a margin detector can be configured to determine a read margin for a memory cell by determining a profile (e.g., a discharge rate profile for a cell under a read operation) and matching it against specifiedlevels region 370, then the programmed state is a hard programmed state and the margin need not be restored; whereas if a margin detector determines that the profile is withinregion 372, then the programmed state is a soft programmed state and the margin likely will need to be restored. The margin detector can similarly operate to determine whether the profile is withinregions state 382. If the profile is determined to be associated withregions regions -
FIG. 4 is a diagram 400 depicting the generation of signal samples for determining margins, according to various embodiments of the invention. In this example, aline 462 depicts a discharging rate during phase two, with a programmed state readmargin 460 and an erased state readmargin 464. To illustrate the generation of signal samples, consider that four different cells in an array have four different rate profiles. For example,cell 1 has aprofile 410,cell 2 has aprofile 420,cell 3 has aprofile 430, andcell 4 has aprofile 440, where each profile indicates a relative strength of the read margins among the profiles. A sampler can be configured to sample the signals at time (“Ts1”) 450, time (“Ts2”) 452, and time (“Ts3”) 454 to form rate profiles (e.g., the rate at which a capacitor is discharged).Sampling profile 410 depicts 3 samples: sample 412 (e.g., a margin sample), sample 414 (e.g., a read sample), and sample 416 (e.g., a margin sample), all of which have values of “0.” The signal samples can be stored in asample repository 490 in afield 494 labeled “signal samples” and associated with an identifier (“Cell 1”) 492. A margin detector can determine that sincesamples state region 470. Thus,cell 1 does not require restoration, and indication (“N,” for “no”) is stored infield 498. A margin restoration circuit can detect the indications of “Y” and “N,” and can select to restore those cells associated with “Y” (for Yes), while foregoing margin restoration for those associated with “N.”Sampling profile 420 depicts 3 signal samples: signal sample 422 (e.g., a margin sample), signal sample 424 (e.g., a read sample), and signal sample 426 (e.g., a margin sample). Note that whilesignal samples signal sample 426 indicates thatprofile 420 changes to a value to “1.” Assignal samples 422 to 426 relate to a softprogrammed state region 472, a margin detector can be configured to note this infield 498 forcell 2. With a “Y” indication stored infield 498,cell 2 will undergo a margin restoration process (not shown). Sampling profiles 430 and 440 depictsignal samples 432 to 436 andsignal samples 442 to 446, respectively. Further, sampling profiles 430 and 440 also are associated with soft erasedstate region 482 and hard erasedstate region 480, respectively. The particulars of signal samples 432-436 and signal samples 442-446 can be stored insample repository 490. Note thatcenter numbers 496 represent read samples that include values read out of the memory cells. -
FIG. 5 is a timing diagram 500 depicting the sampling of signals, according to various embodiments of the invention.Signal 502 triggers the charging of a capacitive element during phase one, as shown bycapacitive element voltage 506.Signal 504 initiates phase two by discharging the capacitive element at a rate (not shown) that can be compared to a firstmargin threshold level 510 and a secondmargin threshold level 512. Sampling signals 520, 530, and 540 respectively trigger the sampling of the discharge rate of the capacitive element attime 522,time 532, andtime 542. In some embodiments, sampling signals 520, 530, and 540 control activation of a sense amplifier to capture signal samples. -
FIG. 6 depicts a cross-sectional view of an example of an integrated circuit implementing a margin manager, according to one embodiment of the invention.Cross-section view 600 shows multiple memory layers being vertically disposed above abase layer 602, which can include logic circuitry for reading data from memory cells as well as detecting the margins for those memory cells, and a semiconductor substrate (e.g., a silicon wafer) upon which the logic circuitry (e.g., CMOS circuitry) can be formed. The logic circuitry, for example, can include amargin manager 650 including amargin detector circuit 652 and a margin restoration circuit 654. Multiple memory layers can include afirst layer 604, asecond layer 606 and an “nth”layer 608 of third dimension memory. In various embodiments, reference memory cells (“R Cell”) 660 can be implemented anywhere inmemory layers 604 to 608. Similarly, sample data cells (“S data”) 670 can be implemented anywhere inmemory layers 604 to 608. -
FIG. 7 is a block diagram 700 depicting a memory access circuit implementing a representative margin manager to reduce effects of memory disturbs in association with read margins, according to various embodiments of the invention. According to an example of the invention,margin manager 790 is configured to operate in connection withmemory access circuit 701 to restore read margins.Memory access circuit 701 is shown to include anX Block 704, aY Block 730, one ormore sense amplifiers 740, and a set of buffers and/or drivers (“Buffers/Drivers”) 750. Note that whileFIG. 7 showsX Block 704 andY Block 730 respectively, the functionality and/or the structure ofmargin manager 790 can be disposed external toX Block 704 andY Block 730. -
Memory access circuit 701 can be coupled with a control signalsbus 705 to receive control signals, such as signals that enable read or write access. Further,memory access circuit 701 can be coupled with a power signalsbus 703 to receive control signals.Memory access circuit 701 can be coupled with an address bus (not shown) to receive at least one subset of addresses (“Ax<n:0>”) 702 of addresses destined forX Block 704 for selecting a horizontal array line (i.e., an “X Line”), and at least another subset of addresses (“Addr<Y>”) 710 destined forY Block 730 for applying specific access voltages on specific vertical lines (i.e., “Y Lines”).Data bus 744 is coupled withmemory access circuit 701 to exchange data with memory plane(s) 712.X Block 704 can include an address decoder (e.g., a predecoder and an X-decoder) for determining which X-Line to access.Y Block 730 also can include another address decoder (e.g., a predecoder and a Y-decoder) for determining a Y-Line. In operation, drivers in Buffers/Drivers 750 can generate write and read voltage signals respectively that are operative to write data into (e.g., Data_Bit(s)_In 746), and to read data from (e.g., Read_Data_Bits(s) 742), memory plane(s) 712.Sense amplifiers 740 operate on the Read_Data_Bits(s) 742 and generate Data_Bit(s)_Out 748 which may be buffered and stored in registers before being output as signals onData bus 744.Data bus 744 may be used for other signal functions, such as communicating I/O, for example. - In view of the foregoing, a margin restoration circuit of
margin manager 790 can controlmemory access circuit 701 to write (or re-write) values into memory cells that are not associated with a specified level of read margin, such as in cases where the memory cells are either in a soft programmed state or in a soft erased state. -
FIG. 8 is a timing diagram 800 depicting the management of margins for multi-level cells, according to various embodiments of the invention. A multi-level cell (“MLC”) is a memory element capable of storing more than a single bit or unit of information and diagram 800 presents an example of contemporaneous read operations and margin verification operations for multi-level cells. As shown, asignal 802 triggers the charging of a capacitive element over time during a first cycle (1st Cycle), as shown by the ramping up (i.e., increasing voltage over time) of capacitive element voltage 806 (Cap Voltage). Here, charging of the capacitive element can occur between the rising and falling edges of thesignal 802. Subsequently, asignal 804 triggers the discharging of the capacitive element over time during a second cycle (2nd Cycle) such that thecapacitive element voltage 806 begins to ramp down (i.e., decreasing voltage over time) upon triggering of the signal 804 (e.g., discharge begins on the rising edge of the signal 804). A discharge rate of the capacitive element can be compared with a margin threshold for a programmed cell “0” and with a margin threshold for an erased cell “1”. Groups of sampling signals 820, 822, 824, and 826 are timed to activate a sense amplifier at certain specific points in time to capture margin samples and read samples about a time point 850 (depicted as a dashed line). -
FIG. 9 is an exemplary state table 900 for the timing diagram depicted inFIG. 8 , according to various embodiments of the invention. Table 900 illustrates acell state 920 for correspondingsequential sensing samples 910 captured according to timing diagram 800 ofFIG. 8 . The aforementioned group of sampling signals 820, 822, 824, and 826 ofFIG. 8 are configured to capture samples shown in groups, 930, 932, 934, and 936, respectively. Further,cell state 920 can also include an indication (e.g., a bit of data) as to whether margin restoration is required (e.g., “need restore,” to indicate that restoration is needed). In some embodiments, state table 900 can be stored in a sample repository (not shown). A portion of one or more memory arrays on one or more memory layers can be used for the sample repository. - The various embodiments of the invention can be implemented in numerous ways, including as a system, a process, an apparatus, or a series of program instructions on a computer readable medium such as a computer readable storage medium or a computer network where the program instructions are sent over optical or electronic communication links. In general, the steps of disclosed processes can be performed in an arbitrary order, unless otherwise provided in the claims.
- The foregoing description, for purposes of explanation, uses specific nomenclature to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that specific details are not required in order to practice the invention. In fact, this description should not be read to limit any feature or aspect of the present invention to any embodiment; rather features and aspects of one embodiment can readily be interchanged with other embodiments. Notably, not every benefit described herein need be realized by each embodiment of the present invention; rather any specific embodiment can provide one or more of the advantages discussed above. In the claims, elements and/or operations do not imply any particular order of operation, unless explicitly stated in the claims. It is intended that the following claims and their equivalents define the scope of the invention.
Claims (20)
1. A margin verification method for a re-writable, non-volatile memory comprising:
selecting at least one memory element of a non-volatile memory array for a read operation;
providing a reference signal;
sensing the reference signal and a leakage signal of the selected memory element during a first cycle of the read operation;
sensing a read current from the selected memory elements of the array and the leakage signal during a second cycle of the read operation;
generating a data signal indicative of stored data in the selected memory elements;
managing a read margin for selected memory elements substantially during the first and second cycles; and
determining if a value of the data signal is within a specified level of the read margin.
2. The method of claim 1 including re-writing the stored data to the selected memory elements to restore the read margin to the specified level of the read margin.
3. The method of claim 1 and further comprising determining whether the value of the stored data is within a first range of resistance values that specify the read margin for the selected memory elements.
4. The method of claim 3 and wherein the first range of resistance values are indicative of a hard state for the stored data.
5. The method of claim 4 and wherein the hard state comprises a hard programmed state for the stored data if the data signal is indicative of a value of zero, or a hard erased state for the stored data if the data signal is indicative of a value of one.
6. The method of claim 1 including determining whether the value of the stored data is associated with a second range of resistance values that specify the read margin for the selected memory elements.
7. The method of claim 6 wherein the second range of resistance values are indicative of a soft state for the stored data.
8. The method of claim 7 wherein the soft state comprises a soft programmed state for the stored data if the data signal is indicative of a value of zero, or a soft erased state for the stored data if the data signal is indicative of a value of one.
9. The method of claim 7 including restoring the read margin for selected memory elements by changing an association of the selected memory elements from the second range of resistance values to a first range of resistance values.
10. The method of claim 1 including managing the read margin as a function of time.
11. The method of claim 1 including providing a capacitance element, and, during the second cycle, determining a rate of current flow to or from the capacitance element as indicative of whether the read margin for selected memory elements is associated with a specified level of read margin.
12. The method of claim 1 wherein the reference signal comprises a reference current.
13. The method of claim 12 including providing the reference current from a reference memory cell of the array.
14. The method of claim 1 wherein the leakage signal comprises leakage currents generated by a subset of the plurality of memory elements that are not selected for the read operation.
15. The method of claim 1 including repeating the sensing steps at selected sample times to form sequential sensing samples, and storing the sequential sensing samples in a sample repository.
16. The method of claim 15 including determining whether a memory cell requires restoration based on the sequential sensing samples.
17. The method of claim 1 wherein each memory element is configured to store at least two-bits of data, and the method includes managing read margins for multi-level cells (MLC).
18. The method of claim 1 wherein the memory array comprises a stack of multiple layers of memory elements.
19. The method of claim 1 wherein the memory array comprises a two-terminal cross-point array of resistive memory cells.
20. The method of claim 1 including providing a capacitance element coupled to at least one of the selected memory elements, and, during the second cycle, determining a rate of current flow to or from the capacitance element by sampling a voltage of the capacitance element to form a profile as indicative of the read margin.
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Also Published As
Publication number | Publication date |
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US20110267871A1 (en) | 2011-11-03 |
US20110080763A1 (en) | 2011-04-07 |
US7978501B2 (en) | 2011-07-12 |
US8208287B2 (en) | 2012-06-26 |
US20100073990A1 (en) | 2010-03-25 |
US7830701B2 (en) | 2010-11-09 |
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