JP2008027571A5 - - Google Patents

Description

Method and memory circuit for operating a resistive memory cell Detailed Description of the Invention

[Background of the present invention]
[Field of the Invention]
The present invention relates to a method for reading stored data from resistive memory cells, particularly conductive bridging random access memory cells (CBRAM memory cells). The invention further relates to a memory circuit having a resistive memory cell.

[Description of prior art]
In a CBRAM memory circuit, information is stored in CBRAM memory cells each having at least one resistive memory element. This resistance memory element can take various resistance states. The stored information is specified by setting each resistance state of the resistive memory element.

  In order to evaluate the contents of the CBRAM memory cell, it is necessary to evaluate the resistance value of the resistive memory element of each resistive memory cell. The evaluation can be performed by applying a voltage and measuring a current flowing through the CBRAM memory cell.

  In order to prevent the resistance state of the resistive memory element from changing while information is being read, the voltage applied to the resistive memory element must not exceed a certain voltage width (for example, 100 mV to 200 mV).

As a result, the resistance value of the resistance state of the resistive memory element is generally 10 ⁴ Ω to 10 ⁹ Ω, and as a result, the width of the current flowing through the memory cell is 100 pA to 10 μA.

  However, in a circuit generally used as a CBRAM memory circuit, a current of less than 1 μA cannot be detected and is detected as 0 μA.

  In the case of a single level design, i.e. when storing binary data in a CBRAM resistive memory cell, the sense amplifier used uses a 5 μA reference current in the memory cell to distinguish between the two logic states. Evaluate the flowing current. In the multi-level design of the CBRAM memory circuit, a relatively low signal current is already distributed in each individual value as a CMOS circuit.

  When storing 2 bits per memory cell, the cell currents are approximately 10 μA (state “11”), 6.66 μA (state “10”), 3.33 μA (state “01”), and 0 μA (state “ 00 "). In order to detect each of these cell currents, a signal current resolution of at least 1.66 μA is required. Realizing the above resolution using conventional circuitry involves complexity.

  Therefore, it is a method for reading memory data from a CBRAM memory cell, which can avoid the above-mentioned disadvantages, and can detect a state related to a resistive memory element of a CBRAM memory circuit with high reliability, particularly in a multi-level design. There is a need to provide a way to obtain. Furthermore, there is a need to provide a CBRAM memory circuit that can read information from CBRAM memory cells by an improved method.

In the corresponding US patent application of the present application (US Application No. 11 / 459,289), an office action was delivered as of October 18, 2007. In the office action, three prior art documents identified as relevant were cited.

[Patent Document 1] US Patent Application Publication No. 2004/0264244 (Publication Date: December 30, 2004)
[Patent Document 2] US Patent Application Publication No. 2006/0209585 (Publication date: September 21, 2006)
[Patent Document 3] US Patent Application Publication No. 2006/0227598 (Publication Date: October 12, 2006)

In Patent Document 1, a write voltage or an erase voltage Vpp corresponding to each of a bit line and a source line is applied to a bit line and a source line connected to a memory cell to be written or erased in a memory array via a voltage switch circuit. A nonvolatile semiconductor memory device including a pulse voltage application circuit that applies a voltage pulse for writing or erasing to a word line connected to a gate electrode of a selection transistor connected to the memory cell while being applied is described. (See the abstract).

In Patent Document 2, a memory cell on a path from a write current source (4W) for supplying a write current to an internal data line (IDL), a bit line (BL), a source line (SL), and a reference potential node (ND) Non-volatile in which the resistance value excluding (MC) is always constant and the resistance value between the memory cell and the variable current source and the resistance value between the memory cell and the reference potential node are set within 500Ω in this current path. A semiconductor memory device is described. (See abstract).

Patent Document 3 describes an MRAM having a plurality of bit lines, a reference bit line, a plurality of memory cells, reference cells, and a reading unit.

  Each memory cell is provided along each bit line. Each of the reference cells is provided along the reference bit line. The memory cell and the reference cell have a tunneling magnetoresistance and a tunneling magnetoresistance for reference. The magnetoresistance of the tunnel effect and the magnetoresistance of the tunnel effect for reference have spontaneous magnetizations in opposite directions based on stored data. The reading unit includes a first resistor unit including a ninth terminal connected to the bit line and a tenth terminal connected to the first power source, an eleventh terminal connected to the reference bit line, and the first terminal A second resistor including a twelfth terminal connected to one power source; and a comparator for comparing a detection voltage generated at the ninth terminal and a reference voltage generated at the eleventh terminal. (See abstract).

In the corresponding European patent application of this application (European application number: EP07012239.5), a European search report was delivered on 19 December 2007. In the European research report, five prior art documents identified as relevant were cited.

[Patent Document 4] US Patent Application Publication No. 2006/126413 (Publication Date: June 15, 2006)
[Patent Document 5] US Patent Application Publication No. 2004/008555 (Publication Date: January 15, 2004)
[Patent Document 6] US Patent Application Publication No. 2004/240294 (Publication date: December 2, 2004)
[Patent Document 7] US Patent No. 6795359 (patent registration date: September 21, 2004)
[Patent Document 8] US Pat. No. 5,881,007 (patent registration date: March 09, 1999)

Patent Document 4 discloses a memory circuit including a CBRAM resistance memory cell, a reference resistance cell, a reading unit, and an evaluation unit. In the CBRAM resistance memory cell, the CBRAM resistance element is connected to a bit line and a word line, and has a CBRAM resistance element and a selection switch. The resistance value of the CBRAM resistance element is set by a write current to store information. The selection switch is driven via the word line and connects the first potential from the CBRAM resistance element to the bit line. The reference resistance cell is connected to the bit line and the reference line, and has a reference element and a reference selection switch. The resistance value of the reference element is set to a resistance threshold value. The reference selection switch is driven by the reference line, and connects the second potential from the reference element to the bit line. The read unit is configured to activate the reference selection switch and the selection switch for the purpose of reading data from the memory. As a result, a current from the memory cell flows through the CBRAM resistance memory cell, Current flows from the reference resistance cell onto the bit line. The evaluation unit is connected to the bit line, and outputs data in the memory according to the result of the amount of electricity assigned to the bit line (see abstract).

U.S. Patent No. 6,057,051 discloses a method and system for sensing the logic state of an unknown initial data bit stored in a selected resistive memory cell. According to one method, a first count is generated that indicates the logic state of an unknown initial data bit stored in a selected resistive memory cell. A second count generated thereafter indicates a data bit having a known first logic state stored in the selected resistive memory cell. A subsequently generated third count indicates a data bit having a known second logic state stored in the selected resistive memory cell. The logic state of the unknown initial data bit stored in the selected resistive memory cell is then determined from the first, second and third counts (see abstract).

Patent Document 6 describes an integrated charge sensing method for sensing the resistance of a resistive memory element. The current flowing through the resistive memory cell is used to charge the capacitor coupled to the digit line. The voltage of the capacitor that matches the voltage of the digit line is applied to one input of the comparator. When the voltage on the bit line exceeds a predetermined fixed voltage applied to the second input to the comparator, the comparator switches logic state, the charge is extracted from the capacitor, and the capacitor is charged again. The number of times that the process of charging and discharging the capacitor occurs during a given period and the capacitor switches during that period represents the resistance of the memory element (see Abstract).

U.S. Patent No. 6,057,051 describes an apparatus and method for sensing or measuring an input current, such as a current representing the logic state of a memory cell. The sensing circuit includes an amplifier, a capacitor, a current source circuit, a clocked comparator, and a clock counter. The current source circuit operates in response to the output of the comparator to supply current to or subtract current from the capacitor during the charge and discharge periods. The count value in the clock counter comes from periodically comparing the capacitor voltage with a reference voltage and is therefore related to the logic state of the memory cell. The magnitude of the current supplied during charging is below the magnitude deducted during discharging, thereby allowing the use of a smaller counter (see abstract).

Patent Document 8 discloses a sense amplifier enable signal generator for a semiconductor memory device. The sense amplifier enable signal generator receives a row address strobe bar signal for selecting a row address of the memory array, outputs a signal in synchronization with the clock signal, and stops inputting the row address strobe bar signal. Then, the count means for stopping the operation, and when the count value output by the count means increases to a pre-programmed time delay set value, a sense amplifier enable signal for instructing the start of the sense amplifier operation is output, and the row address strobe Comparing means for stopping the output of the sense amplifier enable signal when the input of the bar signal is stopped is provided. According to the above invention, the sense amplifier can operate at an appropriate time without being affected by process parameters, operating voltage, temperature, and the like (see the abstract).

[Outline of the Invention]
According to a first aspect of the invention, a method is provided for reading stored data from a resistive memory element. The method uses a controllable select transistor that is controlled by a control value. The method provides a step of detecting a cell current flowing through the resistive memory element, a step of setting the control value depending on the detected cell current, and data stored depending on the control value. It includes a process.

  According to another aspect of the present invention, there is provided a memory circuit for reading stored data, comprising a selection transistor controlled by a control value and a resistive memory element set in a resistance state Is done. The memory circuit sets a control value depending on the detected cell current, and provides an evaluation for detecting the cell current flowing in the resistive memory element in order to provide stored data depending on the control value. The unit is further provided.

[Brief description of the drawings]
In order that the features of the present invention described above may be understood in detail, the present invention outlined in the previous section will be described more specifically with reference to the embodiments shown in the accompanying drawings. The accompanying drawings, however, illustrate exemplary embodiments of the invention and are not to be considered as limiting the scope of the invention, and the invention permits other embodiments that are equally effective. Please note that.

  FIG. 1 is a schematic diagram of a conventional CBRAM memory circuit having CBRAM memory cells. FIG. 2 is a block diagram of a CBRAM memory circuit according to one embodiment. FIG. 3 is a detailed circuit diagram of a CBRAM memory circuit according to an embodiment of the present invention.

  FIG. 4 is a graph showing characteristics of the cell current and the gate voltage at various resistance values of the resistance memory element of the assumed CBRAM memory cell. FIG. 5 is a detailed block diagram of a read circuit for the CBRAM memory circuit. FIG. 6 is a schematic block diagram of a write circuit for the CBRAM memory circuit.

Detailed Description of Preferred Embodiments
FIG. 1 shows a part of a conventional CBRAM memory circuit 1. For clarity and simplicity, only one CBRAM memory cell 2 is shown at the intersection of word line 3 and bit line 4. The memory cell 2 has a selection transistor 5. The select transistor 5 is connected in series to the resistive memory element 6 between the bit line 4 and a predetermined plate potential VPL supplied by a plate voltage source (not shown).

  Specifically, the first terminal (source or drain terminal) of the selection transistor 5 is connected to the bit line 4. The second terminal (drain or source terminal) of the selection transistor 5 is connected to the first terminal of the resistive memory element 6. The first terminal of the resistive memory element 6 is connected to the plate potential VPL. A control terminal (gate terminal) of the selection transistor 5 is connected to the word line 3.

  The resistive memory element 6 is configured as a CBRAM memory element and is also referred to as a programmable metallization cell (PMC) resistive memory element. Such a resistive memory element 6 can have different resistance states with different resistance values depending on the programming (memory) state.

  Programming of the resistive element 6 can be performed by applying a programming voltage to the resistive element 6 so that the resistive memory element is in a resistive state having a first low resistance value.

  The resistive memory device can be set to a resistance state having the second highest resistance value by using an erase voltage having a polarity that is usually reversed compared to the programming voltage.

  Programming and erasing of the resistive memory element 6 can be performed by establishing a conductive path or degrading the established conductive path due to a conductive material (eg, Ag) extending into the solid electrolyte. it can. Since the function of such a resistive memory element is well known in the art, a more detailed description is omitted in this specification.

  In connection with the embodiments of the CBRAM memory circuit described below, instead of the CBRAM resistive memory element, other resistive memory elements that can obtain different resistance states with different resistance values may be used.

  In the addressing of the memory cell 2, the word line 3 is activated (that is, an activation signal is applied to the word line), and the selection transistor 5 is closed (indicating conductivity), whereby the bit line 4 is electrically conductive. This can be performed by being connected to the resistive memory element 6 through the selection transistor 5.

  The read operation can be performed using the read circuit 8. The read circuit 8 applies a predetermined potential to the bit line 4 and evaluates the current flowing through the bit line 4 with respect to the addressed resistive memory element 6. The resistance state of the memory cell 2 is determined depending on the current value.

  Reading a multi-bit memory cell (ie, a memory cell that can have more than two resistance states) also determines the width of the current flowing through the memory cell by applying a read voltage to the bit line. Can be performed in a similar manner. Depending on a predetermined current range flowing through the memory cell, a specific resistance state is assigned to the memory cell, and stored data corresponding to the specific resistance state can be output.

  The above embodiment describes the CBRAM memory cell 2 having the programming circuit 10. A predetermined programming current that flows in a direction depending on the data to be written generally flows to the activated memory cell 2 via the bit line 4. Thereby, the resistive memory element 6 of the memory cell 2 is set to a higher resistance state or a lower resistance state.

  In the multi-level memory cell, the programming circuit 10 is configured such that the resistance value of the resistive memory element 6 falls within a specific range corresponding to a specific resistance state of the CBRAM memory cell 2. The programming current is applied to the bit line 4 using the current level in the programming circuit. As a result, a bit line potential for programming or erasing the resistive memory element 6 of the resistive memory cell 2 is generated on each bit line.

  In particular, a peak current may occur during programming (that is, during the operation of putting the resistive memory element 6 in a low resistance state). The generation of the peak current occurs due to the capacity of the bit line when the increase in current as a result of the decrease in the resistance value is supplied from the charge accumulated on the bit line 4 in the resistance memory element 6. To do. The increased current flowing through the resistive memory element 6 significantly exceeds the current supplied by the programming circuit 10 and can cause damage in the resistive memory element 6.

  Conventionally, detecting a current flowing through a memory cell during reading is particularly difficult in the case of a multilevel memory cell. The difficulty is because the detected current value is very low and cannot be reliably detected using a corresponding evaluation circuit with sufficient accuracy to reliably associate with a specific state.

  In one embodiment, as shown in FIG. 2, reading of a memory cell using a current value I flowing through the memory cell 2 controlled to be constant by the control unit 12 is provided. A control value S required for the control unit 12 to perform control can be assigned to the resistance state of the memory cell 2.

  FIG. 3 shows a detailed view of one embodiment of a memory circuit according to the present invention. In FIG. 3, the same reference numerals are used for elements having the same or similar functions as those in FIG. The memory circuit shown in FIG. 3 is generally based on the concept of using a selection transistor 5 (for example, a field effect transistor such as a MOSFET) as part of the control circuit 10.

  In the memory circuit, the selection transistor 5 is no longer opened and closed according to the voltage application to the word line for addressing as in the prior art, but a predetermined current is passed through the memory cell 2 via the respective bit lines 4. Is addressed by using a suitable similar activation potential via the word line 3.

  Such an address is achieved by a read circuit 8 that applies a predetermined bit line potential VBL to the bit line 4 and applies a control value S to the addressed word line 3. This application is performed by the word line decoder 13.

  The word line decoder 13 applies a control potential to the activated word line depending on the address ADR of the applied word line. The word line decoder 13 also deactivates the remaining word line 3 having a potential such as a plate potential VPL or a ground potential so that each select transistor 5 is completely opened (non-conductively).

  In the adjusted state (that is, when a predetermined current flows to the memory cell 2 via the bit line 4), the control value S is assigned to the data D read from the memory cell 2. The control value S corresponds to each discrete potential from one set of potential values, and depends on the characteristics of the selection transistor 5 in the memory cell 2 for various resistance states of the resistive memory element 6. Have a sufficient potential distance from each other.

  FIG. 4 is a graph illustrating typical characteristics of a typical memory cell with a resistive memory element 6 having four different resistance states. The various resistance values for each of these illustrated resistance states are 10 kΩ, 35 kΩ, 50 kΩ, and 1 MΩ.

  In the first resistance state, the resistance value of the resistive memory element 6 is 10 kΩ, and when a constant current of 5 μA is passed through the memory cell, the control potential applied to the selection transistor 5 is 2.1V. In the second state, the resistance value of the resistance element is 35 kΩ, and the control potential is 2.25V.

  In the third state, the resistance value of the resistance element 6 is 50 kΩ, and the control potential is 2.4V. In the fourth state, the resistance value of the resistive memory element 6 is high, 1 MΩ, and it is impossible to obtain a constant current of 5 μA in the resistive memory element 6 by a voltage generally used in the memory circuit. Therefore, it is essentially 0 μA.

  FIG. 5 shows the read circuit 8 in more detail. The read circuit 8 generates the control value S by appropriately supplying a potential from a voltage divider formed by the plurality of resistors 31 to 35. The first resistor 31 to the fifth resistor 35 are connected in series with each other, and are connected in series between the reference potential and the ground potential VGND.

  The first node N1 disposed between the first resistor 31 and the second resistor 32 is connected to the input of the driver 45 via the first transistor 41. The second node N2 disposed between the second resistor 32 and the third resistor 33 is connected to the input of the driver 45 via the second transistor 42.

  A third node N3 arranged between the third resistor 33 and the fourth resistor 34 is connected to the input of the driver 45 via the third transistor 43. A fourth node N4 disposed between the fourth resistor and the fifth resistor 35 is connected to the input of the driver 45 via the fourth transistor 44. In this way, a kind of analog demultiplexer is formed.

  The output driver 45 is configured as a feedback-coupled operational amplifier that outputs a voltage supplied from one of the transistors 41 to 44 and applied to the first input as the control value S. be able to. The control terminals of the transistors 41 to 44 are connected to the decoder 46, respectively.

  Depending on the counter value of the counter 47, the decoder 46 closes any one of the transistors 41 to 44, and opens or maintains each of the other transistors. The control unit 48 starts the read operation by calculating the counter 47. As a result, each of the transistors 41 to 44 is alternatively closed sequentially and the other transistors are opened.

The bit line 4 is connected to a voltage source via an ammeter 49 so that a potential having a supply potential amount is supplied. Ammeter 49 detects the current flowing in the bit line 4 with respect to the reference value (reference current I _REF), and outputs a comparison signal according to the comparison result, and a comparison unit.

  The calculation by the counter 47 indicates that the current on the bit line 4 is changed to an ammeter 49 depending on whether the control voltage applied to the selection transistor 5 has increased or decreased due to sequential switching of the transistors 41 to 44. As determined by the above, the operation is stopped when a predetermined current value is exceeded or falls below.

  When the current value flowing through the bit line 4 reaches a predetermined current value, the current counter value is output as stored data D. Alternatively, when the current flowing through the bit line 4 exceeds or falls below a predetermined current, the current counter value is output as stored data D.

  In the present embodiment, when the counter 47 is provided as a 2-bit counter, the read circuit 8 in FIG. 5 can be used to detect four different states. In this case, a multi-bit memory circuit capable of storing 2 bits in each memory cell can be realized. In the configuration in which the electrical properties corresponding to the characteristics of FIG. 3 are obtained, each voltage can be generated from each resistor 31-35 by using a voltage divider.

  In order to evaluate the multi-bit memory cell corresponding to the characteristics of FIG. 4, each voltage is supplied to each node N1-N4, which defines each limit of the range of various resistance states set within the memory cell. Need to be done.

  In the illustrated embodiment, each of the voltages may be 2.175, 2.325, and 2.6V. In this case, in order to read four different states from the multi-bit memory cell and detect the four states of the multi-bit memory cell, only three read voltages need to be supplied to the three nodes N1 to N3. is there.

  FIG. 6 shows a memory circuit according to another embodiment. In this embodiment, the control value is applied to the addressed word line 3 via the word line decoder 7 and writing to the memory cell is performed. This writing is performed so that the peak current generated while the resistance state of the resistance element transitions from the high or low state is limited.

  For this purpose, the programming circuit 10 supplies a programming voltage. This programming voltage changes the resistive element of the addressed memory cell from a high resistance state to a low resistance state.

  In contrast to the conventional CBRAM memory circuit, the activation of the word line 3 is performed such that the programming operation is started as a result of the selection transistor 5 connecting the resistance element 6 to the bit line. When the resistance value of the resistance element 6 decreases, the current flowing through the memory cell increases.

  This increase in current is detected by the programming circuit 10 using the galvanometer 49 based on the current flowing through the bit line 4, for example.

  When the value of the current flowing through the memory cell exceeds the limit value, the potential of the control value is lowered via the word line decoder 7 on the word line 3 and the source-drain resistance of the selection transistor 5 is increased. Thereby, the current value is limited. Thus, the value of the current flowing through the resistive memory element of the memory cell 2 can be limited so that damage to the memory cell is avoided.

  In summary, a method for reading data according to an embodiment provides a control value for addressing a select transistor. This control value is set depending on the detected cell current and specifies information in the resistive memory cell. For this purpose, the cell current flowing through the resistive memory element is compared against a reference current, and the control value is set depending on the comparison result.

  In general, the control value is set such that the cell current refers to the reference current. When the cell current of the resistive memory element is kept constant, various resistance values of the resistive memory element in the resistive memory cell lead to different control values of the selection transistor.

  By using different gate voltages of the selection transistor at various resistance values of the resistive memory element, the state of the resistive memory cell can be easily evaluated. This is because, due to different increases in cell current-gate voltage characteristics, an easily detected voltage difference is obtained for the evaluation of the resistive memory cell, depending on the resistance value of the resistive memory element in the resistive memory cell. Because it is.

  According to another embodiment, a measurement value (voltage value or current value) for evaluating the resistive memory cell is applied to the selection transistor, and the measurement value indicates a difference between the cell current and the reference current. Change until the indicator changes. The measurement value at which the index indicating the difference changes is set as the control value.

  Further, the measurement value may be changed according to each discrete value. In addition, the measurement value may be selected from a number of different values. In this case, when the measurement voltage values are sequentially changed and applied, the index indicating the difference between the cell current and the reference current changes when the measurement values are changed sequentially. The measured value is set as the control value.

  Specifically, the number of different values of the control value is selected by subtracting one from the number of detectable resistance states of the resistive memory cell.

  According to another aspect, a memory circuit with a select transistor for reading stored data is provided. The memory circuit includes a selection transistor controlled by a control value and a resistance memory element set in a resistance state.

  The memory circuit further includes a reading unit for detecting a cell current flowing through the resistive memory element. The reading unit sets a control value depending on the detected cell current and provides data to be stored based on the control value.

  The evaluation unit may include a comparison unit for comparing a cell current flowing through the resistance memory cell and a reference current, and a control unit for setting a control value depending on the comparison result.

  Further, the control unit may be configured to set a control value so that the cell current corresponds to the reference current.

  The control unit may include a measurement unit. The measurement unit gives a measurement value to the selected transistor, and changes the measurement value until the comparison unit detects an index indicating a difference between the cell current and the reference current. The said control part may be comprised so that the value for a measurement from which the parameter | index which shows the said difference changes may be set as a control value. Therefore, the measurement unit may be configured to change the measurement value according to each discrete value.

Further, the measurement unit (measurement circuit) may select a measurement value from a number of different values. In this case, the control unit controls the last applied measurement value when the index indicating the difference between the cell current and the reference current I _REF changes between the measurement values applied in sequence. It is set as a value.

  The foregoing description relates to embodiments of the invention and other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims.

1 is a schematic block diagram of a conventional CBRAM memory circuit including CBRAM memory cells. It is a block diagram of one embodiment of the CBRAM memory circuit. 1 is a detailed circuit block diagram in one embodiment of a CBRAM memory circuit according to the present invention. FIG. It is the graph which showed each characteristic of the gate voltage and cell current in each various resistance value assumed of the resistive memory element of the said CBRAM memory cell. FIG. 3 is a detailed block diagram of a read circuit for the CBRAM memory circuit. 2 is a schematic block diagram of a write circuit for the CBRAM memory circuit. FIG.