DE102006033915B3 - Memory data reading method for e.g. conductive bridging RAM memory circuit, involves detecting current flowing via cell and adjusting control parameter based on current, where measuring parameter is selected from different values of cell - Google Patents

Abstract

The method involves detecting a current (I) flowing through a memory cell (2). A control parameter (S) is adjusted depending on the detected current such that the current corresponds to reference current. The current flowing through the memory cell is compared with the reference current. A measuring parameter is applied to an evaluation transistor, and is changed until a sign changes a difference between the current and the reference current. The measuring parameter is selected from different resistance values of the memory cell. An independent claim is also included for a memory circuit with a reading unit.

Description

The The invention relates to a method for reading out a storage date from a resistance memory cell, in particular a CBRAM memory cell (CBRAM: Conductive bridging RAM). The invention further relates a memory circuit having a resistance memory cell.

In CBRAM memory circuits, as they are known from the DE 10 2004 056 911 A1 and the DE 10 2004 058 132 B3 information is stored in CBRAM memory cells, each having a resistive memory element. The resistance memory element can assume different resistance values, so that the information to be stored can be determined by changing the resistance value of the resistance memory element. Consequently, in order to evaluate the content of the CBRAM memory cell, an evaluation of the resistance value of the resistance memory element of the relevant memory cell is necessary. This can be done by applying a voltage and measuring the resulting current flowing through the CBRAM memory cell. In order not to change the resistance value of the resistance memory element when the information is read out, the voltages applied thereto to the resistance memory element must not be outside a certain voltage range, eg between 100 and 200 mV. The resistance value of the resistance memory element is typically between 10 ⁴ and 10 ⁹ Ω, so that currents through the memory cells between 100 pA and 10 uA result. In the circuit technique commonly used for CBRAM memory circuits, however, currents below 1 μA are no longer resolvable, so that they are detected as 0 μA. In a single-level design, ie with binary storage of data in the CBRAM resistive memory cells, a potential sense amplifier would evaluate the current flowing through the memory cell using a reference current of 5 μA to distinguish between two logic states. In the case of a multilevel design of the CBRAM memory circuit, the signal current, which is already relatively small for CMOS circuit technology, is further divided between the individual values. When storing 2 bits / memory cell, the cell currents are about 10 μA (state "11"), 6.66 μA (state "10"), 3.33 μA (state "01") and 0 μA (state "00"). ), which requires a resolution of the signal current of at least 1.66 μA, which is difficult to implement with conventional circuit technology.

It It is therefore an object of the present invention to provide a method for Reading a memory datum from a CBRAM memory cell available in which the aforementioned disadvantages are avoided, and wherein, especially in a multilevel design, detecting the state of the resistive memory element of the CBRAM memory circuit reliable be performed can. It is a further object of the present invention to provide a CBRAM memory circuit available to provide information from CBRAM memory cells in an improved way can be read out.

These Tasks are achieved by the method of claim 1 and the memory circuit solved according to claim 8.

Further advantageous embodiments of the invention are specified in the dependent claims.

According to one The first aspect of the present invention is a method for reading out a storage data from a resistance memory cell provided the one over a control variable controllable Selection transistor has. The method comprises the steps of Detecting a cell current flowing through the resistive memory cell, of setting the control quantity depending on the detected cell stream and providing one of the control size associated Information as storage date.

The inventive method has the advantage that the control variable driving the selection transistor, the dependent is adjusted by the detected cell current, the information determined in the resistance memory cell. This is in particular the cell current flowing through the resistive memory cell with a Reference current compared and the control variable depending on the result of the comparison set. Usually will set the control size so that the cell stream as possible corresponds to the reference current. The different resistance values of the resistance memory element located in the resistance memory cell to lead to different control variables of the selection transistor, when the cell current kept constant by the resistive memory cell shall be. With the different gate voltage of the selection transistor at different resistance values of the resistive memory element a simple evaluation of the state of the resistance memory cell, because due to the different slopes of the cell current gate voltage characteristic for the Resistive memory cell dependent of the resistance value of the resistor memory cell arranged in the Resistive memory element yield easily detectable voltage differences.

According to a preferred embodiment, a measured variable is applied to the selection transistor sets and changes until a sign of a difference between the cell current and the reference current changes, wherein the measured variable at which the sign of the difference changes is set as a control variable.

Preferably the measure becomes discrete Values changed.

Farther can the measured variable from a Number of different values are selected, with one Change the sign of a difference between the cell stream and the reference current between consecutively applied measured variables Last measured quantity set as control variable becomes.

Especially can be a number of different values of control size by 1 reduced number of detectable states of the resistance memory cell chosen become.

According to one Another aspect of the present invention is a memory circuit for reading a storage data with a resistance memory cell, the one over a control variable controllable Selection transistor has provided. The memory circuit has Furthermore, an evaluation unit to one through the resistance memory cell flowing Cell current to detect the control variable depending on the detected cell current to set and information associated with the control size as To provide save date.

Preferably the evaluation unit comprises a comparator unit to the by the resistive memory cell flowing cell stream with a Compare reference current and a control unit to the control size dependent on to adjust the result of the comparison.

Preferably the control unit is configured to set the control quantity so that the cell current as possible corresponds to the reference current.

The Control unit may have a measuring circuit to send a measured variable to the Selection transistor to create and change them until the Comparator unit determines that a sign of a difference has changed between the cell current and the reference current, wherein the measuring circuit is further adapted to the measured quantity, at which changes the sign of the difference, to be set as a control variable. In this case, the measuring circuit can be designed to discrete the measured variable Change values.

Farther can be provided that the measuring circuit from the measured variable Select number of different values and when changing the sign of a difference between the Cell current and the reference current between consecutively applied Measured variables last set measured variable as a control variable.

preferred embodiments The present invention will now be described with reference to the accompanying drawings explained in more detail. It demonstrate:

1 a schematic representation of a CBRAM memory circuit with a CBRAM memory cell according to the prior art;

2 a block diagram of a CBRAM memory circuit according to an embodiment of the invention;

3 a more detailed circuit diagram of a CBRAM memory circuit according to the embodiment of the invention;

4 a characteristic of the cell current over the gate voltage at various resistances of the resistive memory element of the considered CBRAM memory cell; and

5 a more detailed schematic representation of the readout circuit for the CBRAM memory circuit according to the invention; and

6 a schematic representation of a write circuit for the CBRAM memory circuit.

In 1 is a section of a conventional CBRAM memory circuit 1 shown, for ease of illustration, only a CBRAM memory cell 2 at a crossroads of a wordline 3 and a bit line 4 is shown. The memory cell 2 includes a selection transistor 5 in series with a resistive memory element 6 is connected between the bit line and a fixed plate potential VPL. In detail, a first terminal of the selection transistor 5 with the bit line and a second terminal of the selection transistor 5 with a first terminal of the resistive memory element 6 connected. A second terminal of the resistor storage element 6 is connected to the plate potential VPL. A control terminal of the selection transistor 5 is with the wordline 3 connected.

The resistance memory element 6 is formed as a CBRAM resistive memory element, also called a PMC (Programmable Metallization Cell), and the like. Such a resistance memory element may have different resistance values depending on the programming state. Can be programmed such a resistance element 6 by applying a programming voltage whereby the resistive memory element assumes a first low resistance value. By means of an erase voltage having one of the opposite polarity of programming voltage, the resistance memory element can be placed in a state of high resistance. Programming and clearing the resistor memory element 6 essentially takes place by forming and regressing an electrically conductive path from a material migrating into a solid electrolyte, eg Ag. The operation of such a resistance memory element is well known in the prior art and will not be discussed further herein. Instead of a CBRAM resistive memory element, other resistive memory elements which can assume different states with different resistance values can also be used in conjunction with the embodiments of the CBRAM memory circuit according to the invention described below.

Addressing the memory cell 2 essentially takes place by activating the word line, ie an activation signal is applied to the word line, whereby the selection transistor 5 closed (conductive), so that the bit line 4 via the selection transistor 5 with the resistance memory element 6 is connected. The readout is now done using a readout circuit 8th which has a predetermined potential on the bit line 4 applies and the over the bit line 4 and by the addressed resistance memory element 6 evaluates flowing electricity. Depending on the magnitude of the current, the resistance state of the memory cell 2 certainly.

The Reading a multibit memory cell, i. a memory cell, which have more than two states can be done in much the same way, with the application the read voltage is detected on the bit line, in which Area the resulting current is through the memory cell. Depending on the area in which the current through the memory cell is located, the memory cell can be assigned a specific state and a corresponding date will be issued.

Described is the CBRAM memory cell 2 with a programming circuit 10 , in which usually via the bit line through the activated memory cell 2 a predetermined programming current is applied in a direction dependent on the datum to be written, around the resistive element 6 the memory cell 2 in a high-impedance or low-impedance state. In a multilevel memory cell, the programming circuit 10 be designed so that the resistance value of the resistive memory element is brought into a certain range, which corresponds to a particular state of the CBRAM memory cell 2 equivalent. The programming current is applied to the bit line by means of a current mirror in the programming circuit, so that a bit line potential is established on the bit line, whereby the resistance element 6 the resistance memory cell is programmed or deleted.

In particular, in programming, ie in a process in which the resistance memory element is brought to a low-impedance state, it comes to a current peak due to the capacity of the bit line when the resistance memory element by the decrease of the resistance value 6 grow de electricity 6 is operated from the charge stored on the bit line. This increased current through the resistive memory element 6 exceeds that through the programming circuitry 10 provided power, and may lead to damage of the resistance memory element.

The detection of the current through the memory cell during readout is difficult, in particular in the case of a multilevel memory cell, since the currents are very low, so that they can not be reliably detected by a corresponding evaluation circuit so accurately that a specific state can be assigned to them. As in 2 is shown, the concept of the invention provides to read the state of a memory cell when a current I through the memory cell 2 using a rule unit 12 is constantly regulated. The control variable S required for the control unit can be a state of the memory cell 2 clearly assign.

In 3 a more detailed representation of the memory circuit according to the invention is shown. Like reference numerals correspond to elements of the same or similar functions. With the memory circuit of 3 In essence, the concept is pursued, the readout transistor 5 to be used as part of a control circuit, wherein the readout transistor is no longer closed or opened according to an applied wordline address, but with a suitable analogue activation potential on the wordline 3 is driven so that a predetermined current through the memory cell 2 flows. This is achieved by the readout circuit 8th a fixed bit line potential VBL to the bit line 4 applies and the control variable S to the word line to be addressed 3 invests. The application is made using a word line decoder 13 of the control potential to the word line to be activated depending on an applied word line address ADR 3 and the remaining word lines with a potential, eg the plate potential VPL or a Ground potential, drives, so that the respective selection transistors 5 completely open (non-conductive). The control quantity S is in the controlled state, ie when the predetermined current through the bit line 4 and through the memory cell 2 flows, one from the memory cell 2 date to be read D, assignable. The control quantity S corresponds to a respective potential which, due to the transfer characteristic of the selection transistor 5 in the memory cell 2 for the various resistance states of the resistive memory element 6 has a sufficient potential gap.

In 4 are exemplary characteristic curves of an exemplary memory cell with four different states of the resistive element 6 shown. The various resistance values of the states are 10 kΩ, 35 kΩ, 50 kΩ and 1 MΩ. It can be seen that at a constant current of 5 μA through the memory cell in a first state in which the resistance element has a resistance of 10 kΩ, the control potential applied to the selection transistor 5 is applied, 2.1 V is, in a second state in which the resistance value of the resistive element 35 kΩ, the control potential is 2.25V, in a third state where the resistance of the resistive element 6 50 kΩ, the control potential is 2.4 V and that in a fourth state, in which the resistance element has a high resistance of 1 MΩ. is such that with voltages commonly used in the memory circuit, the constant current of 5 μA is not achievable and therefore is substantially 0 μA.

In 5 is the readout circuit 8th shown in more detail. The readout circuit 8th generates a control quantity S by appropriately tapping a potential from a voltage divider that has multiple resistors 31 to 35 is trained. The first to fifth resistance 31 to 35 are connected in series between a reference potential and a ground potential V _GND . A first node N1 between the first resistor 31 and the second resistor 32 is via a first transistor 41 , a second node N2 between the second resistor 32 and the third resistor 33 is via a second transistor 42 , a third node N3 between the third resistor 33 and the fourth resistor 34 is via a third transistor 43 and a fourth node N4 between the fourth resistor 34 and the fifth resistor 35 is via a fourth transistor 44 with an input of a driver 45 connected. An output driver 45 is essentially formed as a feedback operational amplifier, the voltage applied in the first input, the voltage from the transistors 41 - 44 is delivered, as control size S outputs. Control terminals of the transistors 41 to 44 are each with a decoder 46 connected, which depends on a counter value of a counter 47 each one of the transistors 41 to 44 closes and leaves the other transistors in an open state or leaves. Using a control unit 48 a read is started by the counter 47 is incremented, so that in turn each of the transistors 41 to 44 is closed.

The bit line 4 is via a current detector 49 connected to a voltage source so that, for example, provides a potential equal to a supply voltage. The current detector 49 detects the via the bit line 4 flowing current depending on a reference variable (reference current I _REF ) and outputs a corresponding comparison signal.

The counting up of the counter 47 is stopped when detected by the current detector 49 , Current on the bit line 4 exceeds or falls below the predetermined current, depending on whether the voltage applied to the selection transistor by the succession of transistors 41 to 44 rises or falls. When the power over the bit line 4 reaches the predetermined current or exceeds or falls below, the current count 47 output as date D.

In the present case, the readout circuit 8th of the 5 to read out four different states, so that the counter 47 can be provided as a 2-bit counter. It is then possible to realize a multi-bit memory circuit in which 2 bits can be stored in each memory cell. In a configuration leading to an electrical behavior according to the characteristic of 3 leads, can be easily the corresponding voltages using the voltage divider from the resistors 31 to 35 to generate. To evaluate the multi-bit memory cell, the characteristic of the 4 then voltages should be provided at nodes N1 through N4 that define the boundaries of the various state areas that the memory cell can occupy. In the example shown this could be the voltages of 2.175, 2.325 and 2.6V. In this case, to read out four different states from the multi-bit memory cell, only three read voltages at three nodes N1 to N3 could be provided to detect four states of the multi-bit memory cell.

In 6 a memory circuit according to another embodiment is shown, in which a control variable via the word line decoder 7 to the addressed word line 3 is applied to describe the memory cell so that a peak current that can occur during the transition from a high to a low resistance of the resistive element limited. This is the programming circuit 10 a programming chip ready, with which the resistive element of the addressed memory cell can be brought from a high-impedance to a low-impedance state. Unlike previous CBRAM memory circuits, the word line now becomes 3 so activated that the selection transistor is the resistance element 6 connects to the bit line, so that a programming operation is started. Decreases the resistance of the resistor element 6 Thus, the current through the memory cell increases due to the programming circuitry 10 eg with the help of the current detector 49 through the flow of current through the bit line 4 can be detected. If the current flow through the memory cell exceeds a limit value, the word line decoder is used 7 on the wordline 3 reduces the potential of the control variable, so that the volume resistance of the selection transistor 5 is increased, whereby the current can be limited. In this way, the current through the resistive memory element of the memory cell 2 limit, causing damage to the memory cell 2 can be avoided.

1

CBRAM memory circuit

2

memory cell

3

wordline

4

bit

5

selection transistor

6

resistive element

7

Word line decoder

8th

readout circuit

10

programming circuit

12

control unit

31 to 35

first until fifth resistance

N1 to N4

first to fourth node

41 to 44

first to the fourth transistor

45

decoder

47

counter

48

control unit

49

current detector

55

driver

Claims (14)

Method for reading out a storage date from a resistance memory cell ( 2 ) having a selection transistor controllable by a control quantity, comprising the steps of: detecting a cell current flowing through the resistance memory cell; Adjusting the control quantity depending on the detected cell current. The method of claim 1, wherein the signal passing through the resistive memory cell ( 2 ) is compared with a reference current, and wherein the control quantity is adjusted depending on the result of the comparison. The method of claim 2, wherein the control quantity is set will that the cell current as possible corresponds to the reference current. Method according to claim 2 or 3, wherein a measured variable is applied to the selection transistor ( 5 ) is applied and changed until a sign of a difference between the cell current and the reference current changes, wherein the measured variable at which the sign of the difference changes is set as a control variable. The method of claim 4, wherein the measurand is discrete Values changed becomes. Method according to one of claims 4 or 5, wherein the measured variable from a Number of different values is selected, with a change of the Sign a difference between the cell current and the reference current between consecutively applied measured variables, the last applied measured variable is set as a control variable becomes. Method according to claim 6, wherein the number of different Values of the control variable by one reduced number of detectable states of the resistive memory cell chosen becomes. Memory circuit ( 1 ) with a resistance memory cell ( 2 ), which has a selectable via a control terminal selection transistor ( 5 ) and a current output, and one with the current output of the resistive memory cell ( 2 ) and the control terminal of the selection transistor ( 5 ) connected readout unit ( 8th ) to cause a cell current flowing through the resistive memory cell at the current output of the resistive memory cell ( 2 ) and by a control variable (S) dependent on the detected cell current at the control terminal of the selection transistor ( 5 ), the read-out unit ( 8th ) provides information associated with the control quantity as a storage date. Memory circuit according to claim 8, wherein the readout unit ( 8th ) comprises: - a current detector ( 49 ) by the resistance memory cell ( 2 ) to compare flowing cell current with a reference current, and - a control unit ( 48 ) to adjust the control amount depending on the result of the comparison. A memory circuit according to claim 9, wherein the control unit ( 48 ) is configured to adjust the control amount so that the cell current as possible corresponds to the reference current. Memory circuit according to claim 9 or 10, the control unit ( 48 ) a measuring circuit ( 41 - 44 . 45 ) to apply a measurand to the selection transistor ( 5 ) and to modify them until a comparator unit determines that a sign of a difference between the cell current and the reference current has changed, the control unit ( 48 ) is further configured to set the measurand at which the sign of the difference changes as a control quantity. Memory circuit ( 1 ) according to claim 11, wherein the measuring circuit is designed to change the measured variable by discrete values. Memory circuit ( 1 ) according to one of claims 11 or 12, wherein the measuring circuit is designed to select the measured variable from a number of different values, and wherein the control unit ( 48 ) sets at a change in the sign of a difference between the cell current and the reference _current I _REF between consecutively applied measured variables, the last applied measured variable as a control variable. Memory circuit ( 1 ) according to claim 13, wherein the number of different values of the control quantity of a number of detectable states of the resistance memory cell (1) reduced by one 2 ) is selected.