US20120190195A1 - Methods for fabricating semiconductor devices having local contacts - Google Patents
Methods for fabricating semiconductor devices having local contacts Download PDFInfo
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- US20120190195A1 US20120190195A1 US13/014,561 US201113014561A US2012190195A1 US 20120190195 A1 US20120190195 A1 US 20120190195A1 US 201113014561 A US201113014561 A US 201113014561A US 2012190195 A1 US2012190195 A1 US 2012190195A1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Abstract
Description
- Embodiments of the subject matter generally relate to semiconductor device fabrication methods, and more particularly, relate to fabrication methods for forming local contacts to doped regions formed in a semiconductor substrate.
- Transistors, such as metal oxide semiconductor field-effect transistors (MOSFETs), are the core building block of the vast majority of semiconductor devices. Some semiconductor devices, such as high performance processor devices, can include millions of transistors. For such devices, decreasing transistors size, and thus increasing transistor density, has traditionally been a high priority in the semiconductor manufacturing industry. As the size and spacing of the transistors decrease, it is more difficult to avoid inadvertent creation of electrical connections between adjacent devices, which, in turn, reduces yield.
- A method is provided for fabricating a semiconductor device structure. The semiconductor device includes a gate structure overlying a semiconductor substrate and a doped region formed in the semiconductor substrate adjacent to the gate structure. The method involves the steps of forming a first layer of dielectric material overlying the gate structure and the doped region, isotropically etching the first layer of dielectric material, forming a second layer of dielectric material overlying the first layer of dielectric material after isotropically etching the first layer, and forming a conductive contact within the first layer and the second layer. The conductive contact is electrically connected to the doped region.
- In another embodiment, a method is provided for fabricating a CMOS device on a semiconductor substrate having a first transistor region and a second transistor region. The method involves the steps of forming a layer of a stress-inducing material overlying the first transistor region and the second transistor region, removing portions of the stress-inducing material overlying the second transistor region, and isotropically etching portions of the stress-inducing material overlying the first transistor region after removing the portions of the stress-inducing material overlying the second transistor region. The method continues by forming a layer of a dielectric material overlying the first transistor region and the second transistor region, and forming conductive contacts in the layer of the dielectric material that are electrically connected to doped regions formed in the semiconductor substrate.
- In yet another embodiment, a method is provided for fabricating a semiconductor device that includes a plurality of gate structures overlying a semiconductor substrate and doped regions formed in the semiconductor substrate adjacent to each respective gate structure. The method involves the steps of conformably depositing a stress-inducing nitride material overlying the gate structures and the doped regions, isotropically etching portions of the stress-inducing nitride material overlying the gate structures, conformably depositing an oxide material overlying the stress-inducing nitride material after isotropically etching the portions of the stress-inducing nitride material overlying the gate structures, and forming conductive contacts in the oxide material. Each conductive contact overlies and is electrically connected to a respective doped region.
- This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
- A more complete understanding of the subject matter may be derived by referring to the detailed description and claims when considered in conjunction with the following figures, wherein like reference numbers refer to similar elements throughout the figures.
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FIGS. 1-9 are cross-sectional views that illustrate a CMOS semiconductor device structure and methods for fabricating the CMOS semiconductor device structure in exemplary embodiments; and -
FIG. 10 is a cross-sectional view that illustrates a CMOS semiconductor device structure and related methods for fabricating the CMOS semiconductor device structure in accordance with one embodiment. - The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description.
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FIGS. 1-9 illustrate a CMOSsemiconductor device structure 100 and related process steps for fabricating the CMOSsemiconductor device structure 100 with conductive electrical contacts (also referred to herein as local contacts) to doped source/drain regions formed in a semiconductor substrate. Although the subject matter is described herein in the context of a CMOS semiconductor device, the subject matter is not intended to be limited to CMOS semiconductor devices, and may be utilized with other MOS semiconductor devices which are not CMOS semiconductor devices. Additionally, although the term “MOS device” properly refers to a device having a metal gate electrode and an oxide gate insulator, that term will be used throughout to refer to any semiconductor device that includes a conductive gate electrode (whether metal or other conductive material) that is positioned over a gate insulator (whether oxide or other insulator) which, in turn, is positioned over a semiconductor substrate. Various steps in the fabrication of MOS semiconductor devices are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well known process details. - Referring now to
FIG. 1 , the fabrication process begins after front end of line (FEOL) processing steps are performed to fabricate a CMOSsemiconductor device structure 100 that includes a plurality ofMOS transistor structures regions semiconductive material 102, such as monocrystalline silicon or another silicon-comprising material, in a conventional manner. For example, theregions semiconductor material 102 may be isolated by performing shallow trench isolation (STI) or another suitable process known in the art to form aninsulating material 105, such as silicon dioxide, in between theregions semiconductor material 102. Theinsulating material 105 may hereinafter be referred to for convenience, but without limitation, as the field oxide. In an exemplary embodiment, theisolated regions transistor structures type region 101 ofsemiconductor material 102 may be formed by maskingregion 103 and implanting N-type ions, such as phosphorous or arsenic ions, intoregion 101. In this regard, portions of the N-type region 101 functions as N-wells forPMOS transistor structures region 101. Similarly, the N-type region 101 may be masked and P-wells forNMOS transistor structures region 103 by implanting P-type ions, such as boron ions, intoregion 103. For convenience, the N-type (or N-well)region 101 may alternatively be referred to herein as the PMOS transistor region and P-type (or P-well)region 103 may alternatively be referred to herein as the NMOS transistor region. - As illustrated in
FIG. 1 , eachtransistor structure gate structure semiconductor substrate 102 that functions as a gate electrode for therespective transistor structure gate structures gate structure semiconductor substrate 102, and at least one layer of conductive material overlying the dielectric material. It should be understood that various numbers, combinations and/or arrangements of materials may be utilized for the gate structures in a practical embodiment, and the subject matter described herein is not limited to any particular number, combination, or arrangement of gate material(s) in the gate structure. Additionally, the subject matter is not intended to be limited to any particular number of gate structures. Eachtransistor structure regions semiconductor substrate 102 adjacent to itsrespective gate structure respective transistor structures doped regions drain regions 120 for thePMOS transistor structures PMOS transistor region 101 using thegate structures NMOS transistor region 103 is masked, and N-type source/drain regions 122 for theNMOS transistor structures NMOS transistor region 103 using thegate structures PMOS transistor region 101 is masked. It should be appreciated that althoughFIG. 1 depicts the source/drain regions as being integrally formed with or otherwise contiguous with source/drain regions of adjacent transistor structures for purposes of illustration, the subject matter is not intended to be limited to any particular arrangement of the source/drain regions. - In an exemplary embodiment, the source/
drain regions contact regions 124 formed on their upper surface to facilitate forming electrical connections between the source/drain regions transistor structures contact regions 124 may be realized as a metal silicide layer formed on exposed upper surfaces of the source/drain regions gate structures - Still referring to
FIG. 1 , in an exemplary embodiment, the fabrication process continues by forming a layer of a stress-inducingdielectric material 130 overlying thetransistor structures material 130 may be formed by conformably depositing a layer of tensile stress-inducing silicon nitride using a plasma-enhanced chemical vapor deposition (PECVD) process. The desired amount of tensile stress provided by the deposited layer of silicon nitride material can be modified by adjusting the chamber conditions for the PECVD process (e.g., voltage, temperature, pressure, gas ratios, or the like) to achieve a layer of tensile stress-inducingsilicon nitride material 130 having the desired tensile stress properties. For convenience, but without limitation, the stress-inducingdielectric material 130 is alternatively referred to herein as the tensile stress-inducing nitride material. The tensile stress-inducingnitride material 130 provides a tensile stress that increases the mobility of electrons in the channel region of theNMOS transistor structures - In an exemplary embodiment, after forming the layer of tensile stress-inducing
nitride material 130, the fabrication process continues by forming a layer of anoxide material 132 overlying the layer of tensile stress-inducingnitride material 130, resulting in the CMOSsemiconductor device structure 100 ofFIG. 1 . The layer ofoxide material 132 is formed by conformably depositing an oxide material overlying the layer of tensile stress-inducingmaterial 130 using a chemical vapor deposition (CVD) process. The layer ofoxide material 132 functions as an etch stop layer that protects the portions of the underlying tensile stress-inducingmaterial 130 that overlie theNMOS transistor region 103, as described in greater detail below. In an exemplary embodiment, the thickness of the layer ofoxide material 132 is less than about 20 nanometers (nm). - Referring now to
FIG. 2 , in an exemplary embodiment, the fabrication process continues by masking theNMOS transistor region 103 and removing portions of the tensile stress-inducingnitride material 130 and portions of theoxide material 132 overlying thePMOS transistor region 101. In this regard, a layer of masking material (e.g., a photoresist material) is formed overlying thedevice structure 100 ofFIG. 1 , and the portions of the masking material overlying thePMOS transistor region 101 are removed (e.g., using photolithography) to define an etch mask that exposes portions of theoxide material 132 and the tensile stress-inducingmaterial 130 overlying thePMOS transistor region 101. The exposed portions of the tensile stress-inducingnitride material 130 and theoxide material 132 overlying thePMOS transistor region 101 are removed by performing plasma-based reactive ion etching (RIE) to anisotropically etch the tensile stress-inducingnitride material 130 and theoxide material 132 with an anisotropic etchant chemistry using the patterned masking material as an etch mask. Depending on the embodiment, the tensile stress-inducingnitride material 130 and theoxide material 132 may be removed concurrently during a single etch process step, or theoxide material 132 may be removed during a first etch process step and the tensile stress-inducingnitride material 130 removed during a subsequent etch process step. The masking material is resistant to the anisotropic etchant chemistry and/or has a thickness such that theunderlying oxide material 132 on theNMOS transistor region 103 is not exposed and remains intact during the etch process step(s). After removing the tensile stress-inducingmaterial 130 and theoxide material 132 from thePMOS transistor region 101, any remaining masking material overlying theNMOS transistor region 103 is removed, resulting in thedevice structure 100 ofFIG. 2 . - Referring now to
FIG. 3 , in an exemplary embodiment, the fabrication process continues by forming a layer of a second stress-inducingdielectric material 140 overlying thedevice structure 100 ofFIG. 2 . In an exemplary embodiment, the thickness of the layer of the second stress-inducingdielectric material 140 is greater than or equal to the thickness of the first stress-inducingdielectric material 130, however, the subject matter is not intended to be limited to any particular thickness for the second stress-inducingdielectric material 140, and in alternate embodiments, the thickness of the layer of the second stress-inducingdielectric material 140 may be less than the thickness of the first stress-inducingdielectric material 130. In the illustrated embodiment, the thickness of the layer of the second stress-inducingdielectric material 140 is substantially equal to the sum of the thicknesses of the first stress-inducingdielectric material 130 and theoxide material 132. - In an exemplary embodiment, the second stress-inducing
material 140 is realized as a compressive stress-inducing material. The layer of compressive stress-inducingmaterial 140 is preferably formed by conformably depositing a layer of compressive stress-inducing silicon nitride using a PECVD process. As described above, the desired amount of compressive stress provided by the deposited layer of silicon nitride material can be modified by adjusting the chamber conditions for the PECVD process to achieve a layer of compressive stress-inducing silicon nitride material 144 having the desired compressive stress properties. For convenience, but without limitation, the second stress-inducingdielectric material 140 is alternatively referred to herein as the compressive stress-inducing nitride material. The compressive stress-inducingnitride material 140 provides a compressive stress that increases the mobility of holes in the channel region of thePMOS transistor structures - Referring now to
FIG. 4 , in an exemplary embodiment, after forming the compressive stress-inducingnitride material 140, the fabrication process continues by masking thePMOS transistor region 101 and removing portions of the compressive stress-inducingmaterial 140 overlying theNMOS transistor region 103. In this regard, a layer of maskingmaterial 146 is formed overlying thedevice structure 100 ofFIG. 3 , and portions of the maskingmaterial 146 overlying theNMOS transistor region 103 are removed to define an etch mask that exposes theNMOS transistor region 103. In an exemplary embodiment, the layer of maskingmaterial 146 is formed by applying a photoresist material overlying thedevice structure 100 ofFIG. 3 , then patterning and removing portions of the photoresist material overlying theNMOS transistor region 103 using photolithography. For convenience, but without limitation, the maskingmaterial 146 is alternatively referred to herein as photoresist material. After patterning and removing portions of thephotoresist material 146, the exposed portions of the compressive stress-inducingnitride material 140 overlying theNMOS transistor region 103 are removed using the remainingphotoresist material 146 as an etch mask. In an exemplary embodiment, the exposed portions of the compressive stress-inducingnitride material 140 are removed using an anisotropic etch process that stops on theoxide material 132, for example, by plasma-based RIE using an anisotropic etchant, such as an argon plasma chemistry, a fluorocarbon-based plasma chemistry, or sulfur hexafluoride (SF6) chemistry, with an applied bias voltage to anisotropically etch the compressive stress-inducingnitride material 140 with good selectivity to theoxide material 132. In this regard, the anisotropic etchant used to etch the compressive stress-inducingnitride material 140 does not etch theunderlying oxide material 132 at the same rate or otherwise does not attack theunderlying oxide material 132, such that theunderlying oxide material 132 acts as an etch stop. Thephotoresist material 146 prevents the anisotropic etchant from removing portions of the compressive stress-inducingnitride material 140 overlying thePMOS transistor region 101 while the exposed portions of the compressive stress-inducingnitride material 140 overlying theNMOS transistor region 103 are etched until theunderlying oxide material 132 is exposed. Thephotoresist material 146 is preferably resistant to the anisotropic etchant chemistry and/or has a thickness such that the upper surfaces of the compressive stress-inducingnitride material 140 overlying thePMOS transistor region 101 is not exposed during the etch process step. - Referring now to
FIG. 5 , in an exemplary embodiment, the fabrication process continues by removing thephotoresist material 146 overlying thePMOS transistor region 101 and isotropically etching the compressive stress-inducingnitride material 140 overlying thePMOS transistor region 101 after thephotoresist material 146 is removed. In this regard, thephotoresist material 146 may be removed by a photoresist removal process using commonly known etchant chemistries that remove thephotoresist material 146 while leaving theoxide material 132 substantially intact. In the illustrated embodiment ofFIG. 5 , thephotoresist material 146 is completely removed, that is, thephotoresist material 146 is removed until the compressive stress-inducingnitride material 140 is exposed. After removing thephotoresist material 146, the fabrication process continues by isotropically etching the compressive stress-inducing nitride material 144 by plasma etching using an isotropic etchant chemistry to isotropically etch the compressive stress-inducingnitride material 140 with good selectivity to theoxide material 132. In this manner, theoxide material 132 protects the underlying tensile stress-inducingnitride material 130 overlying theNMOS transistor region 103 while the compressive stress-inducingnitride material 140 overlyingPMOS transistor region 101 is etched. - In an exemplary embodiment, the operating conditions of the isotropic etch process are modified to etch the upper portions of the compressive stress-inducing
nitride material 140, that is, the portions of the compressive stress-inducingnitride material 140 on top of or adjacent to the sidewalls of thegate structures nitride material 140, that is, the portions of the compressive stress-inducingmaterial 140 overlying the doped source/drain regions 120. For example, in an exemplary embodiment, the isotropic plasma etch process is performed using a carbon trifluoride/oxygen/helium (CHF3/O2/He) plasma without applying a bias voltage to achieve higher mass transport rates at or near the upper portions of thegate structures gate structures underlying semiconductor substrate 102 increases. Thus, although the portions of the compressive stress-inducingnitride material 140 overlying thegate structures material 140 overlying the doped source/drain regions 120 are etched concurrently during the isotropic etch process, by virtue of the etch rate being greater for the portions of the compressive stress-inducingnitride material 140 overlying thegate structures nitride material 140 on top of thegate structures nitride material 140 adjacent to thegate structures nitride material 140 in contact with the contact regions 124). - Referring now to
FIG. 6 , in an exemplary embodiment, the fabrication process begins by forming a layer ofdielectric material 150 overlying thedevice structure 100 ofFIG. 5 , resulting in thedevice structure 100 ofFIG. 6 . In an exemplary embodiment, the layer ofdielectric material 150 is realized as a layer of an oxide material, such as silicon dioxide, that is conformably deposited overlying thedevice structure 100 ofFIG. 5 to a thickness chosen such that theoxide material 150 fills any gaps between neighboringgate structures gate structures gate structures nitride material 140. For example, a layer of silicon dioxide be formed by CVD or atomic layer deposition (ALD) at a temperature that is less than about 500° C. until the gaps between thegate structures gate structures dielectric material 150 is alternatively referred to herein as an oxide material. - Referring now to
FIG. 7 , in an exemplary embodiment, after forming the layer ofoxide material 150, the fabrication process continues by removing portions of thedielectric materials planar surface 152 that is aligned with the upper surface of thegate structures device structure 100 illustrated byFIG. 7 . In an exemplary embodiment, the fabrication process planarizes thedielectric materials dielectric materials semiconductor substrate 102 until reaching the upper surface of thegate structures dielectric materials gate structures dielectric materials gate structures planar surface 152 that is aligned with the upper surfaces of thegate structures - Referring now to
FIGS. 8-9 , in an exemplary embodiment, after the planarization step, the fabrication process continues by selectively removing portions of thedielectric materials drain regions local contacts regions regions local contacts planar surface 152, and portions of the masking material are selectively removed to define a mask that exposes portions of theoxide material 150 overlying the source/drain regions regions gate structures dielectric materials gate structures local contacts adjacent gate structures dielectric materials oxide material nitride material underlying nitride material oxide material nitride material contact regions 124 are exposed. After removing exposed portions of thenitride material regions - After creating voided
regions contact regions 124, the fabrication process continues by forminglocal contacts regions local contacts conductive material 180 that provides an electrical connection to source/drain regions local contacts conductive material 180, such as a tungsten material, to a thickness chosen such that theconductive material 180 fills the voidedregions gate structures local contacts gate structures regions contact regions 124 to provide a conductive electrical connection between the source/drain regions contact regions 124 andlocal contacts semiconductor substrate 102 and/orcontact regions 124. Although not illustrated, it should be noted that in some embodiments, a relatively thin layer of a barrier material may be formed in the voidedregions conductive material 180. After forming the layer ofconductive material 180 for thelocal contacts CMOS device structure 100 to remove portions of theconductive material 180 that did not fill the voided regions to obtain a substantiallyplanar surface 190 that is aligned with the upper surface of thegate structures semiconductor device structure 100 ofFIG. 9 . In this regard, theconductive material 180 is uniformly removed across the CMOSsemiconductor device structure 100 until reaching thegate structures conductive material 180 with a chemical slurry and stopping when the upper surfaces of thegate structures - After forming the local contacts, the fabrication process may continue by performing well known back end of line (BEOL) process steps to complete fabrication of the CMOS
semiconductor device structure 100 in a conventional manner. For example, the through-contact fabrication process may proceed by forming an interlayer dielectric material overlying theplanar surface 190, forming vias in the interlayer dielectric material, and forming a metal interconnect layer (e.g., Metal 1) overlying the interlayer dielectric material, and repeating these metallization steps until all of the necessary metal interconnect layers have been formed. -
FIG. 10 illustrates an alternate embodiment of the fabrication process described above. In the alternate embodiment, after removing the compressive stress-inducingnitride material 140 from theNMOS transistor region 103, thephotoresist material 146 overlying thePMOS transistor region 101 is only partially removed before isotropically etching the compressive stress-inducingnitride material 140 overlying thePMOS transistor region 101. In this regard, thephotoresist material 146 may be partially removed by performing a photoresist removal process for a predetermined amount of time that removes the portions of thephotoresist material 146 overlying thegate structures photoresist material 146 adjacent to thegate structures drain regions 120 substantially intact. In an exemplary embodiment, thephotoresist material 146 is removed until the height of thephotoresist material 146 disposed betweenadjacent gate structures drain regions 120 is less than the height of thegate structures photoresist material 146, the fabrication process continues by isotropically etching the compressive stress-inducingnitride material 140 using an isotropic etchant chemistry that is selective to theoxide material 132 in a similar manner as described above in the context ofFIG. 5 . In this regard, thephotoresist material 146 protects the compressive stress-inducingnitride material 140 overlying the doped source/drain regions 120 adjacent togate structures material 140 on top of thegate structures gate structures nitride material 140 on top of thegate structures nitride material 140 overlying the source/drain regions 120. After isotropically etching the exposed portions of the compressive stress-inducingnitride material 140, the fabrication process continues by removing the remaining portions of thephotoresist material 146 and completing fabrication oflocal contacts semiconductor device structure 100 as described in the context ofFIGS. 6-9 . - To briefly summarize, one advantage of the fabrication processes described herein is that by isotropically etching the compressive stress-inducing
nitride material 140 to round the corners near the top of thegate structures oxide material 150 is capable of filling the gaps between thePMOS gate structures PMOS gate structures oxide material 150, which in turn, prevents undesirable electrical connections that may otherwise be created when theconductive material 180 for thelocal contacts semiconductor substrate 102. It should be appreciated that although the subject matter is described herein in the context of isotropically etching the compressive stress-inducingnitride material 140 for thePMOS transistors nitride material 130 for theNMOS transistors nitride material 130 and before forming the layer ofoxide material 132, the tensile stress-inducingnitride material 130 may be isotropically etched using an isotropic etch process that is modified to etch the upper portions of the tensile stress-inducing nitride material 130 (e.g., the portions of the tensile stress-inducingnitride material 130 ontop gate structures gate structures nitride material 130 overlying the doped source/drain regions gate structures nitride material 130 on top of thegate structures nitride material 130 between adjacent to thegate structures drain regions 122. In this embodiment, after isotropically etching the tensile stress-inducingnitride material 130, the fabrication process continues by forming the layer ofoxide material 132 and removing portions of the tensile stress-inducingnitride material 130 and theoxide material 132 from thePMOS transistor region 101, as described above in the context ofFIGS. 1-2 , before completing fabrication of local contacts for the CMOS semiconductor device structure. In yet other embodiments, the order in which the tensile and compressive stress-inducing dielectric materials are formed may be interchanged, in which case, the first stress-inducingdielectric material 130 may be realized as a compressive stress-inducing material that is removed from theNMOS region 103, and the second stress-inducingdielectric material 140 may be realized as a tensile stress-inducing nitride material that is isotropically etched using an isotropic etch process after being removed from thePMOS region 101, in a similar manner as described above. - While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the described embodiment or embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope defined by the claims, which includes known equivalents and foreseeable equivalents at the time of filing this patent application.
Claims (21)
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US13/014,561 US8216928B1 (en) | 2011-01-26 | 2011-01-26 | Methods for fabricating semiconductor devices having local contacts |
TW100139292A TWI511187B (en) | 2011-01-26 | 2011-10-28 | Methods for fabricating semiconductor devices having local contacts |
KR1020110128623A KR101541437B1 (en) | 2011-01-26 | 2011-12-02 | Methods for fabricating semiconductor devices having local contacts |
CN201110415066.3A CN102623390B (en) | 2011-01-26 | 2011-12-13 | Make the method with the semiconductor device of local node |
DE102012201025.4A DE102012201025B4 (en) | 2011-01-26 | 2012-01-25 | Method for producing semiconductor devices with local contacts |
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US13/014,561 US8216928B1 (en) | 2011-01-26 | 2011-01-26 | Methods for fabricating semiconductor devices having local contacts |
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US20120190195A1 true US20120190195A1 (en) | 2012-07-26 |
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JP4173672B2 (en) * | 2002-03-19 | 2008-10-29 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method thereof |
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US7288451B2 (en) * | 2005-03-01 | 2007-10-30 | International Business Machines Corporation | Method and structure for forming self-aligned, dual stress liner for CMOS devices |
US7785950B2 (en) | 2005-11-10 | 2010-08-31 | International Business Machines Corporation | Dual stress memory technique method and related structure |
US7935587B2 (en) * | 2006-06-09 | 2011-05-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Advanced forming method and structure of local mechanical strained transistor |
US8536660B2 (en) * | 2008-03-12 | 2013-09-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid process for forming metal gates of MOS devices |
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