US20120132459A1 - Circuit board including aligned nanostructures - Google Patents
Circuit board including aligned nanostructures Download PDFInfo
- Publication number
- US20120132459A1 US20120132459A1 US13/366,184 US201213366184A US2012132459A1 US 20120132459 A1 US20120132459 A1 US 20120132459A1 US 201213366184 A US201213366184 A US 201213366184A US 2012132459 A1 US2012132459 A1 US 2012132459A1
- Authority
- US
- United States
- Prior art keywords
- nanostructure
- electrode
- circuit board
- substrate
- polymer substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/032—Organic insulating material consisting of one material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0393—Flexible materials
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/207—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a prefabricated paste pattern, ink pattern or powder pattern
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/167—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed resistors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0162—Silicon containing polymer, e.g. silicone
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0203—Fillers and particles
- H05K2201/0242—Shape of an individual particle
- H05K2201/026—Nanotubes or nanowires
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/032—Materials
- H05K2201/0323—Carbon
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0502—Patterning and lithography
- H05K2203/0522—Using an adhesive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
- H05K2203/105—Using an electrical field; Special methods of applying an electric potential
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1173—Differences in wettability, e.g. hydrophilic or hydrophobic areas
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1453—Applying the circuit pattern before another process, e.g. before filling of vias with conductive paste, before making printed resistors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49121—Beam lead frame or beam lead device
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49162—Manufacturing circuit on or in base by using wire as conductive path
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Definitions
- the described technology relates generally to a circuit board including aligned nanostructures.
- Some embodiments disclosed herein include a circuit board having a polymer substrate, a first electrode and a second electrode disposed on a surface of the polymer substrate, and at least one nanostructure electrically connected to the first and second electrodes.
- FIG. 1 is a perspective view of a circuit board according to one embodiment.
- FIG. 2 is a plan view ((a) of FIG. 2 ) and a cross-sectional view ((b) of FIG. 2 ) of the circuit board shown in FIG. 1 .
- FIG. 3 is a flowchart illustrating a method for fabricating a circuit board according to one embodiment.
- FIGS. 4 to 11 are plan views ((a) of FIGS. 4 to 11 ) and cross-sectional views ((b) of FIGS. 4 to 11 ) illustrating a method for fabricating a circuit board according to one embodiment.
- FIGS. 12 to 17 are plan views ((a) of FIGS. 12 to 17 ) and cross-sectional views ((b) of FIGS. 12 to 17 ) illustrating a method for fabricating a circuit board according to another embodiment.
- FIGS. 18 to 25 are plan views ((a) of FIGS. 18 to 25 ) and cross-sectional views ((b) of FIGS. 18 to 25 ) illustrating a method for fabricating a circuit board according to another embodiment.
- FIG. 1 is a perspective view of a circuit board according to one embodiment.
- FIG. 2 is a plan view ((a) of FIG. 2 ) and a cross-sectional view ((b) of FIG. 2 ) of the circuit board shown in FIG. 1 .
- the cross-sectional view is taken from a line A-A′ in the plan view.
- a circuit board 100 may include a polymer substrate 111 , a first electrode 112 , a second electrode 113 and at least one nanostructure 114 .
- the polymer substrate 111 may be, for example, a flexible substrate.
- the flexible substrate may be a silicon polymer substrate such as a polydimethylsiloxane (PDMS) substrate.
- PDMS is flexible, inert, nontoxic and incombustible, and thus may be a suitable material for bio-applications or other similar applications.
- the first electrode 112 and the second electrode 113 are disposed on a surface of the polymer substrate 111 .
- the first electrode 112 and the second electrode 113 may be disposed on the surface of the polymer substrate 111 in an arrangement in which portions of the respective first and second electrodes 112 and 113 are depressed in the polymer substrate 111 , as shown in FIG. 1 .
- the first electrode 112 and the second electrode 113 may be disposed on the surface of the polymer substrate 111 in an arrangement in which portions of respective first and second electrodes 112 and 113 are disposed above the surface of the polymer substrate 111 .
- the first and second electrodes 112 and 113 are conductors, and may include, for example, a metal or a doped polysilicon.
- Each of the first electrode 112 and the second electrode 113 may include a multilayer structure having a gold layer 121 and a palladium layer 122 as shown in FIG. 2 . As illustrated in FIGS. 1 and 2 , the first electrode 112 and the second electrode 113 are disposed above some of the at least one nanostructure 114 ; alternatively, the first electrode 112 and the second electrode 113 may be disposed below some of the at least one nanostructure 114 .
- the at least one nanostructure 114 is electrically connected to the first electrode 112 and the second electrode 113 .
- FIGS. 1 and 2 illustrate the at least one nanostructure 114 connected to the first and second electrodes.
- the connection between the at least one nanostructure 114 and the first and second electrodes 112 and 113 is not limited to a case in which each of the at least one nanostructure 114 is directly connected to the first and second electrodes 112 and 113 .
- a portion of one nanostructure of the at least one nanostructure 114 may be electrically connected to the first electrode 112
- a portion of another nanostructure of the at least one nanostructure 114 may be electrically connected to the second electrode 113
- the one nanostructure and the other nanostructure may be electrically connected to each other.
- a portion of one nanostructure of the at least one nanostructure 114 may be electrically connected to the first electrode 112
- a portion of another nanostructure of the at least one nanostructure 114 may be electrically connected to the second electrode 113
- the one nanostructure and the other nanostructure may be electrically connected to each other via at least yet another nanostructure of the at least one nanostructure 114 .
- the at least one nanostructure 114 may include, for example, a nanotube, a nanowire, or a nanorod, each having a linear structure.
- the nanotube may be a carbon nanotube.
- the nanowire and nanorod may be formed of various materials including a conductive polymer, vanadium oxide, indium oxide, zinc oxide, tin oxide, cadmium oxide, silicon, germanium, gallium nitride, or combinations thereof.
- the at least one nanostructure 114 may be aligned in a longitudinal direction L of a pattern 123 formed by the at least one nanostructure 114 .
- the alignment of the at least one nanostructure 114 in the longitudinal direction L does not mean that all of the at least one nanostructure 114 are aligned in the longitudinal direction L.
- the alignment of the at least one nanostructure 114 in the longitudinal direction L excludes a case in which at least one nanostructure 114 is arbitrarily disposed.
- the alignment of the at least one nanostructure 114 in the longitudinal direction L means that the at least one nanostructure 114 is intentionally aligned in the longitudinal direction L.
- the at least one nanostructure 114 is aligned in the longitudinal direction L.
- a resistance between the first electrode 112 and the second electrode 113 may be reduced compared to the case in which the at least one nanostructure 114 is arbitrarily disposed.
- At least a portion of the at least one nanostructure 114 may be disposed within the polymer substrate 111 as shown in FIG. 2 .
- the polymer substrate 111 may act to protect the at least one nanostructure 114 .
- the possibility of the at least one nanostructure 114 being separated from the polymer substrate 111 may be reduced compared to a case in which the at least one nanostructure 114 is disposed outside the polymer substrate 111 .
- the at least one nanostructure 114 when a portion or all of the at least one nanostructure 114 is disposed within the polymer substrate 111 , noise caused by a liquid or the like with which the at least one nanostructure 114 may come in contact may be reduced compared to the case in which the at least one nanostructure 114 is disposed outside the polymer substrate 111 .
- the at least one nanostructure 114 may be formed above the surface of the polymer substrate 111 .
- the at least one nanostructure 114 may be used as an electric line for electrically connecting the first electrode 112 to the second electrode 113 .
- electrical characteristics of the at least one nanostructure 114 may be changed according to an amount or degree of light, molecules, deoxyribonucleic acid (DNA) or temperature.
- the at least one nanostructure 114 may be used as a component of a sensor or a transistor.
- the circuit board 100 does not necessarily include a closed circuit formed in the polymer substrate 111 . That is, the circuit board 100 may have the first electrode 112 , the second electrode 113 and the at least one nanostructure 114 electrically connected between the first and second electrodes which are formed on the polymer substrate 111 without the closed circuit.
- nanostructures are not randomly arranged but are uniformly arranged between electrodes, and thus the circuit board may have a small resistance between the electrodes.
- a nanostructure circuit is depressed in a polymer substrate, and thus the circuit board may be flexible and stable.
- FIG. 3 is a flowchart illustrating a method for fabricating a circuit board according to one embodiment.
- a first substrate is provided.
- the first substrate may be, for example, a substrate formed of a metal (e.g., gold, aluminum), a semiconductor (e.g., silicon, silicon-on-insulator), glass or an oxide (e.g., SiO 2 ).
- a circuit including a first electrode, a second electrode, and at least one nanostructure is formed on the first substrate.
- the at least one nanostructure may have a nanotube, a nanowire, or a nanorod, each having a linear structure.
- the nanotube may be a carbon nanotube.
- the nanowire and nanorod may be formed of various materials including a conductive polymer, vanadium oxide, indium oxide, zinc oxide, tin oxide, cadmium oxide, silicon, germanium, gallium nitride, or combinations thereof.
- the circuit is then transferred from the first substrate to a surface of a second substrate formed of a polymer.
- the second substrate may be, for example, a flexible substrate.
- the flexible substrate may be a silicon polymer substrate such as, by way of example, a PDMS substrate.
- Block 330 may include blocks 331 to 333 as shown in FIG. 3 .
- a fluid material is provided on the first substrate with the circuit.
- the fluid material provided on the first substrate is cured by a conventional method.
- the second substrate obtained by curing the fluid material is separated from the first substrate so that the circuit is transferred from the first substrate to the second substrate.
- the circuit When the circuit board is fabricated by the method as described above, the circuit may be formed in the substrate made of a semiconductor, a metal, glass, or an oxide using a conventional microfabrication process and then transferred to the polymer substrate, so that the circuit may be easily formed on the polymer substrate.
- the circuit board when the circuit board is fabricated in the manner as described above, at least a portion of the at least one nanostructure may be disposed in the polymer substrate.
- FIGS. 4 to 11 are plan views ((a) of FIGS. 4 to 11 ) and cross-sectional views ((b) of FIGS. 4 to 11 ) illustrating a method for fabricating a circuit board according to one embodiment.
- the cross-sectional view of each drawing is taken from a line A-A′ in the plan view.
- a first substrate 431 is prepared.
- Various kinds of substrates as described above with reference to FIG. 3 may be used as the first substrate 431 .
- a polar molecular layer pattern 432 and a nonpolar molecular layer pattern 433 are formed on the first substrate 431 .
- the formation of the polar molecular layer pattern 432 and the nonpolar molecular layer pattern 433 allows a surface of the first substrate 431 to be divided into a region where the polar molecular layer pattern 432 is formed and a region where the nonpolar molecular layer pattern 433 is formed.
- the polar molecular layer pattern 432 may be charged with positive or negative ions in accordance with the used material.
- an oxide nanostructure usually having surface charges is provided onto the polar molecular layer pattern 432 , the oxide nanostructure adheres to the surface of the polar molecular layer pattern 432 by electrostatic interaction between the oxide nanostructure and the polar molecular layer pattern 432 .
- the polar molecular layer pattern 432 may be, for example, a self-assembled monolayer (SAM) having a compound with a carboxyl group terminus (—COOH/—COO ⁇ ). In this case, the polar molecular layer pattern 432 is charged with negative ions.
- SAM self-assembled monolayer
- the compound having the carboxyl group terminus may be, for example, 16-mercaptohexadecanoic acid (MHA).
- MHA 16-mercaptohexadecanoic acid
- the polar molecular layer pattern 432 may be, for example, an SAM having 2-mercaptoimidazole (2-MI) or a compound having an amino group terminus (—NH 2 /—NH 3 + ). In this case, the polar molecular layer pattern 432 is charged with positive ions.
- the compound having the amino group terminus may be, for example, cysteamine.
- the polar molecular layer pattern 432 may be, for example, an SAM having aminopropyltriethoxysilane (APTES).
- the nonpolar molecular layer pattern 433 is not charged with positive or negative ions but neutral. Accordingly, when the oxide nanostructure is used as the nanostructure, the nanostructure may not be attached to the nonpolar molecular layer pattern 433 . Even when the nanostructure is attached to the nonpolar molecular layer, the nanostructure may be relatively easily detached from the nonpolar molecular layer compared to the nanostructures attached to the polar molecular layer pattern 432 .
- the nonpolar molecular layer pattern 432 may be, for example, an SAM having a compound with a methyl terminus.
- the suitable material for forming the nonpolar molecular layer pattern 433 may be a thiol compound such as 1-octadecanethiol (ODT).
- ODT 1-octadecanethiol
- the suitable material for forming the nonpolar molecular layer pattern 433 may be, for example, a silane compound such as octadecyltrichlorosilane (OTS), octadecyltrimethoxysilane (OTMS) or octadecyltriethoxysilane (OTE).
- the polar molecular layer pattern 432 and the nonpolar molecular layer pattern 433 may be formed by, for example, a dip-pen nanolithography (DPN) method, a microcontact printing method ( ⁇ CP) or a photolithography method.
- DPN dip-pen nanolithography
- ⁇ CP microcontact printing method
- photolithography method for example, a photolithography method.
- the first electrode 412 and the second electrode 413 are formed on the polar molecular layer pattern 432 .
- the first electrode 412 and the second electrode 413 are conductors, and may be a metal such as aluminum (Al), palladium (Pd), titanium (Ti), or gold (Au) or doped polysilicon.
- Each of the first electrode 412 and the second electrode 413 may have a single-layer structure or a multilayer structure (e.g., Au/Pd or Au/Ti).
- each of the first electrode 412 and the second electrode 413 may include a gold layer 421 and a palladium layer 422 . Patterning of the first electrode 412 and the second electrode 413 may be carried out by, for example, a photolithography process or a lift-off process.
- the at least one nanostructure 414 is self-assembled with the polar molecular layer pattern 432 .
- the at least one nanostructure 414 may be self-assembled with the polar molecular layer pattern 432 by immersing the first substrate 431 into a solution 441 including nanostructures.
- the at least one nanostructure 414 may be self-assembled with the polar molecular layer pattern 432 by immersing the first substrate 431 into the solution 441 including the nanostructures and applying a bias voltage between the first substrate 431 and the solution 441 . Such an immersion is illustrated in FIG. 9 .
- the bias voltage is applied between the first substrate 431 and the solution 441 , the at least one nanostructure 414 may be self-assembled with the polar molecular layer pattern 432 at an improved speed.
- the at least one nanostructure 414 charged with positive ions may be self-assembled with the polar molecular layer pattern 432 at a higher speed.
- a positive (+) bias is applied to the first substrate 431 where the polar molecular layer pattern 432 charged with positive ions is formed, the at least one nanostructure 414 charged with negative ions may be self-assembled with the polar molecular layer pattern 432 at a higher speed.
- the solution 441 including nanostructures for example, carbon nanotubes
- a solution including nanowires may be formed by putting the nanowires into deionized water and applying an ultrasonic wave thereto.
- the surfaces of the nanostructures may be oxidized in the air and the nanostructures having an oxide on their surfaces may be charged with positive or negative ions. Accordingly, when the first substrate 431 is immersed into the solution including the charged nanostructures as described above, the nanostructures may be adsorbed onto the polar molecular layer pattern 432 caused by electrostatic interaction between the polar molecular layer pattern 432 and the nanostructures.
- the electrostatic interaction between the nanostructures and the polar molecular layer pattern 432 may be a charge-charge interaction or a van der Waals force such as a dipole-driven force.
- zinc oxide exhibits a positive charge due to the presence of an oxygen vacancy, so that the nanostructures formed of the zinc oxide are strongly adsorbed onto the surface of the polar molecular layer pattern 432 charged with negative ions.
- vanadium oxide exhibits a negative charge so that it is adsorbed onto the surface of the polar molecular layer pattern 432 charged with positive ions.
- the carbon nanotube is adsorbed onto not only the surface of the polar molecular layer pattern 432 charged with positive ions but also the surface of the polar molecular layer pattern 432 charged with negative ions.
- the at least one nanostructure 414 When the at least one nanostructure 414 is self-assembled with the polar molecular layer pattern 432 , the at least one nanostructure 414 may be aligned in the longitudinal direction L of the polar molecular layer pattern 432 .
- the number of nanostructure(s) having an angle of 45° or less with respect to the longitudinal direction L is at least two times the number of the nanostructure(s) having an angle exceeding 45° with respect to the longitudinal direction L, it can be determined that the at least one nanostructure 414 is aligned in the longitudinal direction L.
- the degree of the alignment of the at least one nanostructure 414 in the longitudinal direction L may be increased with a smaller width W of the polar molecular layer pattern 432 .
- the width W of the polar molecular layer pattern 432 may be less than 1 ⁇ 2 of the average length of the at least one nanostructure 414 .
- the at least one nanostructure 414 is attached to the polar molecular layer pattern 432 after the first electrode 412 and the second electrode 413 are formed.
- the at least one nanostructure 414 may be attached to the polar molecular layer pattern 432 before the first electrode 412 and the second electrode 413 are formed.
- a fluid material 434 is provided on the first substrate 431 and then cured.
- the second substrate 411 is formed of a polymer by curing the fluid material 434 .
- the fluid material 434 may be, for example, a pre-polymer such as PDMS.
- PDMS may be, for example, cured by heating or ultraviolet (UV) irradiation.
- the second substrate 411 obtained by curing the fluid material 434 is separated from the first substrate 431 so that the first electrode 412 , the second electrode 413 and the at least one nanostructure 414 are transferred from the first substrate 431 to the second substrate 411 .
- FIGS. 12 to 17 are plan views ((a) of FIGS. 12 to 17 ) and cross-sectional views ((b) of FIGS. 12 to 17 ) illustrating a method for fabricating a circuit board according to another embodiment.
- the cross-sectional view of each drawing is taken from a line A-A′ in the plan view.
- a first substrate 1231 is prepared.
- a nonpolar molecular layer pattern 1233 is formed on the first substrate 1231 .
- Various materials as described in the previously disclosed embodiment may be used as suitable materials for forming the nonpolar molecular layer pattern 1233 .
- the nonpolar molecular layer pattern 1233 is formed to expose a certain region of a surface of the first substrate 1231 as shown in FIG. 13 .
- the at least one nanostructure 1214 is self-assembled with the exposed region of the first substrate 1231 .
- the at least one nanostructure 1214 may be self-assembled with the exposed region by immersing the first substrate 1231 into a solution including the nanostructures.
- the at least one nanostructure 1214 may be self-assembled with the exposed region by immersing the first substrate 1231 into the solution 1241 including the nanostructures and applying a bias voltage between the first substrate 1231 and the solution 1241 .
- Such an immersion is substantially identical to those illustrated in FIGS. 8 and 9 , so that a detailed description thereof is omitted for simplicity of description.
- the at least one nanostructure 1214 When the at least one nanostructure 1214 is self-assembled with the exposed region, the at least one nanostructure 1214 may be aligned in the longitudinal direction L of the exposed region.
- the degree of the alignment of the at least one nanostructure 1214 may be increased with a smaller width W of the exposed region.
- the width W of the exposed region may be less than 1 ⁇ 2 of the average length of the at least one nanostructure 1214 .
- the at least one nanostructure 1214 is attached to the exposed region of the first substrate 1231 after the first electrode 1212 and the second electrode 1213 are formed.
- the at least one nanostructure 1214 may be attached to the exposed region of the first substrate 1231 before the first electrode 1212 and the second electrode 1213 are formed.
- the second substrate 1211 obtained by curing the fluid material 1234 is separated from the first substrate 1231 , so that the first electrode 1212 , the second electrode 1213 and the at least one nanostructure 1214 are transferred from the first substrate 1231 to the second substrate 1211 .
- FIGS. 18 to 25 are plan views ((a) of FIGS. 18 to 25 ) and cross-sectional views ((b) of FIGS. 18 to 25 ) illustrating a method for fabricating a circuit board according to another embodiment.
- the cross-sectional view of each drawing is taken from a line A-A′ in the plan view.
- a first substrate 1831 is prepared.
- a release layer 1835 is formed on the first substrate 1831 .
- the release layer 1835 acts to allow at least one nanostructure 1814 to be formed on the first substrate 1831 in a subsequent process to be more easily transferred to a second substrate 1811 .
- a suitable material for forming the release layer 1835 may be a nonpolar material including a methyl group at its terminus. In some embodiments, the release layer 1835 may be omitted.
- a first electrode 1812 and a second electrode 1813 are formed on the release layer 1835 .
- Various materials as described in the previously described embodiment may be used as suitable materials for forming the first electrode 1812 and the second electrode 1813 .
- Each of the first electrode 1812 and the second electrode 1813 may have a multilayer structure including a gold layer 1821 and a palladium layer 1822 as shown in FIG. 20 .
- a sacrificial layer pattern 1836 is formed on the first substrate 1831 .
- the sacrificial layer pattern 1836 is formed to expose a certain region of the release layer 1835 , the first electrode 1812 and the second electrode 1813 .
- the suitable material for forming the sacrificial layer pattern 1836 may be, for example, a photoresist.
- the first substrate 1831 is immersed into a solution including the nanostructures to attach the at least one nanostructure 1814 onto the first substrate 1831 .
- the nanostructures attached onto the sacrificial layer pattern 1836 are removed.
- the nanostructures may not be attached to the release layer 1835 , so that the nanostructures on the release layer 1835 may be also removed while the sacrificial layer pattern 1836 is removed.
- the nanostructures may be electrostatically connected to the first electrode 1812 and the second electrode 1813 , so that only the at least one nanostructure 1814 attached to the first electrode 1812 or the second electrode 1813 is not removed.
- a solvent such as, for example, acetone may be used to remove the sacrificial layer pattern 1836 .
- a fluid material 1834 is provided on the first substrate 1831 and then cured.
- the second substrate 1811 is formed of a polymer by the curing the fluid material 1834 .
- the second substrate 1811 obtained by curing the fluid material 1834 is separated from the first substrate 1831 , so that the first electrode 1812 , the second electrode 1813 and the at least one nanostructure 1814 are transferred from the first substrate 1831 to the second substrate 1811 .
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Carbon And Carbon Compounds (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Circuit boards having a polymer substrate, a first electrode and a second electrode disposed on a surface of the polymer substrate, and at least one nanostructure electrically connected to the first and second electrodes are generally disclosed.
Description
- This application is a divisional of U.S. application Ser. No. 12/234,529, filed Sep. 19, 2008, which claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2008-0076382, filed on Aug. 5, 2008, the contents of which are herein incorporated by reference in their entirety.
- The described technology relates generally to a circuit board including aligned nanostructures.
- Recently, there is an increasing amount of interest in new devices based on nanostructures such as carbon nanotubes and nanowires. These devices which employ nano technology are being used in a variety of fields such as electronics, mechanics, optics, and biological engineering.
- In particular, research into utilizing the superior electronic, mechanical and structural properties of carbon nanotubes in flexible electronics is underway. As examples of technology using carbon nanotubes in flexible electronics, Y. J. Jung, et al., 2006 Nano Lett. 6 413, and K. Bradley, et al., 2003 Nano Lett. 3 1353 disclose methods of making a composite of carbon nanotubes and polymer. However, carbon nanotubes are typically grown in a costly and time-consuming chemical vapor deposition (CVD) process, which prevents the cost-efficient mass production of flexible electronics.
- Some embodiments disclosed herein include a circuit board having a polymer substrate, a first electrode and a second electrode disposed on a surface of the polymer substrate, and at least one nanostructure electrically connected to the first and second electrodes.
- The Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. The Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
-
FIG. 1 is a perspective view of a circuit board according to one embodiment. -
FIG. 2 is a plan view ((a) ofFIG. 2 ) and a cross-sectional view ((b) ofFIG. 2 ) of the circuit board shown inFIG. 1 . -
FIG. 3 is a flowchart illustrating a method for fabricating a circuit board according to one embodiment. -
FIGS. 4 to 11 are plan views ((a) ofFIGS. 4 to 11 ) and cross-sectional views ((b) ofFIGS. 4 to 11 ) illustrating a method for fabricating a circuit board according to one embodiment. -
FIGS. 12 to 17 are plan views ((a) ofFIGS. 12 to 17 ) and cross-sectional views ((b) ofFIGS. 12 to 17 ) illustrating a method for fabricating a circuit board according to another embodiment. -
FIGS. 18 to 25 are plan views ((a) ofFIGS. 18 to 25 ) and cross-sectional views ((b) ofFIGS. 18 to 25 ) illustrating a method for fabricating a circuit board according to another embodiment. - In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. The illustrative embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented here. It will be readily understood that the components of the present disclosure, as generally described herein, and illustrated in the Figures, can be arranged, substituted, combined, and designed in a wide variety of different configurations, all of which are explicitly contemplated and make part of this disclosure.
- It will also be understood that when an element or layer is referred to as being “on” or “connected to” another element or layer, the element or layer may be directly on or connected to the other element or layer or intervening elements or layers may be present.
-
FIG. 1 is a perspective view of a circuit board according to one embodiment.FIG. 2 is a plan view ((a) ofFIG. 2 ) and a cross-sectional view ((b) ofFIG. 2 ) of the circuit board shown inFIG. 1 . The cross-sectional view is taken from a line A-A′ in the plan view. As illustrated inFIGS. 1 and 2 , acircuit board 100 may include apolymer substrate 111, afirst electrode 112, asecond electrode 113 and at least onenanostructure 114. - The
polymer substrate 111 may be, for example, a flexible substrate. The flexible substrate may be a silicon polymer substrate such as a polydimethylsiloxane (PDMS) substrate. PDMS is flexible, inert, nontoxic and incombustible, and thus may be a suitable material for bio-applications or other similar applications. - The
first electrode 112 and thesecond electrode 113 are disposed on a surface of thepolymer substrate 111. Thefirst electrode 112 and thesecond electrode 113 may be disposed on the surface of thepolymer substrate 111 in an arrangement in which portions of the respective first andsecond electrodes polymer substrate 111, as shown inFIG. 1 . In addition, although not shown, thefirst electrode 112 and thesecond electrode 113 may be disposed on the surface of thepolymer substrate 111 in an arrangement in which portions of respective first andsecond electrodes polymer substrate 111. The first andsecond electrodes first electrode 112 and thesecond electrode 113 may include a multilayer structure having agold layer 121 and apalladium layer 122 as shown inFIG. 2 . As illustrated inFIGS. 1 and 2 , thefirst electrode 112 and thesecond electrode 113 are disposed above some of the at least onenanostructure 114; alternatively, thefirst electrode 112 and thesecond electrode 113 may be disposed below some of the at least onenanostructure 114. - The at least one
nanostructure 114 is electrically connected to thefirst electrode 112 and thesecond electrode 113.FIGS. 1 and 2 illustrate the at least onenanostructure 114 connected to the first and second electrodes. The connection between the at least onenanostructure 114 and the first andsecond electrodes nanostructure 114 is directly connected to the first andsecond electrodes nanostructure 114 may be electrically connected to thefirst electrode 112, a portion of another nanostructure of the at least onenanostructure 114 may be electrically connected to thesecond electrode 113, and the one nanostructure and the other nanostructure may be electrically connected to each other. In addition, a portion of one nanostructure of the at least onenanostructure 114 may be electrically connected to thefirst electrode 112, a portion of another nanostructure of the at least onenanostructure 114 may be electrically connected to thesecond electrode 113, and the one nanostructure and the other nanostructure may be electrically connected to each other via at least yet another nanostructure of the at least onenanostructure 114. - In one embodiment, the at least one
nanostructure 114 may include, for example, a nanotube, a nanowire, or a nanorod, each having a linear structure. The nanotube may be a carbon nanotube. The nanowire and nanorod may be formed of various materials including a conductive polymer, vanadium oxide, indium oxide, zinc oxide, tin oxide, cadmium oxide, silicon, germanium, gallium nitride, or combinations thereof. - In one embodiment, the at least one
nanostructure 114 may be aligned in a longitudinal direction L of apattern 123 formed by the at least onenanostructure 114. The alignment of the at least onenanostructure 114 in the longitudinal direction L does not mean that all of the at least onenanostructure 114 are aligned in the longitudinal direction L. The alignment of the at least onenanostructure 114 in the longitudinal direction L excludes a case in which at least onenanostructure 114 is arbitrarily disposed. The alignment of the at least onenanostructure 114 in the longitudinal direction L means that the at least onenanostructure 114 is intentionally aligned in the longitudinal direction L. For example, when the number of nanostructure(s) having an angle of 45° or less with respect to the longitudinal direction L is at least two times the number of the nanostructure(s) having an angle exceeding 45° with respect to the longitudinal direction L, it can be determined that the at least onenanostructure 114 is aligned in the longitudinal direction L. When the at least onenanostructure 114 is aligned in the longitudinal direction L, a resistance between thefirst electrode 112 and thesecond electrode 113 may be reduced compared to the case in which the at least onenanostructure 114 is arbitrarily disposed. - At least a portion of the at least one
nanostructure 114 may be disposed within thepolymer substrate 111 as shown inFIG. 2 . In this case, thepolymer substrate 111 may act to protect the at least onenanostructure 114. For example, when a portion or all of the at least onenanostructure 114 is disposed within thepolymer substrate 111, the possibility of the at least onenanostructure 114 being separated from thepolymer substrate 111 may be reduced compared to a case in which the at least onenanostructure 114 is disposed outside thepolymer substrate 111. For example, when a portion or all of the at least onenanostructure 114 is disposed within thepolymer substrate 111, noise caused by a liquid or the like with which the at least onenanostructure 114 may come in contact may be reduced compared to the case in which the at least onenanostructure 114 is disposed outside thepolymer substrate 111. Unlike as illustrated inFIG. 2 , the at least onenanostructure 114 may be formed above the surface of thepolymer substrate 111. - In one embodiment, the at least one
nanostructure 114 may be used as an electric line for electrically connecting thefirst electrode 112 to thesecond electrode 113. For example, electrical characteristics of the at least onenanostructure 114 may be changed according to an amount or degree of light, molecules, deoxyribonucleic acid (DNA) or temperature. In this case, the at least onenanostructure 114 may be used as a component of a sensor or a transistor. - The
circuit board 100 does not necessarily include a closed circuit formed in thepolymer substrate 111. That is, thecircuit board 100 may have thefirst electrode 112, thesecond electrode 113 and the at least onenanostructure 114 electrically connected between the first and second electrodes which are formed on thepolymer substrate 111 without the closed circuit. - As described above, nanostructures are not randomly arranged but are uniformly arranged between electrodes, and thus the circuit board may have a small resistance between the electrodes. In addition, a nanostructure circuit is depressed in a polymer substrate, and thus the circuit board may be flexible and stable.
-
FIG. 3 is a flowchart illustrating a method for fabricating a circuit board according to one embodiment. Beginning inblock 310, a first substrate is provided. The first substrate may be, for example, a substrate formed of a metal (e.g., gold, aluminum), a semiconductor (e.g., silicon, silicon-on-insulator), glass or an oxide (e.g., SiO2). - In
block 320, a circuit including a first electrode, a second electrode, and at least one nanostructure is formed on the first substrate. The at least one nanostructure, for example, may have a nanotube, a nanowire, or a nanorod, each having a linear structure. The nanotube may be a carbon nanotube. The nanowire and nanorod may be formed of various materials including a conductive polymer, vanadium oxide, indium oxide, zinc oxide, tin oxide, cadmium oxide, silicon, germanium, gallium nitride, or combinations thereof. When the circuit is formed on the first substrate, the closed circuit may not be necessarily formed, and the first electrode, the second electrode and the at least one nanostructure may be formed on the first substrate without the closed circuit. - In block 330, the circuit is then transferred from the first substrate to a surface of a second substrate formed of a polymer. The second substrate may be, for example, a flexible substrate. The flexible substrate may be a silicon polymer substrate such as, by way of example, a PDMS substrate. Block 330 may include
blocks 331 to 333 as shown inFIG. 3 . Inblock 331, a fluid material is provided on the first substrate with the circuit. In block 332, the fluid material provided on the first substrate is cured by a conventional method. Inblock 333, the second substrate obtained by curing the fluid material is separated from the first substrate so that the circuit is transferred from the first substrate to the second substrate. - When the circuit board is fabricated by the method as described above, the circuit may be formed in the substrate made of a semiconductor, a metal, glass, or an oxide using a conventional microfabrication process and then transferred to the polymer substrate, so that the circuit may be easily formed on the polymer substrate. In addition, when the circuit board is fabricated in the manner as described above, at least a portion of the at least one nanostructure may be disposed in the polymer substrate.
-
FIGS. 4 to 11 are plan views ((a) ofFIGS. 4 to 11 ) and cross-sectional views ((b) ofFIGS. 4 to 11 ) illustrating a method for fabricating a circuit board according to one embodiment. The cross-sectional view of each drawing is taken from a line A-A′ in the plan view. - Referring to
FIG. 4 , afirst substrate 431 is prepared. Various kinds of substrates as described above with reference toFIG. 3 may be used as thefirst substrate 431. - Referring to
FIG. 5 , a polarmolecular layer pattern 432 and a nonpolarmolecular layer pattern 433 are formed on thefirst substrate 431. The formation of the polarmolecular layer pattern 432 and the nonpolarmolecular layer pattern 433 allows a surface of thefirst substrate 431 to be divided into a region where the polarmolecular layer pattern 432 is formed and a region where the nonpolarmolecular layer pattern 433 is formed. - The polar
molecular layer pattern 432 may be charged with positive or negative ions in accordance with the used material. When an oxide nanostructure usually having surface charges is provided onto the polarmolecular layer pattern 432, the oxide nanostructure adheres to the surface of the polarmolecular layer pattern 432 by electrostatic interaction between the oxide nanostructure and the polarmolecular layer pattern 432. In one embodiment, when thefirst substrate 431 is formed of gold, the polarmolecular layer pattern 432 may be, for example, a self-assembled monolayer (SAM) having a compound with a carboxyl group terminus (—COOH/—COO−). In this case, the polarmolecular layer pattern 432 is charged with negative ions. The compound having the carboxyl group terminus may be, for example, 16-mercaptohexadecanoic acid (MHA). In another embodiment, when thefirst substrate 431 is formed of gold, the polarmolecular layer pattern 432 may be, for example, an SAM having 2-mercaptoimidazole (2-MI) or a compound having an amino group terminus (—NH2/—NH3 +). In this case, the polarmolecular layer pattern 432 is charged with positive ions. The compound having the amino group terminus may be, for example, cysteamine. In still another embodiment, when thefirst substrate 431 is formed of silica (SiO2), the polarmolecular layer pattern 432 may be, for example, an SAM having aminopropyltriethoxysilane (APTES). - The nonpolar
molecular layer pattern 433 is not charged with positive or negative ions but neutral. Accordingly, when the oxide nanostructure is used as the nanostructure, the nanostructure may not be attached to the nonpolarmolecular layer pattern 433. Even when the nanostructure is attached to the nonpolar molecular layer, the nanostructure may be relatively easily detached from the nonpolar molecular layer compared to the nanostructures attached to the polarmolecular layer pattern 432. The nonpolarmolecular layer pattern 432 may be, for example, an SAM having a compound with a methyl terminus. In one embodiment, when thefirst substrate 431 is formed of gold, the suitable material for forming the nonpolarmolecular layer pattern 433 may be a thiol compound such as 1-octadecanethiol (ODT). In another embodiment, when thefirst substrate 431 is formed of silica, silicon, or aluminum, the suitable material for forming the nonpolarmolecular layer pattern 433 may be, for example, a silane compound such as octadecyltrichlorosilane (OTS), octadecyltrimethoxysilane (OTMS) or octadecyltriethoxysilane (OTE). - The polar
molecular layer pattern 432 and the nonpolarmolecular layer pattern 433 may be formed by, for example, a dip-pen nanolithography (DPN) method, a microcontact printing method (μCP) or a photolithography method. - Referring to
FIG. 6 , thefirst electrode 412 and thesecond electrode 413 are formed on the polarmolecular layer pattern 432. Thefirst electrode 412 and thesecond electrode 413 are conductors, and may be a metal such as aluminum (Al), palladium (Pd), titanium (Ti), or gold (Au) or doped polysilicon. Each of thefirst electrode 412 and thesecond electrode 413 may have a single-layer structure or a multilayer structure (e.g., Au/Pd or Au/Ti). As illustrated inFIG. 6 , each of thefirst electrode 412 and thesecond electrode 413 may include agold layer 421 and apalladium layer 422. Patterning of thefirst electrode 412 and thesecond electrode 413 may be carried out by, for example, a photolithography process or a lift-off process. - Referring to
FIG. 7 , the at least onenanostructure 414 is self-assembled with the polarmolecular layer pattern 432. In one embodiment, as illustrated inFIG. 8 , the at least onenanostructure 414 may be self-assembled with the polarmolecular layer pattern 432 by immersing thefirst substrate 431 into asolution 441 including nanostructures. - In another embodiment, as illustrated in
FIG. 9 , the at least onenanostructure 414 may be self-assembled with the polarmolecular layer pattern 432 by immersing thefirst substrate 431 into thesolution 441 including the nanostructures and applying a bias voltage between thefirst substrate 431 and thesolution 441. Such an immersion is illustrated inFIG. 9 . When the bias voltage is applied between thefirst substrate 431 and thesolution 441, the at least onenanostructure 414 may be self-assembled with the polarmolecular layer pattern 432 at an improved speed. For example, when a negative (−) bias is applied to thefirst substrate 431 where the polarmolecular layer pattern 432 charged with negative ions is formed, the at least onenanostructure 414 charged with positive ions may be self-assembled with the polarmolecular layer pattern 432 at a higher speed. In addition, when a positive (+) bias is applied to thefirst substrate 431 where the polarmolecular layer pattern 432 charged with positive ions is formed, the at least onenanostructure 414 charged with negative ions may be self-assembled with the polarmolecular layer pattern 432 at a higher speed. - The
solution 441 including nanostructures, for example, carbon nanotubes, may be formed by putting the carbon nanotubes into 1,2-dichlorobenzene and applying an ultrasonic wave thereto. In addition, a solution including nanowires may be formed by putting the nanowires into deionized water and applying an ultrasonic wave thereto. - The surfaces of the nanostructures may be oxidized in the air and the nanostructures having an oxide on their surfaces may be charged with positive or negative ions. Accordingly, when the
first substrate 431 is immersed into the solution including the charged nanostructures as described above, the nanostructures may be adsorbed onto the polarmolecular layer pattern 432 caused by electrostatic interaction between the polarmolecular layer pattern 432 and the nanostructures. - The electrostatic interaction between the nanostructures and the polar
molecular layer pattern 432 may be a charge-charge interaction or a van der Waals force such as a dipole-driven force. - In one embodiment, zinc oxide (ZnO) exhibits a positive charge due to the presence of an oxygen vacancy, so that the nanostructures formed of the zinc oxide are strongly adsorbed onto the surface of the polar
molecular layer pattern 432 charged with negative ions. In another embodiment, vanadium oxide (V2O5) exhibits a negative charge so that it is adsorbed onto the surface of the polarmolecular layer pattern 432 charged with positive ions. In still another embodiment, the carbon nanotube is adsorbed onto not only the surface of the polarmolecular layer pattern 432 charged with positive ions but also the surface of the polarmolecular layer pattern 432 charged with negative ions. - When the at least one
nanostructure 414 is self-assembled with the polarmolecular layer pattern 432, the at least onenanostructure 414 may be aligned in the longitudinal direction L of the polarmolecular layer pattern 432. For example, when the number of nanostructure(s) having an angle of 45° or less with respect to the longitudinal direction L is at least two times the number of the nanostructure(s) having an angle exceeding 45° with respect to the longitudinal direction L, it can be determined that the at least onenanostructure 414 is aligned in the longitudinal direction L. The degree of the alignment of the at least onenanostructure 414 in the longitudinal direction L may be increased with a smaller width W of the polarmolecular layer pattern 432. For example, the width W of the polarmolecular layer pattern 432 may be less than ½ of the average length of the at least onenanostructure 414. - Referring to
FIGS. 6 and 7 , the at least onenanostructure 414 is attached to the polarmolecular layer pattern 432 after thefirst electrode 412 and thesecond electrode 413 are formed. Alternatively, the at least onenanostructure 414 may be attached to the polarmolecular layer pattern 432 before thefirst electrode 412 and thesecond electrode 413 are formed. - Referring to
FIG. 10 , afluid material 434 is provided on thefirst substrate 431 and then cured. Thesecond substrate 411 is formed of a polymer by curing thefluid material 434. Thefluid material 434 may be, for example, a pre-polymer such as PDMS. PDMS may be, for example, cured by heating or ultraviolet (UV) irradiation. - Referring to
FIG. 11 , thesecond substrate 411 obtained by curing thefluid material 434 is separated from thefirst substrate 431 so that thefirst electrode 412, thesecond electrode 413 and the at least onenanostructure 414 are transferred from thefirst substrate 431 to thesecond substrate 411. -
FIGS. 12 to 17 are plan views ((a) ofFIGS. 12 to 17 ) and cross-sectional views ((b) ofFIGS. 12 to 17 ) illustrating a method for fabricating a circuit board according to another embodiment. The cross-sectional view of each drawing is taken from a line A-A′ in the plan view. - Referring to
FIG. 12 , afirst substrate 1231 is prepared. - Referring to
FIG. 13 , a nonpolarmolecular layer pattern 1233 is formed on thefirst substrate 1231. Various materials as described in the previously disclosed embodiment may be used as suitable materials for forming the nonpolarmolecular layer pattern 1233. The nonpolarmolecular layer pattern 1233 is formed to expose a certain region of a surface of thefirst substrate 1231 as shown inFIG. 13 . - Referring to
FIG. 14 , afirst electrode 1212 and asecond electrode 1213 are formed on thefirst substrate 1231. Various materials as described in the previously-described embodiment may be used as suitable materials for forming thefirst electrode 1212 and thesecond electrode 1213. Each of thefirst electrode 1212 and thesecond electrode 1213 may include a multilayer structure having a gold (Au)layer 1221 and a palladium (Pd)layer 1222 as shown inFIG. 14 . - Referring to
FIG. 15 , the at least onenanostructure 1214 is self-assembled with the exposed region of thefirst substrate 1231. In one embodiment, the at least onenanostructure 1214 may be self-assembled with the exposed region by immersing thefirst substrate 1231 into a solution including the nanostructures. In another embodiment, the at least onenanostructure 1214 may be self-assembled with the exposed region by immersing thefirst substrate 1231 into the solution 1241 including the nanostructures and applying a bias voltage between thefirst substrate 1231 and the solution 1241. Such an immersion is substantially identical to those illustrated inFIGS. 8 and 9 , so that a detailed description thereof is omitted for simplicity of description. When the at least onenanostructure 1214 is self-assembled with the exposed region, the at least onenanostructure 1214 may be aligned in the longitudinal direction L of the exposed region. The degree of the alignment of the at least onenanostructure 1214 may be increased with a smaller width W of the exposed region. For example, the width W of the exposed region may be less than ½ of the average length of the at least onenanostructure 1214. - Referring to
FIGS. 14 and 15 , the at least onenanostructure 1214 is attached to the exposed region of thefirst substrate 1231 after thefirst electrode 1212 and thesecond electrode 1213 are formed. Alternatively, the at least onenanostructure 1214 may be attached to the exposed region of thefirst substrate 1231 before thefirst electrode 1212 and thesecond electrode 1213 are formed. - Referring to
FIG. 16 , afluid material 1234 is provided on thefirst substrate 1231 and then cured. Thesecond substrate 1211 is formed of a polymer by curing thefluid material 1234. - Referring to
FIG. 17 , thesecond substrate 1211 obtained by curing thefluid material 1234 is separated from thefirst substrate 1231, so that thefirst electrode 1212, thesecond electrode 1213 and the at least onenanostructure 1214 are transferred from thefirst substrate 1231 to thesecond substrate 1211. - As described above, the at least one
nanostructure 1214 may be attached onto the bare surface of thefirst substrate 1231 exposed between the nonpolarmolecular layers 1233. The bare surface of thefirst substrate 1231 is naturally polarized, so that it can act similarly to the polarmolecular layer pattern 432 described with reference toFIGS. 4 to 11 . That is, the at least onenanostructure 1214 may not be attached to the nonpolarmolecular layer pattern 1233 but attached to the exposed region of thefirst substrate 1231, so that it can be aligned in the longitudinal direction of the exposed region. -
FIGS. 18 to 25 are plan views ((a) ofFIGS. 18 to 25 ) and cross-sectional views ((b) ofFIGS. 18 to 25 ) illustrating a method for fabricating a circuit board according to another embodiment. The cross-sectional view of each drawing is taken from a line A-A′ in the plan view. - Referring to
FIG. 18 , afirst substrate 1831 is prepared. - Referring to
FIG. 19 , arelease layer 1835 is formed on thefirst substrate 1831. Therelease layer 1835 acts to allow at least onenanostructure 1814 to be formed on thefirst substrate 1831 in a subsequent process to be more easily transferred to asecond substrate 1811. A suitable material for forming therelease layer 1835 may be a nonpolar material including a methyl group at its terminus. In some embodiments, therelease layer 1835 may be omitted. - Referring to
FIG. 20 , afirst electrode 1812 and asecond electrode 1813 are formed on therelease layer 1835. Various materials as described in the previously described embodiment may be used as suitable materials for forming thefirst electrode 1812 and thesecond electrode 1813. Each of thefirst electrode 1812 and thesecond electrode 1813 may have a multilayer structure including agold layer 1821 and apalladium layer 1822 as shown inFIG. 20 . - Referring to
FIG. 21 , asacrificial layer pattern 1836 is formed on thefirst substrate 1831. Thesacrificial layer pattern 1836 is formed to expose a certain region of therelease layer 1835, thefirst electrode 1812 and thesecond electrode 1813. The suitable material for forming thesacrificial layer pattern 1836 may be, for example, a photoresist. - Referring to
FIG. 22 , thefirst substrate 1831 is immersed into a solution including the nanostructures to attach the at least onenanostructure 1814 onto thefirst substrate 1831. - Referring to
FIG. 23 , by removing thesacrificial layer pattern 1836, the nanostructures attached onto thesacrificial layer pattern 1836 are removed. In addition, the nanostructures may not be attached to therelease layer 1835, so that the nanostructures on therelease layer 1835 may be also removed while thesacrificial layer pattern 1836 is removed. Accordingly, the nanostructures may be electrostatically connected to thefirst electrode 1812 and thesecond electrode 1813, so that only the at least onenanostructure 1814 attached to thefirst electrode 1812 or thesecond electrode 1813 is not removed. When a photoresist pattern is used as thesacrificial layer pattern 1836, a solvent such as, for example, acetone may be used to remove thesacrificial layer pattern 1836. - Referring to
FIG. 24 , afluid material 1834 is provided on thefirst substrate 1831 and then cured. Thesecond substrate 1811 is formed of a polymer by the curing thefluid material 1834. - Referring to
FIG. 25 , thesecond substrate 1811 obtained by curing thefluid material 1834 is separated from thefirst substrate 1831, so that thefirst electrode 1812, thesecond electrode 1813 and the at least onenanostructure 1814 are transferred from thefirst substrate 1831 to thesecond substrate 1811. - From the foregoing, it will be appreciated that various embodiments of the present disclosure have been described herein for purposes of illustration, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the following claims.
Claims (20)
1. A circuit board comprising:
a polymer substrate;
a first electrode and a second electrode disposed on a surface of the polymer substrate; and
at least one nanostructure electrically connected to the first electrode and the second electrode,
wherein the at least one nanostructure is aligned in a longitudinal direction of a pattern formed by the at least one nanostructure.
2. The circuit board of claim 1 , wherein the polymer substrate is a flexible substrate.
3. The circuit board of claim 1 , wherein the polymer substrate is a silicon polymer substrate.
4. The circuit board of claim 1 , wherein the polymer substrate is a polydimethylsiloxane (PDMS) substrate.
5. The circuit board of claim 1 , wherein the at least one nanostructure is used as an electric line.
6. The circuit board of claim 1 , wherein the circuit board is used as a sensor.
7. The circuit board of claim 1 , wherein at least a portion of the at least one nanostructure is disposed within the polymer substrate.
8. The circuit board of claim 1 , wherein the at least one nanostructure comprises any one selected from the group consisting of a nanotube, a nanowire and a nanorod.
9. The circuit board of claim 1 , wherein a first number of the nanostructures having an angle of 45° or less with respect to the longitudinal direction is at least two times a second number of the nanostructures having an angle exceeding 45° with respect to the longitudinal direction.
10. A circuit board comprising:
a polymer substrate;
a first electrode and a second electrode disposed at least partially within the polymer substrate; and
at least one nanostructure electrically connected to the first electrode and the second electrode, wherein the at least one nanostructure is configured to adhere to charged surfaces, and wherein the at least one nanostructure is aligned in a longitudinal direction extending between the first electrode and the second electrode.
11. The circuit board of claim 10 , wherein the substrate is a flexible substrate.
12. The circuit board of claim 10 , wherein the nanostructure is configured to have electrical conductivity which changes in response to an ambient condition.
13. The circuit board of claim 10 , wherein the nanostructure comprises a metal oxide.
14. The circuit board of claim 10 , wherein the nanostructure comprises a carbon nanotube.
15. The circuit board of claim 10 , wherein a first number of the nanostructures having an angle of 45° or less with respect to the longitudinal direction is at least two times a second number of the nanostructures having an angle exceeding 45° with respect to the longitudinal direction.
16. The circuit board of claim 10 , wherein the at least one nanostructure is at least partially disposed within the polymer substrate.
17. The circuit board of claim 16 , wherein the charged surfaces comprises a polar molecular pattern.
18. The circuit board of claim 10 , wherein at least one of the first electrode and the second electrode is a multi-layer electrode.
19. A circuit board comprising:
a first electrode and a second electrode;
at least one nanostructure electrically connected to the first electrode and the second electrode, wherein the at least one nanostructure is aligned in a longitudinal direction of a pattern formed by the at least one nanostructure; and
a cured polymer substrate, wherein the first electrode, the second electrode, and the at least one nanostructure are disposed at least partially within the polymer substrate.
20. The circuit board of claim 19 , wherein a first number of the nanostructures having an angle of 45° or less with respect to the longitudinal direction is at least two times a second number of the nanostructures having an angle exceeding 45° with respect to the longitudinal direction.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/366,184 US20120132459A1 (en) | 2008-08-05 | 2012-02-03 | Circuit board including aligned nanostructures |
US14/622,092 US20150181704A1 (en) | 2008-08-05 | 2015-02-13 | Circuit board including aligned nanostructures |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2008-0076382 | 2008-08-05 | ||
KR1020080076382A KR101071325B1 (en) | 2008-08-05 | 2008-08-05 | Circuit board comprising a aligned nanostructure and method for fabricating the circuit board |
US12/234,529 US8245393B2 (en) | 2008-08-05 | 2008-09-19 | Method for fabricating a circuit board including aligned nanostructures |
US13/366,184 US20120132459A1 (en) | 2008-08-05 | 2012-02-03 | Circuit board including aligned nanostructures |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/234,529 Division US8245393B2 (en) | 2008-08-05 | 2008-09-19 | Method for fabricating a circuit board including aligned nanostructures |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/622,092 Division US20150181704A1 (en) | 2008-08-05 | 2015-02-13 | Circuit board including aligned nanostructures |
Publications (1)
Publication Number | Publication Date |
---|---|
US20120132459A1 true US20120132459A1 (en) | 2012-05-31 |
Family
ID=41651853
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/234,529 Expired - Fee Related US8245393B2 (en) | 2008-08-05 | 2008-09-19 | Method for fabricating a circuit board including aligned nanostructures |
US13/366,184 Abandoned US20120132459A1 (en) | 2008-08-05 | 2012-02-03 | Circuit board including aligned nanostructures |
US14/622,092 Abandoned US20150181704A1 (en) | 2008-08-05 | 2015-02-13 | Circuit board including aligned nanostructures |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/234,529 Expired - Fee Related US8245393B2 (en) | 2008-08-05 | 2008-09-19 | Method for fabricating a circuit board including aligned nanostructures |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/622,092 Abandoned US20150181704A1 (en) | 2008-08-05 | 2015-02-13 | Circuit board including aligned nanostructures |
Country Status (2)
Country | Link |
---|---|
US (3) | US8245393B2 (en) |
KR (1) | KR101071325B1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103424438A (en) * | 2013-09-04 | 2013-12-04 | 浙江工商大学 | Palladium plating multi-wall carbon nanotube smell sensor suitable for prawns |
CN104287698A (en) * | 2014-09-16 | 2015-01-21 | 苏州能斯达电子科技有限公司 | Flexible and attachable sensor used for neck pulse detection and manufacturing method of flexible and attachable sensor used for neck pulse detection |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5136976B2 (en) * | 2007-09-12 | 2013-02-06 | 独立行政法人産業技術総合研究所 | Vanadium oxide thin film pattern and manufacturing method thereof |
US8178787B2 (en) * | 2008-08-26 | 2012-05-15 | Snu R&Db Foundation | Circuit board including aligned nanostructures |
KR101223475B1 (en) * | 2010-07-30 | 2013-01-17 | 포항공과대학교 산학협력단 | Fabrication method for carbon nanotube film and sensor based carbon nanotube film |
US9273004B2 (en) | 2011-09-29 | 2016-03-01 | International Business Machines Corporation | Selective placement of carbon nanotubes via coulombic attraction of oppositely charged carbon nanotubes and self-assembled monolayers |
KR101402989B1 (en) * | 2013-06-12 | 2014-06-11 | 한국과학기술연구원 | a fabricating method of carbon nanotube-based field effect transistor and carbon nanotube-based field effect transistor fabricated thereby |
WO2015156661A1 (en) * | 2014-04-07 | 2015-10-15 | Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek Tno | Method of producing a patterned nanowires network |
KR102042137B1 (en) | 2014-05-30 | 2019-11-28 | 한국전자통신연구원 | An electronic device and the method for fabricating the same |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030068432A1 (en) * | 1998-08-14 | 2003-04-10 | The Board Of Trustees Of The Leland Stanford Junior University | Carbon nanotube devices |
US20040041154A1 (en) * | 2002-09-04 | 2004-03-04 | Fuji Xerox Co., Ltd. | Electric part and method of manufacturing the same |
US6905655B2 (en) * | 2002-03-15 | 2005-06-14 | Nanomix, Inc. | Modification of selectivity for sensing for nanostructure device arrays |
US6918284B2 (en) * | 2003-03-24 | 2005-07-19 | The United States Of America As Represented By The Secretary Of The Navy | Interconnected networks of single-walled carbon nanotubes |
US20100019355A1 (en) * | 2008-07-25 | 2010-01-28 | Theodore I Kamins | Multi-Level Nanowire Structure And Method Of Making The Same |
US7736979B2 (en) * | 2007-06-20 | 2010-06-15 | New Jersey Institute Of Technology | Method of forming nanotube vertical field effect transistor |
US7956525B2 (en) * | 2003-05-16 | 2011-06-07 | Nanomix, Inc. | Flexible nanostructure electronic devices |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6027958A (en) * | 1996-07-11 | 2000-02-22 | Kopin Corporation | Transferred flexible integrated circuit |
US6472705B1 (en) * | 1998-11-18 | 2002-10-29 | International Business Machines Corporation | Molecular memory & logic |
US7067867B2 (en) * | 2002-09-30 | 2006-06-27 | Nanosys, Inc. | Large-area nonenabled macroelectronic substrates and uses therefor |
WO2004049403A2 (en) * | 2002-11-22 | 2004-06-10 | Florida State University | Depositing nanowires on a substrate |
WO2004051219A2 (en) * | 2002-11-27 | 2004-06-17 | Molecular Nanosystems, Inc. | Nanotube chemical sensor based on work function of electrodes |
US7232771B2 (en) * | 2003-11-04 | 2007-06-19 | Regents Of The University Of Minnesota | Method and apparatus for depositing charge and/or nanoparticles |
EP1578173A1 (en) | 2004-03-18 | 2005-09-21 | C.R.F. Società Consortile per Azioni | Light emitting device comprising porous alumina and manufacturing process thereof |
US8333948B2 (en) * | 2004-10-06 | 2012-12-18 | The Regents Of The University Of California | Carbon nanotube for fuel cell, nanocomposite comprising the same, method for making the same, and fuel cell using the same |
DE102005038121B3 (en) * | 2005-08-11 | 2007-04-12 | Siemens Ag | Process for the integration of functional nanostructures in micro- and nanoelectric circuits |
CN101310373B (en) * | 2005-09-29 | 2012-01-25 | 松下电器产业株式会社 | Method of mounting electronic circuit constituting member |
WO2007047523A2 (en) * | 2005-10-14 | 2007-04-26 | Pennsylvania State University | System and method for positioning and synthesizing of nanostructures |
JP2007158117A (en) | 2005-12-06 | 2007-06-21 | Canon Inc | Manufacturing method of nanowire arrangement substrate, and of electrical device using the manufacturing method |
JP2007158119A (en) * | 2005-12-06 | 2007-06-21 | Canon Inc | Electric element having nano wire and its manufacturing method, and electric element assembly |
KR100874026B1 (en) | 2006-04-04 | 2008-12-17 | 재단법인서울대학교산학협력재단 | Biosensor using nanowires and its manufacturing method |
KR20070112733A (en) | 2006-05-22 | 2007-11-27 | 재단법인서울대학교산학협력재단 | Method of nanostructure assembly and alignment through self-assembly method and their application method |
JP2007329351A (en) | 2006-06-08 | 2007-12-20 | Sharp Corp | Thin-line-form structure assembly, electronic device having same assembly, manufacturing methods of these, and orienting method of same thin-line-form structure |
WO2008018726A1 (en) | 2006-08-07 | 2008-02-14 | Seoul National University Industry Foundation | Nanostructure sensors |
DE102007001743A1 (en) * | 2006-09-29 | 2008-04-03 | Osram Opto Semiconductors Gmbh | Semiconductor laser has laser active semiconductor sequence layer with principal surface that is arranged on heat conducting layer |
KR100829573B1 (en) | 2006-11-02 | 2008-05-14 | 삼성전자주식회사 | Electronic device, field effect transistor, and method of fabricating the same |
CN101652382B (en) * | 2006-12-04 | 2016-04-06 | 特拉维夫大学拉莫特有限公司 | The formation of organic nanostructure array |
KR101287735B1 (en) * | 2006-12-08 | 2013-07-18 | 엘지디스플레이 주식회사 | Method of manufacturing thin film transistor and method of manufacturing liquid crystal display device using the same |
US7821061B2 (en) * | 2007-03-29 | 2010-10-26 | Intel Corporation | Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications |
US8980991B2 (en) * | 2007-06-08 | 2015-03-17 | Xerox Corporation | Intermediate transfer members comprised of hydrophobic carbon nanotubes |
US7427238B1 (en) * | 2007-07-26 | 2008-09-23 | Oprandi Arthur V | Golf club swinging guide |
KR101319499B1 (en) * | 2008-02-22 | 2013-10-17 | 엘지디스플레이 주식회사 | Method for forming layer and pattern of nanowire or carbon nanotube using chemical self assembly and fabricating method in liquid crystal display device thereby |
US8178787B2 (en) * | 2008-08-26 | 2012-05-15 | Snu R&Db Foundation | Circuit board including aligned nanostructures |
-
2008
- 2008-08-05 KR KR1020080076382A patent/KR101071325B1/en active IP Right Grant
- 2008-09-19 US US12/234,529 patent/US8245393B2/en not_active Expired - Fee Related
-
2012
- 2012-02-03 US US13/366,184 patent/US20120132459A1/en not_active Abandoned
-
2015
- 2015-02-13 US US14/622,092 patent/US20150181704A1/en not_active Abandoned
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030068432A1 (en) * | 1998-08-14 | 2003-04-10 | The Board Of Trustees Of The Leland Stanford Junior University | Carbon nanotube devices |
US6905655B2 (en) * | 2002-03-15 | 2005-06-14 | Nanomix, Inc. | Modification of selectivity for sensing for nanostructure device arrays |
US20040041154A1 (en) * | 2002-09-04 | 2004-03-04 | Fuji Xerox Co., Ltd. | Electric part and method of manufacturing the same |
US6918284B2 (en) * | 2003-03-24 | 2005-07-19 | The United States Of America As Represented By The Secretary Of The Navy | Interconnected networks of single-walled carbon nanotubes |
US7956525B2 (en) * | 2003-05-16 | 2011-06-07 | Nanomix, Inc. | Flexible nanostructure electronic devices |
US7736979B2 (en) * | 2007-06-20 | 2010-06-15 | New Jersey Institute Of Technology | Method of forming nanotube vertical field effect transistor |
US20100019355A1 (en) * | 2008-07-25 | 2010-01-28 | Theodore I Kamins | Multi-Level Nanowire Structure And Method Of Making The Same |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103424438A (en) * | 2013-09-04 | 2013-12-04 | 浙江工商大学 | Palladium plating multi-wall carbon nanotube smell sensor suitable for prawns |
CN104287698A (en) * | 2014-09-16 | 2015-01-21 | 苏州能斯达电子科技有限公司 | Flexible and attachable sensor used for neck pulse detection and manufacturing method of flexible and attachable sensor used for neck pulse detection |
Also Published As
Publication number | Publication date |
---|---|
KR20100016766A (en) | 2010-02-16 |
US8245393B2 (en) | 2012-08-21 |
KR101071325B1 (en) | 2011-10-07 |
US20150181704A1 (en) | 2015-06-25 |
US20100032197A1 (en) | 2010-02-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20150181704A1 (en) | Circuit board including aligned nanostructures | |
Schmaltz et al. | Self‐assembled monolayers as patterning tool for organic electronic devices | |
US9954175B2 (en) | Carbon nanotube-graphene hybrid transparent conductor and field effect transistor | |
US9607725B2 (en) | Graphene structure, method for producing the same, electronic device element and electronic device | |
KR100777853B1 (en) | Compound used to form a self-assembled monolayer, layer structure, semiconductor component having a layer structure, and method for producing a layer structure | |
US9601697B2 (en) | Systems and process for forming carbon nanotube sensors | |
JP2007129227A (en) | Manufacturing method for electronic device, winding manufacturing process, thin-film transistor, and coating device | |
KR101039630B1 (en) | Method to assemble nano-structure on a substrate and nano-molecule device comprising nano-structure formed thereby | |
US9596762B2 (en) | Method of fabricating a circuit board | |
Sizov et al. | Self-assembled interface monolayers for organic and hybrid electronics | |
US9053941B2 (en) | Photolithographically defined contacts to carbon nanostructures | |
Li et al. | Transfer printing of submicrometer patterns of aligned carbon nanotubes onto functionalized electrodes | |
KR100963204B1 (en) | Fabricating Method Of Flexible Transparent Electrode | |
WO2010137664A1 (en) | Alkylsilane laminate, method for producing the same, and thin-film transistor | |
JP2008258532A (en) | Manufacturing method for thin film transistor and thin film transistor manufactured by its method | |
WO2006025391A1 (en) | Molecular device and method for manufacturing the same | |
KR101029995B1 (en) | High Integrating Method of 1 Dimensional or 2 Dimensional Conductive Nanowires Using Charged Materials, and High Integrated Conductive Nanowires by the Same | |
WO2016055951A1 (en) | Method for manufacturing an electronic device, particularly a device made of carbon nanotubes | |
Peng et al. | Fabrication and Electrical Characterization of Multiwalled Carbon Nanotube‐Based Circuit at Room Temperature | |
Cho | Development of high-rate nano-scale offset printing technology for electric and bio applications | |
WO2012082135A1 (en) | Systems and process for forming carbon nanotube sensors | |
Kienzl | Quartett, Op. 99 | |
Peng et al. | Research Article Fabrication and Electrical Characterization of Multiwalled Carbon Nanotube-Based Circuit at Room Temperature |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |