US20120049198A1 - Array substrate - Google Patents
Array substrate Download PDFInfo
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- US20120049198A1 US20120049198A1 US12/954,901 US95490110A US2012049198A1 US 20120049198 A1 US20120049198 A1 US 20120049198A1 US 95490110 A US95490110 A US 95490110A US 2012049198 A1 US2012049198 A1 US 2012049198A1
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- Prior art keywords
- material layer
- inorganic material
- layer
- electrode
- via hole
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- 239000000758 substrate Substances 0.000 title claims abstract description 73
- 229910010272 inorganic material Inorganic materials 0.000 claims abstract description 67
- 239000011147 inorganic material Substances 0.000 claims abstract description 67
- 239000011368 organic material Substances 0.000 claims abstract description 50
- 239000010409 thin film Substances 0.000 claims abstract description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 148
- 239000012044 organic layer Substances 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 11
- 238000000034 method Methods 0.000 description 9
- 239000004020 conductor Substances 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000004075 alteration Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
Definitions
- the present invention relates to an array substrate, and more particularly, to an array substrate with a structure to keep transparent electrodes from cracking.
- liquid crystal displays are widely used in electronic devices because of their advantages, such as light weight, small volume, low power consumption, and radiation-free characteristics.
- a plurality of scan lines and a plurality of data lines are disposed on an array substrate of a liquid crystal display panel.
- the scan lines and the data lines are arranged perpendicular to each other to divide the substrate into a plurality of pixel units.
- Each of the pixel units has a pixel electrode and a thin film transistor (TFT).
- the thin film transistor is electrically connected to the scan line and the data line, for being a switching device of the pixel electrode.
- the pixel electrode which is used in the substrate of a transmissive liquid crystal display panel and in the transmissive area of a transflective liquid crystal display panel, is made of a transparent conductive material, such as indium tin oxide (ITO).
- ITO indium tin oxide
- the transparent conductive material is formed on the planar layer as the pixel electrode. Because of the large difference in the coefficients of thermal expansion between the normal material of the planar layer and the transparent conductive material, there will be cracks generated at the area with weaker mechanical structure in the transparent conductive material after thermal treatment of the substrate, such as annealing.
- a method of manufacturing an array substrate comprises: providing a substrate, wherein a thin film transistor is disposed on the substrate, and the thin film transistor comprises a gate electrode, a gate insulating layer, a source electrode, and a drain electrode; forming an organic material layer covering the substrate and the thin film transistor; forming a via hole in the organic material layer to expose the drain electrode; forming a first inorganic material layer, wherein the first inorganic material layer covers at least a sidewall of the via hole and a part of the organic material layer, and the first inorganic material layer exposes at least the drain electrode; and finally, forming a patterned transparent pixel electrode layer on the first inorganic material layer, wherein the patterned transparent pixel electrode layer contacts the drain electrode through the via hole.
- an array substrate comprises: a substrate, wherein a thin film transistor is disposed on the substrate, and the thin film transistor comprises a gate electrode, a gate insulating layer, a source electrode, and a drain electrode; an organic material layer covering the substrate and the thin film transistor; a via hole penetrating the organic material layer and exposing the drain electrode; a first inorganic material layer, covering at least a sidewall of the via hole and a part of the organic material layer and exposing the drain electrode; and a patterned transparent pixel electrode layer disposed on the first inorganic material layer and in the via hole and contacting the drain electrode.
- the patterned transparent pixel electrode layer is disposed on the inorganic material layer. Because the coefficients of thermal expansion are similar to each other between the patterned transparent pixel electrode layer and the inorganic material layer, cracks will not be formed in the patterned transparent pixel electrode layer on the inorganic material layer due to temperature variations.
- FIG. 1 is a schematic diagram illustrating a top view of an array substrate according to the preferred embodiment of the present invention.
- FIG. 2 is a schematic diagram illustrating a cross-sectional view of the array substrate along the line AA′ and the line BB′ in FIG. 1 according to the first preferred embodiment of the present invention.
- FIG. 3 is a schematic diagram illustrating a cross-sectional view of the array substrate along the line AA′ and the line BB′ in FIG. 1 according to the second preferred embodiment of the present invention.
- FIG. 4 is a schematic diagram illustrating a cross-sectional view of the array substrate along the line AA′ and the line BB′ in FIG. 1 according to the third preferred embodiment of the present invention.
- FIG. 5 is a schematic diagram illustrating a cross-sectional view of the array substrate along the line AA′ and the line BB′ in FIG. 1 according to the fourth preferred embodiment of the present invention.
- FIGS. 6-10 are schematic diagrams illustrating methods of manufacturing an array substrate in the present invention.
- FIG. 1 is a schematic diagram illustrating a top view of an array substrate according to the preferred embodiment of the present invention.
- FIG. 2 is a schematic diagram illustrating a cross-sectional view of the array substrate along the line AA′ and the line BB′ in FIG. 1 according to the first preferred embodiment of the present invention.
- an array substrate 10 comprises a substrate 12 divided into a device area 14 and a pixel area 16 , wherein a thin film transistor 18 is disposed in the device area 14 .
- the thin film transistor 18 comprises a gate electrode 20 , a gate insulating layer 22 , which covers the gate electrode 20 and the device area 14 and the pixel area 16 of the substrate 12 , a semiconductor layer 24 disposed on the gate insulating layer 22 , and a source electrode 26 and a drain electrode 28 disposed on the gate insulating layer 22 and on the semiconductor layer 24 . Additionally, the source electrode 26 and the drain electrode 28 are separately disposed on the two sides of the gate electrode 20 .
- An organic material layer 30 covers the gate insulating layer 22 on the device area 14 of the substrate 12 and the gate insulating layer 22 on the pixel area 16 of the substrate 12 .
- a via hole 32 penetrates the organic material layer 30 to expose the drain electrode 28 through the via hole 32 , and the via hole 32 can be a contact hole of the drain electrode 28 .
- a first inorganic material layer 34 such as silicon nitride or silicon oxide, entirely covers the organic material layer 30 on the device area 14 of the substrate 12 and the organic material layer 30 on the pixel area 16 of the substrate 12 . The first inorganic layer 34 covers and contacts a sidewall of the via hole 32 , and the drain electrode 28 is exposed through the via hole 32 .
- a preferred thickness of the first inorganic material layer 34 is substantially about 3000 angstroms.
- a patterned transparent pixel electrode layer 36 is disposed on a part of the first inorganic material layer 34 and in the via hole 32 to contact the drain electrode 28 .
- the pattered transparent pixel electrode layer 36 comprises at least two main pixel electrodes 38 and a bridge electrode 40 disposed between and connected to the two main pixel electrodes 38 , and a width of the bridge electrode 40 is smaller than a width of each main pixel electrode 38 .
- the transparent pixel electrode layer 36 can be made of indium tin oxide (ITO) or other transparent conductive materials.
- FIG. 3 is a schematic diagram illustrating a cross-sectional view of the array substrate along the line AA′ and the line BB′ in FIG. 1 according to the second preferred embodiment of the present invention.
- the first inorganic material layer 34 can cover only a part of the organic material layer 30 on the device area 14 and the pixel area 16 .
- the first inorganic layer 34 is disposed only on the sidewall of the via hole 32 , on the organic material layer 30 around the via hole 32 , on the organic material layer 30 right under the bridge electrode 40 , and on the organic material layer 30 around an area right under the bridge electrode 40 .
- the allocation of other devices on the array substrate of the second preferred embodiment is similar to the first preferred embodiment and will not be redundantly described.
- FIG. 4 is a schematic diagram illustrating a cross-sectional view of the array substrate along the line AA′ and the line BB′ in FIG. 1 according to the third preferred embodiment of the present invention, wherein the identical components will be marked with the same symbols.
- the array substrate 10 can further comprise a second inorganic material layer 134 disposed between the gate insulating layer 22 and the organic layer 30 in the device area 14 and the pixel area 16 of the substrate 12 , and the second inorganic layer 134 consequently covers the thin film transistor 18 .
- the similarity between the third embodiment and the first embodiment is that a first inorganic material layer 34 entirely covers the organic material layer 30 on the device area 14 and the pixel area 16 of the substrate 12 , and the first inorganic material layer 34 covers and contacts the sidewall of the via hole 32 .
- the preferred thickness of the first inorganic material layer in the third preferred embodiment is different from the preferred thickness of the first inorganic material layer in the first preferred embodiment.
- the preferred thickness of the first inorganic material layer 34 and the second inorganic material layer 134 are both substantially about 1500 angstroms, but the present invention is not limited to this.
- the first inorganic material layer 34 and the second inorganic material layer 134 can be silicon nitride or silicon oxide, and the allocation of other devices on the array substrate of the third preferred embodiment is similar to the first preferred embodiment and will not be redundantly described.
- FIG. 5 is a schematic diagram illustrating a cross-sectional view of the array substrate along the line AA′ and the line BB′ in FIG. 1 according to the fourth preferred embodiment of the present invention.
- the first inorganic material layer 34 can cover only a part of the organic material layer 30 on the device area 14 and the pixel area 16 .
- the first inorganic layer 34 is disposed only on the sidewall of the via hole 32 , on the organic material layer 30 around the via hole 32 , on the organic material layer 30 right under the bridge electrode 40 , and on the organic material layer 30 around an area right under the bridge electrode 40 .
- the allocation of other devices on the array substrate of the fourth preferred embodiment is similar to the third preferred embodiment.
- a substrate 12 divided into a device area 14 and a pixel area 16 is provided, and a thin film transistor 18 is disposed in the device area 14 , wherein the thin film transistor 18 comprises a gate electrode 20 , a gate insulating layer 22 , which covers the gate electrode 20 and the device area 14 and the pixel area 16 of the substrate 12 , a semiconductor layer 24 disposed on the gate insulating layer 22 , and a source electrode 26 and a drain electrode 28 disposed on the gate insulating layer 22 and separately disposed on the two sides of the gate electrode 20 .
- an organic material layer 30 is formed, and the organic material layer 30 entirely covers the substrate 12 and the thin film transistor 18 , wherein the preferred material of the organic material layer 30 is an organic photo resist.
- a via hole 32 is further formed in the organic material layer 30 right over the drain electrode 28 to make the drain electrode 28 exposed through the via hole 32 , wherein the via hole 32 can be a contact hole of the drain electrode 28 .
- a first inorganic material layer 34 is formed, and the first inorganic material layer 34 consequently covers the organic material layer 30 , the sidewall of the via hole 32 , and a part of the drain electrode 28 . Then, an etching process is performed to remove a part of the first inorganic material layer 34 over the drain electrode 28 and expose the drain electrode 28 .
- the preferred material of the first inorganic material layer 34 is silicon nitride, and the thickness is substantially about 3000 angstroms.
- a patterned transparent pixel electrode layer 36 is then formed on the first inorganic material layer 34 .
- the patterned transparent pixel electrode layer 36 is disposed on the surface of the first inorganic material layer 34 and on the first inorganic material layer 34 over the sidewall of the via hole 32 .
- the patterned transparent pixel electrode 36 contacts the drain electrode 28 .
- the patterned transparent pixel electrode layer 36 comprises at least two main electrodes 38 and a bridge electrode 40 .
- the bridge electrode 40 is disposed between the two main pixel electrodes 38 and connected to the two main pixel electrodes 38 , and the width of the bridge electrode is smaller than the width of each main pixel electrode 38 .
- the patterned transparent pixel electrode layer 36 can be indium tin oxide (ITO) or other transparent conductive materials.
- the method of manufacturing the array substrate in the second preferred embodiment there is only a little difference between the method of manufacturing the array substrate in the second preferred embodiment and the method of manufacturing the array substrate in the first preferred embodiment.
- a part of the first inorganic material layer 34 on the surface of the organic layer 30 needs to be removed during the process, which removes the first inorganic material layer 34 on the drain electrode 28 , as shown in FIG. 7 .
- the first inorganic material layer 34 only remains on the organic material layer 30 over the sidewall of the via hole 32 , on the organic material layer 30 around the via hole 32 , on the organic material layer 30 right under the bridge electrode 40 , and on the organic material layer 30 around an area right under the bridge electrode 40 .
- the patterned transparent pixel electrode 36 is formed, as in the process described in the first preferred embodiment, to form the array substrate 10 shown in FIG. 3 .
- FIG. 8 firstly a substrate 12 divided into a device area 14 and a pixel area 16 is provided, and a thin film transistor 18 is disposed in the device area 14 , wherein the thin film transistor 18 comprises a gate electrode 20 , a gate insulating layer 22 , which covers the gate electrode 20 and the device area 14 and the pixel area 16 of the substrate 12 , a semiconductor layer 24 disposed on the gate insulating layer 22 , and a source electrode 26 and a drain electrode 28 disposed on the gate insulating layer 22 and separately disposed on the two sides of the gate electrode 20 .
- the thin film transistor 18 comprises a gate electrode 20 , a gate insulating layer 22 , which covers the gate electrode 20 and the device area 14 and the pixel area 16 of the substrate 12 , a semiconductor layer 24 disposed on the gate insulating layer 22 , and a source electrode 26 and a drain electrode 28 disposed on the gate insulating layer 22 and separately disposed on the two sides of the gate electrode 20 .
- a second inorganic material layer 134 is formed, and the second inorganic material layer 134 entirely covers the device area 14 and the pixel area 16 of the substrate 12 and entirely covers the thin film transistor 18 .
- the second inorganic material layer 134 is silicon nitride or silicon oxide, and the preferred thickness of the second inorganic material layer 134 is substantially about 1500 angstroms.
- an organic material layer 30 is formed, and the organic material layer 30 entirely covers the second inorganic material layer 134 in the device area 14 and in the pixel area 16 .
- a via hole 32 is further formed in the organic material layer 30 right over the drain electrode 28 , to expose the second inorganic material layer 134 through the via hole 32 .
- a first inorganic material layer 34 is formed and the first inorganic material layer 34 consequently covers the organic material layer 30 , the sidewall of the via hole 32 , and a part of the second inorganic material layer 34 .
- an etching process is performed to remove a part of the first inorganic material layer 34 and a part of the second inorganic material layer 134 over the drain electrode 28 , and the drain electrode 28 is exposed.
- a patterned transparent pixel electrode layer 36 is then formed on the first inorganic material layer 34 .
- the patterned transparent pixel electrode layer 36 is disposed at least on a part of the surface of the first inorganic material layer 34 and on the first inorganic material layer 34 over the sidewall of the via hole 32 .
- the patterned transparent pixel electrode layer 36 contacts the drain electrode 28 .
- the patterned transparent pixel electrode layer 36 comprises at least two main electrodes 38 and a bridge electrode 40 .
- the bridge electrode 40 is disposed between the two main pixel electrodes 38 and connected to the two main pixel electrodes 38 , and the width of the bridge electrode is smaller than the width of each main pixel electrode 38 .
- the patterned transparent pixel electrode layer 36 can be indium tin oxide (ITO) or other transparent conductive materials.
- the method of manufacturing the array substrate in the fourth preferred embodiment there is only a little difference between the method of manufacturing the array substrate in the fourth preferred embodiment and the method of manufacturing the array substrate in the third preferred embodiment.
- the array substrate 10 in the fourth preferred embodiment a part of the first inorganic material layer 34 on the surface of the organic layer 30 needs to be removed during the process, which removes the first inorganic material layer 34 and the second inorganic material layer 134 on the drain electrode 28 .
- the first inorganic material layer 34 only remains on the organic material layer 30 over the sidewall of the via hole 32 , on the organic material layer 30 around the via hole 32 , on the organic material layer 30 right under the bridge electrode 40 , and on the organic material layer 30 around an area right under the bridge electrode 40 .
- the patterned transparent pixel electrode 36 is formed, as the process described in the third preferred embodiment, to form the array substrate 10 shown in FIG. 5 .
- an inorganic material layer such as silicon nitride
- the inorganic material layer is disposed especially on the sidewall of the via hole, on the organic material layer around the via hole and on the organic material under the bridge electrode, to keep the patterned transparent pixel electrode from directly contacting the organic material layer.
- the normal patterned transparent pixel electrode is indium tin oxide (ITO), and the respective coefficients of thermal expansion for indium tin oxide (ITO) and silicon nitride are similar to each other.
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Abstract
An array substrate includes a substrate, an organic layer, a via hole, an inorganic layer, and a patterned transparent pixel electrode layer. The thin film transistor is disposed on the substrate, and the thin film transistor comprises a drain electrode. The organic material layer covers the substrate and the thin film transistor. The via hole penetrates the organic material layer and exposes the drain electrode. The inorganic material layer covers at least a sidewall of the via hole and a part of the organic material layer, and exposes the drain electrode through the via hole. The patterned transparent pixel electrode layer is disposed on the first inorganic material layer and in the via hole, and the patterned transparent pixel electrode layer contacts the drain electrode.
Description
- 1. Field of the Invention
- The present invention relates to an array substrate, and more particularly, to an array substrate with a structure to keep transparent electrodes from cracking.
- 2. Description of the Prior Art
- Among current display technologies, liquid crystal displays are widely used in electronic devices because of their advantages, such as light weight, small volume, low power consumption, and radiation-free characteristics.
- In general, a plurality of scan lines and a plurality of data lines are disposed on an array substrate of a liquid crystal display panel. The scan lines and the data lines are arranged perpendicular to each other to divide the substrate into a plurality of pixel units. Each of the pixel units has a pixel electrode and a thin film transistor (TFT). The thin film transistor is electrically connected to the scan line and the data line, for being a switching device of the pixel electrode. The pixel electrode, which is used in the substrate of a transmissive liquid crystal display panel and in the transmissive area of a transflective liquid crystal display panel, is made of a transparent conductive material, such as indium tin oxide (ITO).
- Generally, there is a planar layer covering the scan lines, the data lines, and the thin film transistors, and then the transparent conductive material is formed on the planar layer as the pixel electrode. Because of the large difference in the coefficients of thermal expansion between the normal material of the planar layer and the transparent conductive material, there will be cracks generated at the area with weaker mechanical structure in the transparent conductive material after thermal treatment of the substrate, such as annealing.
- It is one of the objectives of the present invention to provide an array substrate to solve the above-mentioned problem of cracks in the transparent conductive material.
- According to a preferred embodiment of the present invention, a method of manufacturing an array substrate comprises: providing a substrate, wherein a thin film transistor is disposed on the substrate, and the thin film transistor comprises a gate electrode, a gate insulating layer, a source electrode, and a drain electrode; forming an organic material layer covering the substrate and the thin film transistor; forming a via hole in the organic material layer to expose the drain electrode; forming a first inorganic material layer, wherein the first inorganic material layer covers at least a sidewall of the via hole and a part of the organic material layer, and the first inorganic material layer exposes at least the drain electrode; and finally, forming a patterned transparent pixel electrode layer on the first inorganic material layer, wherein the patterned transparent pixel electrode layer contacts the drain electrode through the via hole.
- According to another preferred embodiment of the present invention, an array substrate comprises: a substrate, wherein a thin film transistor is disposed on the substrate, and the thin film transistor comprises a gate electrode, a gate insulating layer, a source electrode, and a drain electrode; an organic material layer covering the substrate and the thin film transistor; a via hole penetrating the organic material layer and exposing the drain electrode; a first inorganic material layer, covering at least a sidewall of the via hole and a part of the organic material layer and exposing the drain electrode; and a patterned transparent pixel electrode layer disposed on the first inorganic material layer and in the via hole and contacting the drain electrode.
- In the present invention, the patterned transparent pixel electrode layer is disposed on the inorganic material layer. Because the coefficients of thermal expansion are similar to each other between the patterned transparent pixel electrode layer and the inorganic material layer, cracks will not be formed in the patterned transparent pixel electrode layer on the inorganic material layer due to temperature variations.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
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FIG. 1 is a schematic diagram illustrating a top view of an array substrate according to the preferred embodiment of the present invention. -
FIG. 2 is a schematic diagram illustrating a cross-sectional view of the array substrate along the line AA′ and the line BB′ inFIG. 1 according to the first preferred embodiment of the present invention. -
FIG. 3 is a schematic diagram illustrating a cross-sectional view of the array substrate along the line AA′ and the line BB′ inFIG. 1 according to the second preferred embodiment of the present invention. -
FIG. 4 is a schematic diagram illustrating a cross-sectional view of the array substrate along the line AA′ and the line BB′ inFIG. 1 according to the third preferred embodiment of the present invention. -
FIG. 5 is a schematic diagram illustrating a cross-sectional view of the array substrate along the line AA′ and the line BB′ inFIG. 1 according to the fourth preferred embodiment of the present invention. -
FIGS. 6-10 are schematic diagrams illustrating methods of manufacturing an array substrate in the present invention. - Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will understand, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . .”
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FIG. 1 is a schematic diagram illustrating a top view of an array substrate according to the preferred embodiment of the present invention.FIG. 2 is a schematic diagram illustrating a cross-sectional view of the array substrate along the line AA′ and the line BB′ inFIG. 1 according to the first preferred embodiment of the present invention. - Please refer to
FIG. 1 andFIG. 2 , anarray substrate 10 comprises asubstrate 12 divided into adevice area 14 and apixel area 16, wherein athin film transistor 18 is disposed in thedevice area 14. Thethin film transistor 18 comprises agate electrode 20, agate insulating layer 22, which covers thegate electrode 20 and thedevice area 14 and thepixel area 16 of thesubstrate 12, asemiconductor layer 24 disposed on thegate insulating layer 22, and asource electrode 26 and adrain electrode 28 disposed on thegate insulating layer 22 and on thesemiconductor layer 24. Additionally, thesource electrode 26 and thedrain electrode 28 are separately disposed on the two sides of thegate electrode 20. - An
organic material layer 30, such as organic photo resist, covers thegate insulating layer 22 on thedevice area 14 of thesubstrate 12 and thegate insulating layer 22 on thepixel area 16 of thesubstrate 12. Avia hole 32 penetrates theorganic material layer 30 to expose thedrain electrode 28 through thevia hole 32, and thevia hole 32 can be a contact hole of thedrain electrode 28. A firstinorganic material layer 34, such as silicon nitride or silicon oxide, entirely covers theorganic material layer 30 on thedevice area 14 of thesubstrate 12 and theorganic material layer 30 on thepixel area 16 of thesubstrate 12. The firstinorganic layer 34 covers and contacts a sidewall of thevia hole 32, and thedrain electrode 28 is exposed through thevia hole 32. A preferred thickness of the firstinorganic material layer 34 is substantially about 3000 angstroms. A patterned transparentpixel electrode layer 36 is disposed on a part of the firstinorganic material layer 34 and in thevia hole 32 to contact thedrain electrode 28. The pattered transparentpixel electrode layer 36 comprises at least twomain pixel electrodes 38 and abridge electrode 40 disposed between and connected to the twomain pixel electrodes 38, and a width of thebridge electrode 40 is smaller than a width of eachmain pixel electrode 38. In addition, the transparentpixel electrode layer 36 can be made of indium tin oxide (ITO) or other transparent conductive materials. -
FIG. 3 is a schematic diagram illustrating a cross-sectional view of the array substrate along the line AA′ and the line BB′ inFIG. 1 according to the second preferred embodiment of the present invention. According to the second preferred embodiment of the present invention, the firstinorganic material layer 34 can cover only a part of theorganic material layer 30 on thedevice area 14 and thepixel area 16. As shown inFIG. 3 , the firstinorganic layer 34 is disposed only on the sidewall of thevia hole 32, on theorganic material layer 30 around thevia hole 32, on theorganic material layer 30 right under thebridge electrode 40, and on theorganic material layer 30 around an area right under thebridge electrode 40. The allocation of other devices on the array substrate of the second preferred embodiment is similar to the first preferred embodiment and will not be redundantly described. -
FIG. 4 is a schematic diagram illustrating a cross-sectional view of the array substrate along the line AA′ and the line BB′ inFIG. 1 according to the third preferred embodiment of the present invention, wherein the identical components will be marked with the same symbols. As shown inFIG. 4 , thearray substrate 10 can further comprise a secondinorganic material layer 134 disposed between thegate insulating layer 22 and theorganic layer 30 in thedevice area 14 and thepixel area 16 of thesubstrate 12, and the secondinorganic layer 134 consequently covers thethin film transistor 18. The similarity between the third embodiment and the first embodiment is that a firstinorganic material layer 34 entirely covers theorganic material layer 30 on thedevice area 14 and thepixel area 16 of thesubstrate 12, and the firstinorganic material layer 34 covers and contacts the sidewall of thevia hole 32. - However, the preferred thickness of the first inorganic material layer in the third preferred embodiment is different from the preferred thickness of the first inorganic material layer in the first preferred embodiment. In the third preferred embodiment, the preferred thickness of the first
inorganic material layer 34 and the secondinorganic material layer 134 are both substantially about 1500 angstroms, but the present invention is not limited to this. In addition, the firstinorganic material layer 34 and the secondinorganic material layer 134 can be silicon nitride or silicon oxide, and the allocation of other devices on the array substrate of the third preferred embodiment is similar to the first preferred embodiment and will not be redundantly described. -
FIG. 5 is a schematic diagram illustrating a cross-sectional view of the array substrate along the line AA′ and the line BB′ inFIG. 1 according to the fourth preferred embodiment of the present invention. According to the fourth preferred embodiment of the present invention, the firstinorganic material layer 34 can cover only a part of theorganic material layer 30 on thedevice area 14 and thepixel area 16. As shown inFIG. 5 , the firstinorganic layer 34 is disposed only on the sidewall of thevia hole 32, on theorganic material layer 30 around thevia hole 32, on theorganic material layer 30 right under thebridge electrode 40, and on theorganic material layer 30 around an area right under thebridge electrode 40. The allocation of other devices on the array substrate of the fourth preferred embodiment is similar to the third preferred embodiment. - The following description will detail the method of manufacturing an array substrate in the first preferred embodiment and the second preferred embodiment of the present invention as shown in
FIG. 6 andFIG. 7 , wherein the identical components will be marked with the same symbols. As shown inFIG. 6 , firstly asubstrate 12 divided into adevice area 14 and apixel area 16 is provided, and athin film transistor 18 is disposed in thedevice area 14, wherein thethin film transistor 18 comprises agate electrode 20, agate insulating layer 22, which covers thegate electrode 20 and thedevice area 14 and thepixel area 16 of thesubstrate 12, asemiconductor layer 24 disposed on thegate insulating layer 22, and asource electrode 26 and adrain electrode 28 disposed on thegate insulating layer 22 and separately disposed on the two sides of thegate electrode 20. Following that, anorganic material layer 30 is formed, and theorganic material layer 30 entirely covers thesubstrate 12 and thethin film transistor 18, wherein the preferred material of theorganic material layer 30 is an organic photo resist. Then, avia hole 32 is further formed in theorganic material layer 30 right over thedrain electrode 28 to make thedrain electrode 28 exposed through thevia hole 32, wherein thevia hole 32 can be a contact hole of thedrain electrode 28. - As shown in
FIG. 7 , a firstinorganic material layer 34 is formed, and the firstinorganic material layer 34 consequently covers theorganic material layer 30, the sidewall of the viahole 32, and a part of thedrain electrode 28. Then, an etching process is performed to remove a part of the firstinorganic material layer 34 over thedrain electrode 28 and expose thedrain electrode 28. The preferred material of the firstinorganic material layer 34 is silicon nitride, and the thickness is substantially about 3000 angstroms. - Please refer to
FIG. 2 . After completing the process of etching the firstinorganic material layer 34, a patterned transparentpixel electrode layer 36 is then formed on the firstinorganic material layer 34. The patterned transparentpixel electrode layer 36 is disposed on the surface of the firstinorganic material layer 34 and on the firstinorganic material layer 34 over the sidewall of the viahole 32. The patternedtransparent pixel electrode 36 contacts thedrain electrode 28. Additionally, the patterned transparentpixel electrode layer 36 comprises at least twomain electrodes 38 and abridge electrode 40. Thebridge electrode 40 is disposed between the twomain pixel electrodes 38 and connected to the twomain pixel electrodes 38, and the width of the bridge electrode is smaller than the width of eachmain pixel electrode 38. The patterned transparentpixel electrode layer 36 can be indium tin oxide (ITO) or other transparent conductive materials. Then the array substrate in the first preferred embodiment of the present invention is completed. - There is only a little difference between the method of manufacturing the array substrate in the second preferred embodiment and the method of manufacturing the array substrate in the first preferred embodiment. According to the
array substrate 10 in the second preferred embodiment, a part of the firstinorganic material layer 34 on the surface of theorganic layer 30 needs to be removed during the process, which removes the firstinorganic material layer 34 on thedrain electrode 28, as shown inFIG. 7 . The firstinorganic material layer 34 only remains on theorganic material layer 30 over the sidewall of the viahole 32, on theorganic material layer 30 around the viahole 32, on theorganic material layer 30 right under thebridge electrode 40, and on theorganic material layer 30 around an area right under thebridge electrode 40. Then, the patternedtransparent pixel electrode 36 is formed, as in the process described in the first preferred embodiment, to form thearray substrate 10 shown inFIG. 3 . - The following description will detail the method of manufacturing an array substrate in the third preferred embodiment and the fourth preferred embodiment of the present invention as shown in
FIGS. 8-10 , wherein the identical components will be marked with the same symbols. As shown inFIG. 8 , firstly asubstrate 12 divided into adevice area 14 and apixel area 16 is provided, and athin film transistor 18 is disposed in thedevice area 14, wherein thethin film transistor 18 comprises agate electrode 20, agate insulating layer 22, which covers thegate electrode 20 and thedevice area 14 and thepixel area 16 of thesubstrate 12, asemiconductor layer 24 disposed on thegate insulating layer 22, and asource electrode 26 and adrain electrode 28 disposed on thegate insulating layer 22 and separately disposed on the two sides of thegate electrode 20. Following that, a secondinorganic material layer 134 is formed, and the secondinorganic material layer 134 entirely covers thedevice area 14 and thepixel area 16 of thesubstrate 12 and entirely covers thethin film transistor 18. According to the preferred embodiment of the present invention, the secondinorganic material layer 134 is silicon nitride or silicon oxide, and the preferred thickness of the secondinorganic material layer 134 is substantially about 1500 angstroms. - As shown in
FIG. 9 , anorganic material layer 30 is formed, and theorganic material layer 30 entirely covers the secondinorganic material layer 134 in thedevice area 14 and in thepixel area 16. Then, a viahole 32 is further formed in theorganic material layer 30 right over thedrain electrode 28, to expose the secondinorganic material layer 134 through the viahole 32. As shown inFIG. 10 , a firstinorganic material layer 34 is formed and the firstinorganic material layer 34 consequently covers theorganic material layer 30, the sidewall of the viahole 32, and a part of the secondinorganic material layer 34. Then, an etching process is performed to remove a part of the firstinorganic material layer 34 and a part of the secondinorganic material layer 134 over thedrain electrode 28, and thedrain electrode 28 is exposed. - As shown in
FIG. 4 , a patterned transparentpixel electrode layer 36 is then formed on the firstinorganic material layer 34. The patterned transparentpixel electrode layer 36 is disposed at least on a part of the surface of the firstinorganic material layer 34 and on the firstinorganic material layer 34 over the sidewall of the viahole 32. The patterned transparentpixel electrode layer 36 contacts thedrain electrode 28. In addition, the patterned transparentpixel electrode layer 36 comprises at least twomain electrodes 38 and abridge electrode 40. Thebridge electrode 40 is disposed between the twomain pixel electrodes 38 and connected to the twomain pixel electrodes 38, and the width of the bridge electrode is smaller than the width of eachmain pixel electrode 38. The patterned transparentpixel electrode layer 36 can be indium tin oxide (ITO) or other transparent conductive materials. Then thearray substrate 10 in the third preferred embodiment of the present invention is completed. - There is only a little difference between the method of manufacturing the array substrate in the fourth preferred embodiment and the method of manufacturing the array substrate in the third preferred embodiment. According to the
array substrate 10 in the fourth preferred embodiment, a part of the firstinorganic material layer 34 on the surface of theorganic layer 30 needs to be removed during the process, which removes the firstinorganic material layer 34 and the secondinorganic material layer 134 on thedrain electrode 28. And the firstinorganic material layer 34 only remains on theorganic material layer 30 over the sidewall of the viahole 32, on theorganic material layer 30 around the viahole 32, on theorganic material layer 30 right under thebridge electrode 40, and on theorganic material layer 30 around an area right under thebridge electrode 40. Then, the patternedtransparent pixel electrode 36 is formed, as the process described in the third preferred embodiment, to form thearray substrate 10 shown inFIG. 5 . - In the present invention, an inorganic material layer, such as silicon nitride, is disposed under the patterned transparent pixel electrode layer. The inorganic material layer is disposed especially on the sidewall of the via hole, on the organic material layer around the via hole and on the organic material under the bridge electrode, to keep the patterned transparent pixel electrode from directly contacting the organic material layer. Additionally, the normal patterned transparent pixel electrode is indium tin oxide (ITO), and the respective coefficients of thermal expansion for indium tin oxide (ITO) and silicon nitride are similar to each other. Therefore, by disposing an inorganic material layer under the patterned transparent pixel electrode, cracks in the patterned transparent pixel electrode layer on the inorganic material layer will not be generated by temperature variations, and the completeness of the patterned transparent pixel electrode on the sidewall of the via hole and under the bridge electrode can be especially maintained.
- Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.
Claims (8)
1. An array substrate, comprising:
a substrate, wherein a thin film transistor is disposed on the substrate, and the thin film transistor comprises a gate electrode, a gate insulating layer, a source electrode, and a drain electrode;
an organic material layer, covering the substrate and the thin film transistor;
a via hole, penetrating the organic material layer and exposing the drain electrode;
a first inorganic material layer, covering at least a sidewall of the via hole and a part of the organic material layer, and exposing the drain electrode; and
a patterned transparent pixel electrode layer, disposed on the first inorganic material layer and in the via hole, and contacting the drain electrode.
2. The array substrate in claim 1 , wherein the patterned transparent pixel electrode layer comprises at least two main pixel electrodes and a bridge electrode, the bridge electrode is disposed between the two main pixel electrodes and connected to the two main pixel electrodes, and a width of the bridge electrode is smaller than a width of one of the two main pixel electrodes.
3. The array substrate in claim 1 , wherein the first inorganic material layer is disposed only on the sidewall of the via hole, on the organic material layer around the via hole, and on the organic material layer under the bridge electrode.
4. The array substrate in claim 1 , wherein the first inorganic material layer is disposed on the sidewall of the via hole and the first inorganic material layer entirely covers an upper surface of the organic material layer.
5. The array substrate in claim 1 , further comprising: a second inorganic material layer disposed between the gate insulating layer and the organic material layer, wherein the second inorganic material layer exposes a part of the drain electrode.
6. The array substrate in claim 5 , wherein the second inorganic material layer is silicon nitride.
7. The array substrate in claim 1 , wherein the organic material layer is an organic photo resist.
8. The array substrate in claim 1 , wherein the first inorganic material layer is silicon nitride.
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TW099128617A TWI439985B (en) | 2010-08-26 | 2010-08-26 | Array substrate and method of fabricating the same |
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US12/954,897 Expired - Fee Related US8021972B1 (en) | 2010-08-26 | 2010-11-28 | Method of manufacturing array substrate |
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CN107808886A (en) * | 2017-11-01 | 2018-03-16 | 京东方科技集团股份有限公司 | Cross hole connection structure and manufacture method, array base palte and manufacture method, display device |
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CN113517306B (en) * | 2021-07-14 | 2023-07-18 | 福州京东方光电科技有限公司 | Display substrate, manufacturing method, display screen and device |
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KR100858297B1 (en) * | 2001-11-02 | 2008-09-11 | 삼성전자주식회사 | Reflective-transmissive type liquid crystal display device and method of manufacturing the same |
KR100776939B1 (en) | 2001-12-28 | 2007-11-21 | 엘지.필립스 엘시디 주식회사 | method for fabricating a Transflective liquid crystal display device |
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KR100611152B1 (en) * | 2003-11-27 | 2006-08-09 | 삼성에스디아이 주식회사 | Flat Panel Display |
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KR100846974B1 (en) * | 2006-06-23 | 2008-07-17 | 베이징 보에 옵토일렉트로닉스 테크놀로지 컴퍼니 리미티드 | Tft lcd array substrate and manufacturing method thereof |
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- 2010-08-26 TW TW099128617A patent/TWI439985B/en not_active IP Right Cessation
- 2010-11-28 US US12/954,901 patent/US20120049198A1/en not_active Abandoned
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CN107808886A (en) * | 2017-11-01 | 2018-03-16 | 京东方科技集团股份有限公司 | Cross hole connection structure and manufacture method, array base palte and manufacture method, display device |
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US8021972B1 (en) | 2011-09-20 |
TWI439985B (en) | 2014-06-01 |
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