US20110266613A1 - Semiconductor component and method of manufacture - Google Patents
Semiconductor component and method of manufacture Download PDFInfo
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- US20110266613A1 US20110266613A1 US12/771,869 US77186910A US2011266613A1 US 20110266613 A1 US20110266613 A1 US 20110266613A1 US 77186910 A US77186910 A US 77186910A US 2011266613 A1 US2011266613 A1 US 2011266613A1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 53
- 238000000034 method Methods 0.000 title claims description 59
- 239000003989 dielectric material Substances 0.000 claims abstract description 72
- 239000000463 material Substances 0.000 claims abstract description 38
- 239000004020 conductor Substances 0.000 claims description 74
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 61
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
Abstract
Description
- The present invention relates, in general, to electronics and, more particularly, to semiconductor components and their manufacture.
- Metal-Oxide Semiconductor Field Effect Transistors (“MOSFETS”) are a common type of power switching device. A MOSFET device includes a source region, a drain region, a channel region extending between the source and drain regions, and a gate structure provided adjacent to the channel region. The gate structure includes a conductive gate electrode layer disposed adjacent to and separated from the channel region by a thin dielectric layer. When a voltage of sufficient strength is applied to the gate structure to place the MOSFET device in an on state, a conduction channel region forms between the source and drain regions thereby allowing current to flow through the device. When the voltage that is applied to the gate is not sufficient to cause channel formation, current does not flow and the MOSFET device is in an off state.
- In the past, the semiconductor industry used various different device structures and methods to form MOSFETS. One particular structure for a vertical power MOSFET used trenches that were formed in an active area of the MOSFET. A portion of those trenches were used as the gate regions of the transistor. Some of these transistors also had a shield conductor that assisted in lowering the gate-to-drain capacitance of the transistor. Lowering the gate-to-drain capacitance of the transistors increases the transition rate of their drain-to-source voltage during turn-on and turn-off of the transistors. A low gate-to-drain capacitance reduces the switching power losses of the MOSFET, and hence results in increased efficiency in some applications. However, in applications in which the MOSFET serves as, for example, a high side FET, where its source is coupled to the drain of a low side FET to form a switch node, the increased transition rate during turn-off may lead to ringing at the switch node. The ringing becomes more pronounced in packages having a high source inductance and can cause the systems in which the transistors are used to malfunction and dissipate a large amount of energy.
- Accordingly, it would be advantageous to have a semiconductor component and a method for forming the semiconductor component that predictably and reliably optimizes the gate-to-drain capacitance of a FET to achieve a good trade-off between efficiency and switch node ringing. It would be of further advantage for the semiconductor component to be cost efficient to manufacture.
- The present invention will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying drawing figures, in which like reference characters designate like elements and in which:
-
FIG. 1 is a schematic of a circuit that includes semiconductor components in accordance with embodiments of the present invention; -
FIG. 2 is a plan view of a semiconductor component during manufacture in accordance with an embodiment of the present invention; -
FIG. 3 is cross-sectional view of a portion of the semiconductor component ofFIG. 2 taken along the region of section line 3-3 ofFIG. 2 but at a later stage of manufacture; -
FIG. 4 is cross-sectional view of a portion of the semiconductor component ofFIG. 2 taken along the region of section line 4-4 ofFIG. 2 but at a later stage of manufacture; -
FIG. 5 is cross-sectional view of a portion of the semiconductor component ofFIG. 2 taken along the region of section line 5-5 ofFIG. 2 but at a later stage of manufacture; -
FIG. 6 is a cross-sectional view of the semiconductor component ofFIG. 2 taken along section line 6-6 ofFIG. 2 , but at a later stage of manufacture; -
FIG. 7 is a cross-sectional view of the semiconductor component ofFIG. 4 at an earlier stage of manufacture; -
FIG. 8 is a cross-sectional view of the semiconductor component ofFIG. 7 at a later stage of manufacture; -
FIG. 9 is a cross-sectional view of the semiconductor component ofFIG. 8 at a later stage of manufacture; -
FIG. 10 is a cross-sectional view of the semiconductor component ofFIG. 3 at a later stage of manufacture; -
FIG. 11 is a cross-sectional view of the semiconductor component ofFIG. 5 at a later stage of manufacture; -
FIG. 12 is a cross-sectional view of the semiconductor component ofFIG. 9 at a later stage of manufacture; -
FIG. 13 is a cross-sectional view of the semiconductor component ofFIG. 10 at a later stage of manufacture; -
FIG. 14 is a cross-sectional view of the semiconductor component ofFIG. 12 at a later stage of manufacture; -
FIG. 15 is a cross-sectional view of the semiconductor component ofFIG. 13 at a later stage of manufacture; -
FIG. 16 is a cross-sectional view of the semiconductor component ofFIG. 11 at a later stage of manufacture; -
FIG. 17 is a cross-sectional view of the semiconductor component ofFIG. 14 at a later stage of manufacture; -
FIG. 18 is a cross-sectional view of the semiconductor component ofFIG. 15 at a later stage of manufacture; -
FIG. 19 is a cross-sectional view of the semiconductor component ofFIG. 16 at a later stage of manufacture; -
FIG. 20 is a cross-sectional view of the semiconductor component ofFIG. 17 at a later stage of manufacture; -
FIG. 21 is a cross-sectional view of the semiconductor component ofFIG. 18 at a later stage of manufacture; -
FIG. 22 is a cross-sectional view of the semiconductor component ofFIG. 19 at a later stage of manufacture; -
FIG. 23 is a cross-sectional view of the semiconductor component ofFIG. 20 at a later stage of manufacture; -
FIG. 24 is a cross-sectional view of the semiconductor component ofFIG. 21 at a later stage of manufacture; -
FIG. 25 is a cross-sectional view of the semiconductor component ofFIG. 22 at a later stage of manufacture; -
FIG. 26 is a plan view of a semiconductor component during manufacture in accordance with another embodiment of the present invention; -
FIG. 27 is a cross-sectional view of the semiconductor component ofFIG. 26 taken along section line 30-30, but at an early stage of manufacture; -
FIG. 28 is a cross-sectional view of the semiconductor component ofFIG. 27 at a later stage of manufacture; -
FIG. 29 is a cross-sectional view of the semiconductor component ofFIG. 28 at a later stage of manufacture; -
FIG. 30 is a cross-sectional view of the semiconductor component ofFIG. 29 in accordance with another embodiment of the present invention; -
FIG. 30A is a cross-sectional view of the semiconductor component ofFIG. 26 taken alongsection line 30A-30A; -
FIG. 31 is a cross-sectional view of the semiconductor component ofFIG. 26 in accordance with another embodiment of the present invention, where the cross-sectional view is taken along section line 30-30; -
FIG. 32 is a cross-sectional view of the semiconductor component ofFIG. 26 in accordance with another embodiment of the present invention, where the cross-sectional view is taken along section line 30-30; -
FIG. 33 is a plan view of a semiconductor component during manufacture in accordance with another embodiment of the present invention; -
FIG. 34 is a plan view of a portion of the semiconductor component ofFIG. 33 ; -
FIG. 35 is a cross-sectional view of the semiconductor component ofFIG. 33 taken along section line 35-35 ofFIG. 33 , but at a later stage of manufacture; -
FIG. 36 is a cross-sectional view of the semiconductor component ofFIG. 33 taken along section line 36-36 ofFIG. 33 , but at a later stage of manufacture; -
FIG. 37 is a cross-sectional view of the semiconductor component ofFIG. 33 taken along section line 37-37 ofFIG. 33 , but at a later stage of manufacture; and -
FIG. 38 is a plan view of a semiconductor component during manufacture in accordance with another embodiment of the present invention. - For simplicity and clarity of the illustration, elements in the figures are not necessarily drawn to scale and the same reference characters in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of a MOSFET, or an emitter or a collector of a bipolar transistor, or a cathode or an anode of a diode, and a control electrode means an element of the device that controls current through the device such as a gate of a MOSFET or a base of a bipolar transistor. Although the devices are explained herein as certain N-channel or P-channel devices, or having certain N-type or P-type doped regions, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with embodiments of the present invention. The use of the words approximately or about means that a value of an element has a parameter that is expected to be very close to a stated value or position or state. However, it is well known in the art that there are always minor variances that prevent the values or positions from being exactly as stated. It is well established in the art that variances of up to about ten percent (10%) (and up to twenty percent (20%) for semiconductor doping concentrations) are regarded as reasonable variance from the ideal goal as described. For clarity of the drawings, doped regions of semiconductor component structures are illustrated as having generally straight line edges and precise angular corners. However, those skilled in the art understand that due to the diffusion and activation of dopants the edges of doped regions generally may not be straight lines and the corners may not be precise angles.
- In addition, the description may illustrate a cellular design (where the body regions are a plurality of cellular regions) or a single body design (where the body region is comprised of a single region formed in an elongated pattern, typically in a serpentine pattern or formed in a plurality of stripes). However, it is intended that the description is applicable to both a cellular implementation and a single base implementation.
- In some instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present disclosure. The following detailed description is merely exemplary in nature and is not intended to limit the disclosure of this document and uses of the disclosed embodiments. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding text, including the title, technical field, background, or abstract.
- Generally, the present invention provides a semiconductor component having one or more trenches in which a shield electrode and a gate electrode are formed.
FIG. 1 is a schematic of acircuit 19 having asemiconductor component 10 manufactured in accordance with embodiments of the present invention.Circuit 19 includes a control ordriver circuit 33 coupled tosemiconductor component 10.Semiconductor component 10 includes ahigh side FET 25 connected to alow side FET 27. More particularly,high side FET 25 has a drain coupled for receiving an input signal VIN, a source connected to a drain oflow side FET 27 to form a phase or switchingnode 31, and a gate coupled for receiving a gate drive signal from acontrol circuit 33.Low side FET 27 has a source coupled for receiving a source of operating potential VSS and a gate coupled for receiving a gate drive signal fromcontrol circuit 33. A parasitic diode DH and a parasitic junction capacitance CJH are formed from the drain to the source ofhigh side FET 25. A series connected parasitic shield capacitance (CSHIELDH) and a parasitic shield resistance (RSHIELDH) are formed from the drain to the source ofhigh side FET 25. A parasitic diode DL and a parasitic junction capacitance CJL are formed from the drain to the source oflow side FET 27. A series connected parasitic shield capacitance (CSHIELDL) and a parasitic shield resistance (RSHIELDL) are formed from the drain to the source oflow side FET 27. -
Control circuit 33 has an input coupled for receiving a Pulse Width Modulation (PWM) Signal, VPWM, an output connected to the gate ofhigh side FET 25, and another output connected to the gate oflow side FET 27. - In accordance with an aspect of the present invention, trenches are lined with a dielectric material such as, for example, an oxide layer, and polysilicon shield electrodes are formed over the oxide layer in one or more of the trenches. A portion of the oxide layer is removed to expose portions of the sidewalls of the trenches and top surfaces of the electrical conductors. A dielectric material is formed over the top surfaces of the electrically conductive materials. A gate dielectric material such as, for example, a gate oxide, may be formed on the sidewalls and over the dielectric material in one or more of the trenches. Gate electrodes are formed over the gate dielectric material. A predetermined percentage of the shield electrodes are connected to the gate electrodes to increase the gate-to-drain capacitance to a desired value that mitigates ringing. Some or all of the remaining shield electrodes may be connected to the source electrodes.
- In accordance with another aspect of the present invention, the shield electrodes are connected to the gate electrodes by disconnecting the trenches containing the shield electrodes from the other trenches in the trench array and connecting the shield electrodes in the trenches that have been disconnected to the electrically conductive material that forms the gate electrode. In addition to increasing the gate-to-drain capacitance, the on resistance (Rds(on)) of the FET is reduced because a portion of the shield electrodes are connected to the gate electrodes allowing for the formation of an accumulation layer on the bottom portions of the trench sidewalls when the device is on.
- In accordance with another aspect of the present invention, trenches are placed underlying the gate pads and lined with a thick dielectric layer. Electrical conductors are formed over the thick dielectric layers in the trenches to support the breakdown voltage BVdss. The electrical conductors underlying the gate pads are connected to the gate electrode, thereby increasing the gate-to-drain capacitance. The gate-to-drain capacitance can be adjusted by varying the number of trenches formed underlying the gate pad. Although the trenches have been described as being formed under the gate pads, this is not a limitation of the present invention. The trenches can be placed anywhere in the semiconductor die.
- In accordance with another aspect of the present invention, the gate-to-drain capacitance per unit area may be increased by forming a dopant layer in the portions of the semiconductor material between the trenches that underlie the gate pad and adjacent to the surface of the semiconductor material.
- In accordance with another aspect of the present invention, the series resistance of the shield electrode is adjusted to damp ringing. In a shielded FET, a large percentage of the output capacitance is the oxide capacitance from the shield electrode to the drain electrode. The shield-to-drain capacitance appears in parallel with the drain-to-source capacitance and acts with its associated series resistance to form an integrated snubber in converter applications. The series resistance of the shield electrode may be adjusted by contacting the shield electrode at a single location along each trench. Alternatively, the series resistance of the shield electrode may be adjusted by connecting two or more of the shield electrodes together at regions near the ends of the trenches and contacting the shield electrode and the source electrode in one out of N trenches. Preferably, N is an integer ranging from two to one hundred. Even more preferably, N is an integer that ranges from two to ten.
- In a high side FET, increasing the shield resistance slows down the switching of the MOSFET since the shield electrode is not strongly coupled to the source electrode, and hence is not as effective at reducing the gate-to-drain capacitance during switching. This reduces the switch node ringing during turn-off of the high side FET.
- In a low side FET, increasing the resistance of the shield electrode reduces the switch node ringing during turn-on of the high side FET. It also reduces the reverse recovery charge (Qrr) of the low side FET and increases the softness factor. This is important in converters such as, for example, Buck converters because the body diode of the low side FET is forward biased during the dead time when both the high and low side FETS are off. The output capacitance of a power MOSFET appears in parallel with the body diode and therefore is charged or discharged every time the drain voltage is switched.
-
FIG. 2 is an enlarged plan view of asemiconductor component 10 in accordance with an embodiment of the present invention. What is shown inFIG. 2 is a portion of a semiconductor die orsemiconductor chip 12 havingedge regions 14 and acenter region 16. It should be noted thatsemiconductor component 10 comprisessemiconductor chip 12. Thus, elements ofsemiconductor chip 12 are also elements ofsemiconductor component 10.Edge regions 14 are also referred to as a die edge or inactive area andcenter region 16 is also referred to as a die center or active area. A peripherally locatedshield electrode trench 21 is formed in edge regions orinactive area 14 and aroundactive area 16. Aperipheral portion 82B of ashield electrode 81 is formed in peripheralshield electrode trench 21. Theperipheral portion 82B ofshield electrode 81 serves as a termination structure forsemiconductor component 10. Preferably, an oxide thickness inperipheral portion 82B is selected to adjust the breakdown voltage of thesemiconductor component 10. A plurality oftrenches 20 extend from a portion of peripheralshield electrode trench 21 adjacent aside 22 of semiconductor die 12 to a portion of peripheralshield electrode trench 21 adjacent aside 24 of semiconductor die 12.Trenches 20 havegate contact portions 30 nearside 22,gate contact portions 32 nearside 24, and centrally locatedshield contact portions 34. Centrally locatedshield contact portions 34 may be referred to as central shield contact portions.Central portions shield electrode 81 are formed fromtrenches gate contact portions shield contact portions 34 oftrenches 20 may be wider than the portions oftrenches 20 betweengate contact portions 30 and centralshield contact portions 34 and may be wider than the portions oftrenches 20 between centralshield contact portions 34 andgate contact portions 32 to allow for the formation ofgate contacts 36 ingate contact portions 30,gate contacts 38 ingate contact portions 32, and shield-to-source contacts 40 in centralshield contact portions 34. Althoughtrenches trenches trenches 42 are spaced apart fromtrench 21 and the ends oftrenches 20 are in contact withtrench 21. It should be noted thatperipheral portion 82B ofshield electrode 81 may be referred to as a peripheral shielding electrode or a peripheral shield electrode andcentral portions shield electrode 81 may be referred to as central shielding electrodes or central shield electrodes. - A plurality of
trenches 42 are formed between and spaced apart from peripheralshield electrode trench 21, wheretrenches 42 extend fromside 22 toside 24 of semiconductor die 12.Trenches 42 have gate-to-shield contact portions 44 nearside 22 and gate-to-shield contact portions 46 nearside 24. Gate-to-shield contact portions 44 includegate contacts 36A andperipheral shield contacts 48 and gate-to-shield contact portions 46 includegate contacts 38A andperipheral shield contacts 50. Gate-to-shield contact portions trenches 42 have substantially the same width along their lengths between gate-to-shield portions Gate contacts 36A are electrically connected toperipheral shield contacts 48 andgate contacts 38A are electrically connected toperipheral shield contacts 50. Thus, the shield electrodes of some of the field effect transistors are connected to the gate electrode. It should be understood that a gate feed metallization system may be formed over portions ofgate contact portions gate contacts 36A toperipheral shield contacts 48 andgate contacts 38A to peripheral shield interconnects 50. Connecting the shield electrodes to the gate electrode increases the gate-to-drain capacitance ofsemiconductor component 10, which reduces the ringing on the falling edge at switch node 31 (shown inFIG. 1 ) when the field effect transistor is used as, for example, a high side field effect transistor. The number of shield electrodes connected to the gate electrode is selected in accordance with the desired increase in gate-to-drain capacitance.FIG. 2 shows that 20 percent of the shield electrodes are connected to the gate electrode, i.e., one out of five shield electrodes are connected to the gate electrode. This is not a limitation of the present invention. For example, one out of two of the shield electrodes may be connected to the gate electrode, one out of three of the shield electrodes may be connected to the gate electrode, one out of four of the shield electrodes may be connected to the gate electrode, etc. - It should be noted that the present invention is not limited to having one out of N shield electrodes connected to the gate electrode. Alternatively, one or
more trenches 42 may be adjacent to each other such that the number N varies in the same semiconductor die. -
FIG. 3 is a cross-sectional view of asemiconductor component 10 in accordance with an embodiment of the present invention, where the cross-sectional view is taken along section line 3-3 ofFIG. 2 . The cross-sectional view ofsemiconductor component 10 illustrates a portion ofedge region 14 adjacent toside 22. What is shown inFIG. 3 aretrenches semiconductor material 11, wheretrench 21 has sidewalls 71 and afloor 73,trenches 20 have sidewalls 70 andfloors 72, andtrenches 42 have sidewalls 74 andfloors 76. By way of example,semiconductor material 11 is comprised of anepitaxial layer 15 formed on asubstrate layer 13 and has asurface 23. A layer ofdielectric material 80 is formed along sidewalls 70, 71, and 74 and overfloors conductive material 82 is formed ondielectric layer 80 intrenches 20, an electricallyconductive material 82B is formed ondielectric layer 80 intrench 21, and an electricallyconductive material 82A is formed ondielectric layer 80 intrenches 42. In accordance with embodiments,trenches conductive material conductive material 82B vertically fills more oftrench 21 than electricallyconductive materials trenches conductive material 82B is closer to surface 23 than the top of electricallyconductive material 82 and the top of electricallyconductive material 82A. Adielectric material 84 is formed over electricallyconductive material dielectric material 85 is formed on or fromsurface 23. Alternatively, a single dielectric layer may be formed over electricallyconductive material dielectric material conductive material shield electrode 81. Hence electricallyconductive material Gate electrodes 88A are formed overshield electrodes 82 and the portions ofdielectric material 84 overshield electrodes 82, andgate electrodes 88B are formed overshield electrodes 82A and over the portions ofdielectric material 84 that are formed overshield electrodes 82A. Silicide layers 90 are formed fromgate electrodes - A layer of
dielectric material 91 is formed oversilicide layers 90 and over the exposed portions ofdielectric layer 85. Contact openings are formed indielectric material 91 to expose portions ofsilicide layers 90 andelectrical contacts Contacts metal layer 101 is formed to contactelectrical contacts Semiconductor component 10 includes adrain contact structure 108 that is made up of a dopedregion 110, a dopedregion 112, anelectrical contact 116, and adrain metallization system 118.Drain metallization system 118 may also be referred to as adrain metal 118. In accordance with another embodiment, a dopedregion 112 is coupled to dopedregion 110 through asilicide layer 114. A layer of dielectric material (not shown) may be formed on the exposed portions ofdielectric layer 91, onmetal gate feed 101, and ondrain metallization system 118. -
FIG. 4 is a cross-sectional view ofsemiconductor component 10 taken along section line 4-4 ofFIG. 2 . What is shown inFIG. 4 is doped orbody regions 126,body enhancement regions 129,source regions 150, silicide layers 90 and 92,source contacts 134, andsource metallization system 106 during manufacture.Source metallization system 106 may be referred to as asource metal 106 orsource metal layer 106. In addition,FIG. 4 illustratesdrain contact structure 108 that is made up of a dopedregion 110, a dopedregion 112, anelectrical contact 116, and adrain metallization system 118. -
FIG. 5 is a cross-sectional view ofsemiconductor component 10 taken along section line 5-5 ofFIG. 2 . What is shown inFIG. 5 are centralshield contact portions 34 during manufacture. Centralshield contact portions 34 includeelectrical contacts 102A in contact withshield electrodes 82,electrical contacts 102 in contact withshield electrodes 82B, andsource metal 106 in contact withelectrical contacts reference characters 102 to distinguish the electrical contacts of centralshield contact portions 34 from the electrical contacts of peripheralshield contact portions -
FIG. 6 is a cross-section view ofsemiconductor component 10 taken along section line 6-6 ofFIG. 2 . What is shown inFIG. 6 iscontact portion 44 having agate interconnect 36A coupled topolysilicon portion 88B throughsilicide layer 90 andperipheral shield contact 48 coupled topolysilicon portion 82A.Gate interconnect 36A is electrically coupled toperipheral shield contact 48 throughmetal gate feed 101. It should be noted that the shield and gate electrodes may be referred to as electrical conductors and when the electrically conductive material of the shield and gate electrodes is polysilicon, the shield and gate electrodes may be referred to as polysilicon structures, polysilicon electrodes, or the like. -
FIG. 7 is a cross-sectional view of the portion ofsemiconductor component 10 fromFIG. 4 , but at an earlier stage of manufacture.Portions 82 ofshield electrode 81 have been formed intrenches 20,portions 82A ofshield electrode 81 have been formed intrenches 42, andportions 82B ofshield electrode 81 has been formed intrench 21. For the sake of clarity,portions shield electrode 82 are referred to as shield electrodes. A layer ofdielectric material 85 such as, for example, oxide, having a thickness ranging from about 250 Å to about 750 Å is formed from or onsurface 23, from or on the exposed portions ofsidewalls dielectric layer 84. By way of example,dielectric layer 85 has a thickness of about 450 Å. The portions ofdielectric material 85 alongsidewalls oxide stubs 93,gate oxide 85 is grown throughoxide stubs 93. - A layer of
polysilicon 88 having a thickness ranging from about 3,500 Å to about 6,000 Å is formed ondielectric layer 85 and preferably fillstrenches epitaxial layer 15 is N-type, the conductivity type ofpolysilicon layer 88 is preferably N-type.Polysilicon layer 88 is annealed so that it is substantially free of voids. By way of example,polysilicon layer 88 is doped with phosphorus, has a thickness of about 5,000 Å, and is annealed at a temperature of about 900° C. for about 60 minutes.Polysilicon layer 88 is treated with a buffered hydrofluoric acid dip to remove any oxide that may have formed on its surface. -
FIG. 8 is a cross-sectional view ofsemiconductor component 10 fromFIG. 7 , but at a later stage of manufacture.Polysilicon layer 88 is planarized using, for example, a chemical mechanical planarization (“CMP”) process that is selective for the material ofdielectric layer 85, i.e.,dielectric layer 85 serves as an etch stop for the CMP process. Planarization ofpolysilicon layer 88leaves portions 88A intrenches 20,portions 88B intrenches 42, andportion 88C intrench 21. The method for planarizingpolysilicon layer 88 is not a limitation of the present invention. Other suitable planarization techniques include wet etching techniques, dry etching techniques, combinations of wet and dry etching techniques, or the like. A layer of photoresist is patterned overportions polysilicon layer 88 and over portions ofdielectric layer 85. More particularly, the photoresist layer is patterned to form a maskingstructure 130 having a maskingelement 132 that protects a sub-portion ofportion 88C intrench 21 and anopening 133 that exposes portions ofdielectric layer 85 andportions polysilicon layer 88. Maskingstructure 130 is also referred to as a mask or an implant mask. - An impurity material of, for example, P-type conductivity is implanted into the portions of
epitaxial layer 15 that are laterally adjacent totrenches epitaxial layer 15 that are unprotected by maskingelement 132. The implant forms dopedregions 126 which serve as a P-type body implant. The impurity material is also implanted intoportions polysilicon layer 88. Suitable dopants for the P-type implant include boron, indium, or the like. Maskingstructure 130 is removed and dopedregions 126 are annealed. AlthoughFIG. 7 has been described as a continuation of the structure shown inFIG. 4 , it should be noted that it may also be a continuation of the structure shown inFIG. 3 . - Referring now to
FIGS. 9-11 , a layer of photoresist is patterned overpolysilicon portions dielectric layer 85 to form a maskingstructure 140 havingmasking elements 142 andopenings elements 142protect shield electrode 82B, portions ofgate electrodes trench 21, andtermination region 14.Opening 144 exposes portions ofgate electrodes body region 126 that are in the active or device region, i.e., the portions ofgate electrodes FIG. 9 .Polysilicon portions Opening 146 exposes a portion ofdielectric layer 85 overepitaxial layer 15. It should be noted thatFIGS. 9-11 are cross-sections taken at substantially the same time during the manufacture ofsemiconductor component 10, but at different locations. More particularly,FIG. 9 is a cross-sectional view that continues from the cross-sectional view shown inFIG. 8 ;FIG. 10 is a cross-sectional view that continues from the cross-sectional view shown inFIG. 3 ; andFIG. 11 is a cross-sectional view that continues from the cross-sectional view shown inFIG. 5 . Maskingstructure 140 is also referred to as a mask or an implant mask. An impurity material of N-type conductivity is implanted into the portions ofepitaxial layer 15 that are laterally adjacent totrenches 20, i.e., the portions ofepitaxial layer 15 that containdoped regions 126 and that are unprotected by maskingelement 142. The implant forms dopedregions 150 which serve as source regions forsemiconductor component 10 and a dopedregion 110 that serves as a drain contact implant to preclude inversion of surface charge.Doped region 110 is also referred to as a drain ring. Maskingstructure 140 is removed and dopedregions - Referring now to
FIGS. 12 and 13 ,polysilicon portions polysilicon layer 88 that are intrenches surface 23. Preferably,polysilicon portion 88C is substantially completely removed fromtrench 21. By way of example,polysilicon portions dielectric layer 85, i.e., an isotropic etch that etches polysilicon and stops ondielectric layer 85. By way of example, the isotropic etch recessespolysilicon portions surface 23.Portions FIGS. 12 and 13 are cross-sections taken at substantially the same time during the manufacture ofsemiconductor component 10, but at different locations. More particularly,FIG. 12 is a cross-sectional view that continues from the cross-sectional view shown inFIG. 9 andFIG. 13 is a cross-sectional view that continues from the cross-sectional view shown inFIG. 10 . -
Polysilicon portions dielectric layer 85 are cleaned using a dilute or buffered hydrofluoric acid solution. In accordance with one example, the clean removes about 35 Å fromdielectric layer 85 and removes substantially all oxide formed on the top surfaces ofpolysilicon portions gate electrodes 88A,gate contact electrode 88B, and ondielectric layer 85. Preferably, the refractory metal is cobalt having a thickness ranging from about 100 Å to about 1,000 Å. The cobalt that is in contact with polysilicon or silicon is converted to cobalt silicide using a rapid thermal anneal technique. For example, the refractory metal is heated to a temperature ranging from about 350° C. to about 850° C. The heat treatment causes the cobalt to react with the silicon to form cobalt silicide in all regions in which the cobalt contacts polysilicon or silicon. Thus, cobalt silicide layers 90 are formed fromgate electrodes 88A and cobalt silicide layers 90 are formed fromgate contact electrodes 88B. The portions of the cobalt overdielectric layer 85 remain unreacted. After the formation of the cobalt silicide layers 90, any unreacted cobalt is removed using, for example, a selective wet etch. After removal of the unreacted cobalt, the cobalt silicide is annealed again using, for example, a rapid thermal anneal process. It should be understood that the type of silicide is not a limitation of the present invention. For example, other suitable silicides include nickel silicide, platinum silicide, titanium silicide, or the like. - Referring now to
FIGS. 14-16 , a layer ofdielectric material 160 having a thickness ranging from about 3,000 Å to about 12,000 Å is formed onsilicide layers 90 and ondielectric layer 85. It should be noted thatFIGS. 14-16 are cross-sectional views taken at substantially the same time during the manufacture ofsemiconductor component 10, but at different locations. More particularly,FIG. 14 is a cross-sectional view that continues from the cross-sectional view shown inFIG. 12 ;FIG. 15 is a cross-sectional view that continues from the cross-sectional view shown inFIG. 13 ; andFIG. 16 is a cross-sectional view that continues from the cross-sectional view shown inFIG. 11 .Dielectric layer 160 may be comprised of a single layer of dielectric material or a dielectric material comprised of a plurality of sub-layers. In accordance with an embodiment of the present invention,dielectric layer 160 is a multi-layer dielectric material comprising a phosphorus doped layer formed by atmospheric pressure chemical vapor deposition (“APCVD”) and a silane based oxide layer formed by plasma enhanced chemical vapor deposition (“PECVD”). Preferably the phosphorus doped layer is formed onsilicide layers 90 anddielectric layer 85 and has a thickness of about 4,500 Å and the silane based oxide layer is formed on the phosphorus doped layer and has a thickness of about 4,800 Å.Dielectric layer 160 is planarized using, for example, a CMP process. After planarization,dielectric layer 160 preferably has a thickness of about 7,000 Å. Alternately,dielectric layer 160 may be a layer of borophosphosilicate glass (“BPSG”) which can be reflowed by heating. - Still referring to
FIGS. 14-16 , a layer of photoresist is patterned overdielectric layer 160 to form a maskingstructure 162 havingmasking elements 164 andopenings dielectric layer 160. Maskingstructure 162 is also referred to as a mask or an etch mask. - Referring now to
FIGS. 17-19 , the exposed portions ofdielectric layer 160 are anisotropically etched using, for example, a reactive ion etch to formopenings openings 170A expose portions ofsource region 150 andbody region 126 that are adjacent to trench 20 and portions of dopedregion 150 that are betweenadjacent trenches 20;opening 170B exposespolysilicon portion 82B;openings opening 170C exposes a portion ofepitaxial layer 15 including a portion of dopedregion 110; andopenings 170F expose portions ofshield electrodes 82. Preferably, the anisotropic etch that formsopenings 170A-170F is selective tosilicide layer 90, i.e., the etch stops onsilicide layer 90. It should be noted thatFIGS. 17-19 are cross-sectional views taken at substantially the same time during the manufacture ofsemiconductor component 10, but at different locations. More particularly,FIG. 17 is a cross-sectional view that continues from the cross-sectional view shown inFIG. 14 ;FIG. 18 is a cross-sectional view that continues from the cross-sectional view shown inFIG. 15 ; andFIG. 19 is a cross-sectional view that continues from the cross-sectional view shown inFIG. 16 . -
Openings 170A extend intobody region 126, opening 170B extends intoshield electrode 82B, opening 170C extends through dopedregion 110 intoepitaxial layer 15, andopenings 170F extend intoshield electrodes 82, and serve as contact openings. The exposed portions ofepitaxial layer 15 that containdoped regions 150, the exposed portion ofepitaxial layer 15, and the exposed portions ofshield electrodes dielectric material 160. The exposed portion ofsilicide layer 90, the exposed portions ofepitaxial layer 15 that containdoped regions 150, the exposed portion ofepitaxial layer 15, and the exposed portions ofshield electrodes silicide layer 90, the exposed portions ofepitaxial layer 15 that containdoped regions 150, the exposed portion ofepitaxial layer 15, and the exposed portions ofshield electrodes - Referring now to
FIGS. 20-22 , optionally an impurity material of P-type conductivity is implanted into the exposed portions ofepitaxial layer 15 that containdoped regions 126, the exposed portion ofepitaxial layer 15, and the exposed portions ofshield electrodes FIGS. 20-22 are cross-sections taken at substantially the same time during the manufacture ofsemiconductor component 10, but at different locations. More particularly,FIG. 20 is a cross-sectional view that continues from the cross-sectional view shown inFIG. 17 ;FIG. 21 is a cross-sectional view that continues from the cross-sectional view shown inFIG. 18 ; andFIG. 22 is a cross-sectional view that continues from the cross-sectional view shown inFIG. 19 . The implant forms dopedregions 129 in the portions of dopedregion 126 that are exposed byopenings 170A (shown inFIG. 17 ) and dopedregion 112 in the portion ofepitaxial layer 15 that is exposed by opening 170C (shown inFIGS. 17-19 ). Becausepolysilicon portions polysilicon portions doped regions Doped regions shield electrodes - Optionally, silicide layers 92 are formed in the portions of
epitaxial layer 15 exposed byopenings 170A, i.e., the exposed portions ofdoped regions shield electrodes openings silicide layer 114 is formed in the portion ofepitaxial layer 15 exposed by opening 170C. By way of example, silicide layers 92, 96, and 114 are titanium silicide layers. Like silicide layers 90, the type of silicide formed inopenings openings - Preferably, a barrier layer (not shown) is formed in
openings 170A-170F. Suitable materials for the barrier layer include titanium nitride, titanium tungsten, or the like. A conductive layer (not shown) such as, for example, tungsten is deposited to fillopenings contacts openings Contacts - Referring now to
FIGS. 23-25 , ametallization system 192 such as, for example, an aluminum-copper (AlCu) metallization system, is formed in contact withcontacts FIGS. 23-25 are cross-sections taken at substantially the same time during the manufacture ofsemiconductor component 10, but at different locations. More particularly,FIG. 23 is a cross-sectional view that continues from the cross-sectional view shown inFIG. 20 ;FIG. 24 is a cross-sectional view that continues from the cross-sectional view shown inFIG. 21 ; andFIG. 25 is a cross-sectional view that continues from the cross-sectional view shown inFIG. 22 . A layer of photoresist is patterned overmetallization system 192 to form a maskingstructure 194 havingmasking elements 196 andopenings 198 that expose portions ofmetallization system 192. Maskingstructure 194 is also referred to as a mask or an etch mask. - Referring again to
FIGS. 3-5 , the exposed portions of metallization system 192 (shown inFIGS. 23-25 ) are etched to form agate conductor 101 in contact withelectrical contacts source conductor 106 in contact withelectrical contacts side drain conductor 118 in contact withelectrical contacts 116. Maskingstructure 194 is removed. A passivation layer (not shown) may be formed overconductors dielectric material 91. -
FIG. 26 is an enlarged plan view of asemiconductor component 300 in accordance with another embodiment of the present invention. What is shown inFIG. 26 is a portion of a semiconductor die orsemiconductor chip 12 in which agate bond pad 302 is formed.Gate bond pad 302 is shown by broken lines. A peripheralshield electrode trench 21 is formed inedge region 14 and aroundactive area 16. A plurality oftrenches 304 are formed insemiconductor material 11 ofsemiconductor chip 12.Trenches 304 havegate contact portions trenches 304 are shown as having a substantially uniform width, it should be noted thatgate contact portions trenches 304 may be wider than the portions oftrenches 304 betweengate contact portions trenches 304 betweengate contact portions gate contacts gate bond pad 302. It should be noted that the formation ofgate contact portions gate contacts trenches 304. - Referring now to
FIG. 27 , plurality oftrenches 304 havingsidewalls 320 andfloors 322 are formed in a portion ofsemiconductor material 11.Trenches 304 may be formed at the same time and using the same method as used for formingtrenches semiconductor component 10 in embodiments in whichtrenches 304 are included in conjunction with the embodiments ofsemiconductor component 10. It should be understood thatFIG. 27 may be a cross-sectional view of the semiconductor component ofFIG. 26 taken along section line 30-30 orsection line 30A-30A ofFIG. 26 , but at an early stage of manufacture. - Referring now to
FIG. 28 , a layer ofdielectric material 326 is formed over or fromsidewalls 320 and over or fromfloors 322 intrenches 304. Preferably,dielectric material 326 is oxide having a thickness selected to support the breakdown voltage BVdss.Oxide layer 326 may be formed at the same time and using the same method as used for formingdielectric material 80 ofsemiconductor component 10 in embodiments in whichoxide layer 326 is included in conjunction with the embodiments ofsemiconductor component 10. By way of example, the thickness ofoxide layer 326 is at least 750 Angstroms for a breakdown voltage of about 30 volts. A layer ofpolysilicon 328 having a thickness ranging from about 3,500 Å to about 6,000 Å is formed ondielectric layer 326 and preferably fillstrenches 304. When the conductivity type ofepitaxial layer 15 is N-type, the conductivity type ofpolysilicon layer 328 is preferably N-type.Polysilicon layer 328 is annealed so that it is substantially free of voids. By way of example,polysilicon layer 328 is doped with phosphorus, has a thickness of about 5,000 Å, and is annealed at a temperature of about 1,100 Degrees Celsius (° C.) for about 20 minutes.Polysilicon layer 328 may be formed at the same time and using the same method as used for forming the polysilicon ofshield electrodes 82 ofsemiconductor component 10 in embodiments in whichpolysilicon layer 328 included in conjunction with the embodiments ofsemiconductor component 10. - Referring now to
FIG. 29 ,polysilicon layer 328 is planarized using, for example, a CMP process that is selective for the material ofdielectric layer 326, i.e.,dielectric layer 326 serves as an etch stop for the CMP process. Planarization ofpolysilicon layer 328 leavesportions 328A ofpolysilicon layer 328 intrenches 304. The method for planarizingpolysilicon layer 328 is not a limitation of the present invention. Other suitable planarization techniques include wet etching techniques, dry etching techniques, combinations of wet and dry etching techniques, or the like. Optionally, an impurity material of N-type conductivity is implanted into the portions ofepitaxial layer 15 that are laterally adjacent totrenches 304. The implant forms dopedregions 330 which help preventepitaxial layer 15 from becoming fully depleted. The distance to which dopedregions 330 extend intoepitaxial layer 15 is not a limitation of the present invention. Thus,doped regions 330 can extend to a distance that ranges fromsurface 23 tofloors 322 or even deeper. It should be noted thatFIGS. 27-29 are cross sectional views that may be taken along section line 30-30 orsection line 30A-30A ofFIG. 26 . -
FIG. 30 is a cross-sectional view ofsemiconductor component 300 taken along section line 30-30 ofFIG. 26 . What is shown inFIG. 30 ispolysilicon portions 328A recessed using an isotropic etch that selectively removes polysilicon. By way of example,polysilicon portions 328A are recessed using a reactive ion etch. Portions ofdielectric layer 326 oversurface 23 are stripped using an isotropic wetetch leaving portions 326A intrenches 304. A suitable etchant for strippingdielectric layer 326 is a buffered hydrofluoric acid solution. A layer ofdielectric material 336 having a thickness ranging from about 3,000 Å to about 12,000 Å is formed overpolysilicon portions 328A andsurface 23. It should be noted thatdielectric layer 336 is the same interlayer dielectric material as formed over the active region. By way of example,dielectric layer 336 is oxide. Ametallization system 338 such as, for example, an aluminum-copper (AlCu) metallization system, is formed ondielectric layer 336.Layers gate bond pad 302. -
FIG. 30A is a cross-sectional view ofsemiconductor component 300 taken alongsection line 30A-30A ofFIG. 26 . The description ofFIG. 30A is similar toFIG. 30 except thatFIG. 30A also showselectrical contacts 312 that extend throughdielectric layer 336 intoepitaxial layer 15. Suitable materials forelectrical contacts 312 are the same as forelectrical contacts semiconductor component 10. -
FIG. 31 is a cross-sectional view of asemiconductor component 340 in accordance with another embodiment of the present invention.Semiconductor component 340 is similar tosemiconductor component 300 except that dopedregion 330 has been replaced by dopedregion 330A, where dopedregion 330A extends to a region between the floors 332 oftrenches 304 and an interface betweenepitaxial layer 15 andsubstrate layer 13. The cross-sectional view ofFIG. 31 may be taken along section line 30-30 shown inFIG. 26 . -
FIG. 32 is a cross-sectional view of asemiconductor component 350 in accordance with another embodiment of the present invention.Semiconductor component 350 differs fromsemiconductor components 300 and 300A in that dopedregions semiconductor component 350. The cross-sectional view ofFIG. 31 may be taken along section line 30-30 shown inFIG. 26 . -
FIG. 33 is an enlarged plan view of asemiconductor component 400 in accordance with another embodiment of the present invention. What is shown inFIG. 33 is a portion of a semiconductor die orsemiconductor chip 12 in which agate bond pad 402 is formed. Ametal gate feed 406 is formed in anedge region 404 and partially around anactive area 408. A plurality oftrenches 410 are formed insemiconductor material 11 ofsemiconductor chip 12.Trenches 410 are connected together bytrench 21. More particularly, the ends oftrenches 410 are connected to trench 21.Trenches 410 havegate contact portions shield contact portions portion 421 ofmetal gate feed 406, i.e., the portion of metal gate feed 406 that is near the portion ofsemiconductor component 400 opposite fromgate bond pad 402 is shown as extending fromcontact portion 412 to contactportion 414, this is not a limitation of the present invention. For example, portions ofmetal gate feed 406 may be absent from the regions nearshield contact portion 416.Portion 409 oftrenches 410 andcontact portions FIGS. 34-37 . - Referring now to
FIG. 34 , an expanded plan view of a portion ofsemiconductor component 400 is illustrated.Trenches 410 are shown in greater detail compared toFIG. 33 .Trenches 410 extend fromgate contact region 412 togate contact region 414 and includeshield contact portions 416.Gate contact portions shield contact portions 416 oftrenches 410 may be wider than the portions oftrenches 410 betweengate contact portions 412 andshield contact portions 416 and they may be wider than the portions oftrenches 410 betweengate contact portions 414 andshield contact portions 416 to allow for the formation ofgate contact interconnects shield contacts 416A.Gate contacts 412A are electrically connected togate metal feed 420 ingate contact region 412,gate contacts 414A are electrically connected togate metal feed 422 ingate contact region 414, andshield contacts 416A are electrically connected to sourcemetal 426.FIG. 34 illustratesportions metal gate feed 406 andsource metal 426.Portion 420 is overcontact portion 412 that is between adjacent broken lines,portion 422 is overcontact portion 414 that is between adjacent broken lines, and source contact 426 is over the region that is between adjacent broken lines that includescontacts -
FIG. 35 is a cross-sectional view oftrenches 410 taken along section line 35-35 ofFIG. 33 . What is shown inFIG. 35 isshield contacts 416A during manufacture. Adielectric material 430 is formed oversidewalls 426 andfloors 428 oftrenches 410 and shieldelectrodes 432 are formed overdielectric material 430. Adielectric material 434 is formed overshield electrodes 432 and agate dielectric material 433 is formed over portions ofsidewalls 426 and overepitaxial layer 15. A layer ofdielectric material 436 is formed overepitaxial layer 15 and openings (not shown) are formed through portions ofdielectric layer 436 anddielectric material 434 to expose portions ofshield electrodes 432.Shield contacts 416A are formed to contactshield electrodes 432. A shieldelectrode metal layer 446 is formed in contact withshield contacts 416A. Shieldelectrode metal layer 446 may be the same as the source metal layer. Techniques for formingdielectric material 430,shield electrodes 432,dielectric material shield contacts 416A, and shieldelectrode metal layer 446 have been described above. In accordance with the example shown inFIGS. 33-37 ,shield contacts 416A are formed to contact a portion of ashield electrode 432 every other trench. However, this is not a limitation of the present invention.Shield contacts 416A may be formed such that ashield contact 416A is made to contact a portion of a shield electrode in every trench, orshield contacts 416A may be formed such that ashield contact 416A is made to contact ashield electrode 432 in one of N trenches, or ashield contact 416A is made to contact ashield electrode 432 in a variable number of trenches.FIG. 35 illustrates an embodiment in which N is 2 such that ashield contact 416A is made to contact ashield electrode 432 in one of two trenches. It should be noted thatshield electrodes 432 intrenches 410 are coupled together by the shield electrode portions formed intrench 21. -
FIG. 36 is a cross-sectional view oftrenches 410 taken along section line 36-36 ofFIG. 33 . What is shown inFIG. 36 isgate contacts 412A during manufacture. It should be noted that the formation ofgate contacts 414A is the same as the formation ofgate contacts 412A.Dielectric material 430 is formed over thesidewalls 426 andfloors 428 oftrenches 410 and shieldelectrodes 432 are formed overdielectric material 430. Adielectric material 434 is formed overshield electrodes 432 and agate dielectric material 433 is formed over portions ofsidewalls 426 and overepitaxial layer 15.Gate conductors 450 are formed overdielectric material 434 andsilicide layers 452 are formed from portions ofgate conductors 450. Openings (not shown) are formed through portions ofdielectric layer 436 to exposesilicide layers 452 andshield electrode 432.Gate contacts 412A are formed to contact silicide layers 452 andshield contacts 414A are formed to contactshield contact 432. Ametal gate feed 420 is formed in contact withgate contacts 412A. Techniques for formingdielectric material 430,gate electrodes 450,dielectric material gate contacts 412 A shield contacts 414A, andmetal gate interconnect 420 have been described above. -
FIG. 37 is a cross-sectional view oftrenches 410 taken along section line 37-37 ofFIG. 33 . A gatepad metallization system 464 is formed over a portion ofdielectric layer 436. By way of example, gatepad metallization system 464 is formed from the same layer of electrically conductive material asmetal gate interconnect 420. -
FIG. 38 is an enlarged plan view of asemiconductor component 10A in accordance with another embodiment of the present invention. What is shown inFIG. 38 is a portion of a semiconductor die orsemiconductor chip 12 havingedge regions 14 and acenter region 16.Semiconductor component 10A is similar tosemiconductor component 10 illustrated and described with reference toFIGS. 2-25 , except that in one portion ofsemiconductor chip 12 twotrenches 42 are adjacent to each other and in another portion ofsemiconductor chip 12 threetrenches 42 are adjacent to each other. Except for this difference, the description ofsemiconductor component 10A is similar to that ofsemiconductor component 10. It should be noted that the number oftrenches 42 that are adjacent to each other and the number oftrenches 20 betweentrenches 42 are not limitations of the present invention. - Although certain preferred embodiments and methods have been disclosed herein, it will be apparent from the foregoing disclosure to those skilled in the art that variations and modifications of such embodiments and methods may be made without departing from the spirit and scope of the invention. For example, a semiconductor component may be comprised of
semiconductor component semiconductor component 10 andsemiconductor component 300; or a semiconductor component may be comprised ofsemiconductor component semiconductor component
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US20130248992A1 (en) * | 2012-03-20 | 2013-09-26 | Balaji Padmanabhan | Electronic device including a trench and a conductive structure therein having a contact within a schottky region and a process of forming the same |
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