US20110253970A1 - Transparent nanowire transistors and methods for fabricating same - Google Patents
Transparent nanowire transistors and methods for fabricating same Download PDFInfo
- Publication number
- US20110253970A1 US20110253970A1 US13/065,396 US201113065396A US2011253970A1 US 20110253970 A1 US20110253970 A1 US 20110253970A1 US 201113065396 A US201113065396 A US 201113065396A US 2011253970 A1 US2011253970 A1 US 2011253970A1
- Authority
- US
- United States
- Prior art keywords
- nanowires
- gate
- transparent
- layer
- oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000002070 nanowire Substances 0.000 title claims abstract description 138
- 238000000034 method Methods 0.000 title claims description 23
- 239000000758 substrate Substances 0.000 claims abstract description 50
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 110
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 80
- 239000011787 zinc oxide Substances 0.000 claims description 40
- -1 siloxane moiety Chemical group 0.000 claims description 30
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims description 26
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 22
- 238000011282 treatment Methods 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 18
- 239000011521 glass Substances 0.000 claims description 15
- 229920003023 plastic Polymers 0.000 claims description 14
- 239000011159 matrix material Substances 0.000 claims description 13
- 239000004033 plastic Substances 0.000 claims description 13
- 150000004706 metal oxides Chemical class 0.000 claims description 11
- 239000000203 mixture Substances 0.000 claims description 11
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 claims description 10
- 229910044991 metal oxide Inorganic materials 0.000 claims description 10
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 9
- 230000008878 coupling Effects 0.000 claims description 9
- 238000010168 coupling process Methods 0.000 claims description 9
- 238000005859 coupling reaction Methods 0.000 claims description 9
- 229910052733 gallium Inorganic materials 0.000 claims description 9
- 239000007859 condensation product Substances 0.000 claims description 8
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 7
- 125000001181 organosilyl group Chemical group [SiH3]* 0.000 claims description 7
- 229910003437 indium oxide Inorganic materials 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 239000000725 suspension Substances 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 5
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 4
- 238000006482 condensation reaction Methods 0.000 claims description 3
- HRHKULZDDYWVBE-UHFFFAOYSA-N indium;oxozinc;tin Chemical compound [In].[Sn].[Zn]=O HRHKULZDDYWVBE-UHFFFAOYSA-N 0.000 claims description 3
- QHGNHLZPVBIIPX-UHFFFAOYSA-N tin(ii) oxide Chemical class [Sn]=O QHGNHLZPVBIIPX-UHFFFAOYSA-N 0.000 claims description 3
- 230000037230 mobility Effects 0.000 abstract description 20
- 230000005669 field effect Effects 0.000 abstract description 6
- 239000011368 organic material Substances 0.000 abstract description 2
- 239000011147 inorganic material Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 74
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 33
- 150000002500 ions Chemical class 0.000 description 31
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 20
- 239000012212 insulator Substances 0.000 description 19
- 229910052681 coesite Inorganic materials 0.000 description 18
- 229910052906 cristobalite Inorganic materials 0.000 description 18
- 239000000377 silicon dioxide Substances 0.000 description 18
- 229910052682 stishovite Inorganic materials 0.000 description 18
- 229910052905 tridymite Inorganic materials 0.000 description 18
- 229920001621 AMOLED Polymers 0.000 description 15
- 238000000869 ion-assisted deposition Methods 0.000 description 14
- 230000003287 optical effect Effects 0.000 description 13
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 12
- 125000000217 alkyl group Chemical group 0.000 description 9
- 239000013078 crystal Substances 0.000 description 9
- 238000000231 atomic layer deposition Methods 0.000 description 8
- 230000005540 biological transmission Effects 0.000 description 7
- 238000000151 deposition Methods 0.000 description 7
- 238000000349 field-emission scanning electron micrograph Methods 0.000 description 7
- 229920000139 polyethylene terephthalate Polymers 0.000 description 7
- 239000005020 polyethylene terephthalate Substances 0.000 description 7
- 239000010409 thin film Substances 0.000 description 7
- 239000004215 Carbon black (E152) Substances 0.000 description 6
- 238000003491 array Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 230000006870 function Effects 0.000 description 6
- 229930195733 hydrocarbon Natural products 0.000 description 6
- 150000002430 hydrocarbons Chemical class 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 238000012512 characterization method Methods 0.000 description 5
- 125000001188 haloalkyl group Chemical group 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 150000002739 metals Chemical class 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 241000669326 Selenaspidus articulatus Species 0.000 description 4
- 238000013459 approach Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 241000155258 Plebejus glandon Species 0.000 description 3
- 125000003545 alkoxy group Chemical group 0.000 description 3
- 125000003118 aryl group Chemical group 0.000 description 3
- 125000000751 azo group Chemical group [*]N=N[*] 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 238000011109 contamination Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 125000005842 heteroatom Chemical group 0.000 description 3
- 238000004020 luminiscence type Methods 0.000 description 3
- 238000000255 optical extinction spectrum Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 125000002924 primary amino group Chemical group [H]N([H])* 0.000 description 3
- 238000001338 self-assembly Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 238000003786 synthesis reaction Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 238000000411 transmission spectrum Methods 0.000 description 3
- 238000002525 ultrasonication Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910018557 Si O Inorganic materials 0.000 description 2
- 229910008062 Si-SiO2 Inorganic materials 0.000 description 2
- 229910006403 Si—SiO2 Inorganic materials 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000006664 bond formation reaction Methods 0.000 description 2
- 229910052794 bromium Inorganic materials 0.000 description 2
- 125000000484 butyl group Chemical group [H]C([*])([H])C([H])([H])C([H])([H])C([H])([H])[H] 0.000 description 2
- 125000004432 carbon atom Chemical group C* 0.000 description 2
- 229910052800 carbon group element Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 238000009833 condensation Methods 0.000 description 2
- 230000005494 condensation Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 125000001495 ethyl group Chemical group [H]C([H])([H])C([H])([H])* 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 229920002457 flexible plastic Polymers 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- 150000004820 halides Chemical class 0.000 description 2
- 125000005843 halogen group Chemical group 0.000 description 2
- 125000001183 hydrocarbyl group Chemical group 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 229910052740 iodine Inorganic materials 0.000 description 2
- 125000000959 isobutyl group Chemical group [H]C([H])([H])C([H])(C([H])([H])[H])C([H])([H])* 0.000 description 2
- 125000001449 isopropyl group Chemical group [H]C([H])([H])C([H])(*)C([H])([H])[H] 0.000 description 2
- 238000000608 laser ablation Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 2
- 125000004108 n-butyl group Chemical group [H]C([H])([H])C([H])([H])C([H])([H])C([H])([H])* 0.000 description 2
- 125000004123 n-propyl group Chemical group [H]C([H])([H])C([H])([H])C([H])([H])* 0.000 description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 125000005004 perfluoroethyl group Chemical group FC(F)(F)C(F)(F)* 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 125000001436 propyl group Chemical group [H]C([*])([H])C([H])([H])C([H])([H])[H] 0.000 description 2
- 238000004549 pulsed laser deposition Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000001878 scanning electron micrograph Methods 0.000 description 2
- 125000002914 sec-butyl group Chemical group [H]C([H])([H])C([H])([H])C([H])(*)C([H])([H])[H] 0.000 description 2
- 239000013545 self-assembled monolayer Substances 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 2
- 125000000999 tert-butyl group Chemical group [H]C([H])([H])C(*)(C([H])([H])[H])C([H])([H])[H] 0.000 description 2
- 238000002207 thermal evaporation Methods 0.000 description 2
- CLXMTJZPFVPWAX-UHFFFAOYSA-N trichloro-[dichloro(trichlorosilyloxy)silyl]oxysilane Chemical compound Cl[Si](Cl)(Cl)O[Si](Cl)(Cl)O[Si](Cl)(Cl)Cl CLXMTJZPFVPWAX-UHFFFAOYSA-N 0.000 description 2
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 2
- 125000003837 (C1-C20) alkyl group Chemical group 0.000 description 1
- YVXDRFYHWWPSOA-BQYQJAHWSA-N 1-methyl-4-[(e)-2-phenylethenyl]pyridin-1-ium Chemical group C1=C[N+](C)=CC=C1\C=C\C1=CC=CC=C1 YVXDRFYHWWPSOA-BQYQJAHWSA-N 0.000 description 1
- YSCNMFDFYJUPEF-OWOJBTEDSA-N 4,4'-diisothiocyano-trans-stilbene-2,2'-disulfonic acid Chemical compound OS(=O)(=O)C1=CC(N=C=S)=CC=C1\C=C\C1=CC=C(N=C=S)C=C1S(O)(=O)=O YSCNMFDFYJUPEF-OWOJBTEDSA-N 0.000 description 1
- JNCMHMUGTWEVOZ-UHFFFAOYSA-N F[CH]F Chemical compound F[CH]F JNCMHMUGTWEVOZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000005355 Hall effect Effects 0.000 description 1
- 239000004793 Polystyrene Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 229910007541 Zn O Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 125000003277 amino group Chemical group 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000002041 carbon nanotube Substances 0.000 description 1
- 229910021393 carbon nanotube Inorganic materials 0.000 description 1
- 239000002238 carbon nanotube film Substances 0.000 description 1
- 125000003178 carboxy group Chemical group [H]OC(*)=O 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- WBLIXGSTEMXDSM-UHFFFAOYSA-N chloromethane Chemical compound Cl[CH2] WBLIXGSTEMXDSM-UHFFFAOYSA-N 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 229920006037 cross link polymer Polymers 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- ZJULYDCRWUEPTK-UHFFFAOYSA-N dichloromethyl Chemical compound Cl[CH]Cl ZJULYDCRWUEPTK-UHFFFAOYSA-N 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- GNTDGMZSJNCJKK-UHFFFAOYSA-N divanadium pentaoxide Chemical compound O=[V](=O)O[V](=O)=O GNTDGMZSJNCJKK-UHFFFAOYSA-N 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- VUWZPRWSIVNGKG-UHFFFAOYSA-N fluoromethane Chemical compound F[CH2] VUWZPRWSIVNGKG-UHFFFAOYSA-N 0.000 description 1
- 229910021482 group 13 metal Inorganic materials 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 125000001072 heteroaryl group Chemical group 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 1
- 238000002329 infrared spectrum Methods 0.000 description 1
- 229910052809 inorganic oxide Inorganic materials 0.000 description 1
- 125000001972 isopentyl group Chemical group [H]C([H])([H])C([H])(C([H])([H])[H])C([H])([H])C([H])([H])* 0.000 description 1
- 125000003253 isopropoxy group Chemical group [H]C([H])([H])C([H])(O*)C([H])([H])[H] 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- GRVDJDISBSALJP-UHFFFAOYSA-N methyloxidanyl Chemical compound [O]C GRVDJDISBSALJP-UHFFFAOYSA-N 0.000 description 1
- 125000000740 n-pentyl group Chemical group [H]C([H])([H])C([H])([H])C([H])([H])C([H])([H])C([H])([H])* 0.000 description 1
- 125000003506 n-propoxy group Chemical group [H]C([H])([H])C([H])([H])C([H])([H])O* 0.000 description 1
- 125000001971 neopentyl group Chemical group [H]C([*])([H])C(C([H])([H])[H])(C([H])([H])[H])C([H])([H])[H] 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 125000001147 pentyl group Chemical group C(CCCC)* 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000011112 polyethylene naphthalate Substances 0.000 description 1
- 229920002223 polystyrene Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 229930195734 saturated hydrocarbon Natural products 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
- ZBZJXHCVGLJWFG-UHFFFAOYSA-N trichloromethyl(.) Chemical compound Cl[C](Cl)Cl ZBZJXHCVGLJWFG-UHFFFAOYSA-N 0.000 description 1
- 125000002023 trifluoromethyl group Chemical group FC(F)(F)* 0.000 description 1
- 238000002371 ultraviolet--visible spectrum Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Definitions
- transistor performance metrics such as high on-current (I on ), high on/off current ratio (I on /I off ), high field-effect mobility ( ⁇ eff ), steep subthreshold slope (S), and small threshold voltage (V T ) variation during transistor operation are required to realize commercially viable logic circuits and display devices.
- Nanowire transistors i.e., transistors incorporating semiconducting nanowires as charge transporting channel materials
- TFTs thin film transistors
- the use of pre-formed nanowires also allows low-temperature device processing, which is essential for applications such as circuits fabricated on plastic substrates. While there have been several recent reports of transparent transistors fabricated with ZnO, SnO 2 , In 2 O 3 or other semiconducting oxide thin films, or with carbon nanotube networks as the active channel layers and opaque source and drain metals, or with carbon nanotube films and transparent source/drain electrodes (see e.g., Carcia, P. F.
- the present teachings provide nanowire-based transistors and circuits that can comprise one or more semiconducting nanowires as the channel material.
- the nanowire transistor structures of the present teachings can be fully transparent and comprise components made from various transparent materials.
- nanowire transistors described herein can comprise one or more non-transparent nanowires (e.g., without limitation, nanowires made from Group 14 elements such as Si, Ge, and alloys thereof, one or more Group 13-15 elements such as GaAs, GaN, and InP, and one or more Group 12-16 elements such as CdS and CdSe) as well as transparent oxide nanowires (e.g., without limitation, ZnO, In 2 O 3 , and SnO 2 nanowires), and transparent gate and source/drain electrodes.
- the nanowire transistors of the present teachings can exhibit high performance n-type transistor characteristics with satisfactory optical transparency.
- the nanowire transistors of the present teachings can be attractive as pixel switching and driving transistors in active-matrix organic light-emitting diode (AMOLED) displays, and can supply sufficient current to drive pixels employing reported electroluminescent organic materials.
- AMOLED active-matrix organic light-emitting diode
- the transparency of the drive circuitry can enable significant increases in aperture ratio in active-matrix arrays, which can lead to higher display brightness and decreased power consumption.
- the high mobility of the nanowire channel materials also can allow faster switching of the transistor circuits, which can allow circuit approaches such as direct digital drive of display elements.
- the nanowire transistor devices of the present teachings can comprise one or more semiconducting nanowires extending between a source electrode and a drain electrode, and a gate dielectric in contact with the one or more semiconducting nanowires.
- the device can include a single semiconducting nanowire as the channel material.
- the device can include a plurality of semiconducting nanowires to fulfill larger current carrying needs.
- the one or more semiconducting nanowires can be prepared from a Group 14 element such as, without limitation, Si and Ge.
- transparent semiconducting nanowires prepared from transparent metal oxides such as, without limitation, ZnO, In 2 O 3 , and SnO 2 , can be used.
- the gate dielectric can be an inorganic layer of one or more transparent metal oxides.
- the gate dielectric can be a Group 3 metal oxide, a Group 5 metal oxide, or a Group 13 metal oxide such as, but not limited to, aluminum oxide (Al 2 O 3 ), yttrium oxide (Y 2 O 3 ), tantalum pentoxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), and vanadium oxide (V 2 O 5 ).
- Such metal oxides can optionally include one or more dopants.
- the oxide gate dielectric can be deposited by various techniques known in the art including, without limitation, thermal evaporation, sputtering, metalorganic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), ion-assisted deposition (IAD), and pulsed-laser deposition (PLD).
- MOCVD metalorganic chemical vapor deposition
- ALD atomic layer deposition
- IAD ion-assisted deposition
- PLD pulsed-laser deposition
- the gate dielectric can be an organic multi-layer composition.
- This multi-layer composition can comprise periodically alternating layers of one or more layers that include a polarizable moiety, and one or more layers that can comprise a silyl or siloxane moiety.
- the polarizable moiety e.g., without limitation, a ⁇ -polarizable moiety
- the siloxane moiety can comprise oligomeric or polymeric moieties having —Si—O— bonds.
- the sigma moiety can comprise a hydrocarbon as described in more detail below.
- the polarizable moiety can be a moiety having at least one of a dipole moment, an electron releasing moiety, an electron withdrawing moiety, a combination of such moieties, a zwitterion and a net charge.
- the polarizable moiety can be a non-linear optical (NLO) chromophore.
- the chromophore can comprise a ⁇ -conjugated system, which can comprise a system of atoms covalently bonded with alternating single and multiple (e.g., double) bonds (e.g., C ⁇ C—C ⁇ C—C and C ⁇ C—N ⁇ N—C).
- the ⁇ -conjugated system can comprise one or more heteroatoms such as, but not limited to, nitrogen (N), oxygen (O), and sulfur (S).
- the ⁇ -conjugated system can comprise one or more aromatic rings (aryl or heteroaryl) linked by conjugated hydrocarbon chains.
- the aromatic rings can be linked by conjugated chains that include heteroatoms and heteroatom-containing groups (e.g., azo groups [—N ⁇ N—]).
- the polarizable moiety can be a chromophore that comprises a stilbazolium group.
- polarizable moieties that can be used according to the present teachings are described in U.S. Pat. No. 6,855,274, in particular the NLO structures of FIGS. 1-2 , 11 , and 13 - 15 thereof; U.S. Pat. No. 6,549,685, in particular the NLO structures of FIGS. 2-3 thereof; and U.S. Pat. No. 5,156,918, in particular the NLO structures of FIGS. 4-5 thereof, each with reference to the corresponding specification regarding alternate embodiments, synthesis, and characterization, and each of which is incorporated by reference herein in its entirety.
- the polarizable moiety can comprise a stilbazonium group.
- At least some of the alternating layers can be coupled to an adjacent layer by a coupling layer that comprises a siloxane matrix.
- the coupling can be performed via a condensation reaction or chemisorption using known silicon chemistry.
- two layers including the polarizable moiety can be coupled to each other by a coupling layer that comprises a siloxane matrix, resulting in a three-layered composition that includes alternating layers of a first layer including a polarizable moiety, a coupling layer that includes a siloxane matrix, and a second layer that includes a polarizable moiety.
- One or more layers including a polarizable moiety also can be crosslinked by a siloxane matrix.
- the alternating layers can be coupled or covalently bonded to one another or the siloxane matrix via a condensation reaction.
- the three-layer composition described above can include condensation products of a silane-substituted stilbazolium compound (e.g., 4-[[(4-(N,N-bis((hydroxy)ethyl)amino]-phenyl]azo]-1-(4-trichlorosilyl)benzyl-pyridinium iodide, or 4-[[(4-(N,N-bis((hydroxyl)ethyl)amino]-phenyl]azo]-1-(4-dichloroiodosilyl)benzyl-pyridinium iodide) and a trisiloxane compound (e.g., without limitation, octachlorotrisiloxane or other similar compounds including Si—O bonding sequence with hydrolyzable groups).
- the multi-layer composition also can include a hydrocarbon layer (i.e., a sigma moiety).
- a hydrocarbon layer can comprise a C 1 - about C 20 alkyl group or a C 1 - about C 20 haloalkyl group.
- Such a hydrocarbon layer can be coupled to a coupling layer that comprises a siloxane matrix, or it can be coupled to a layer comprising a polarizable moiety directly or via a coupling layer that comprises a siloxane matrix as described above.
- the alkyl or haloalkyl group can be functionalized with silyl moieties having hydrolyzable groups.
- the alternating layers can include a condensation product of a bis(silyl)- about C 4 to about C 20 alkyl compound (e.g., without limitation, Cl 3 Si(CH2) n SiCl 3 , (CH 3 O) 3 Si(CH 2 ) n Si(OCH 3 ) 3 , and (Me 2 N) 3 Si(CH 2 ) n Si(NMe 2 ) 3 , where n can be 4, 5, 6, 7, 8, 9, or 10) and a trisiloxane compound (e.g., without limitation, octachlorotrisiloxane or other similar compounds including Si—O bonding sequence with hydrolyzable groups).
- a bis(silyl)- about C 4 to about C 20 alkyl compound e.g., without limitation, Cl 3 Si(CH2) n SiCl 3 , (CH 3 O) 3 Si(CH 2 ) n Si(OCH 3 ) 3 , and (Me 2 N) 3 Si(CH 2 ) n Si
- Such bis-silylated compounds are hydrolyzable to a degree at least partially sufficient for substrate sorption or condensation or intermolecular crosslinking via siloxane bond formation under the processing or fabrication conditions employed.
- the polarizable moiety can be derivatized to include similar silyl hydrolyzable groups, to allow bond formation with the siloxane coupling layer and/or the hydrocarbon layer.
- the hydrocarbon layers and the layers comprising a polarizable moiety can be individually self-assembled monolayers. Synthesis of such self-assembled nanodielectric (SAND) materials are more fully described in Yoon, M-H. et al., PNAS, 102 (13): 4678-4682 (2005), which is incorporated by reference herein in its entirety.
- the gate dielectric can be a polymer.
- the gate dielectric can be a polymer such as, without limitation, polyhydroxystyrene and polystyrene.
- the gate dielectric can be a crosslinked polymer, examples of which include, but are not limited to, the various crosslinked polymeric dielectric materials described in U.S. patent application Ser. Nos. 11/315,076, 60/816,952, and 60/861,308, each of which is incorporated by reference herein in its entirety.
- the source electrode and the drain electrode can be prepared from various transparent conductive oxides. Examples include, without limitation, indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide, zinc oxide, zinc indium tin oxide (ZITO), and other similar optionally doped metal oxides (e.g., fluorinated tin oxide, gallium zinc oxide (GZO), gallium indium oxide (GIO) and gallium indium tin oxide (GITO)).
- ITO indium tin oxide
- IZO indium zinc oxide
- ZITO zinc indium tin oxide
- metal oxides e.g., fluorinated tin oxide, gallium zinc oxide (GZO), gallium indium oxide (GIO) and gallium indium tin oxide (GITO)
- a nanowire transistor device of the present teachings also can, without limitation, comprise a gate electrode prepared from one or more of the transparent conductive oxides described above.
- the gate dielectric can be deposited on a transparent substrate.
- suitable substrates include but are not limited to glass and various transparent plastic materials (both rigid and flexible).
- flexible plastic substrates include, but are not limited to, polyethylene terephthalate (PET) and polyethylene naphthalate (PEN).
- the present teachings further provide methods for fabricating a nanowire transistor device.
- Such a method can comprise applying a gate electrode layer on a substrate, applying a dielectric layer on the gate electrode layer, applying one or more semiconducting nanowires on the dielectric layer, and applying a source electrode and a drain electrode on the dielectric layer, wherein the application of the gate electrode layer, the application of the dielectric layer, the application of the one or more semiconducting nanowires, and the application of the source electrode and the drain electrode are conducted at a temperature less than about 100° C. (e.g., at or near room temperature).
- Each of the gate electrode layer, the dielectric layer, the source electrode, the drain electrode, and the substrate can be transparent (for example, by using the various suitable materials disclosed herein), and one or more semiconducting nanowires can extend between the source electrode and the drain electrode.
- the application of the one or more semiconducting nanowires can involve dispersing a suspension that includes one or more semiconducting nanowires on the dielectric layer.
- the application of the dielectric layer can comprise forming at least one condensation product of a silane-substituted stilbazoium compound and a trisiloxane compound, and optionally, at least one condensation product of a bis(silyl)- about C 4 to about C 20 alkyl compound and a trisiloxane compound.
- the resulting nanowire transistor device can be subjected to ozone treatment to further improve its device performance, for example, to increase its field effect mobility.
- FIG. 1 a is a cross-sectional view of an embodiment of a nanowire transistor (NWT) device according to the present teachings.
- the illustrated device consists of a SiO 2 buffer layer (500 nm), a patterned IZO (In—Zn—O) gate electrode (120 nm), an atomic layer deposition (ALD)-deposited Al 2 O 3 gate insulator (18 nm), a single In 2 O 3 nanowire (D ⁇ 20 nm) or ZnO nanowire (D ⁇ 120 nm) for the active channel, and ITO for the source/drain electrodes (120 nm).
- Scale bar 100 ⁇ m.
- FIG. 1 b is a top-view field-emission scanning electron microscopic (FE-SEM) image of an NWT device analogous to the one illustrated in FIG. 1 a .
- Scale bar 100 ⁇ m.
- FIG. 1 c is a top-view SEM image of a single In 2 O 3 nanowire region (D/L ⁇ 20 nm/1.80 ⁇ m) of an NWT device analogous to the one illustrated in FIG. 1 a .
- Scale bar 1.5 ⁇ m.
- FIG. 1 d is a top-view SEM image of a single ZnO nanowire region (D/L ⁇ 120 nm/1.66 ⁇ m) of an NWT device analogous to the one illustrated in FIG. 1 a .
- Scale bar 1.5 ⁇ m.
- FIG. 2 a shows the gate leakage current (B: black dots) and the drain leakage current (A: red dots) of a representative In 2 O 3 NWT device according to the present teachings.
- the inset shows the bias configurations.
- Arrows indicate appropriate axis. Data points are shown for the device before (black dots, 1) and after (red solid line, 2) two minutes of ozone treatment.
- Black, red, green and blue (square, circular, up and down triangle) data points correspond to 1st, 2 nd ,3 rd and 4 th sweeps. The time between sweeps is ⁇ 1 second.
- the bias sweep rate (dV g /d t ) is 2 V/sec.
- Blue (1), red (2), and green (3) data points correspond to linear-scale I ds -V gs , log-scale I ds -V gs and ⁇ eff Arrows indicate appropriate axis.
- FIG. 3 b shows the Ids-Vds characteristics of a representative In2O3 NWT device analogous to the one illustrated in FIG. 1 a .
- Blue (1), red (2), and green (3) data points correspond to linear-scale I ds -V gs , log-scale I ds -V gs and ⁇ eff . Arrows indicate appropriate axis.
- FIG. 3 d shows the I ds -V ds characteristics of a representative ZnO NWT device analogous to the one illustrated in FIG. 1 a .
- FIG. 4 shows the optical transmission spectra for regions containing an In 2 O 3 NWT or a ZnO NWT according to the present teachings on a glass substrate (ITO (source/drain)/In 2 O 3 or ZnO nanowires/Al 2 O 3 (dielectric)/IZO (gate)/SiO 2 /glass). Blue and red lines correspond to In 2 O 3 and ZnO NWTs, respectively.
- the inset shows a photographic image of a glass substrate having 23,000 In 2 O 3 NWT devices deposited on its surface, with text on an underlying opaque layer clearly visible.
- FIG. 5 a is a cross-sectional view of a fully transparent and flexible NWT device according to the present teachings.
- the illustrated device consists of a plastic substrate, a patterned ITO gate electrode (120 nm), an ALD-deposited Al 2 O 3 gate insulator (50 nm), a single In 2 O 3 nanowire (D/L ⁇ 20 nm/1.79 ⁇ m) for the active channel, and ITO for the source/drain electrodes (120 nm).
- FIG. 5 b is a photographic image of arrays of representative In 2 O 3 NWTs deposited on a plastic substrate, showing the optical clarity and mechanical flexibility of the NWTs.
- FIG. 5 c shows the optical transmission spectrum of one of the transistor array regions containing In 2 O 3 NWTs on the plastic substrate (ITO(S/D)/In 2 O 3 NWs/Al 2 O 3 /ITO(G)/plastic substrate) shown in FIG. 5 b.
- Blue (1), red (2), and green (3) data points correspond to linear-scale I ds -V gs , log-scale I ds -V gs and ⁇ eff . Arrows indicate appropriate axis.
- FIG. 6 a is a cross-sectional view of another embodiment of an NWT device according to the present teachings, specifically, one incorporating self-assembled nanodielectrics (SAND) as the gate insulator.
- SAND self-assembled nanodielectrics
- FIG. 6 b is a top-view FE-SEM image of a representative device having the structure illustrated in FIG. 6 a .
- Scale bar 1.5 ⁇ m.
- V of a representative In 2 O 3 NWT having the structure illustrated in FIG. 6 a .
- Green (1), red (2) and blue (3) data points corresponding to linear-scale I ds -V gs , log-scale I ds -V gs and field effect mobility.
- FIG. 7 b shows the I ds -V ds characteristics of a representative In 2 O 3 NWT having the structure illustrated in FIG. 6 a.
- FIG. 8 a shows the transconductance (g m ) at 5 V g of a representative In 2 O 3 NWT having the structure illustrated in FIG. 6 a.
- FIG. 8 b shows the channel conductance (g d ) from 0.0 V d to 1.8 V d of a representative In 2 O 3 NWT having the structure illustrated in FIG. 6 a.
- FIG. 9 a shows the top and cross-sectional pixel structure of a drive transistor in a NW-AMOLED array.
- each NWT in the circuit structures consists of a SiO 2 buffer layer (200 nm), a patterned ITO gate electrode (100 nm), a SAND gate dielectric (24 nm), multiple In 2 O 3 nanowires for the active channel, ITO for the S-D electrodes (100 nm), and a SiO 2 passivation layer (200 nm).
- the ITO pad on the right serves as the cathode for the organic light-emitting diode (OLED).
- FIG. 9 b is a top-view FE-SEM image of several 54 ⁇ 176 ⁇ m pixels within a 2 ⁇ 2 mm NWT array layout (rectangles with rounded ends), along with control transistors.
- FIG. 9 c is a schematic for a circuit as shown in FIG. 9 a for a single pixel, consisting of 1 switching transistor (T 1 ), 2 driving transistors (T 2 and T 3 ) and 1 storage capacitor.
- the bias condition to operate transistor circuit (2 V on scan line for fully turn-on, varying 0 V to 4 V on data line, and 5 V on V dd line).
- FIG. 9 d is an FE-SEM image of a representative region within an NWT transistor channel, showing multiple In 2 O 3 nanowires connected between S-D electrodes.
- the diameter of a nanowire and the channel length between S-D electrodes of the device are ⁇ 50 nm and ⁇ 1.5 ⁇ m, respectively. Scale bar: 1.5 ⁇ m.
- FIG. 10 b shows the I ds -V ds characteristics for the representative device, with V gs varying from 0.0 V to 3.0 V in 0.5 V steps.
- FIG. 10 c shows the output current-voltage characteristics for a single-pixel circuit consisting of one switching transistor and two driving transistors (I ds versus V ds for the parallel combination of T 2 and T 3 ) for various steps in “data” line voltage (2 V on scan line to fully turn-on T 1 , 0.0 V to 4.0 V on data line in 0.5 V steps).
- FIG. 10 d shows the I on , I off , V T and S values of 10 representative NWT devices, with red lines indicating the average values for the respective parameters.
- FIG. 11 shows the optical transmission spectrum for representative regions within an NWT channel of a 2 ⁇ 2 mm NW-AMOLED display element (SiO 2 (passivation)/ITO (source/drain)/In 2 O 3 (active channel)/SAND (gate insulator)/ITO (gate)).
- the inset shows an image of a fully transparent NW-AMOLED substrate consisting of three 2 ⁇ 2 mm transistor arrays, 340 unit pixels, 80 test devices, 6 alignment marks, 20 test patterns, and contact pads.
- FIG. 12 a is a cross-sectional view of yet another embodiment of an NWT device structure according to the present teachings.
- this embodiment consists of a SiO 2 buffer layer, a patterned ITO gate electrode (120 nm), a SAND gate insulator (15 nm), and a single SnO 2 nanowire.
- the NWT can be partially (e.g., Al) or fully transparent (e.g., ITO).
- FIG. 12 c shows typical output plots for a representative SnO 2 NWT device having the structure illustrated in FIG. 12 a.
- FIG. 13 a is a cross-sectional view of yet another embodiment of an NWT device structure according to the present teachings.
- this embodiment consists of a SiO 2 buffer layer, a patterned ITO gate electrode (120 nm), a SAND gate insulator (15 nm), and a single Ge nanowire.
- the NWT can be partially (e.g., Al) or fully transparent (e.g., ITO).
- FIG. 13 b shows typical output plots for a p-type Ge NWT device having the structure illustrated in FIG. 13 a.
- FIG. 13 d shows typical output plots for an n-type Ge NWT device having the structure illustrated in FIG. 13 a.
- FIGS. 14 a - c show photographic images of NW-AMOLED substrates (top row) and NWT channel regions (bottom row) according to the present teachings, specifically, in which the semiconducting nanowires are as follows: a) In 2 O 3 , b) SnO 2 , and c) p-type Ge.
- compositions are described as having, including, or comprising specific components, or where processes are described as having, including, or comprising specific process steps, it is contemplated that compositions of the present teachings also consist essentially of, or consist of, the recited components, and that the processes of the present teachings also consist essentially of, or consist of, the recited processing steps.
- halide or “halogen” refers to F, Cl, Br, and I.
- amino refers to —NH 2 , an —NH-alkyl group, and an —N(alkyl) 2 group.
- alkoxy refers to an —O-alkyl group.
- alkoxy groups include, but are not limited to, methoxy, ethoxy, propoxy (e.g., n-propoxy and isopropoxy), t-butoxy groups, and the like.
- alkyl refers to a straight-chain or branched saturated hydrocarbon group.
- alkyl groups include methyl (Me), ethyl (Et), propyl (e.g., n-propyl and isopropyl), butyl (e.g., n-butyl, isobutyl, sec-butyl, tert-butyl), pentyl groups (e.g., n-pentyl, isopentyl, neopentyl), and the like.
- an alkyl group can have 1 to 20 carbon atoms, i.e., a C 1-20 alkyl group.
- an alkyl group can have 1 to 6 carbon atoms, and can be referred to as a “lower alkyl group.”
- lower alkyl groups include methyl, ethyl, propyl (e.g., n-propyl and isopropyl), and butyl groups (e.g., n-butyl, isobutyl, sec-butyl, tert-butyl).
- haloalkyl refers to an alkyl group having one or more halogen substituents.
- haloalkyl groups include, but are not limited to, CF 3 , C 2 F 5 , CHF 2 , CH 2 F, CCl 3 , CHCl 2 , CH 2 Cl, C 2 Cl 5 , and the like.
- Perhaloalkyl groups i.e., alkyl groups wherein all of the hydrogen atoms are replaced with halogen atoms (e.g., CF 3 and C 2 F 5 ), are included within the definition of “haloalkyl.”
- a C 1-20 haloalkyl group can have the formula —C i X 2j — or —C i H 2i-j X j —, wherein X is F, Cl, Br, or I, i is an integer in the range of 1 to 20, and j is an integer in the range of 0 to 40, provided that i is less than or equal to 2j.
- FIG. 1 a shows a cross-sectional view of an NWT structure with an individually addressed bottom gate.
- the structure of FIG. 1 a includes a SiO 2 buffer layer, a patterned IZO gate electrode, an atomic layer deposition (ALD)-derived high- ⁇ Al 2 O 3 gate insulator, a single-crystal semiconducting In 2 O 3 or ZnO nanowire for the active channel, and ITO for the source/drain electrodes.
- ALD atomic layer deposition
- ITO for the source/drain electrodes.
- no further passivation layers are used so that the dielectric above the nanowire is air.
- 2 O 3 nanowires and ZnO nanowires can be prepared according to procedures described in Li, C. et al., Adv. Mater., 15: 143-145 (2003) and Banerjee, D. et al., Nanotechnology, 15: 404-409 (2004), both of which are incorporated by reference herein in their entireties.
- FIG. 1 b shows a top view field-emission scanning electron microscopic (FE-SEM) image of an NWT device analogous to the one illustrated in FIG. 1 a .
- the IZO gate overlaps with the ITO source/drain electrodes.
- transistor performance can be improved.
- FE-SEM images of single In 2 O 3 and ZnO nanowires between source and drain electrodes are shown in FIGS. 1 c and 1 d , respectively.
- the corresponding nanowire diameters (D) and lengths (L) of single In 2 O 3 or ZnO nanowires addressed between source and drain on the glass substrates are 20 nm/1.80 ⁇ m and 120 nm/1.66 ⁇ m, respectively.
- FIG. 2 a shows the gate and drain leakage currents of a representative In 2 O 3 NWT device for the bias configurations shown in the inset.
- the drain leakage current here is the summation of the body current leakage of the In 2 O 3 nanowire ( ⁇ 40 pA at 2 V) and the leakage current through the gate dielectric ( ⁇ 1 pA at 2 V).
- the Al 2 O 3 gate dielectric exhibits good insulating properties with an electrical breakdown field larger than about 8 MV/cm (see Lin, H. C., et al., Appl. Phys. Lett., 87: 182904-1-3 (2005)), and a dielectric constant of ⁇ 9.
- the thin Al 2 O 3 gate dielectric allows the channel potential to be modulated at a relatively low gate voltage without significant gate leakage, resulting in a steep S and a high I on /I off .
- I ds -V gs gate-source voltage
- the improvement in the S value can be due to the change in terms of a reduction in the interfacial trap states and in fixed surface charge states. See e.g., Ju, S. et al., Appl. Phys. Lett., 89: 193506-1-3 (2006).
- Ozone treatment not only can remove defects and contamination from the nanowire surface, but can also change the work function. See e.g., Lang, O. et al., J. Appl. Phys., 86: 5687-5691 (1999) and Gassenbauer, Y. et al., Phys. Review B, 73: 245312-1-11 (2006).
- Ozone is also expected to increase the density of oxygen vacancies near the nanowire surface. Because oxygen vacancies can act as donor states, ozone treatment can increase the conductivity of the nanowire. Although the ITO and IZO microstructures and chemical bonding states are somewhat more complex, the basic crystal structures are sufficiently similar to those of In 2 O 3 and ZnO to reasonably expect that the In 2 O 3 and ZnO nanowire work functions will increase similarly upon ozone treatment. Thus, the source/drain-nanowire contact should not significantly change on ozone treatment.
- FIG. 2 c shows the log-scale drain current versus gate-source voltage (I ds -V gs ) characteristics of a representative In 2 O 3 NWT device analogous to the one illustrated in FIG. 1 a during four successive sweeps from ⁇ 2 V to +2 V, illustrating the stability of the In 2 O 3 NWTs of the present teachings.
- the I ds -V gs curves are comparable following bias sweeps, with consistent I on /I off , S, and V T values.
- I ds -V gs curves were swept from negative gate voltage (V g ( ⁇ )) to positive gate voltage (V g (+)) and back to V g ( ⁇ ) as shown in FIG. 2 d . Over this bias range, the hysteresis is modest, which illustrates the high quality of the Al 2 O 3 gate insulator and indicates negligible charge trapping and detrapping in the gate insulator.
- FIGS. 3 a and 3 c show the drain current versus gate-source voltage (I ds -V gs ) characteristics for representative single In 2 O 3 and ZnO NWTs.
- the ⁇ eff of the representative In 2 O 3 NWT, deduced from transconductance (g m dI d /dV g ) varied from ⁇ 514 to 300 cm 2 N-sec as the gate bias was increased from 0 V to 2 V, following a trend that is observed in NWTs, TFTs and MOSFETs.
- S dV gs /d log I ds (mV/dec).
- a small S value is required for switching transistors, ideally approaching the theoretical limit of about 60 mV/dec.
- the present S values were extracted from the linear portion of the log I ds versus V gs plot ( FIGS. 3 a and 3 c ).
- the very small S values in the In 2 O 3 and ZnO devices of the present teachings are comparable with those of previously reported non-transparent In 2 O 3 and ZnO NWT devices. See Liu, F. et al., Appl. Phys. Lett., 86: 213101-1-3 (2005) and Chang, P.-C. et al., Appl. Phys. Lett., 89: 133113 (2006).
- FIGS. 3 b and 3 d show the drain current versus drain-source voltage (I ds -V ds ) characteristics of representative fully transparent single In 2 O 3 and ZnO NWTs according to the present teachings. These devices exhibited typical enhancement mode long-channel FET behavior.
- the performance of these In 2 O 3 and ZnO NWT devices is comparable with that of previously reported non-transparent In 2 O 3 and ZnO NWT devices.
- NWTs can be compared to planar transistors by comparing the I on and g m per unit width (g m /W), using the nanowire diameter as the device width.
- the In 2 O 3 nanowire on glass exhibited an I on density of about 600 mA/mm and a g m /W of ⁇ 212 mS/mm. Both values are more than 5 times higher than those obtained in prior studies on transparent transistors using In 2 O 3 thin films, even after adjusting for the differences in gate lengths and gate capacitance.
- the single-crystal nature of the nanowires, along with the formation of relatively high quality interfaces, are believed to play key roles.
- FIG. 4 shows the optical transmission spectra through the In 2 O 3 and ZnO NWT structures, with the substrate absorption removed. As shown in FIG. 4 , an average transmittance of greater than about 90% were observed in the visible and near-infrared spectrum for both transistor types. With the substrate included, optical transmissions of about 82% (In 2 O 3 NWT+glass substrate) and about 83% (ZnO NWT+glass substrate) in the 350 nm-1350 nm wavelength range were observed. The NWT array regions measured 1.0′′ ⁇ 0.5′′ (the glass substrate measured 1.5′′ ⁇ 1.0′′), and contained 23,000 NWT device patterns. In the embodiments studied, the substrates were entirely covered by the SiO 2 buffer layer and the Al 2 O 3 gate insulator.
- the source/drain regions and the gate regions covered about 45% and about 25% of the total NWT array region, respectively. Due to their small diameter, the optical absorption of the In 2 O 3 and ZnO nanowires should thus be negligible, and the area covered by the nanowires was relatively small compared to the entire NWT array. The observation of a greater than about 90% optical transmission indicates that the transmission losses due to the various layers, including the nanowires, were negligible, and that visible light could readily penetrate the dense NWTs.
- the inset in FIG. 4 shows a transparent In 2 O 3 NWT device structure, with text on an underlying opaque layer clearly visible.
- NWT devices can include a flexible plastic substrate.
- a polyethylene terephthalate (PET) plastic substrate e.g., Melinex, DuPont
- PET polyethylene terephthalate
- FIG. 5 a A cross-sectional view of a representative fully transparent and flexible In 2 O 3 NWT device structure with an individually addressed bottom gate is shown in FIG. 5 a .
- Specific embodiments of such devices can include a single In 2 O 3 nanowire addressed between the source and drain contacts having D and L of 20 nm and 1.79 ⁇ m, respectively.
- the gate and source/drain electrodes can be made from ITO.
- FIG. 5 b is a photographic image of a plastic substrate (PET) containing arrays of In 2 O 3 NWTs according to these embodiments, showing their optical clarity and mechanical flexibility.
- FIG. 5 c shows the optical transmission spectrum of one of the transistor array regions containing In 2 O 3 NWTs on the plastic substrate (ITO(S/D)/In 2 O 3 NWs/Al 2 O 3 /ITO(G)/plastic substrate) shown in FIG. 5 b .
- the optical transmission through the NWT structure and substrate was measured to be about 81% in the 350 nm-1350 nm wavelength range.
- FIG. 5 d shows the I ds -V gs characteristic of a representative single In 2 O 3 NWT on the plastic substrate.
- the lower but respectable response characteristics on the plastic substrate could reflect the effects of high temperature deposition (300° C.) and post rapid thermal annealing (RTP, 500° C. for 30 s in N 2 ).
- NWTs of the present teachings can include a gate dielectric made from an organic multi-layered composition.
- This multi-layered composition can include periodically alternating layers of one or more layers that include a polarizable moiety, and one or more layers that include a silyl or siloxane moiety.
- these layers can be individually self-assembled monolayers. Synthesis of such self-assembled nanodielectric (SAND) materials are more fully described in Yoon, M-H. et al., PNAS, 102 (13): 4678-4682 (2005), which is incorporated by reference herein in its entirety.
- nanowire transistors using individual In 2 O 3 nanowires as the channel material and a ⁇ 15 nm thick SAND as the dielectric were investigated.
- the NWTs studied used an individually addressable indium zinc oxide (IZO) bottom-gate and Al source/drain electrodes ( FIG. 6 ), which rendered the channel region completely transparent.
- the diameter and length of the In 2 O 3 nanowires were 20 nm and 1.6 ⁇ m, respectively.
- the device characteristics FIG.
- the field-effect mobility ( ⁇ eff ) which was extracted from the g m and g d of the NWTs, along with an estimated gate-to-channel capacitance, is also plotted versus gate bias in FIG. 7 a . The value of ⁇ eff varied from ⁇ 1447 cm 2 N-sec to ⁇ 300 cm 2 N-sec over the reported gate bias range.
- SAND-based NWTs according to the present teachings is better than other In 2 O 3 nanowire transistors and comparable with poly-Si TFTs and ⁇ -Si TFTs, in terms of S and ⁇ eff . Because it is desirable to obtain high ⁇ eff and a steep S to fabricate fast switching transistors and high-speed logic electronic devices, these results indicate that SAND-based In 2 O 3 NWTs can support the requirements of these devices.
- pixel drivers for active matrix displays such as active matrix liquid crystal displays (AMLCDs), active matrix light-emitting diodes (AMLEDs), and active matrix organic light-emitting diodes (AMOLEDs).
- AMLCDs active matrix liquid crystal displays
- AMLEDs active matrix light-emitting diodes
- AMOLEDs active matrix organic light-emitting diodes
- increasing the aperture ratio is necessary to increase efficiency and reduce power consumption.
- maximizing the aperture ratio corresponds to minimizing the transistor and capacitor physical sizes.
- Transparent transistors would allow stacking of the drive transistors with the OLEDs, which would allow a larger transistor size (width/length) and capacitor size (single or dual capacitors).
- Device geometries could then be optimized to improve metrics such as peak luminescence, Commission Internationale de L'Eclairage Coordinates (CIE), and power consumption.
- CIE Commission Internationale de L'Eclairage Coordinates
- the present NWTs can exhibit relatively high performance in comparison to typical TFTs for display applications, which should allow higher operating speeds and/or smaller device areas.
- driving transistors on RGB pixels must provide ⁇ 2.44 ⁇ A (red), ⁇ 1.01 ⁇ A (green), ⁇ 1.46 ⁇ A (blue) and ⁇ 3.9 ⁇ A (white), respectively.
- the present transparent NWTs were found to be suitable for switching and driving transistors on such pixels. It is also expected that the required current for AMOLED operation will decrease with the increasing aperture ratio provided by all-transparent components. The realization of flexible and transparent NWTs such as those according to the present teachings therefore could also enable high resolution and low-power consumption products such as heads-up displays.
- the present teachings also provide fully transparent transistor display circuit elements (e.g., usable to drive a AM display), in which the switching and driving circuits are comprised of transistors using In 2 O 3 nanowires as active channel materials.
- these transistors can include a multilayer self-assembled gate dielectric (SAND) as a gate insulator and indium tin oxide (ITO) as transparent conductive gate and S-D electrodes.
- SAND self-assembled gate dielectric
- ITO indium tin oxide
- a coplanar transistor structure consisting of ITO S-D electrodes/In 2 O 3 NW/SAND/bottom ITO gate electrodes can be used.
- a robust gate insulator typically is required to maintain high breakdown voltage and low density of defect states.
- Use of the SAND dielectric can ensure high ⁇ eff , a steep S, low operating voltage and a high on-off current ratio (I on /I off ).
- FIG. 9 shows FE-SEM images of several 54 ⁇ 176 ⁇ m pixels within a 2 ⁇ 2 mm array (30 ⁇ 10 pixels).
- the equivalent circuit usable for a single active pixel, shown in FIG. 9 c can include one switching transistor (T 1 ), two driving transistors (T 2 and T 3 ) and one storage capacitor (C st ).
- the transparent driving and switching NWTs regions can allow significant reductions in the area of the transistor circuitry.
- FIG. 9 d shows an FE-SEM image of representative In 2 O 3 nanowires which are connected between S-D electrodes.
- the ITO gate overlaps with the ITO S-D electrodes to ensure gating of the full length of the nanowire channel, thereby improving transistor performance.
- FIG. 10 shows the measured current-voltage (I-V) characteristics of representative NWTs.
- the design of these patterns, including width and length, are exactly same as those of the NWT circuits in the pixel array, except for the addition of extended contact pads for electrical probing.
- several surface treatments were performed: i) following deposition of nanowires, plasma ashing was performed for 90 seconds in Ar and O 2 ambient on only the S-D contact region of nanowires (active regions of nanowires were covered by photoresist); and ii) after ITO metal deposition, active regions of NWTs were subjected to an ozone treatment for 1 minute to remove defects and contamination on the nanowire surface, and change the relative work functions of In 2 O 3 and ITO S-D metals.
- FIG. 10 a shows a family of drain current versus gate-source voltage (I ds -V gs ) characteristics for a representative NWT.
- the single crystal nature of the In 2 O 3 nanowire is expected to allow high mobilities by decreasing scattering at the intergrain regions.
- the SAND dielectric has previously been found to be suitable for realizing relatively high performance in other oxide nanowires.
- the inset in FIG. 10 a shows the hysteresis of the devices for bias sweeps from negative gate voltage (V g ( ⁇ )) to positive gate voltage (V g (+)) and from V g (+) to V g ( ⁇ ).
- the hysteresis was modest over the bias range, which illustrates the high quality of the SAND gate dielectric and In 2 O 3 NW materials, and indicates negligible charge trapping and detrapping in/on the SAND and at the nanowire/SAND interface.
- FIG. 10 d shows the I on /I off , V T and S characteristics of ten representative transistors, with the red lines indicated the average values.
- the average values of I on , I off , V T and S were 2.73 ⁇ A, 143 pA, 0.02 V and 0.35 V/dec, respectively (these values were extracted from I ds -V gs curves at 0.1 V ds ).
- the drain current versus drain-source voltage (I ds -V gs ) characteristics of representative In 2 O 3 NWTs are shown in FIG. 10 b . As can be seen from FIG. 10 b , these representative In 2 O 3 NWTs exhibited typical n-type transistor characteristics.
- FIG. 10 c shows the measured output current of the circuit (I ds of T 2 and T 3 in parallel) versus the output voltage (V dd ).
- the various curves correspond to various values of data line voltage (0 V to 4 V in 0.5 V steps).
- the steps in data line voltage correspond to changes in Vgs for the drive transistors (T 2 and T 3 ).
- the total capacitance on a unit pixel was calculated to be about 0.25 pF/cm 2 .
- the NWTs circuits showed more than 90% yield.
- the higher ⁇ eff and steeper S of SAND-based In 2 O 3 NWTs can allow smaller transistor area and can support the requirements of fast switching transistors and high-speed transistors for NW-AMOLED. Faster switching could enable approaches such as direct digital drive of pixels, which would reduce the complexity of interface circuitry.
- the OLED parameters and target display specifications such as the peak RGB luminescence and efficiency, Commission Internationale de L'Eclairage Coordinates (CIE), and power consumptions dictate specific performance levels which must be considered in the design/simulation/extraction of the transistor current levels and minimum storage capacitor size.
- CIE Commission Internationale de L'Eclairage Coordinates
- the target values are as follows: i) target peak luminescence of 300 cd/m 2 l; ii) target color coordinates of red (0.65, 0.34), green (0.27, 0.63), blue (0.14, 0.16), and white (0.31, 0.32); and iii) EL efficiency of 6 cd/A (red at 300 cd/m2), 23 cd/A (green at 600 cd/m2), and 6 cd/A (blue at 200 cd/m2).
- a unit pixel size is 54 ⁇ 176 ⁇ m
- the EL opening area on a unit pixel is 20 ⁇ 106 ⁇ m
- an aperture ratio is 46%
- polarizer transmission is 40%.
- the driving transistors on RGB pixels should provide at least ⁇ 2.44 ⁇ A on a unit red pixel, ⁇ 1.01 ⁇ A on a unit green pixel, and ⁇ 1.46 ⁇ A on a unit blue pixel, respectively.
- FIG. 11 shows the optical transmission spectra through the 2 ⁇ 2 mm nanowire-based region usable for AM-OLED. The optical transmission was measured to be about 72% in the 350 nm-1350 nm wavelength range.
- the inset shows a photographic image of the 1 ⁇ 1 inch glass substrate which consists of three 2 ⁇ 2 mm transistor arrays, 340 unit pixels, 80 test NWT devices, 6 alignment marks, 20 test patterns, and contact pads.
- a 500 nm thick layer of SiO 2 was deposited by plasma-enhanced chemical vapor deposition (PECVD) on Corning 1737 glass substrates and served as a buffer and planarization layer.
- PECVD plasma-enhanced chemical vapor deposition
- An 18 nm thick layer of Al 2 O 3 was then deposited using atomic layer deposition (ALD) at 300° C. in an ASM Microchemistry F-120 ALCVDTM system using trimethyl aluminum (Al(CH 3 ) 3 ) (TMA) and water as precursors.
- the substrates were annealed at 500° C. for 30 seconds under N 2 to improve the film quality.
- a suspension of In 2 O 3 or ZnO nanowires in VLSI grade 2-propanol solution was disbursed on the gate-patterned substrates.
- Single-crystal semiconducting In 2 O 3 nanowires were synthesized by a pulsed laser ablation process (see Li, C. et al., Adv. Mater., 15: 143-145 (2003)), with average diameter and length of 20 nm and 5 ⁇ m, respectively.
- Powdered ZnO nanowires synthesized by thermal evaporation and condensation were purchased from Nanolab Inc.
- ITO source/drain electrodes were deposited by IAD at room temperature and patterned by photolithography. Following source/drain electrode patterning, the NWTs, while shielded from UV light, were subjected to an ozone treatment (UV-Ozone cleaner, UVO 42-220, Jelight Co. Ltd.) for 2 minutes to achieve optimum transistor performance in terms of I on , I on :I off , S, and ⁇ eff .
- UV-Ozone cleaner UVO 42-220, Jelight Co. Ltd.
- the ozone environment was obtained by setting the oxygen content to 50 ppm, the UV wavelength to 184.9 nm and UV lamp power to 28 milliwatts per cm 2 at 254 nm.
- Fully transparent and flexible In 2 O 3 NWT devices using PET also were fabricated with a PET/ITO(G)/Al 2 O 3 /In 2 O 3 nanowire/ITO(S/D) structure ( FIG. 5 a ).
- the 50 nm thick layer of Al 2 O 3 layer was deposited at 200° C.
- ITO for the gate and source/drain electrodes was deposited by IAD.
- the lengths of the nanowires of given transistors between source and drain were obtained from the FE-SEM images, and accounted for the angle between the nanowire and the electrode edges.
- the 200 nm thick layer of SiO 2 was deposited on Corning 1737A glass substrates as a buffer layer for planarization.
- a 24 nm thick layer of SAND was then deposited on the patterned ITO gate metals using a self-assembly method. Following SAND deposition, contact holes were patterned for anode opening for electroluminescence and bottom gate electrode contacts on the pixel. Next, a suspension of In 2 O 3 nanowires in VLSI grade 2-propanol solution was disbursed on the device substrates.
- Single-crystal semiconducting In 2 O 3 nanowires were synthesized by a pulsed laser ablation process, with average diameter and length of 50 nm and 5 ⁇ m, respectively.
- Al source/drain contacts were fabricated by spattering.
- ITO S-D electrodes they were deposited by IAD at room temperature and patterned by lift-off method. Nanowires on the unnecessary regions were removed by ultrasonication except nanowires which were addressed between S-D electrodes.
- the NWTs while shielded from UV light, were subjected to an ozone treatment using UV-Ozone cleaner for 1 minute to achieve optimum transistor performance in terms of I on , I on :I off , S, and ⁇ eff .
- the devices were passivated by depositing a 200 nm of e-beam evaporated SiO 2 as a passivation layer to planarize NWTs array for EL deposition.
- a 200 nm thick SiO 2 layer was deposited on Si or Corning 1737A glass substrates as a buffer layer for planarization.
- a 15 nm thick layer of SAND was then deposited on the patterned ITO gate metals using a self-assembly method.
- a suspension of SnO 2 nanowires in VLSI grade 2-propanol solution was disbursed on the device substrates.
- Al source/drain contacts were fabricated by spattering.
- ITO S-D electrodes were deposited by IAD at room temperature and patterned by a lift-off method. Nanowires on the unnecessary regions were removed by ultrasonication except nanowires which were addressed between S-D electrodes.
- FIG. 12 shows the structure and electrical characteristic of a representative single SnO 2 NWT using SAND as the gate dielectric.
- Different substrates Si—SiO 2 , Glass-SiO 2
- source/drain contact Al, ITO
- a 200 nm thick SiO 2 was deposited on Si or Corning 1737A glass substrates as a buffer layer for planarization.
- a 15 nm thick layer of SAND was then deposited on the patterned ITO gate metals using a self-assembly method.
- a suspension of p- or n-type Ge nanowires in VLSI grade 2-propanol solution was disbursed on the device substrates.
- Al source/drain contacts were fabricated by spattering.
- ITO S-D electrodes were deposited by IAD at room temperature and patterned by a lift-off method. Nanowires on the unnecessary regions were removed by ultrasonication except nanowires which were addressed between S-D electrodes.
- FIG. 13 shows the structure and electrical characteristic of representative single p-type and n-type Ge NWTs using SAND as the gate dielectric.
- Different substrates Si—SiO 2 , Glass-SiO 2
- source/drain contact Al, ITO
- FIG. 14 shows photographic images of NW-AMOLED substrates (top row) and NWT channel regions (bottom row) according to the present teachings, specifically, in which the semiconducting nanowires are as follows: a) In 2 O 3 , b) SnO 2 , and c) p-type Ge.
- the respective device structures consist of a glass-SiO 2 substrate, an ITO gate electrode, a SAND gate dielectric, ITO source/drain electrodes, and a single nanowire channel region of In 2 O 3 ( FIG. 14 a ), SnO 2 ( FIG. 14 b ), or Ge ( FIG. 14 c ).
- the Ge-based devices have similar optical transparency compared to similar devices based on metal oxide nanowires.
- the work function of an as-grown ITO thin film was measured using an AC-2, RKI Instruments photoelectron spectrometer.
- the UV-Vis spectra were recorded with a Varian Cary 1 E spectrophotometer.
- Electrical I-V measurements were performed using a Keithley 4200 semiconductor characterization system.
- the NWs within a device were imaged with a Hitachi S-4800 FE-SEM following electrical characterization.
- k eff ⁇ 9.0 is the effective dielectric constant of Al 2 O 3
- L is the channel length of the NWTs ( ⁇ 1.80 ⁇ m for In 2 O 3 NW, ⁇ 1.66 ⁇ m for ZnO NW)
- k eff ⁇ 9.0 is the effective dielectric constant of Al 2 O 3
- L is the channel length of the NWTs ( ⁇ 1.80 ⁇ m for In 2 O 3 NW, ⁇ 1.66 ⁇ m for ZnO NW)
- r is the radius of the NWTs (10 nm for In 2 O 3 NW, 60 nm for ZnO NW)
- t ox ⁇ 18 nm is the thickness of gate insulator
- dI ds /dV gs is the transconductance
- V ds is drain voltage.
- V T ⁇ ( V T V G ⁇ ( g m_max ) - I D ⁇ ( g m_max ) g m_max ⁇ ⁇
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Nanotechnology (AREA)
- Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Materials Engineering (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
- This application is a continuation of and claims priority benefit of application Ser. No. 12/131,697 filed Jun. 2, 2008, and issued as U.S. Pat. No. 7,910,932 on Mar. 22, 2011, and 60/932,636 filed Jun. 1, 2007, each of which is incorporated herein by reference in its entirety.
- This invention was made with government support under Grant No. NCC-2-1363 awarded by the National Aeronautics and Space Administration Institute for Nanoelectronics and Computing and Grant No. DMR0520513 awarded by the National Science Foundation. The government has certain rights in the invention.
- Development of optically transparent and mechanically flexible electronic circuitry represents an enabling step toward next-generation display technologies, including “see-through” and conformable products. In addition to transparency and flexibility, transistor performance metrics such as high on-current (Ion), high on/off current ratio (Ion/Ioff), high field-effect mobility (μeff), steep subthreshold slope (S), and small threshold voltage (VT) variation during transistor operation are required to realize commercially viable logic circuits and display devices.
- Nanowire transistors (NWTs), i.e., transistors incorporating semiconducting nanowires as charge transporting channel materials, are of particular interest for future display devices because of their high carrier mobilities and stability compared with other thin film transistors (TFTs). The use of pre-formed nanowires also allows low-temperature device processing, which is essential for applications such as circuits fabricated on plastic substrates. While there have been several recent reports of transparent transistors fabricated with ZnO, SnO2, In2O3 or other semiconducting oxide thin films, or with carbon nanotube networks as the active channel layers and opaque source and drain metals, or with carbon nanotube films and transparent source/drain electrodes (see e.g., Carcia, P. F. et al., Appl. Phys. Lett., 82: 1117-1119 (2003); Fortunato, E. et al., Thin Solid Films, 487: 205-211 (2005); Hoffman, R. L. et al., Appl. Phys. Lett., 82: 733-735 (2003); Nomura, K. et al., Science, 300: 1269-1272 (2003); Presley, R. E. et al., J. Phys. D: Appl. Phys., 37: 2810-2813 (2004); Wang, L. et al., Nature Mater., 5: 893-900 (2006); Hur, S.-H. et al., Appl. Phys. Lett., 86, 243502-1-3 (2005); and Takenobu, T. et al., Appl. Phy. Lett., 88: 33511-1-3 (2006)), there have been no reports of fully transparent NWTs fabricated with all-transparent gate and source/drain electrodes and displaying high levels of transistor performance.
- In light of the foregoing, the present teachings provide nanowire-based transistors and circuits that can comprise one or more semiconducting nanowires as the channel material. In some non-limiting embodiments, the nanowire transistor structures of the present teachings can be fully transparent and comprise components made from various transparent materials. Given the small diameter of a nanowire, “fully transparent” nanowire transistors described herein can comprise one or more non-transparent nanowires (e.g., without limitation, nanowires made from
Group 14 elements such as Si, Ge, and alloys thereof, one or more Group 13-15 elements such as GaAs, GaN, and InP, and one or more Group 12-16 elements such as CdS and CdSe) as well as transparent oxide nanowires (e.g., without limitation, ZnO, In2O3, and SnO2 nanowires), and transparent gate and source/drain electrodes. The nanowire transistors of the present teachings can exhibit high performance n-type transistor characteristics with satisfactory optical transparency. Among various applications, the nanowire transistors of the present teachings can be attractive as pixel switching and driving transistors in active-matrix organic light-emitting diode (AMOLED) displays, and can supply sufficient current to drive pixels employing reported electroluminescent organic materials. The transparency of the drive circuitry can enable significant increases in aperture ratio in active-matrix arrays, which can lead to higher display brightness and decreased power consumption. The high mobility of the nanowire channel materials also can allow faster switching of the transistor circuits, which can allow circuit approaches such as direct digital drive of display elements. - In certain embodiments, the nanowire transistor devices of the present teachings can comprise one or more semiconducting nanowires extending between a source electrode and a drain electrode, and a gate dielectric in contact with the one or more semiconducting nanowires. In some embodiments, the device can include a single semiconducting nanowire as the channel material. In other embodiments, the device can include a plurality of semiconducting nanowires to fulfill larger current carrying needs. As described above, in some embodiments, the one or more semiconducting nanowires can be prepared from a
Group 14 element such as, without limitation, Si and Ge. In other embodiments, transparent semiconducting nanowires prepared from transparent metal oxides such as, without limitation, ZnO, In2O3, and SnO2, can be used. - In some embodiments, the gate dielectric can be an inorganic layer of one or more transparent metal oxides. For example, the gate dielectric can be a
Group 3 metal oxide, aGroup 5 metal oxide, or a Group 13 metal oxide such as, but not limited to, aluminum oxide (Al2O3), yttrium oxide (Y2O3), tantalum pentoxide (Ta2O5), hafnium oxide (HfO2), and vanadium oxide (V2O5). Such metal oxides can optionally include one or more dopants. The oxide gate dielectric can be deposited by various techniques known in the art including, without limitation, thermal evaporation, sputtering, metalorganic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), ion-assisted deposition (IAD), and pulsed-laser deposition (PLD). - In certain embodiments, the gate dielectric can be an organic multi-layer composition. This multi-layer composition can comprise periodically alternating layers of one or more layers that include a polarizable moiety, and one or more layers that can comprise a silyl or siloxane moiety. The polarizable moiety (e.g., without limitation, a π-polarizable moiety) can include conjugated π-electrons. The siloxane moiety can comprise oligomeric or polymeric moieties having —Si—O— bonds. In particular embodiments, there can be one or more layers that comprise a sigma moiety among the periodically alternating layers. The sigma moiety can comprise a hydrocarbon as described in more detail below.
- In some embodiments, the polarizable moiety can be a moiety having at least one of a dipole moment, an electron releasing moiety, an electron withdrawing moiety, a combination of such moieties, a zwitterion and a net charge. For example, the polarizable moiety can be a non-linear optical (NLO) chromophore. In some embodiments, the chromophore can comprise a π-conjugated system, which can comprise a system of atoms covalently bonded with alternating single and multiple (e.g., double) bonds (e.g., C═C—C═C—C and C═C—N═N—C). The π-conjugated system can comprise one or more heteroatoms such as, but not limited to, nitrogen (N), oxygen (O), and sulfur (S). In some embodiments, the π-conjugated system can comprise one or more aromatic rings (aryl or heteroaryl) linked by conjugated hydrocarbon chains. In certain embodiments, the aromatic rings can be linked by conjugated chains that include heteroatoms and heteroatom-containing groups (e.g., azo groups [—N═N—]). For example, the polarizable moiety can be a chromophore that comprises a stilbazolium group.
- Various polarizable moieties that can be used according to the present teachings are described in U.S. Pat. No. 6,855,274, in particular the NLO structures of
FIGS. 1-2 , 11, and 13-15 thereof; U.S. Pat. No. 6,549,685, in particular the NLO structures ofFIGS. 2-3 thereof; and U.S. Pat. No. 5,156,918, in particular the NLO structures ofFIGS. 4-5 thereof, each with reference to the corresponding specification regarding alternate embodiments, synthesis, and characterization, and each of which is incorporated by reference herein in its entirety. In particular embodiments, the polarizable moiety can comprise a stilbazonium group. - At least some of the alternating layers can be coupled to an adjacent layer by a coupling layer that comprises a siloxane matrix. The coupling can be performed via a condensation reaction or chemisorption using known silicon chemistry. For example, two layers including the polarizable moiety can be coupled to each other by a coupling layer that comprises a siloxane matrix, resulting in a three-layered composition that includes alternating layers of a first layer including a polarizable moiety, a coupling layer that includes a siloxane matrix, and a second layer that includes a polarizable moiety. One or more layers including a polarizable moiety also can be crosslinked by a siloxane matrix. In some embodiments, at least some of the alternating layers can be coupled or covalently bonded to one another or the siloxane matrix via a condensation reaction. For example, the three-layer composition described above can include condensation products of a silane-substituted stilbazolium compound (e.g., 4-[[(4-(N,N-bis((hydroxy)ethyl)amino]-phenyl]azo]-1-(4-trichlorosilyl)benzyl-pyridinium iodide, or 4-[[(4-(N,N-bis((hydroxyl)ethyl)amino]-phenyl]azo]-1-(4-dichloroiodosilyl)benzyl-pyridinium iodide) and a trisiloxane compound (e.g., without limitation, octachlorotrisiloxane or other similar compounds including Si—O bonding sequence with hydrolyzable groups). Exemplary hydrolyzable groups comprise, without limitation, halides, hydroxyl groups, alkoxy groups, amine groups, and carboxyl groups.
- In some embodiments, the multi-layer composition also can include a hydrocarbon layer (i.e., a sigma moiety). Such a hydrocarbon layer can comprise a C1- about C20 alkyl group or a C1- about C20 haloalkyl group. Such a hydrocarbon layer can be coupled to a coupling layer that comprises a siloxane matrix, or it can be coupled to a layer comprising a polarizable moiety directly or via a coupling layer that comprises a siloxane matrix as described above. To allow coupling, the alkyl or haloalkyl group can be functionalized with silyl moieties having hydrolyzable groups. For example, at least some of the alternating layers can include a condensation product of a bis(silyl)- about C4 to about C20 alkyl compound (e.g., without limitation, Cl3Si(CH2)nSiCl3, (CH3O)3Si(CH2)nSi(OCH3)3, and (Me2N)3Si(CH2)nSi(NMe2)3, where n can be 4, 5, 6, 7, 8, 9, or 10) and a trisiloxane compound (e.g., without limitation, octachlorotrisiloxane or other similar compounds including Si—O bonding sequence with hydrolyzable groups). Such bis-silylated compounds are hydrolyzable to a degree at least partially sufficient for substrate sorption or condensation or intermolecular crosslinking via siloxane bond formation under the processing or fabrication conditions employed. Similarly, the polarizable moiety can be derivatized to include similar silyl hydrolyzable groups, to allow bond formation with the siloxane coupling layer and/or the hydrocarbon layer. In particular embodiments, the hydrocarbon layers and the layers comprising a polarizable moiety can be individually self-assembled monolayers. Synthesis of such self-assembled nanodielectric (SAND) materials are more fully described in Yoon, M-H. et al., PNAS, 102 (13): 4678-4682 (2005), which is incorporated by reference herein in its entirety.
- In further embodiments, the gate dielectric can be a polymer. For example, the gate dielectric can be a polymer such as, without limitation, polyhydroxystyrene and polystyrene. In certain embodiments, the gate dielectric can be a crosslinked polymer, examples of which include, but are not limited to, the various crosslinked polymeric dielectric materials described in U.S. patent application Ser. Nos. 11/315,076, 60/816,952, and 60/861,308, each of which is incorporated by reference herein in its entirety.
- The source electrode and the drain electrode can be prepared from various transparent conductive oxides. Examples include, without limitation, indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide, zinc oxide, zinc indium tin oxide (ZITO), and other similar optionally doped metal oxides (e.g., fluorinated tin oxide, gallium zinc oxide (GZO), gallium indium oxide (GIO) and gallium indium tin oxide (GITO)). A nanowire transistor device of the present teachings also can, without limitation, comprise a gate electrode prepared from one or more of the transparent conductive oxides described above.
- In various embodiments and to provide a fully transparent nanowire transistor device, the gate dielectric can be deposited on a transparent substrate. Examples of suitable substrates include but are not limited to glass and various transparent plastic materials (both rigid and flexible). Examples of flexible plastic substrates include, but are not limited to, polyethylene terephthalate (PET) and polyethylene naphthalate (PEN).
- The present teachings further provide methods for fabricating a nanowire transistor device. Such a method can comprise applying a gate electrode layer on a substrate, applying a dielectric layer on the gate electrode layer, applying one or more semiconducting nanowires on the dielectric layer, and applying a source electrode and a drain electrode on the dielectric layer, wherein the application of the gate electrode layer, the application of the dielectric layer, the application of the one or more semiconducting nanowires, and the application of the source electrode and the drain electrode are conducted at a temperature less than about 100° C. (e.g., at or near room temperature). Each of the gate electrode layer, the dielectric layer, the source electrode, the drain electrode, and the substrate can be transparent (for example, by using the various suitable materials disclosed herein), and one or more semiconducting nanowires can extend between the source electrode and the drain electrode. In some embodiments, the application of the one or more semiconducting nanowires can involve dispersing a suspension that includes one or more semiconducting nanowires on the dielectric layer. In some embodiments, the application of the dielectric layer can comprise forming at least one condensation product of a silane-substituted stilbazoium compound and a trisiloxane compound, and optionally, at least one condensation product of a bis(silyl)- about C4 to about C20 alkyl compound and a trisiloxane compound. The resulting nanowire transistor device can be subjected to ozone treatment to further improve its device performance, for example, to increase its field effect mobility.
- The foregoing, other features, and advantages of the present teachings, will be more fully understood from the following figures, description, and claims.
- It should be understood that the drawings described below are for illustration purpose only. The drawings are not necessarily to scale and are not intended to limit the scope of the present teachings in any way. The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the office upon request and payment of the necessary fee.
-
FIG. 1 a is a cross-sectional view of an embodiment of a nanowire transistor (NWT) device according to the present teachings. In particular, the illustrated device consists of a SiO2 buffer layer (500 nm), a patterned IZO (In—Zn—O) gate electrode (120 nm), an atomic layer deposition (ALD)-deposited Al2O3 gate insulator (18 nm), a single In2O3 nanowire (D˜20 nm) or ZnO nanowire (D˜120 nm) for the active channel, and ITO for the source/drain electrodes (120 nm). Scale bar: 100 μm. -
FIG. 1 b is a top-view field-emission scanning electron microscopic (FE-SEM) image of an NWT device analogous to the one illustrated inFIG. 1 a. Scale bar: 100 μm. -
FIG. 1 c is a top-view SEM image of a single In2O3 nanowire region (D/L˜20 nm/1.80 μm) of an NWT device analogous to the one illustrated inFIG. 1 a. Scale bar: 1.5 μm. -
FIG. 1 d is a top-view SEM image of a single ZnO nanowire region (D/L˜120 nm/1.66 μm) of an NWT device analogous to the one illustrated inFIG. 1 a. Scale bar: 1.5 μm. -
FIG. 2 a shows the gate leakage current (B: black dots) and the drain leakage current (A: red dots) of a representative In2O3 NWT device according to the present teachings. The inset shows the bias configurations. -
FIG. 2 b shows the linear-scale and log-scale Ids-Vgs characteristics at Vd=0.5 V of a representative In2O3 NWT device analogous to the one illustrated inFIG. 1 a. Arrows indicate appropriate axis. Data points are shown for the device before (black dots, 1) and after (red solid line, 2) two minutes of ozone treatment. -
FIG. 2 c shows the log-scale Ids-Vgs characteristics during four successive sweeps from −4 V to +4 V (Vd=0.5 V) of a representative In2O3 NWT device analogous to the one illustrated inFIG. 1 a. Black, red, green and blue (square, circular, up and down triangle) data points correspond to 1st, 2nd,3rd and 4th sweeps. The time between sweeps is ˜1 second. -
FIG. 2 d shows the measured Ids-Vgs characteristics of a representative In2O3 NWT device analogous to the one illustrated inFIG. 1 a, showing sweeps from −2 Vg to +2 Vg (red circles) and from +2 Vg to −2 Vg (blue squares) as indicated by arrows (Vd=0.5 V). The bias sweep rate (dVg/dt) is 2 V/sec. -
FIG. 3 a shows the Ids-Vgs characteristics at Vd=0.5 V of a representative In2O3 NWT device (D/L˜20 nm/1.80 μm) analogous to the one illustrated inFIG. 1 a. Blue (1), red (2), and green (3) data points correspond to linear-scale Ids-Vgs, log-scale Ids-Vgs and μeff Arrows indicate appropriate axis. -
FIG. 3 b shows the Ids-Vds characteristics of a representative In2O3 NWT device analogous to the one illustrated inFIG. 1 a. Vg is from −0.5 V to 2.5 V at 0.5 V steps, with the maximum current observed at Vg=2.5 V. -
FIG. 3 c shows the Ids-Vgs characteristics at Vd=0.5 V of a representative ZnO NWT device (D/L˜120 nm/1.66 μm) analogous to the one illustrated inFIG. 1 a. Blue (1), red (2), and green (3) data points correspond to linear-scale Ids-Vgs, log-scale Ids-Vgs and μeff. Arrows indicate appropriate axis. -
FIG. 3 d shows the Ids-Vds characteristics of a representative ZnO NWT device analogous to the one illustrated inFIG. 1 a. Vg is from 0.0 V to 3.0 V at 0.5 V steps, with the maximum current observed at Vg=3.0 V. -
FIG. 4 shows the optical transmission spectra for regions containing an In2O3 NWT or a ZnO NWT according to the present teachings on a glass substrate (ITO (source/drain)/In2O3 or ZnO nanowires/Al2O3 (dielectric)/IZO (gate)/SiO2/glass). Blue and red lines correspond to In2O3 and ZnO NWTs, respectively. The inset shows a photographic image of a glass substrate having 23,000 In2O3 NWT devices deposited on its surface, with text on an underlying opaque layer clearly visible. -
FIG. 5 a is a cross-sectional view of a fully transparent and flexible NWT device according to the present teachings. In particular, the illustrated device consists of a plastic substrate, a patterned ITO gate electrode (120 nm), an ALD-deposited Al2O3 gate insulator (50 nm), a single In2O3 nanowire (D/L˜20 nm/1.79 μm) for the active channel, and ITO for the source/drain electrodes (120 nm). -
FIG. 5 b is a photographic image of arrays of representative In2O3 NWTs deposited on a plastic substrate, showing the optical clarity and mechanical flexibility of the NWTs. -
FIG. 5 c shows the optical transmission spectrum of one of the transistor array regions containing In2O3 NWTs on the plastic substrate (ITO(S/D)/In2O3 NWs/Al2O3/ITO(G)/plastic substrate) shown inFIG. 5 b. -
FIG. 5 d shows the Ids-Vgs characteristics at Vd=0.5 V of a representative In2O3 NWT having the structure as illustrated inFIG. 5 a. Blue (1), red (2), and green (3) data points correspond to linear-scale Ids-Vgs, log-scale Ids-Vgs and μeff. Arrows indicate appropriate axis. -
FIG. 6 a is a cross-sectional view of another embodiment of an NWT device according to the present teachings, specifically, one incorporating self-assembled nanodielectrics (SAND) as the gate insulator. -
FIG. 6 b is a top-view FE-SEM image of a representative device having the structure illustrated inFIG. 6 a. Scale bar: 1.5 μm. -
FIG. 6 c is a cross-sectional band diagram of a representative device having the structure illustrated inFIG. 6 a at Vgs=0V. -
FIG. 7 a shows the Ids-Vgs characteristics at Vd=0.5. V of a representative In2O3 NWT having the structure illustrated inFIG. 6 a. Green (1), red (2) and blue (3) data points corresponding to linear-scale Ids-Vgs, log-scale Ids-Vgs and field effect mobility. -
FIG. 7 b shows the Ids-Vds characteristics of a representative In2O3 NWT having the structure illustrated inFIG. 6 a. -
FIG. 8 a shows the transconductance (gm) at 5 Vg of a representative In2O3 NWT having the structure illustrated inFIG. 6 a. -
FIG. 8 b shows the channel conductance (gd) from 0.0 Vd to 1.8 Vd of a representative In2O3 NWT having the structure illustrated inFIG. 6 a. -
FIG. 9 a shows the top and cross-sectional pixel structure of a drive transistor in a NW-AMOLED array. In particular, each NWT in the circuit structures consists of a SiO2 buffer layer (200 nm), a patterned ITO gate electrode (100 nm), a SAND gate dielectric (24 nm), multiple In2O3 nanowires for the active channel, ITO for the S-D electrodes (100 nm), and a SiO2 passivation layer (200 nm). The ITO pad on the right serves as the cathode for the organic light-emitting diode (OLED). -
FIG. 9 b is a top-view FE-SEM image of several 54×176 μm pixels within a 2×2 mm NWT array layout (rectangles with rounded ends), along with control transistors. -
FIG. 9 c is a schematic for a circuit as shown inFIG. 9 a for a single pixel, consisting of 1 switching transistor (T1), 2 driving transistors (T2 and T3) and 1 storage capacitor. The bias condition to operate transistor circuit (2 V on scan line for fully turn-on, varying 0 V to 4 V on data line, and 5 V on Vdd line). -
FIG. 9 d is an FE-SEM image of a representative region within an NWT transistor channel, showing multiple In2O3 nanowires connected between S-D electrodes. The diameter of a nanowire and the channel length between S-D electrodes of the device are ˜50 nm and ˜1.5 μm, respectively. Scale bar: 1.5 μm. -
FIG. 10 a shows the Ids-Vgs characteristics (log scale) of a representative In2O3 NWT (D/L˜50 nm/1.5 μm) analogous to the one illustrated inFIG. 9 a, with red (1), blue (2), green (3), dark blue (4) data points corresponding to Vds=0.1, 0.2, 0.5 and 1.0 V. The inset shows the hysteresis of the representative device at Vds=0.1 V. -
FIG. 10 b shows the Ids-Vds characteristics for the representative device, with Vgs varying from 0.0 V to 3.0 V in 0.5 V steps. -
FIG. 10 c shows the output current-voltage characteristics for a single-pixel circuit consisting of one switching transistor and two driving transistors (Ids versus Vds for the parallel combination of T2 and T3) for various steps in “data” line voltage (2 V on scan line to fully turn-on T1, 0.0 V to 4.0 V on data line in 0.5 V steps). -
FIG. 10 d shows the Ion, Ioff, VT and S values of 10 representative NWT devices, with red lines indicating the average values for the respective parameters. -
FIG. 11 shows the optical transmission spectrum for representative regions within an NWT channel of a 2×2 mm NW-AMOLED display element (SiO2 (passivation)/ITO (source/drain)/In2O3 (active channel)/SAND (gate insulator)/ITO (gate)). The inset shows an image of a fully transparent NW-AMOLED substrate consisting of three 2×2 mm transistor arrays, 340 unit pixels, 80 test devices, 6 alignment marks, 20 test patterns, and contact pads. -
FIG. 12 a is a cross-sectional view of yet another embodiment of an NWT device structure according to the present teachings. In particular, this embodiment consists of a SiO2 buffer layer, a patterned ITO gate electrode (120 nm), a SAND gate insulator (15 nm), and a single SnO2 nanowire. Depending on the materials for the source/drain electrodes, the NWT can be partially (e.g., Al) or fully transparent (e.g., ITO). -
FIG. 12 b shows typical linear-scale and log-scale Ids-Vgs transfer characteristics at Vd=0.5 V of a representative SnO2 NWT having the structure illustrated inFIG. 12 a. Arrows indicate the appropriate axis. -
FIG. 12 c shows typical output plots for a representative SnO2 NWT device having the structure illustrated inFIG. 12 a. -
FIG. 13 a is a cross-sectional view of yet another embodiment of an NWT device structure according to the present teachings. In particular, this embodiment consists of a SiO2 buffer layer, a patterned ITO gate electrode (120 nm), a SAND gate insulator (15 nm), and a single Ge nanowire. Depending on the materials for the source/drain electrodes, the NWT can be partially (e.g., Al) or fully transparent (e.g., ITO). -
FIG. 13 b shows typical output plots for a p-type Ge NWT device having the structure illustrated inFIG. 13 a. -
FIG. 13 c shows typical log-scale Ids-Vgs transfer characteristics at Vd=−4 V of a p-type Ge NWT having the structure illustrated inFIG. 13 a. -
FIG. 13 d shows typical output plots for an n-type Ge NWT device having the structure illustrated inFIG. 13 a. -
FIG. 13 e shows typical log-scale Ids-Vgs transfer characteristics at Vd=−4 V of an n-type Ge NWT having the structure illustrated inFIG. 13 a. -
FIGS. 14 a-c show photographic images of NW-AMOLED substrates (top row) and NWT channel regions (bottom row) according to the present teachings, specifically, in which the semiconducting nanowires are as follows: a) In2O3, b) SnO2, and c) p-type Ge. - Throughout the description, where compositions are described as having, including, or comprising specific components, or where processes are described as having, including, or comprising specific process steps, it is contemplated that compositions of the present teachings also consist essentially of, or consist of, the recited components, and that the processes of the present teachings also consist essentially of, or consist of, the recited processing steps.
- In the application, where an element or component is said to be included in and/or selected from a list of recited elements or components, it should be understood that the element or component can be any one of the recited elements or components and can be selected from a group consisting of two or more of the recited elements or components. The use of the term “include” should be generally understood as open-ended and non-limiting unless specifically stated otherwise.
- The use of the singular herein includes the plural (and vice versa) unless specifically stated otherwise. In addition, where the use of the term “about” is before a quantitative value, the present teachings also include the specific quantitative value itself, unless specifically stated otherwise.
- It should be understood that the order of steps or order for performing certain actions is immaterial so long as the present teachings remain operable. Moreover, two or more steps or actions may be conducted simultaneously.
- As used herein, “halide” or “halogen” refers to F, Cl, Br, and I.
- As used herein, “amino” refers to —NH2, an —NH-alkyl group, and an —N(alkyl)2 group.
- As used herein, “alkoxy” refers to an —O-alkyl group. Examples of alkoxy groups include, but are not limited to, methoxy, ethoxy, propoxy (e.g., n-propoxy and isopropoxy), t-butoxy groups, and the like.
- As used herein, “alkyl” refers to a straight-chain or branched saturated hydrocarbon group. Examples of alkyl groups include methyl (Me), ethyl (Et), propyl (e.g., n-propyl and isopropyl), butyl (e.g., n-butyl, isobutyl, sec-butyl, tert-butyl), pentyl groups (e.g., n-pentyl, isopentyl, neopentyl), and the like. In various embodiments, an alkyl group can have 1 to 20 carbon atoms, i.e., a C1-20 alkyl group. In some embodiments, an alkyl group can have 1 to 6 carbon atoms, and can be referred to as a “lower alkyl group.” Examples of lower alkyl groups include methyl, ethyl, propyl (e.g., n-propyl and isopropyl), and butyl groups (e.g., n-butyl, isobutyl, sec-butyl, tert-butyl).
- As used herein, “haloalkyl” refers to an alkyl group having one or more halogen substituents. Examples of haloalkyl groups include, but are not limited to, CF3, C2F5, CHF2, CH2F, CCl3, CHCl2, CH2Cl, C2Cl5, and the like. Perhaloalkyl groups, i.e., alkyl groups wherein all of the hydrogen atoms are replaced with halogen atoms (e.g., CF3 and C2F5), are included within the definition of “haloalkyl.” For example, a C1-20 haloalkyl group can have the formula —CiX2j— or —CiH2i-jXj—, wherein X is F, Cl, Br, or I, i is an integer in the range of 1 to 20, and j is an integer in the range of 0 to 40, provided that i is less than or equal to 2j.
-
FIG. 1 a shows a cross-sectional view of an NWT structure with an individually addressed bottom gate. As one embodiment of the present teachings, the structure ofFIG. 1 a includes a SiO2 buffer layer, a patterned IZO gate electrode, an atomic layer deposition (ALD)-derived high-κ Al2O3 gate insulator, a single-crystal semiconducting In2O3 or ZnO nanowire for the active channel, and ITO for the source/drain electrodes. In the embodiment shown, no further passivation layers are used so that the dielectric above the nanowire is air. In2O3 nanowires and ZnO nanowires can be prepared according to procedures described in Li, C. et al., Adv. Mater., 15: 143-145 (2003) and Banerjee, D. et al., Nanotechnology, 15: 404-409 (2004), both of which are incorporated by reference herein in their entireties. -
FIG. 1 b shows a top view field-emission scanning electron microscopic (FE-SEM) image of an NWT device analogous to the one illustrated inFIG. 1 a. As shown, the IZO gate overlaps with the ITO source/drain electrodes. By fully covering the nanowire channel, transistor performance can be improved. FE-SEM images of single In2O3 and ZnO nanowires between source and drain electrodes are shown inFIGS. 1 c and 1 d, respectively. For the particular embodiments shown, the corresponding nanowire diameters (D) and lengths (L) of single In2O3 or ZnO nanowires addressed between source and drain on the glass substrates are 20 nm/1.80 μm and 120 nm/1.66 μm, respectively. -
FIG. 2 a shows the gate and drain leakage currents of a representative In2O3 NWT device for the bias configurations shown in the inset. The drain leakage current here is the summation of the body current leakage of the In2O3 nanowire (˜40 pA at 2 V) and the leakage current through the gate dielectric (˜1 pA at 2 V). The Al2O3 gate dielectric exhibits good insulating properties with an electrical breakdown field larger than about 8 MV/cm (see Lin, H. C., et al., Appl. Phys. Lett., 87: 182904-1-3 (2005)), and a dielectric constant of ˜9. The thin Al2O3 gate dielectric allows the channel potential to be modulated at a relatively low gate voltage without significant gate leakage, resulting in a steep S and a high Ion/Ioff. -
FIG. 2 b shows the linear-scale and log-scale drain current versus gate-source voltage (Ids-Vgs) characteristics at Vd=0.5 V for a representative In2O3 NWT device analogous to the one illustrated inFIG. 1 a before (black dots) and after (red solid line) two minutes of ozone treatment. As shown, ozone treatments for two minutes resulted in significant device performance enhancements in terms of S, VT and Ion. Compared to as-fabricated devices, the value was reduced from 600 mV/dec to 160 mV/dec along with improvement in the Ion/Ioff (˜106), and a shift in VT from −1.16 V to −0.27 V. Without wishing to be bound by any particular theory, the improvement in the S value can be due to the change in terms of a reduction in the interfacial trap states and in fixed surface charge states. See e.g., Ju, S. et al., Appl. Phys. Lett., 89: 193506-1-3 (2006). Ozone treatment not only can remove defects and contamination from the nanowire surface, but can also change the work function. See e.g., Lang, O. et al., J. Appl. Phys., 86: 5687-5691 (1999) and Gassenbauer, Y. et al., Phys. Review B, 73: 245312-1-11 (2006). Ozone is also expected to increase the density of oxygen vacancies near the nanowire surface. Because oxygen vacancies can act as donor states, ozone treatment can increase the conductivity of the nanowire. Although the ITO and IZO microstructures and chemical bonding states are somewhat more complex, the basic crystal structures are sufficiently similar to those of In2O3 and ZnO to reasonably expect that the In2O3 and ZnO nanowire work functions will increase similarly upon ozone treatment. Thus, the source/drain-nanowire contact should not significantly change on ozone treatment. However, and again without wishing to be bound by any particular theory, because the ozone treatment can plausibly reduce nanowire surface dangling bonds and carbon contamination and can form an oxygen vacancy-rich surface, transistor characteristics including Ion/Ioff, S, and VT are expected to be enhanced. See Kim, S. Y. et al., J. Appl. Phys., 95: 2560-2563 (2004). -
FIG. 2 c shows the log-scale drain current versus gate-source voltage (Ids-Vgs) characteristics of a representative In2O3 NWT device analogous to the one illustrated inFIG. 1 a during four successive sweeps from −2 V to +2 V, illustrating the stability of the In2O3 NWTs of the present teachings. The Ids-Vgs curves are comparable following bias sweeps, with consistent Ion/Ioff, S, and VT values. Furthermore, for the same device, Ids-Vgs curves were swept from negative gate voltage (Vg(−)) to positive gate voltage (Vg(+)) and back to Vg(−) as shown inFIG. 2 d. Over this bias range, the hysteresis is modest, which illustrates the high quality of the Al2O3 gate insulator and indicates negligible charge trapping and detrapping in the gate insulator. -
FIGS. 3 a and 3 c show the drain current versus gate-source voltage (Ids-Vgs) characteristics for representative single In2O3 and ZnO NWTs. The In2O3 device (same device as inFIGS. 2 a and 2 b) exhibited S=160 mV/dec, Ion/Ioff=106, and VT=−0.27 V. The μeff of the representative In2O3 NWT, deduced from transconductance (gm=dId/dVg) varied from ˜514 to 300 cm2N-sec as the gate bias was increased from 0 V to 2 V, following a trend that is observed in NWTs, TFTs and MOSFETs. The ZnO NWT device exhibited S=0.3 V/dec, Ion/Ioff˜106, VT=−0.07 V, and μeff varied from ˜96 to 70 cm2/V-sec over the gate bias range of 0 V to 3 V. One important device performance metric for high-speed and low-power operation is the S=dVgs/d log Ids (mV/dec). A small S value is required for switching transistors, ideally approaching the theoretical limit of about 60 mV/dec. The present S values were extracted from the linear portion of the log Ids versus Vgs plot (FIGS. 3 a and 3 c). The very small S values in the In2O3 and ZnO devices of the present teachings are comparable with those of previously reported non-transparent In2O3 and ZnO NWT devices. See Liu, F. et al., Appl. Phys. Lett., 86: 213101-1-3 (2005) and Chang, P.-C. et al., Appl. Phys. Lett., 89: 133113 (2006). -
FIGS. 3 b and 3 d show the drain current versus drain-source voltage (Ids-Vds) characteristics of representative fully transparent single In2O3 and ZnO NWTs according to the present teachings. These devices exhibited typical enhancement mode long-channel FET behavior. For the fully transparent In2O3 single NWT device, Ion is about 1×10−5 μA at Vds=1.0 V and Vgs=2.0 V. The Ion of a ZnO single NWT device was about 2 μA at Vds=1.0 V and Vgs=2.0 V. The performance of these In2O3 and ZnO NWT devices is comparable with that of previously reported non-transparent In2O3 and ZnO NWT devices. See e.g., Liu, F. et al., Appl. Phys. Lett., 86: 213101-1-3 (2005); Chang, P.-C. et al., Appl. Phys. Lett., 89: 133113 (2006); Zhang, D. et al., Appl. Phy. Lett., 82: 112-114 (2003); Cha, S. N. et al., Appl. Phy. Lett., 89: 263102-1-3 (2006); Moon, T.-H. et al., Nanotechnology, 17: 2113-2121 (2006); Ju, S. et al., Nano. Lett., 5: 2281-2286 (2005). Because the extraction procedure for μeff involves uncertainties due to the required capacitance estimation (see Example 4 infra), NWTs can be compared to planar transistors by comparing the Ion and gm per unit width (gm/W), using the nanowire diameter as the device width. The In2O3 nanowire on glass exhibited an Ion density of about 600 mA/mm and a gm/W of ˜212 mS/mm. Both values are more than 5 times higher than those obtained in prior studies on transparent transistors using In2O3 thin films, even after adjusting for the differences in gate lengths and gate capacitance. Without wishing to be bound by any particular theory, the single-crystal nature of the nanowires, along with the formation of relatively high quality interfaces, are believed to play key roles. -
FIG. 4 shows the optical transmission spectra through the In2O3 and ZnO NWT structures, with the substrate absorption removed. As shown inFIG. 4 , an average transmittance of greater than about 90% were observed in the visible and near-infrared spectrum for both transistor types. With the substrate included, optical transmissions of about 82% (In2O3 NWT+glass substrate) and about 83% (ZnO NWT+glass substrate) in the 350 nm-1350 nm wavelength range were observed. The NWT array regions measured 1.0″×0.5″ (the glass substrate measured 1.5″×1.0″), and contained 23,000 NWT device patterns. In the embodiments studied, the substrates were entirely covered by the SiO2 buffer layer and the Al2O3 gate insulator. The source/drain regions and the gate regions covered about 45% and about 25% of the total NWT array region, respectively. Due to their small diameter, the optical absorption of the In2O3 and ZnO nanowires should thus be negligible, and the area covered by the nanowires was relatively small compared to the entire NWT array. The observation of a greater than about 90% optical transmission indicates that the transmission losses due to the various layers, including the nanowires, were negligible, and that visible light could readily penetrate the dense NWTs. The inset inFIG. 4 shows a transparent In2O3 NWT device structure, with text on an underlying opaque layer clearly visible. - In some embodiments, NWT devices according to the present teachings can include a flexible plastic substrate. For example, fully transparent and flexible In2O3 NWT devices using a polyethylene terephthalate (PET) plastic substrate (e.g., Melinex, DuPont) were fabricated and characterized. A cross-sectional view of a representative fully transparent and flexible In2O3 NWT device structure with an individually addressed bottom gate is shown in
FIG. 5 a. Specific embodiments of such devices can include a single In2O3 nanowire addressed between the source and drain contacts having D and L of 20 nm and 1.79 μm, respectively. The gate and source/drain electrodes can be made from ITO. To suppress the leakage current due to tensile/compressive stress of the plastic substrate during photolithographic processing (up to 130° C.) and gate insulator deposition (up to 200° C.), a relatively thick Al2O3 gate insulator (50 nm) can be used.FIG. 5 b is a photographic image of a plastic substrate (PET) containing arrays of In2O3 NWTs according to these embodiments, showing their optical clarity and mechanical flexibility. -
FIG. 5 c shows the optical transmission spectrum of one of the transistor array regions containing In2O3 NWTs on the plastic substrate (ITO(S/D)/In2O3 NWs/Al2O3/ITO(G)/plastic substrate) shown inFIG. 5 b. The optical transmission through the NWT structure and substrate was measured to be about 81% in the 350 nm-1350 nm wavelength range.FIG. 5 d shows the Ids-Vgs characteristic of a representative single In2O3 NWT on the plastic substrate. The S value was determined to be about 0.9 V/dec, Ion/Ioff was in the order of 105, VT=−0.6 V, and μeff varied from ˜167 to 120 cm2N-sec over the gate bias range of 1 V to 3.5 V. The lower but respectable response characteristics on the plastic substrate could reflect the effects of high temperature deposition (300° C.) and post rapid thermal annealing (RTP, 500° C. for 30 s in N2). - As an alternative to using inorganic oxides as the gate dielectric, NWTs of the present teachings can include a gate dielectric made from an organic multi-layered composition. This multi-layered composition can include periodically alternating layers of one or more layers that include a polarizable moiety, and one or more layers that include a silyl or siloxane moiety. In particular embodiments, these layers can be individually self-assembled monolayers. Synthesis of such self-assembled nanodielectric (SAND) materials are more fully described in Yoon, M-H. et al., PNAS, 102 (13): 4678-4682 (2005), which is incorporated by reference herein in its entirety.
- In a preliminary study, nanowire transistors using individual In2O3 nanowires as the channel material and a ˜15 nm thick SAND as the dielectric (capacitance ˜180 nF/cm2 and leakage current density ˜1×10−6 A/cm2 up to 2.0 V) were investigated. The NWTs studied used an individually addressable indium zinc oxide (IZO) bottom-gate and Al source/drain electrodes (
FIG. 6 ), which rendered the channel region completely transparent. The diameter and length of the In2O3 nanowires were 20 nm and 1.6 μm, respectively. The device characteristics (FIG. 7 ) following ozone treatment to improve and optimize the device performance exhibited n-type transistor characteristics with a subthreshold slope (S) of 0.2 V/dec, a current on-off ratio (Ion/Ioff) of 106, a threshold voltage (VT) of 0.0 V, and transconductance (gm) and channel conductance (gd) as illustrated inFIG. 8 . The gm at Vd=0.5 V peaked at ˜5.87 μS, and the gd was proportional with the gate voltage. The drain current versus drain-source voltage (Ids-Vds) characteristics of a representative SAND-based In2O3 NWT are shown inFIG. 7 b. The device exhibited high Ion˜12 μA for the single In2O3 nanowire at Vds=1 V, Vgs=1.5 V, respectively. This current level would be sufficient to drive a 71×213 μm pixel at 300 cd/m2 in current-generation electroluminescent technologies. The field-effect mobility (μeff) which was extracted from the gm and gd of the NWTs, along with an estimated gate-to-channel capacitance, is also plotted versus gate bias inFIG. 7 a. The value of μeff varied from ˜1447 cm2N-sec to ˜300 cm2N-sec over the reported gate bias range. The peak value was much higher than recently reported results for In2O3 nanowires (electron mobility of 279 cm2N-sec and 98.1 cm2N-sec, effective mobility 6.93 cm2N-sec) and ideal single-crystal In2O3 bulk mobility (˜160 cm2N-sec). Without wishing to be bound by any particular theory, it is believed that the single crystal nature of the nanowires, along with the quasi-one-dimensional nature of nanowires which inhibits low-angle scattering, could contribute to the relatively high μeff. As shown, the SAND dielectric also appeared suitable for realizing relatively high performance in oxide nanowires. The device performance of SAND-based NWTs according to the present teachings is better than other In2O3 nanowire transistors and comparable with poly-Si TFTs and α-Si TFTs, in terms of S and μeff. Because it is desirable to obtain high μeff and a steep S to fabricate fast switching transistors and high-speed logic electronic devices, these results indicate that SAND-based In2O3 NWTs can support the requirements of these devices. - Possible applications of the present transparent NWTs include pixel drivers for active matrix displays such as active matrix liquid crystal displays (AMLCDs), active matrix light-emitting diodes (AMLEDs), and active matrix organic light-emitting diodes (AMOLEDs). For example, for AMOLEDs, increasing the aperture ratio is necessary to increase efficiency and reduce power consumption. For non-transparent transistors, maximizing the aperture ratio corresponds to minimizing the transistor and capacitor physical sizes. Transparent transistors would allow stacking of the drive transistors with the OLEDs, which would allow a larger transistor size (width/length) and capacitor size (single or dual capacitors). Device geometries could then be optimized to improve metrics such as peak luminescence, Commission Internationale de L'Eclairage Coordinates (CIE), and power consumption. Importantly, the present NWTs can exhibit relatively high performance in comparison to typical TFTs for display applications, which should allow higher operating speeds and/or smaller device areas. For instance, in order to produce white peak luminance of ˜300 cd/m2 (71×213 μm pixel size, 40% aperture ratio, 40% polarizer transmission, 5.1 cd/A of red, 13 cd/A of green, 5.7 cd/A of blue, and (0.31, 0.32) of white CIE) using phosphorescent materials, driving transistors on RGB pixels must provide ˜2.44 μA (red), ˜1.01 μA (green), ˜1.46 μA (blue) and ˜3.9 μA (white), respectively. The present transparent NWTs were found to be suitable for switching and driving transistors on such pixels. It is also expected that the required current for AMOLED operation will decrease with the increasing aperture ratio provided by all-transparent components. The realization of flexible and transparent NWTs such as those according to the present teachings therefore could also enable high resolution and low-power consumption products such as heads-up displays.
- Accordingly, the present teachings also provide fully transparent transistor display circuit elements (e.g., usable to drive a AM display), in which the switching and driving circuits are comprised of transistors using In2O3 nanowires as active channel materials. In some embodiments, these transistors can include a multilayer self-assembled gate dielectric (SAND) as a gate insulator and indium tin oxide (ITO) as transparent conductive gate and S-D electrodes. For these devices, a coplanar transistor structure consisting of ITO S-D electrodes/In2O3 NW/SAND/bottom ITO gate electrodes can be used. A robust gate insulator typically is required to maintain high breakdown voltage and low density of defect states. Use of the SAND dielectric (thickness ˜24 nm) can ensure high μeff, a steep S, low operating voltage and a high on-off current ratio (Ion/Ioff).
-
FIG. 9 shows FE-SEM images of several 54×176 μm pixels within a 2×2 mm array (30×10 pixels). The equivalent circuit usable for a single active pixel, shown inFIG. 9 c, can include one switching transistor (T1), two driving transistors (T2 and T3) and one storage capacitor (Cst). Using optimized layout design, the transparent driving and switching NWTs regions can allow significant reductions in the area of the transistor circuitry.FIG. 9 d shows an FE-SEM image of representative In2O3 nanowires which are connected between S-D electrodes. In the embodiments shown, the ITO gate overlaps with the ITO S-D electrodes to ensure gating of the full length of the nanowire channel, thereby improving transistor performance. Twenty device regions were observed by FE-SEM, and the number of In2O3 nanowires connected between source and drain electrodes on the switching and driving transistors of each pixel were between 4 and 8, with an average value of 6. The diameters of the In2O3 nanowires were between 40 and 50 nm, and the channel lengths distance between S-D electrodes, along axis of each nanowire were between 1.2 and 1.6 μm, respectively. -
FIG. 10 shows the measured current-voltage (I-V) characteristics of representative NWTs. The design of these patterns, including width and length, are exactly same as those of the NWT circuits in the pixel array, except for the addition of extended contact pads for electrical probing. To improve transistor performance, several surface treatments were performed: i) following deposition of nanowires, plasma ashing was performed for 90 seconds in Ar and O2 ambient on only the S-D contact region of nanowires (active regions of nanowires were covered by photoresist); and ii) after ITO metal deposition, active regions of NWTs were subjected to an ozone treatment for 1 minute to remove defects and contamination on the nanowire surface, and change the relative work functions of In2O3 and ITO S-D metals. The electron affinity of In2O3, χIn2 O3 , was 3.7 eV and a surface Fermi level position of EF−EV=3.0 eV, yielding an effective work function ΦIn2 O3 =4.54 eV for n-type material. Based on the work function of ITO (ΦITO=4.9 eV), it is expected that ITO S-D contacts form relatively low barrier height interfaces to n-type In2O3. After these process treatments, the device performance of transistor characteristics in terms of Ion/Ioff, S, and VT was improved significantly. -
FIG. 10 a shows a family of drain current versus gate-source voltage (Ids-Vgs) characteristics for a representative NWT. The tested In2O3 NWTs exhibited an Ion of ˜1 μA (at Vgs=3.0 V, Vds=0.1 V), an Ion/Ioff of 10−5, a VT of 0.1 V, an S value of 0.25 V/dec, and a μeff of ˜258 cm2V−1s−1, respectively. The mobility of SAND-based In2O3 NWTs devices according to the present teachings, therefore, was observed to be compatible or higher than the recently reported results for In2O3 nanowires (electron mobility of 279.05 cm2V−1s−1 and 98.1 cm2V−1s−1, effective mobility 6.93 cm2V−1s−1) and ideal single-crystal In2O3 bulk mobility (˜160 cm2V−1s−1). - Without wishing to be bound by any particular theory, the single crystal nature of the In2O3 nanowire is expected to allow high mobilities by decreasing scattering at the intergrain regions. In addition, the SAND dielectric has previously been found to be suitable for realizing relatively high performance in other oxide nanowires. The inset in
FIG. 10 a shows the hysteresis of the devices for bias sweeps from negative gate voltage (Vg(−)) to positive gate voltage (Vg(+)) and from Vg(+) to Vg(−). The hysteresis was modest over the bias range, which illustrates the high quality of the SAND gate dielectric and In2O3 NW materials, and indicates negligible charge trapping and detrapping in/on the SAND and at the nanowire/SAND interface. -
FIG. 10 d shows the Ion/Ioff, VT and S characteristics of ten representative transistors, with the red lines indicated the average values. The average values of Ion, Ioff, VT and S were 2.73 μA, 143 pA, 0.02 V and 0.35 V/dec, respectively (these values were extracted from Ids-Vgs curves at 0.1 Vds). The drain current versus drain-source voltage (Ids-Vgs) characteristics of representative In2O3NWTs are shown inFIG. 10 b. As can be seen fromFIG. 10 b, these representative In2O3NWTs exhibited typical n-type transistor characteristics. The desirable features of these In2O3 transistors are illustrated by their high Ion˜6 μA at Vds=2.0 V, and Vgs=2.0 V, respectively. In order to operate the transistor circuit, 2.0 V was applied to fully turn on the gate of switching transistor (T1). -
FIG. 10 c shows the measured output current of the circuit (Ids of T2 and T3 in parallel) versus the output voltage (Vdd). The various curves correspond to various values of data line voltage (0 V to 4 V in 0.5 V steps). The steps in data line voltage correspond to changes in Vgs for the drive transistors (T2 and T3). The transistor circuit shows ˜5 μA at Vdd=2.0 V and Vg2=3.0 V. The total capacitance on a unit pixel was calculated to be about 0.25 pF/cm2. Of the 70 transistor circuits that were measured, more than 65 circuits were working uniformly, while 5 circuits showed low on-current levels compared with other transistor circuits. The NWTs circuits showed more than 90% yield. - The higher μeff and steeper S of SAND-based In2O3 NWTs can allow smaller transistor area and can support the requirements of fast switching transistors and high-speed transistors for NW-AMOLED. Faster switching could enable approaches such as direct digital drive of pixels, which would reduce the complexity of interface circuitry.
- The OLED parameters and target display specifications such as the peak RGB luminescence and efficiency, Commission Internationale de L'Eclairage Coordinates (CIE), and power consumptions dictate specific performance levels which must be considered in the design/simulation/extraction of the transistor current levels and minimum storage capacitor size. In order to extract the required current levels sufficient to operate an NW-AMOLED, the target values are as follows: i) target peak luminescence of 300 cd/m2l; ii) target color coordinates of red (0.65, 0.34), green (0.27, 0.63), blue (0.14, 0.16), and white (0.31, 0.32); and iii) EL efficiency of 6 cd/A (red at 300 cd/m2), 23 cd/A (green at 600 cd/m2), and 6 cd/A (blue at 200 cd/m2). Note that a unit pixel size is 54×176 μm, the EL opening area on a unit pixel is 20×106 μm, an aperture ratio is 46%, and polarizer transmission is 40%. As a result, the driving transistors on RGB pixels should provide at least ˜2.44 μA on a unit red pixel, ˜1.01 μA on a unit green pixel, and ˜1.46 μA on a unit blue pixel, respectively. This shows that the current level of SAND-based In2O3 NWTs (˜5 uA on Vdd=2.0 V and Vg2=3.0 V) should be sufficient to drive a 54×176 μm pixel at 300 cd/m2 in current-generation EL device technologies. While poly-Si TFT AMOLED devices can also provide the required drive currents, they require relatively large areas and have relatively low operating voltages. The resolution of the present NWT-integrated arrays is similar to that of a Quarter eXtended Graphics Array (QXGA: resolution of 2048×1536) of a 12-inch display.
FIG. 11 shows the optical transmission spectra through the 2×2 mm nanowire-based region usable for AM-OLED. The optical transmission was measured to be about 72% in the 350 nm-1350 nm wavelength range. The inset shows a photographic image of the 1×1 inch glass substrate which consists of three 2×2 mm transistor arrays, 340 unit pixels, 80 test NWT devices, 6 alignment marks, 20 test patterns, and contact pads. - The following examples are provided to illustrate further and to facilitate the understanding of the present teachings and are not in any way intended to limit the invention.
- A 500 nm thick layer of SiO2 was deposited by plasma-enhanced chemical vapor deposition (PECVD) on Corning 1737 glass substrates and served as a buffer and planarization layer. Individual gate electrodes were formed by sputtering IZO (Rsheet=40Ω/□) and by ion-assisted deposition (IAD) at room temperature (Rsheet=60Ω/□) and subsequent patterning by photolithography and etching. An 18 nm thick layer of Al2O3 was then deposited using atomic layer deposition (ALD) at 300° C. in an ASM Microchemistry F-120 ALCVD™ system using trimethyl aluminum (Al(CH3)3) (TMA) and water as precursors. Following Al2O3 deposition, the substrates were annealed at 500° C. for 30 seconds under N2 to improve the film quality. Next, a suspension of In2O3 or ZnO nanowires in VLSI grade 2-propanol solution was disbursed on the gate-patterned substrates. Single-crystal semiconducting In2O3 nanowires were synthesized by a pulsed laser ablation process (see Li, C. et al., Adv. Mater., 15: 143-145 (2003)), with average diameter and length of 20 nm and 5 μm, respectively. Powdered ZnO nanowires synthesized by thermal evaporation and condensation were purchased from Nanolab Inc. The average diameter and length were 120 nm and 5 μm, respectively, and microstructural characterization indicated that they were highly crystalline (see Banerjee, D. et al. Nanotechnology, 15: 404-409 (2004)). Finally, ITO source/drain electrodes were deposited by IAD at room temperature and patterned by photolithography. Following source/drain electrode patterning, the NWTs, while shielded from UV light, were subjected to an ozone treatment (UV-Ozone cleaner, UVO 42-220, Jelight Co. Ltd.) for 2 minutes to achieve optimum transistor performance in terms of Ion, Ion:Ioff, S, and μeff. The ozone environment was obtained by setting the oxygen content to 50 ppm, the UV wavelength to 184.9 nm and UV lamp power to 28 milliwatts per cm2 at 254 nm. Fully transparent and flexible In2O3 NWT devices using PET (Melinex, DuPont) also were fabricated with a PET/ITO(G)/Al2O3/In2O3 nanowire/ITO(S/D) structure (
FIG. 5 a). The 50 nm thick layer of Al2O3 layer was deposited at 200° C. ITO for the gate and source/drain electrodes was deposited by IAD. The lengths of the nanowires of given transistors between source and drain were obtained from the FE-SEM images, and accounted for the angle between the nanowire and the electrode edges. - The 200 nm thick layer of SiO2 was deposited on Corning 1737A glass substrates as a buffer layer for planarization. The 100 nm thick ITO thin film was deposited by IAD at room temperature (Rsheet=60 ohms per square), and subsequently patterned by photolithography for individually addressed bottom gate electrodes. A 24 nm thick layer of SAND was then deposited on the patterned ITO gate metals using a self-assembly method. Following SAND deposition, contact holes were patterned for anode opening for electroluminescence and bottom gate electrode contacts on the pixel. Next, a suspension of In2O3 nanowires in VLSI grade 2-propanol solution was disbursed on the device substrates. Single-crystal semiconducting In2O3 nanowires were synthesized by a pulsed laser ablation process, with average diameter and length of 50 nm and 5 μm, respectively. Al source/drain contacts were fabricated by spattering. In the case of ITO S-D electrodes, they were deposited by IAD at room temperature and patterned by lift-off method. Nanowires on the unnecessary regions were removed by ultrasonication except nanowires which were addressed between S-D electrodes. Following S-D electrode patterning, the NWTs, while shielded from UV light, were subjected to an ozone treatment using UV-Ozone cleaner for 1 minute to achieve optimum transistor performance in terms of Ion, Ion:Ioff, S, and μeff. After ozone treatment, the devices were passivated by depositing a 200 nm of e-beam evaporated SiO2 as a passivation layer to planarize NWTs array for EL deposition.
- A 200 nm thick SiO2 layer was deposited on Si or Corning 1737A glass substrates as a buffer layer for planarization. A 100 nm thick ITO thin film was deposited by ion-assisted deposition (IAD) at room temperature (Rsheet=60 ohms per square), and subsequently patterned by photolithography for individually addressed bottom gate electrodes. A 15 nm thick layer of SAND was then deposited on the patterned ITO gate metals using a self-assembly method. Next, a suspension of SnO2 nanowires in VLSI grade 2-propanol solution was disbursed on the device substrates. Al source/drain contacts were fabricated by spattering. ITO S-D electrodes were deposited by IAD at room temperature and patterned by a lift-off method. Nanowires on the unnecessary regions were removed by ultrasonication except nanowires which were addressed between S-D electrodes.
-
FIG. 12 shows the structure and electrical characteristic of a representative single SnO2 NWT using SAND as the gate dielectric. Different substrates (Si—SiO2, Glass-SiO2) and source/drain contact (Al, ITO) materials were used. For these devices, typical performance before ozone treatment were: S=0.1-0.4 V/dec, Ion/Ioff˜105-106, VT=±0.2 V, and μeff varied from ˜15 to 30 cm2N-sec over the gate bias range of 1 V to 4 V. Improved device performance is expected with ozone treatment and encapsulation. - A 200 nm thick SiO2 was deposited on Si or Corning 1737A glass substrates as a buffer layer for planarization. A 100 nm thick ITO thin film was deposited by ion-assisted deposition (IAD) at room temperature (Rsheet=60 ohms per square), and subsequently patterned by photolithography for individually addressed bottom gate electrodes. A 15 nm thick layer of SAND was then deposited on the patterned ITO gate metals using a self-assembly method. Next, a suspension of p- or n-type Ge nanowires in VLSI grade 2-propanol solution was disbursed on the device substrates. Al source/drain contacts were fabricated by spattering. ITO S-D electrodes were deposited by IAD at room temperature and patterned by a lift-off method. Nanowires on the unnecessary regions were removed by ultrasonication except nanowires which were addressed between S-D electrodes.
-
FIG. 13 shows the structure and electrical characteristic of representative single p-type and n-type Ge NWTs using SAND as the gate dielectric. Different substrates (Si—SiO2, Glass-SiO2) and source/drain contact (Al, ITO) materials were used. For the p-type Ge NWTs, typical performance before ozone treatment were: S˜1 V/dec, Ion/Ioff˜106, VT=0−(−1) V, and μeff˜30 to 50 cm2/V-sec over the gate bias range of −1 V to −5 V. For the n-type Ge NWTs, typical performance before ozone treatment were: S˜1 V/dec, Ion/Ioff˜104-105, VT=0−1 V, and μeff˜8 to 12 cm2/V-sec over the gate bias range of −1 V to +5 V. Improved device performance is expected with ozone treatment and encapsulation. -
FIG. 14 shows photographic images of NW-AMOLED substrates (top row) and NWT channel regions (bottom row) according to the present teachings, specifically, in which the semiconducting nanowires are as follows: a) In2O3, b) SnO2, and c) p-type Ge. The respective device structures consist of a glass-SiO2 substrate, an ITO gate electrode, a SAND gate dielectric, ITO source/drain electrodes, and a single nanowire channel region of In2O3 (FIG. 14 a), SnO2 (FIG. 14 b), or Ge (FIG. 14 c). As shown inFIG. 14 , the Ge-based devices have similar optical transparency compared to similar devices based on metal oxide nanowires. - The work function of an as-grown ITO thin film was measured using an AC-2, RKI Instruments photoelectron spectrometer. The UV-Vis spectra were recorded with a Varian Cary 1 E spectrophotometer. Electrical I-V measurements were performed using a Keithley 4200 semiconductor characterization system. The NWs within a device were imaged with a Hitachi S-4800 FE-SEM following electrical characterization.
- In contrast to planar transistors in which carrier concentration and mobility can be determined independently, e.g., through the Hall effect and conductivity measurements, the lack of extended lateral geometries in NWTs dictates an alternative approach for determining mobility. Following the typical approach from prior NWT studies, field effect mobilities (μeff) were calculated using a combination of the cylinder-on-plate (COP) capacitance model
-
- and the relationship
-
- obtained from the MOSFET linear region model (see Wang, D. et al., Appl. Phys. Lett., 83: 2432-2434 (2003)), where keff˜9.0 is the effective dielectric constant of Al2O3, L is the channel length of the NWTs (˜1.80 μm for In2O3 NW, ˜1.66 μm for ZnO NW), where keff˜9.0 is the effective dielectric constant of Al2O3, L is the channel length of the NWTs (˜1.80 μm for In2O3 NW, ˜1.66 μm for ZnO NW), r is the radius of the NWTs (10 nm for In2O3 NW, 60 nm for ZnO NW), tox˜18 nm is the thickness of gate insulator, dIds/dVgs is the transconductance, and Vds is drain voltage. In the case of flexible and transparent In2O3 NWTs, L˜1.79 μm and r˜10 nm were used. The geometry of certain devices disclosed herein consisted of the gate dielectric (keff˜9) below and air (keff˜1) above the nanowire. A prior comparison (see, Vashaee, D. et al., J. Appl. Phy., 99: 54310-1-5 (2006)) between electrostatic simulations and an analytic formula for capacitance (a form of the COP equation valid for tox>>r) for a comparable geometry with SiO2/air showed good agreement between the two capacitances over a range of tox/r from 8 to 40, provided that a value of keff=0.5∈R1SiO2 was used. Because the geometry of the tested devices used a higher k dielectric constant and smaller tox/r (˜1.8), the fringing fields were more tightly confined to the gate dielectric layer. Accordingly, a value of keff˜∈R1Al2O3 was chosen, which would tend to overestimate the capacitance (as the appropriate correction factor is greater than 0.5 but less than 1.0), and therefore underestimate the mobility. The transconductances shown in
FIGS. 3 a, 3 b and 4 d have been smoothed by polynomial fit to 3 orders with 20 points fit to the curve. In order to extract VT, the extrapolated -
- was used as it gives an accurate VT. The gate voltage at the maximum gm (Vg(gm
— max)), the drain current at the maximum gm, Id(gm— max), and the maximum gm (gm— max) were obtained fromFIGS. 3 a, 3 c and 5 d. These values were confirmed with VT values obtained from the Ids-Vds curve at Vd=0.1 V. - The present teachings encompass embodiments in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments are therefore to be considered in all respects illustrative rather than limiting on the present teachings described herein. Scope of the present invention is thus indicated by the appended claims rather than by the foregoing description, and all changes that come within the meaning and range of equivalency of the claims are intended to be embraced therein.
Claims (27)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/065,396 US20110253970A1 (en) | 2007-06-01 | 2011-03-21 | Transparent nanowire transistors and methods for fabricating same |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US93263607P | 2007-06-01 | 2007-06-01 | |
US12/131,697 US7910932B2 (en) | 2007-06-01 | 2008-06-02 | Transparent nanowire transistors and methods for fabricating same |
US13/065,396 US20110253970A1 (en) | 2007-06-01 | 2011-03-21 | Transparent nanowire transistors and methods for fabricating same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/131,697 Continuation US7910932B2 (en) | 2007-06-01 | 2008-06-02 | Transparent nanowire transistors and methods for fabricating same |
Publications (1)
Publication Number | Publication Date |
---|---|
US20110253970A1 true US20110253970A1 (en) | 2011-10-20 |
Family
ID=40381316
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/131,697 Active 2028-08-08 US7910932B2 (en) | 2007-06-01 | 2008-06-02 | Transparent nanowire transistors and methods for fabricating same |
US13/065,396 Abandoned US20110253970A1 (en) | 2007-06-01 | 2011-03-21 | Transparent nanowire transistors and methods for fabricating same |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/131,697 Active 2028-08-08 US7910932B2 (en) | 2007-06-01 | 2008-06-02 | Transparent nanowire transistors and methods for fabricating same |
Country Status (3)
Country | Link |
---|---|
US (2) | US7910932B2 (en) |
KR (1) | KR20100047828A (en) |
WO (1) | WO2009038606A2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120132902A1 (en) * | 2010-11-26 | 2012-05-31 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI221341B (en) * | 2003-09-18 | 2004-09-21 | Ind Tech Res Inst | Method and material for forming active layer of thin film transistor |
US7910932B2 (en) * | 2007-06-01 | 2011-03-22 | Northwestern University | Transparent nanowire transistors and methods for fabricating same |
US8030212B2 (en) * | 2007-09-26 | 2011-10-04 | Eastman Kodak Company | Process for selective area deposition of inorganic materials |
US8043978B2 (en) * | 2007-10-11 | 2011-10-25 | Riken | Electronic device and method for producing electronic device |
US8017458B2 (en) * | 2008-01-31 | 2011-09-13 | Northwestern University | Solution-processed high mobility inorganic thin-film transistors |
US8232544B2 (en) * | 2008-04-04 | 2012-07-31 | Nokia Corporation | Nanowire |
US8236680B2 (en) * | 2008-06-20 | 2012-08-07 | Northwestern University | Nanoscale, spatially-controlled Ga doping of undoped transparent conducting oxide films |
KR100963104B1 (en) * | 2008-07-08 | 2010-06-14 | 삼성모바일디스플레이주식회사 | Thin film transistor, method of manufacturing the thin film transistor and flat panel display device having the thin film transistor |
KR101497425B1 (en) * | 2008-08-28 | 2015-03-03 | 삼성디스플레이 주식회사 | Liquid crystal display and method of manufacturing the same |
US7989800B2 (en) * | 2008-10-14 | 2011-08-02 | George Mason Intellectual Properties, Inc. | Nanowire field effect junction diode |
KR101100999B1 (en) * | 2009-01-13 | 2011-12-29 | 삼성모바일디스플레이주식회사 | CMOS Thin Film Transistor and fabrication method thereof and Organic Light Emitting Display device using thereof |
KR101048965B1 (en) * | 2009-01-22 | 2011-07-12 | 삼성모바일디스플레이주식회사 | Organic electroluminescent display |
DE102009014757A1 (en) * | 2009-03-27 | 2010-10-07 | Polyic Gmbh & Co. Kg | Electrical functional layer, manufacturing method and use thereof |
WO2011007677A1 (en) | 2009-07-17 | 2011-01-20 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
WO2011010542A1 (en) * | 2009-07-23 | 2011-01-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
TWI396314B (en) * | 2009-07-27 | 2013-05-11 | Au Optronics Corp | Pixel structure, organic electro-luminescence display unit, and faricating method thereof |
US8754401B2 (en) * | 2009-08-31 | 2014-06-17 | International Business Machines Corporation | Impact ionization field-effect transistor |
WO2011027701A1 (en) * | 2009-09-04 | 2011-03-10 | Semiconductor Energy Laboratory Co., Ltd. | Light-emitting device and method for manufacturing the same |
WO2011027676A1 (en) | 2009-09-04 | 2011-03-10 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
KR101930230B1 (en) | 2009-11-06 | 2018-12-18 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Method for manufacturing semiconductor device |
JP5491835B2 (en) * | 2009-12-02 | 2014-05-14 | グローバル・オーエルイーディー・テクノロジー・リミテッド・ライアビリティ・カンパニー | Pixel circuit and display device |
KR20170116239A (en) | 2009-12-11 | 2017-10-18 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Field effect transistor |
WO2011073044A1 (en) * | 2009-12-18 | 2011-06-23 | Basf Se | Metal oxide field effect transistors on a mechanically flexible polymer substrate having a dielectric that can be processed from solution at low temperatures |
US8759917B2 (en) * | 2010-01-04 | 2014-06-24 | Samsung Electronics Co., Ltd. | Thin-film transistor having etch stop multi-layer and method of manufacturing the same |
US8697467B2 (en) * | 2010-07-26 | 2014-04-15 | The Regents Of The University Of California | Surface and gas phase doping of III-V semiconductors |
KR101759577B1 (en) * | 2010-08-23 | 2017-07-19 | 삼성전자 주식회사 | On-cell TSP active matrix organic light emitting diode structure |
KR101234539B1 (en) * | 2011-01-25 | 2013-02-19 | 연세대학교 산학협력단 | Field effect transistor having random network arrays and method for manufacturing the field effect transistor |
US8987710B2 (en) * | 2011-05-19 | 2015-03-24 | Polyera Corporation | Carbonaceous nanomaterial-based thin-film transistors |
KR101355893B1 (en) * | 2012-11-02 | 2014-01-28 | 경북대학교 산학협력단 | Active image sensor and fabricating method thereof |
US9018660B2 (en) * | 2013-03-25 | 2015-04-28 | Universal Display Corporation | Lighting devices |
CN103943683B (en) * | 2013-12-06 | 2017-12-26 | 山东大学(威海) | A kind of indium tin zinc oxide homogeneity thin film transistor (TFT) and preparation method thereof |
US10692621B2 (en) | 2015-01-30 | 2020-06-23 | Kuprion Inc. | Method of interconnecting nanowires and transparent conductive electrode |
KR20170018718A (en) * | 2015-08-10 | 2017-02-20 | 삼성전자주식회사 | Transparent electrode using amorphous alloy and method for manufacturing the same |
CN106847701B (en) * | 2017-03-20 | 2020-08-25 | 青岛大学 | Preparation method of metal-doped zinc oxide nanofiber field effect transistor |
KR20220006541A (en) | 2019-05-10 | 2022-01-17 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Display devices and electronic devices |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7910932B2 (en) * | 2007-06-01 | 2011-03-22 | Northwestern University | Transparent nanowire transistors and methods for fabricating same |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6306594B1 (en) * | 1988-11-14 | 2001-10-23 | I-Stat Corporation | Methods for microdispensing patterened layers |
US5156918A (en) | 1991-03-28 | 1992-10-20 | Northwestern University | Self-assembled super lattices |
EP0913965A1 (en) | 1997-11-03 | 1999-05-06 | Canon Kabushiki Kaisha | Reduction of the message traffic in a distributed network |
US6855274B1 (en) | 2000-03-22 | 2005-02-15 | Northwestern University | Layer by layer self-assembly of large response molecular electro-optic materials by a desilylation strategy |
US6863943B2 (en) * | 2001-01-12 | 2005-03-08 | Georgia Tech Research Corporation | Semiconducting oxide nanostructures |
US7049625B2 (en) | 2002-03-18 | 2006-05-23 | Max-Planck-Gesellschaft Zur Fonderung Der Wissenschaften E.V. | Field effect transistor memory cell, memory device and method for manufacturing a field effect transistor memory cell |
US7294417B2 (en) * | 2002-09-12 | 2007-11-13 | The Trustees Of Boston College | Metal oxide nanostructures with hierarchical morphology |
US7135728B2 (en) * | 2002-09-30 | 2006-11-14 | Nanosys, Inc. | Large-area nanoenabled macroelectronic substrates and uses therefor |
US7051945B2 (en) | 2002-09-30 | 2006-05-30 | Nanosys, Inc | Applications of nano-enabled large area macroelectronic substrates incorporating nanowires and nanowire composites |
TWI229463B (en) * | 2004-02-02 | 2005-03-11 | South Epitaxy Corp | Light-emitting diode structure with electro-static discharge protection |
US20060003485A1 (en) | 2004-06-30 | 2006-01-05 | Hoffman Randy L | Devices and methods of making the same |
US7405129B2 (en) * | 2004-11-18 | 2008-07-29 | International Business Machines Corporation | Device comprising doped nano-component and method of forming the device |
WO2008089401A2 (en) | 2007-01-18 | 2008-07-24 | Arizona Board Of Regents, Acting For And On Behalfof Arizona State University | Flexible transparent electrodes via nanowires and sacrificial conductive layer |
-
2008
- 2008-06-02 US US12/131,697 patent/US7910932B2/en active Active
- 2008-06-02 WO PCT/US2008/006946 patent/WO2009038606A2/en active Application Filing
- 2008-06-02 KR KR1020097027533A patent/KR20100047828A/en not_active Application Discontinuation
-
2011
- 2011-03-21 US US13/065,396 patent/US20110253970A1/en not_active Abandoned
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7910932B2 (en) * | 2007-06-01 | 2011-03-22 | Northwestern University | Transparent nanowire transistors and methods for fabricating same |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120132902A1 (en) * | 2010-11-26 | 2012-05-31 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US8936965B2 (en) * | 2010-11-26 | 2015-01-20 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
WO2009038606A2 (en) | 2009-03-26 |
WO2009038606A3 (en) | 2009-06-11 |
KR20100047828A (en) | 2010-05-10 |
US20090050876A1 (en) | 2009-02-26 |
WO2009038606A9 (en) | 2009-05-14 |
US7910932B2 (en) | 2011-03-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7910932B2 (en) | Transparent nanowire transistors and methods for fabricating same | |
Ju et al. | Fabrication of fully transparent nanowire transistors for transparent and flexible electronics | |
US10403757B2 (en) | Top-gate self-aligned metal oxide semiconductor TFT and method of making the same | |
US8759917B2 (en) | Thin-film transistor having etch stop multi-layer and method of manufacturing the same | |
US11594639B2 (en) | Thin film transistor, thin film transistor array panel including the same, and method of manufacturing the same | |
JP5562587B2 (en) | Transistor | |
TWI543379B (en) | Thin film transistor and method of producing the same, display device, image sensor, x-ray sensor, and x-ray digital imaging device | |
CN102403361B (en) | Thin-film transistor and manufacture method thereof and possess the device of this thin-film transistor | |
KR102418493B1 (en) | Thin film trnasistor comprising 2d semiconductor and display device comprising the same | |
Park et al. | Influence of illumination on the negative-bias stability of transparent hafnium–indium–zinc oxide thin-film transistors | |
JP5657433B2 (en) | Thin film transistor manufacturing method, thin film transistor, display device, sensor, and X-ray digital imaging device | |
US20180219055A1 (en) | Flexible vertical channel organic thin film transistor and manufacture method thereof | |
US20140239291A1 (en) | Metal-oxide semiconductor thin film transistors and methods of manufacturing the same | |
CN102082170A (en) | Amorphous oxide semiconductor material, field-effect transistor, and display device | |
US8729529B2 (en) | Thin film transistor including a nanoconductor layer | |
KR102212999B1 (en) | Thin Film Transistor Based on Graphine Comprising N-Dopped Graphine Layer as Active Layer | |
Kandpal et al. | Perspective of zinc oxide based thin film transistors: a comprehensive review | |
Arai et al. | Highly reliable oxide‐semiconductor TFT for AMOLED displays | |
Lee et al. | 16‐1: The role of hydrogen and surface potential in the performance and stability of poly‐Si TFTs on plastic substrates | |
KR20110080118A (en) | Thin film transistor having etch stop multi-layers and method of manufacturing the same | |
JP5901420B2 (en) | Thin film transistor manufacturing method | |
KR101308809B1 (en) | Fabrication method of oxide semiconductor thin film transistor and display devices and sensor device applying it | |
Feng et al. | Bottom-contact organic thin film transistors with transparent Ga-doped ZnO source-drain electrodes | |
Im et al. | Photo-Excited Charge Collection Spectroscopy: Probing the traps in field-effect transistors | |
Ha et al. | A comparison of photo-induced hysteresis between hydrogenated amorphous silicon and amorphous IGZO thin-film transistors |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: PURDUE RESEARCH FOUNDATION, INDIANA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JANES, DAVID B.;JU, SANGHYUN;YE, PEIDE;REEL/FRAME:026069/0744 Effective date: 20080806 Owner name: UNIVERSITY OF SOUTHERN CALIFORNIA, A NOT-FOR-PROFI Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ZHOU, CHONGWU;REEL/FRAME:026069/0551 Effective date: 20080822 Owner name: NORTHWESTERN UNIVERSITY, ILLINOIS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MARKS, TOBIN J.;FACCHETTI, ANTONIO;SIGNING DATES FROM 20080722 TO 20080807;REEL/FRAME:026069/0506 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: USA AS REPRESENTED BY THE ADMINISTRATOR OF THE NAS Free format text: CONFIRMATORY LICENSE;ASSIGNOR:PURDUE UNIVERSITY;REEL/FRAME:037371/0254 Effective date: 20111121 |