US20110007848A1 - Method for calibrating iq matching of receiver - Google Patents
Method for calibrating iq matching of receiver Download PDFInfo
- Publication number
- US20110007848A1 US20110007848A1 US12/498,612 US49861209A US2011007848A1 US 20110007848 A1 US20110007848 A1 US 20110007848A1 US 49861209 A US49861209 A US 49861209A US 2011007848 A1 US2011007848 A1 US 2011007848A1
- Authority
- US
- United States
- Prior art keywords
- signal
- receiver
- mixers
- data
- mismatch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/38—Demodulator circuits; Receiver circuits
- H04L27/3845—Demodulator circuits; Receiver circuits using non - coherent demodulation, i.e. not using a phase synchronous carrier
- H04L27/3854—Demodulator circuits; Receiver circuits using non - coherent demodulation, i.e. not using a phase synchronous carrier using a non - coherent carrier, including systems with baseband correction for phase or frequency offset
- H04L27/3863—Compensation for quadrature error in the received signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
- H04B1/30—Circuits for homodyne or synchrodyne receivers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/20—Monitoring; Testing of receivers
- H04B17/21—Monitoring; Testing of receivers for calibration; for correcting measurements
Definitions
- the present invention relates generally to receivers and more to calibrating the mismatch between I data and Q data in such receivers.
- Receivers are utilized in a variety of environments. They are utilized, for example, in RF transceivers in various applications.
- a radio-frequency (RF) input signal amplified by a low-noise amplifier (LNA) is downconverted to in-phase (I) and quadrature-phase (Q) baseband signals by an I mixer and a Q mixer respectively.
- the local oscillator (LO) ports of the I mixer and the Q mixer are driven by an I local-oscillator (LO) signal and Q LO signal, respectively.
- the I mixer LO signal and Q mixer LO signal are orthogonal (90 degree phase shift) to each other.
- I baseband signal and Q baseband signal are then amplified and filtered by baseband filters and variable-gain amplifiers (VGA) before they are digitized by a pair of analog-to-digital converters (ADCs). Due to random process variation, the I path and Q path are not perfectly matched. This results in phase and amplitude mismatches in the I data and Q data, degrading the reception quality and hence increasing the bit-error rate in a digital communication system.
- VGA variable-gain amplifiers
- a method and system for calibrating the mismatch between I data and Q data of a receiver includes an amplifier, first and second mixers coupled to the amplifier, an oscillator for driving the first and second mixers; and first and second filter coupled to the first and second mixers.
- the method and system comprise turning off the amplifier; and injecting a signal into the first and second mixers.
- the method and system also includes measuring the amplitude and phase information of the I and Q data from the first and second mixers based upon the injected signal to provide mismatch information and utilizing the mismatch information to compensate the I data and the Q data during normal operating mode.
- the IQ mismatch of a receiver can be measured and compensated. This allows, for example, for direct-conversion architecture, which is known to have IQ mismatch problem, to be utilized in an effective manner. Furthermore, if this calibration method is applied to other receiver architectures, the yield loss due to IQ mismatch can be minimized.
- FIG. 1 is a block diagram of the architecture of a direct-conversion receiver in accordance with an embodiment.
- FIG. 2 is a block diagram of the architecture of a heterodyne architecture receiver in accordance with an embodiment.
- the present invention relates generally to receivers and more to calibrating the mismatch between I data and Q data in such receivers.
- the following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements.
- Various modifications to the preferred embodiment and the generic principles and features described herein will be readily apparent to those skilled in the art.
- the present invention is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and features described herein.
- FIG. 1 is a block diagram of the architecture of a direct-conversion receiver 100 in accordance with an embodiment.
- FIG. 1 includes an RF input 102 , a low-noise amplifier (LNA) 104 , an I mixer 106 , a Q mixer 108 , local-oscillator (LO) signals 110 and 112 , a single-tone generator 129 , an I path 114 and a Q path 116 , baseband filters and VGAs 118 and 120 , analog-to-digital converters (ADCs) 122 and 124 for I data 122 and for Q data 124 , and digital circuits 126 .
- LNA low-noise amplifier
- I mixer 106 I mixer 106
- Q mixer 108 local-oscillator
- LO local-oscillator
- ADCs analog-to-digital converters
- the radio-frequency (RF) input signal 102 amplified by the low-noise amplifier (LNA) 104 is downconverted to in-phase (I) 114 and quadrature-phase (Q) 116 baseband signals by the I mixer 106 and Q mixer 108 respectively.
- the LO ports of the I mixer 106 and Q mixer 108 are driven by the I local-oscillator (LO) signal 110 and Q local-oscillator (LO) signal 112 , respectively.
- the I LO signal 110 and Q LO signal 112 are orthogonal (90 degree phase shift) with each other.
- the I baseband signal 114 and Q baseband signal 116 are then amplified and filtered by the baseband filters and variable-gain amplifiers (VGAs) 118 and 120 before they are digitized by a pair of analog-to-digital converters (ADCs) 122 and 124 . Due to random process variation, the I path and Q path are not perfectly matched. This results in phase and amplitude mismatches in the I data 128 and Q data 130 , degrading the reception quality and hence increasing the bit error rate in the receiver 100 of a digital communication system.
- VGAs variable-gain amplifiers
- ADCs analog-to-digital converters
- a single-tone generator 129 is utilized in the receiver during calibration mode.
- the LNA 104 is turned off and the single-tone generator 129 is used to inject a sinusoidal signal, the frequency of which is different from the LO frequency, to the input ports of the I mixer 106 and the Q mixers 108 .
- the resulting sinusoidal I and Q data have exactly the same amplitude and 90-degree phase difference.
- the mismatches in the I and Q signal paths cause the amplitude and phase of the I data and Q data to be different.
- This amplitude and phase mismatch information can be measured by the digital circuits 126 during the calibration mode and then can be used to compensate the I data and Q data during the normal operating mode.
- FIG. 1 is a block diagram of the architecture of a direct-conversion receiver 100
- this IQ mismatch measurement technique can be applied to other receiver architectures as well, such as the block diagram of heterodyne architecture 200 as shown in FIG. 2 .
- the signal-tone generator 228 injects a signal to either the input port (node X) 230 or the output port (node Y) 232 of the first mixer.
- Some heterodyne architectures also use image-rejection architecture (not shown in FIG. 2 ) as the first mixer.
- the single-tone generator 228 can be modified to inject a signal to the input port of the LNA (not shown) in an alternate design. In this case, the LNA cannot be turned off.
- LNA phase-locked loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Superheterodyne Receivers (AREA)
Abstract
Description
- The present invention relates generally to receivers and more to calibrating the mismatch between I data and Q data in such receivers.
- Receivers are utilized in a variety of environments. They are utilized, for example, in RF transceivers in various applications. In a receiver, during normal operating mode, a radio-frequency (RF) input signal amplified by a low-noise amplifier (LNA) is downconverted to in-phase (I) and quadrature-phase (Q) baseband signals by an I mixer and a Q mixer respectively. The local oscillator (LO) ports of the I mixer and the Q mixer are driven by an I local-oscillator (LO) signal and Q LO signal, respectively. The I mixer LO signal and Q mixer LO signal are orthogonal (90 degree phase shift) to each other. An I baseband signal and Q baseband signal are then amplified and filtered by baseband filters and variable-gain amplifiers (VGA) before they are digitized by a pair of analog-to-digital converters (ADCs). Due to random process variation, the I path and Q path are not perfectly matched. This results in phase and amplitude mismatches in the I data and Q data, degrading the reception quality and hence increasing the bit-error rate in a digital communication system.
- Accordingly, what is desired is a system and method to address the IQ mismatch issues The system and method should be cost effective, easily implemented and adaptable to existing receivers. The present invention addresses such a need.
- A method and system for calibrating the mismatch between I data and Q data of a receiver is disclosed. The receiver includes an amplifier, first and second mixers coupled to the amplifier, an oscillator for driving the first and second mixers; and first and second filter coupled to the first and second mixers. The method and system comprise turning off the amplifier; and injecting a signal into the first and second mixers. The method and system also includes measuring the amplitude and phase information of the I and Q data from the first and second mixers based upon the injected signal to provide mismatch information and utilizing the mismatch information to compensate the I data and the Q data during normal operating mode.
- In a method and system in accordance with an embodiment, the IQ mismatch of a receiver can be measured and compensated. This allows, for example, for direct-conversion architecture, which is known to have IQ mismatch problem, to be utilized in an effective manner. Furthermore, if this calibration method is applied to other receiver architectures, the yield loss due to IQ mismatch can be minimized.
- The accompanying drawings illustrate several embodiments of the invention and, together with the description, serve to explain the principles of the invention. One skilled in the art will recognize that the particular embodiments illustrated in the drawings are merely exemplary, and are not intended to limit the scope of the present invention.
-
FIG. 1 is a block diagram of the architecture of a direct-conversion receiver in accordance with an embodiment. -
FIG. 2 is a block diagram of the architecture of a heterodyne architecture receiver in accordance with an embodiment. - The present invention relates generally to receivers and more to calibrating the mismatch between I data and Q data in such receivers. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiment and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and features described herein.
-
FIG. 1 is a block diagram of the architecture of a direct-conversion receiver 100 in accordance with an embodiment.FIG. 1 includes anRF input 102, a low-noise amplifier (LNA) 104, anI mixer 106, aQ mixer 108, local-oscillator (LO)signals tone generator 129, anI path 114 and aQ path 116, baseband filters andVGAs data 122 and forQ data 124, anddigital circuits 126. - As before mentioned, in normal operating mode, the radio-frequency (RF)
input signal 102 amplified by the low-noise amplifier (LNA) 104 is downconverted to in-phase (I) 114 and quadrature-phase (Q) 116 baseband signals by theI mixer 106 andQ mixer 108 respectively. The LO ports of the Imixer 106 andQ mixer 108 are driven by the I local-oscillator (LO)signal 110 and Q local-oscillator (LO)signal 112, respectively. TheI LO signal 110 andQ LO signal 112 are orthogonal (90 degree phase shift) with each other. The Ibaseband signal 114 andQ baseband signal 116 are then amplified and filtered by the baseband filters and variable-gain amplifiers (VGAs) 118 and 120 before they are digitized by a pair of analog-to-digital converters (ADCs) 122 and 124. Due to random process variation, the I path and Q path are not perfectly matched. This results in phase and amplitude mismatches in theI data 128 andQ data 130, degrading the reception quality and hence increasing the bit error rate in thereceiver 100 of a digital communication system. - To solve this IQ mismatch problem, the IQ amplitude and phase mismatch needs to be measured and compensated. In an embodiment to measure this IQ mismatch, a single-
tone generator 129 is utilized in the receiver during calibration mode. In calibration mode, the LNA 104 is turned off and the single-tone generator 129 is used to inject a sinusoidal signal, the frequency of which is different from the LO frequency, to the input ports of theI mixer 106 and theQ mixers 108. In an ideal situation where the I and Q signal paths are perfectly matched, the resulting sinusoidal I and Q data have exactly the same amplitude and 90-degree phase difference. In a practical situation, however, the mismatches in the I and Q signal paths cause the amplitude and phase of the I data and Q data to be different. This amplitude and phase mismatch information can be measured by thedigital circuits 126 during the calibration mode and then can be used to compensate the I data and Q data during the normal operating mode. - Besides the particular implementation described above, there are several variations to this technique. Although
FIG. 1 is a block diagram of the architecture of a direct-conversion receiver 100, this IQ mismatch measurement technique can be applied to other receiver architectures as well, such as the block diagram ofheterodyne architecture 200 as shown inFIG. 2 . In this case, the signal-tone generator 228 injects a signal to either the input port (node X) 230 or the output port (node Y) 232 of the first mixer. Some heterodyne architectures also use image-rejection architecture (not shown inFIG. 2 ) as the first mixer. Beside injecting the signal into the input ports of themixers tone generator 228 can be modified to inject a signal to the input port of the LNA (not shown) in an alternate design. In this case, the LNA cannot be turned off. There are many cost-effective ways to implement the integrated single-tone generators - Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.
Claims (14)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/498,612 US20110007848A1 (en) | 2009-07-07 | 2009-07-07 | Method for calibrating iq matching of receiver |
TW098141665A TW201103290A (en) | 2009-07-07 | 2009-12-07 | Method for calibrating IQ matching of receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/498,612 US20110007848A1 (en) | 2009-07-07 | 2009-07-07 | Method for calibrating iq matching of receiver |
Publications (1)
Publication Number | Publication Date |
---|---|
US20110007848A1 true US20110007848A1 (en) | 2011-01-13 |
Family
ID=43427464
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/498,612 Abandoned US20110007848A1 (en) | 2009-07-07 | 2009-07-07 | Method for calibrating iq matching of receiver |
Country Status (2)
Country | Link |
---|---|
US (1) | US20110007848A1 (en) |
TW (1) | TW201103290A (en) |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030176174A1 (en) * | 2002-03-15 | 2003-09-18 | Nokia Corporation, Espoo Finland | Method and apparatus providing calibration technique for RF performance tuning |
US20030231723A1 (en) * | 2002-06-18 | 2003-12-18 | Broadcom Corporation | Digital estimation and correction of I/Q mismatch in direct conversion receivers |
US20040002318A1 (en) * | 2002-05-31 | 2004-01-01 | Kerth Donald A. | Apparatus and method for calibrating image rejection in radio frequency circuitry |
US20040109514A1 (en) * | 2000-02-17 | 2004-06-10 | Rahul Magoon | Method and apparatus for multiple phase splitting for dual band IQ subharmonic mixer |
US6771720B1 (en) * | 2001-03-30 | 2004-08-03 | Skyworks Solutions, Inc. | Amplification control scheme for a receiver |
US20060262872A1 (en) * | 2000-03-15 | 2006-11-23 | Green Roger A | Vector calibration system |
US20060287009A1 (en) * | 2005-06-16 | 2006-12-21 | Siport, Inc. | Systems and methods for dynamically controlling a tuner |
US7187916B2 (en) * | 2003-02-07 | 2007-03-06 | Broadcom Corporation | Method and system for measuring receiver mixer IQ mismatch |
US7251298B1 (en) * | 2003-08-20 | 2007-07-31 | Rf Micro Devices, Inc. | Receiver architecture eliminating static and dynamic DC offset errors |
US20080130800A1 (en) * | 2006-11-30 | 2008-06-05 | Silicon Laboratories, Inc. | Techniques for performing gain and phase correction in a complex radio frequency receiver |
US20080207136A1 (en) * | 2007-02-20 | 2008-08-28 | Haiyun Tang | High Dynamic Range Tranceiver for Cognitive Radio |
-
2009
- 2009-07-07 US US12/498,612 patent/US20110007848A1/en not_active Abandoned
- 2009-12-07 TW TW098141665A patent/TW201103290A/en unknown
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040109514A1 (en) * | 2000-02-17 | 2004-06-10 | Rahul Magoon | Method and apparatus for multiple phase splitting for dual band IQ subharmonic mixer |
US20060262872A1 (en) * | 2000-03-15 | 2006-11-23 | Green Roger A | Vector calibration system |
US6771720B1 (en) * | 2001-03-30 | 2004-08-03 | Skyworks Solutions, Inc. | Amplification control scheme for a receiver |
US20030176174A1 (en) * | 2002-03-15 | 2003-09-18 | Nokia Corporation, Espoo Finland | Method and apparatus providing calibration technique for RF performance tuning |
US20040002318A1 (en) * | 2002-05-31 | 2004-01-01 | Kerth Donald A. | Apparatus and method for calibrating image rejection in radio frequency circuitry |
US20030231723A1 (en) * | 2002-06-18 | 2003-12-18 | Broadcom Corporation | Digital estimation and correction of I/Q mismatch in direct conversion receivers |
US7187916B2 (en) * | 2003-02-07 | 2007-03-06 | Broadcom Corporation | Method and system for measuring receiver mixer IQ mismatch |
US7251298B1 (en) * | 2003-08-20 | 2007-07-31 | Rf Micro Devices, Inc. | Receiver architecture eliminating static and dynamic DC offset errors |
US20060287009A1 (en) * | 2005-06-16 | 2006-12-21 | Siport, Inc. | Systems and methods for dynamically controlling a tuner |
US20080130800A1 (en) * | 2006-11-30 | 2008-06-05 | Silicon Laboratories, Inc. | Techniques for performing gain and phase correction in a complex radio frequency receiver |
US20080207136A1 (en) * | 2007-02-20 | 2008-08-28 | Haiyun Tang | High Dynamic Range Tranceiver for Cognitive Radio |
Also Published As
Publication number | Publication date |
---|---|
TW201103290A (en) | 2011-01-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101114271B1 (en) | RF receiver mismatch calibration system and method | |
KR101776450B1 (en) | Logarithmic Amplifier with Universal Demodulation Capabilities | |
JP4845437B2 (en) | LO leakage and sideband image calibration system and method | |
CN100459413C (en) | System and method for i-q mismatch compensation in a low if or zero if receiver | |
US6999747B2 (en) | Passive harmonic switch mixer | |
US20060068739A1 (en) | Receiver, receiving method and portable wireless apparatus | |
US9948347B2 (en) | Calibrating a transceiver circuit | |
CN101162910A (en) | Local oscillator leakage automatic eliminator | |
CN101442392A (en) | Apparatus, integrated circuit, and method of compensating iq phase mismatch | |
US8670738B2 (en) | Imbalance compensator for correcting mismatch between in-phase branch and quadrature branch, and related imbalance compensation method and direct conversion receiving apparatus thereof | |
US20120257656A1 (en) | Transceivers having loopback switches and methods of calibrating carrier leakage thereof | |
WO2012038336A1 (en) | Complex intermediate frequency mixer stage and calibration thereof | |
US7949324B2 (en) | Method for compensating transmission carrier leakage and transceiving circuit embodying the same | |
CN105610760B (en) | Wireless comprehensive test instrument is to the unbalanced detection method of single carrier QPSK signal IQ | |
CN104811215A (en) | IQ unbalance compensation device and method | |
CN103580609B (en) | The correcting unit of second order inter-modulation modulation distortion, system and bearing calibration | |
US8537950B2 (en) | Architecture to remove a bimodal dynamic DC offset in direct conversion receiver | |
US20070027649A1 (en) | Method and calibration system for iq dc offset and imbalance calibration by utilizing analytic formulas to quickly determined desired compensation values | |
CN106027172A (en) | Method and device for testing receiver chip | |
GB2438082A (en) | Active and passive dual local oscillator mixers comprising triple gate mixer circuits or exclusive NOR switch (XNOR-SW) circuits. | |
US9042482B2 (en) | FBR DC vector offset removal using LO phase switching | |
US20110007848A1 (en) | Method for calibrating iq matching of receiver | |
CN113517938B (en) | Automatic calibration system for transceiver | |
CN101304256B (en) | Method for eliminating direct current bias | |
US7729451B2 (en) | Calibration source for a receiver |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: RALINK TECHNOLOGY (SINGAPORE) CORPORATION, SINGAPO Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FONG, KENG LEONG;JERNG, ALBERT;LO, CHUNGWEN;REEL/FRAME:022922/0007 Effective date: 20090630 |
|
AS | Assignment |
Owner name: MEDIATEK INC., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:RALINK TECHNOLOGY (SINGAPORE) CORPORATION;REEL/FRAME:026992/0524 Effective date: 20110929 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |