US20100320596A1 - Method for fabricating semiconductor package and semiconductor package using the same - Google Patents
Method for fabricating semiconductor package and semiconductor package using the same Download PDFInfo
- Publication number
- US20100320596A1 US20100320596A1 US12/565,171 US56517109A US2010320596A1 US 20100320596 A1 US20100320596 A1 US 20100320596A1 US 56517109 A US56517109 A US 56517109A US 2010320596 A1 US2010320596 A1 US 2010320596A1
- Authority
- US
- United States
- Prior art keywords
- substrate
- terminal
- solder
- solder layer
- semiconductor package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 91
- 239000004065 semiconductor Substances 0.000 title claims abstract description 74
- 229910000679 solder Inorganic materials 0.000 claims abstract description 153
- 239000000758 substrate Substances 0.000 claims abstract description 143
- 239000002245 particle Substances 0.000 claims abstract description 72
- 239000000203 mixture Substances 0.000 claims abstract description 47
- 239000002952 polymeric resin Substances 0.000 claims abstract description 32
- 229920003002 synthetic resin Polymers 0.000 claims abstract description 32
- 229920005989 resin Polymers 0.000 claims description 70
- 239000011347 resin Substances 0.000 claims description 70
- 230000009969 flowable effect Effects 0.000 claims description 38
- 239000003795 chemical substances by application Substances 0.000 claims description 20
- 238000010438 heat treatment Methods 0.000 claims description 17
- 230000008018 melting Effects 0.000 claims description 11
- 238000002844 melting Methods 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 9
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- UHOVQNZJYSORNB-UHFFFAOYSA-N Benzene Chemical compound C1=CC=CC=C1 UHOVQNZJYSORNB-UHFFFAOYSA-N 0.000 description 6
- YXFVVABEGXRONW-UHFFFAOYSA-N Toluene Chemical compound CC1=CC=CC=C1 YXFVVABEGXRONW-UHFFFAOYSA-N 0.000 description 6
- 239000002904 solvent Substances 0.000 description 5
- 229910000967 As alloy Inorganic materials 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 229910052787 antimony Inorganic materials 0.000 description 4
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 4
- 229910052797 bismuth Inorganic materials 0.000 description 4
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 4
- IISBACLAFKSPIT-UHFFFAOYSA-N bisphenol A Chemical compound C=1C=C(O)C=CC=1C(C)(C)C1=CC=C(O)C=C1 IISBACLAFKSPIT-UHFFFAOYSA-N 0.000 description 4
- 239000003638 chemical reducing agent Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 4
- 239000002923 metal particle Substances 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 230000006835 compression Effects 0.000 description 3
- 238000007906 compression Methods 0.000 description 3
- BRLQWZUYTZBJKN-UHFFFAOYSA-N Epichlorohydrin Chemical compound ClCC1CO1 BRLQWZUYTZBJKN-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 239000003054 catalyst Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
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- 238000001879 gelation Methods 0.000 description 2
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- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- -1 aurum Chemical compound 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
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Definitions
- the present invention disclosed herein relates to a method for fabricating semiconductor package and a semiconductor package fabricated using the same.
- the present invention provides a method for fabricating semiconductor package, which is suitable for the multiplying of pin and the narrowing of pitch, and can increase bonding strength.
- the present invention also provides a semiconductor package, which is suitable for the multiplying of pin and the narrowing of pitch, and has bonding strength that has been increased.
- Embodiments of the present invention provide a method for fabricating semiconductor package including: forming a first terminal in a first substrate; providing a mixture including a polymer resin and a solder particle to cover at least one upper surface and side surface of the first terminal; and heating the first substrate at a temperature higher than a melting point of the solder particle to form a solder layer covering the upper surface and side surface of the first terminal.
- the first terminal may protrude upward from an upper surface of the first substrate, and may include a metal pad and a metal bump which is disposed on the metal pad.
- the metal bump may have a pillar type or a stud type.
- the method may further include forming a hole in the first substrate, before forming the first terminal, wherein the first terminal may cover a side wall and bottom of the hole, and the solder layer may fill the hole.
- the method may further include planarizing a front surface and rear surface of the first substrate.
- the mixture may be extended to cover the first terminal and another first terminal adjacent to the first terminal.
- the method may further include removing the polymer resin to expose the solder layer, after forming the solder layer.
- the method may further include: providing a flowable hardening resin covering a side surface of the exposed solder layer; disposing a second substrate, in which a second terminal is formed, on the first substrate to come in contact with the second terminal and the solder layer; and heating the first substrate at a temperature higher than a melting point of the solder layer to couple the first and second terminals through the solder layer, and hardening the flowable hardening resin.
- the method may further include disposing a second substrate, in which a second terminal is formed, on the first substrate before heating the first substrate to bring the second terminal in contact with the first terminal.
- the mixture may further include a hardening agent, and the polymer resin may be hardened with the hardening agent by heating the first substrate.
- the second substrate may include a semiconductor chip.
- a semiconductor package includes: a first substrate; a first terminal on the first substrate; and a solder layer covering a surface of the first terminal which is exposed, without contacting the first substrate.
- the semiconductor package may further include: a second substrate disposed on the first substrate; and a second terminal, adjacent to the first terminal, formed in a lower surface of the second substrate, wherein the solder layer may be extended to cover a side surface of the second terminal.
- the semiconductor package may further include: a dielectric layer filling a space between the first and second substrates; and a solder particle disposed in the dielectric layer, and separated from the solder layer.
- FIGS. 1A through 1F are cross-sectional views illustrating a process of fabricating a semiconductor package according to an embodiment of the inventive concept
- FIGS. 2A through 2F are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept
- FIGS. 3A through 3F are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept
- FIGS. 4A through 4E are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept
- FIGS. 5A and 5B are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept
- FIGS. 6A and 6B are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept
- FIGS. 7A and 7B are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept
- FIGS. 8A and 8B are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept
- FIGS. 9A through 9D are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept.
- FIGS. 10A through 10D are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept.
- FIGS. 1A through 1F are across-sectional views illustrating a process of fabricating a semiconductor package according to an embodiment of the inventive concept.
- a first substrate 1 in which a first pad 2 is formed is prepared.
- the first substrate 1 may be a mounting substrate on which a semiconductor chip is mounted.
- the first substrate 1 may be a silicon substrate, a printed circuit board or a ceramic substrate.
- the first pad 2 may be formed of titanium, nickel, platinum or metal such as aurum, and may be formed in a process such as electric plating.
- a pillar type bump 3 is formed on the first pad 2 .
- the pillar type bump 3 for example, may be formed of copper, and may be formed in a process such as electric plating.
- the first pad 2 and the bump 3 may configure a first terminal 50 .
- a mixture 7 including a solder particle 5 and a polymer resin 6 is doped on the first substrate 1 in which the pillar type bump 3 is formed.
- the mixture 7 covers the both side surfaces and upper surface of the first terminal 50 and fills a space between the first terminal 50 and another first terminal 50 adjacent to it.
- the solder particle 5 and the polymer resin 6 may be mixed at a volume rate of 1:9 to 5:5.
- the solder particle 5 for example, may have a diameter of about 0.1 to 100 ⁇ m.
- the solder particle 5 may be plumbum, stannum, indium, bismuth, antimony, argentum or metal particle such as alloy of these.
- the polymer resin 6 may flow.
- the polymer resin 6 may remove an oxide layer from the surface of the solder particle 5 when being heated.
- the polymer resin 6 may be an epoxy-based resin, and may include bisphenol A and epichlorohydrin.
- the mixture 7 may further include a reductant.
- the mixture 7 may further include a deforming agent.
- the mixture 7 is doped, and the first substrate 1 is heated.
- the first substrate 1 may be heated at a temperature higher than the melting point of the solder particle 5 . Therefore, the heated polymer resin 6 removes an oxide layer from the surface of the solder particle 5 , and the solder particle 5 flows inside the polymer resin 6 to move to the surface of the first pad 2 and the bump 3 , thereby being adhered to the surface. Consequently, a solder layer 10 covering the surface of the first terminal 50 including the bump 3 and the first pad 2 . That is, the solder layer 10 is formed to cover the upper surface and both side surfaces of the pillar type bump 3 and the both side surfaces of the first pad 2 .
- the deforming agent suppresses the production of a gas in the mixture 7 , and thus the solder particle 5 allows wet characteristic to be better expressed in the surface of the bump 3 and the surface of the first pad 2 .
- the polymer resin 6 may be changed into a state before gelation, for example, a resin layer 8 of an almost liquid state by the heating process.
- the solder particle 5 which is far away from the bump 3 and the first pad 2 , cannot reach the surface of the bump 3 and the surface of the first pad 2 , and is left inside the resin layer 8 .
- the solder layer 10 is formed, and the resin layer 8 is removed with a solvent agent.
- the solvent agent may be acetone, benzene, toluene or water.
- the solder particle 5 existing inside the resin layer 8 may be removed together. Accordingly, the solder layer 10 and the upper surface of the first substrate 1 peripheral to it are exposed.
- a semiconductor chip or another substrate may be mounted on the first substrate 1 in FIG. 1D . This case will be described below with reference to FIGS. 1E and 1F .
- a flowable hardening resin 16 is doped to cover the surface of the exposed solder layer 10 and the upper surface of the first substrate 1 .
- the flowable hardening resin 16 may fill a space between solder layers 10 covering the surfaces of the adjacent first terminals 50 .
- the flowable hardening resin 16 may be a material similar to the polymer resin 6 , and may further include a hardening agent.
- the flowable hardening resin 16 may also have a function of removing an oxide layer.
- the solder particle 5 does not exit inside flowable hardening resin 16 .
- the flowable hardening resin is doped, and a second substrate 14 in which a second pad 15 is formed is disposed on the first substrate 1 .
- the second substrate 14 may be another mounting substrate, or may be a semiconductor chip.
- the second pad 15 may be called a second terminal.
- the second substrate 14 is disposed to come in contact with the second pad 15 and the upper surface of the solder layer 10 , and the first substrate 1 is heated at a temperature higher than the melting point of the solder layer 10 .
- the flowable hardening resin 16 removes an oxide layer that may be formed in the surface of the solder layer 10 , and the solder layer 10 flows (or diffuses) to the both side surfaces of the second pad 15 , thereby being adhered.
- the solder layer 10 therefore, may cover the first pad 2 , the pillar type bump 3 and the both side surfaces of the second pad 15 .
- the solder layer 10 may be interposed between the pillar type bump 3 and the second pad 15 .
- the solder layer 10 accordingly, bonds the pillar type bump 3 and the second pad 15 , increasing the bonding strength between the two substrates 1 and 14 .
- the flowable hardening resin 16 reacts with a hardening agent included in it to be hardened through a heating process, being changed into a hardened underfill resin 17 . Accordingly, as illustrated in FIGS. 1E and 1F , a flip chip bonding process and an underfill process for the semiconductor chip may be performed at the same time.
- the electrical connection and physical coupling between the first substrate 1 and the second substrate 14 are achieved by the first pad 2 , the pillar type bump 3 , the second pad 15 and the solder layer 10 covering their surfaces.
- the pillar type bump 3 maintains and supports the pitch between the first substrate 1 and the second substrate 14 .
- the underfill resin 17 fills a space between the first substrate 1 and the second substrate 14 , protecting the semiconductor package against various external environment factors such as moisture and physical impacts.
- the first substrate 1 in FIG. 1D may be mounted on a mother board such as a printed circuit board in an overturned state.
- the first pad 2 , the pillar type bump 3 and the solder layer 10 covering their surfaces configure an external terminal such as a solder bump, and may electrically connect with the mother board.
- the semiconductor chip in the first substrate 1 , the semiconductor chip may be mounted in the surface opposite to a surface in which the solder layer 10 is disposed.
- FIGS. 2A through 2F are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept.
- the pitch between first terminals 50 is broader than the case of embodiment 1.
- a mixture 7 including a solder particle 5 and a polymer resin 6 may be selectively doped on a desired position in a screen printer process, as illustrated in FIG. 2B .
- the oxide layer of the solder particle 5 in the mixture 7 is removed, and the solder particle 5 diffuses to the surface of the first terminal 50 to reveal wet characteristic, thereby forming a solder layer 10 covering the upper surface and both side surfaces of the first terminal 50 .
- a solder particle 5 may be selectively doped on a desired position in a screen printer process, as illustrated in FIG. 2B .
- the oxide layer of the solder particle 5 in the mixture 7 is removed, and the solder particle 5 diffuses to the surface of the first terminal 50 to reveal wet characteristic, thereby forming a solder layer 10 covering the upper surface and both side surfaces of the first terminal 50 .
- the solder particle 5 may not almost be left inside a resin layer 8 .
- the providing of a flowable hardening resin 16 may be performed in a screen printer process.
- detailed processes and process conditions may be the same as those of embodiment 1.
- FIGS. 3A through 3F are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept.
- a first substrate 1 in which a first pad 2 is formed is prepared.
- a stud type bump 4 is formed on the first pad 2 .
- the stud type bump 4 may be separately fabricated in a stud type and be raised on the first pad 2 .
- the stud type bump 4 may be bonded on the first pad 2 .
- the stud type bump 4 may be formed of aurum, copper or an alloy of these.
- the first pad 2 and the stud type bump 4 may configure a first terminal 51 .
- a mixture 7 including a solder particle 5 and a polymer resin 6 is doped on the first substrate 1 in which the stud type bump 4 is formed.
- the mixture 7 covers all the exposed surfaces of the first terminal 50 and fills a space between the first terminal 50 and another first terminal 50 adjacent to it.
- the solder particle 5 and the polymer resin 6 may be mixed at a volume rate of 1:9 to 5:5.
- the solder particle 5 for example, may have a diameter of about 0.1 to 100 ⁇ m.
- the solder particle 5 may be plumbum, stannum, indium, bismuth, antimony, argentum or metal particle such as alloy of these.
- the polymer resin 6 may flow.
- the polymer resin 6 may remove an oxide layer from the surface of the solder particle 5 when being heated.
- the polymer resin 6 may be an epoxy-based resin, and may include bisphenol A and epichlorohydrin.
- the mixture 7 may further include a reductant.
- the mixture 7 may further include a deforming agent.
- the mixture 7 is doped, and the first substrate 1 is heated.
- the first substrate 1 may be heated at a temperature higher than the melting point of the solder particle 5 . Therefore, the heated polymer resin 6 removes an oxide layer from the surface of the solder particle 5 , and the solder particle 5 flows inside the polymer resin 6 to move to the surface of the first terminal 51 , thereby being adhered to the surface. Consequently, a solder layer 10 covering the surface of the first terminal 50 including the bump 4 and the first pad 2 . That is, the solder layer 10 is formed to cover the bent surface of the stud type bump 4 and the both side surfaces of the first pad 2 .
- the deforming agent suppresses the production of a gas in the mixture 7 , and thus the solder particle 5 allows wet characteristic to be better expressed in the surface of the bump 4 and the surface of the first pad 2 .
- the polymer resin 6 may be changed into a state before gelation, for example, a resin layer 8 of an almost liquid state by the heating process.
- the solder particle 5 which is far away from the bump 4 and the first pad 2 , cannot reach the surface of the bump 3 and the surface of the first pad 2 , and is left inside the resin layer 8 .
- the solder layer 10 is formed, and the resin layer 8 is removed with a solvent agent.
- the solvent agent may be acetone, benzene, toluene or water.
- the solder particle 5 existing inside the resin layer 8 may be removed together. Accordingly, the solder layer 10 and the upper surface of the first substrate 1 peripheral to it are exposed.
- a flowable hardening resin 16 is doped to cover the surface of the exposed solder layer 10 and the upper surface of the first substrate 1 .
- the flowable hardening resin 16 may fill a space between solder layers 10 covering the surfaces of the adjacent first terminals 50 .
- the flowable hardening resin 16 may be a material similar to the polymer resin 6 , and may further include a hardening agent.
- the flowable hardening resin 16 may also have a function of removing an oxide layer.
- the solder particle 5 does not exit inside flowable hardening resin 16 .
- the flowable hardening resin is doped, and a second substrate 14 in which a second pad 15 is formed is disposed on the first substrate 1 .
- the second substrate 14 may be another mounting substrate, or may be a semiconductor chip.
- the second pad 15 may be called a second terminal.
- the second substrate 14 is disposed to come in contact with the second pad 15 and the upper surface of the solder layer 10 , and the first substrate 1 is heated at a temperature higher than the melting point of the solder layer 10 .
- the flowable hardening resin 16 removes an oxide layer that may be formed in the surface of the solder layer 10 , and the solder layer 10 flows (or diffuses) to the both side surfaces of the second pad 15 , thereby being adhered.
- the solder layer 10 therefore, may cover the first pad 2 , the stud type bump 4 and the both side surfaces of the second pad 15 .
- the solder layer 10 accordingly, bonds the stud type bump 4 and the second pad 15 , increasing the bonding strength between the two substrates 1 and 14 .
- the flowable hardening resin 16 reacts with a hardening agent included in it to be hardened through a heating process, being changed into a hardened underfill resin 17 . Accordingly, as illustrated in FIGS. 3E and 3F , a flip chip bonding process and an underfill process for the semiconductor chip may be performed at the same time.
- the electrical connection and physical coupling between the first substrate 1 and the second substrate 14 are achieved by the first pad 2 , the stud type bump 4 , the second pad 15 and the solder layer 10 covering their surfaces.
- the stud type bump 4 maintains and supports the pitch between the first substrate 1 and the second substrate 14 .
- the underfill resin 17 fills a space between the first substrate 1 and the second substrate 14 , protecting the semiconductor package against various external environment factors such as moisture and physical impacts.
- the first substrate 1 in FIG. 3D may be mounted on a mother board such as a printed circuit board in an overturned state.
- the first pad 2 , the stud type bump 4 and the solder layer 10 covering their surfaces configure an external terminal such as a solder bump, and may electrically connect with the mother board.
- the semiconductor chip in the first substrate 1 , the semiconductor chip may be mounted in the surface opposite to a surface in which the solder layer 10 is disposed.
- FIGS. 4A through 4E are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept.
- the pitch between first terminals 51 is broader than the case of embodiment 1.
- a mixture 7 including a solder particle 5 and a polymer resin 6 may be selectively doped on a desired position in a screen printer process, as illustrated in FIG. 4B .
- the oxide layer of the solder particle 5 in the mixture 7 is removed, and the solder particle 5 diffuses to the surface of the first terminal 51 to reveal wet characteristic, thereby forming a solder layer 10 covering the bent surface of the first terminal 51 .
- a heating process is performed, the oxide layer of the solder particle 5 in the mixture 7 is removed, and the solder particle 5 diffuses to the surface of the first terminal 51 to reveal wet characteristic, thereby forming a solder layer 10 covering the bent surface of the first terminal 51 .
- the solder particle 5 may not almost be left inside a resin layer 8 .
- the providing of a flowable hardening resin 16 may be performed in a screen printer process.
- detailed processes and process conditions may be the same as those of embodiment 3.
- FIGS. 5A and 5B are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept.
- a first substrate 1 in which a first pad 2 is formed is prepared.
- a pillar type bump 3 is formed on the first pad 2 .
- the first pad 2 and the pillar type bump 3 may configure a first terminal 50 .
- a mixture 26 including a solder particle 5 and a flowable hardening resin 24 is doped on the first substrate 1 in which the pillar type bump 3 is formed.
- the mixture 26 covers all the both side surfaces and upper surface of the first terminal 50 and fills a space between the first terminal 50 and another first terminal 50 adjacent to it.
- the solder particle 5 and the flowable hardening resin 24 may be mixed at a volume rate of 1:9 to 5:5.
- the solder particle 5 may have a diameter of about 0.1 to 100 ⁇ m.
- the solder particle 5 may be plumbum, stannum, indium, bismuth, antimony, argentum or metal particle such as alloy of these.
- the flowable hardening resin 24 may flow and remove an oxide layer.
- the flowable hardening resin 24 may include a hardening agent.
- the flowable hardening resin 24 may further include at least one of a reductant, a catalyst and a deforming agent.
- a second substrate 14 in which a second pad 15 is formed is disposed on the first substrate 1 on which the mixture 26 is doped.
- the second substrate 14 is disposed to come in contact with the first terminal 50 and the upper surface of the pillar type bump 3 , and the first substrate 1 is heated at a temperature higher than the melting point of the solder particle 5 .
- the flowable hardening resin 24 removes an oxide layer that may be formed in the surface of the solder particle 5 , and the solder particle 5 flows (or diffuses) to the both side surfaces of the first terminal 50 and the both side surfaces of the second pad 15 to be adhered, thereby forming a solder layer 10 .
- the solder layer 10 therefore, may cover the first pad 2 , the pillar type bump 3 and the both side surfaces of the second pad 15 .
- the solder layer 10 accordingly, bonds the first terminal 50 and the second pad 15 , increasing the bonding strength between the two substrates 1 and 14 .
- the flowable hardening resin 24 reacts with a hardening agent included in it to be hardened through a heating process, being changed into a hardened underfill resin 25 .
- a solder particle 5 that cannot form the solder layer 10 may be left inside the hardened underfill resin 25 .
- the left solder particle 5 is disposed inside the hardened underfill resin 25 having dielectric properties, limitations such as electrical short between the two substrates 1 and 14 are prevented.
- a flip chip bonding process and an underfill process are performed at the same time, and the bonding strength between the two substrates 1 and 14 is increased by the solder layer 10 .
- the hardened underfill resin 25 further increases the bonding strength between the two substrates 1 and 14 and simultaneously protects a semiconductor package against an external environment.
- FIGS. 6A and 6B are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept.
- the pitch between first terminals 50 is broader than the case of embodiment 5.
- a mixture 7 including a solder particle 5 and a flowable hardening resin 24 may be selectively doped on a desired position in a screen printer process, as illustrated in FIG. 6A .
- a second substrate 14 in which a second pad 15 is formed is disposed on the first substrate 1 , and by applying heat and compression, a solder layer 10 covering the first terminal 50 and the both side walls of the second pad 15 is formed. As shown in FIG.
- solder particle 5 may not almost be left inside the hardened underfill resin 25 .
- detailed processes and process conditions may be the same as those of embodiment 5.
- FIGS. 7A and 7B are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept.
- a first substrate 1 in which a first pad 2 is formed is prepared.
- a stud type bump 4 is formed on the first pad 2 .
- the stud type bump 4 may be formed of aurum, copper or an alloy of these.
- the first pad 2 and the stud type bump 4 may configure a first terminal 51 .
- a mixture 26 including a solder particle 5 and a flowable hardening resin 24 is doped on the first substrate 1 in which the stud type bump 4 is formed.
- the mixture 26 covers the bent surface of the first terminal 51 and fills a space between the first terminal 51 and another first terminal 51 adjacent to it.
- the solder particle 5 and the flowable hardening resin 24 may be mixed at a volume rate of 1:9 to 5:5.
- the solder particle 5 may have a diameter of about 0.1 to 100 ⁇ m.
- the solder particle 5 may be plumbum, stannum, indium, bismuth, antimony, argentum or metal particle such as alloy of these.
- the flowable hardening resin 24 may flow and remove an oxide layer.
- the flowable hardening resin 24 may include a hardening agent.
- the flowable hardening resin 24 may further include at least one of a reductant, a catalyst and a deforming agent.
- a second substrate 14 in which a second pad 15 is formed is disposed on the first substrate 1 on which the mixture 26 is doped.
- the second substrate 14 is disposed to come in contact with the first terminal 51 and the upper surface of the stud type bump 4 , and the first substrate 1 is heated at a temperature higher than the melting point of the solder particle 5 .
- the flowable hardening resin 24 removes an oxide layer that may be formed in the surface of the solder particle 5 , and the solder particle 5 flows (or diffuses) to the bent surface of the first terminal 51 and the both side surfaces of the second pad 15 to be adhered, thereby forming a solder layer 10 .
- the solder layer 10 therefore, may cover the first pad 2 , the stud type bump 4 and the both side surfaces of the second pad 15 .
- the solder layer 10 accordingly, bonds the first terminal 51 and the second pad 15 , increasing the bonding strength between the two substrates 1 and 14 .
- the flowable hardening resin 24 reacts with a hardening agent included in it to be hardened through a heating process, being changed into a hardened underfill resin 25 .
- a solder particle 5 that cannot form the solder layer 10 may be left inside the hardened underfill resin 25 .
- the left solder particle 5 is disposed inside the hardened underfill resin 25 having dielectric properties, limitations such as electrical short between the two substrates 1 and 14 are prevented.
- a flip chip bonding process and an underfill process are performed at the same time, and the bonding strength between the two substrates 1 and 14 is increased by the solder layer 10 .
- the hardened underfill resin 25 further increases the bonding strength between the two substrates 1 and 14 and simultaneously protects a semiconductor package against an external environment.
- FIGS. 8A and 8B are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept.
- the pitch between first terminals 51 is broader than the case of embodiment 7.
- a mixture 7 including a solder particle 5 and a flowable hardening resin 24 may be selectively doped on a desired position in a screen printer process, as illustrated in FIG. 8A .
- a second substrate 14 in which a second pad 15 is formed is disposed on the first substrate 1 , and by applying heat and compression, a solder layer 10 covering the first terminal 51 and the both side walls of the second pad 15 is formed. As shown in FIG.
- solder particle 5 may not almost be left inside the hardened underfill resin 25 .
- detailed processes and process conditions may be the same as those of embodiment 7.
- FIGS. 9A through 9D are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept.
- a via hole 31 is formed in a first substrate 30 . Furthermore, a seed layer covering the side wall and bottom of the via hole 31 is formed.
- the seed layer 27 may be formed of titanium, nickel, platinum, aurum, copper or an alloy of these.
- the seed layer 27 may be formed in a Chemical Vapor Deposition (CVD) process or an Atomic Layer Deposition (ALD) process. Additionally, a planarization etching process may be further performed for forming the seed layer 27 covering the side wall and bottom of the via hole 31 .
- the seed layer 27 may correspond to the first terminal of embodiment 1.
- a mixture 7 including a solder particle 5 and a polymer resin 6 is doped on the first substrate 30 in which the seed layer 27 is formed.
- the mixture 7 is doped to fill the inside of the via hole 31 .
- vacuum may be given to the first substrate 30 .
- the physical properties of the polymer resin 6 and the solder particle 5 may be the same as those of embodiment 1.
- solder via 11 covering the exposed surface of the seed layer 27 and filling the inside of the via hole 31 is formed.
- the solder via 11 is not formed inside a resin layer 8 , and a left solder particle 5 may be included in the resin layer 8 .
- the resin layer is removed with a solvent agent.
- a solder particle 5 that is left inside the resin layer 8 may also be removed together.
- a planarization removal process on the front surface and rear surface of the first substrate 30 , a terminalion of the upper portion and lower portion of the first substrate 30 is removed, and a seed pattern 27 a covering the inner side wall of the via hole 31 and a solder via plug 11 a filling the via hole 31 are formed.
- the first substrate 30 may be used as a mounting substrate such as a printed circuit board or a ceramic substrate on which a semiconductor chip is mounted.
- the first substrate 30 may be a semiconductor chip including a through via such as a through silicon via.
- FIGS. 10A through 10D are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept.
- the pitch between via holes 31 formed on a first substrate 30 is broader than the case of embodiment 9.
- a mixture 7 including a solder particle 5 and a polymer resin 6 may be doped in a screen printer process.
- vacuum may be given to the first substrate 30 in order for the mixture 7 to fill the via hole 31 .
- the order and condition of a process may be the same as those of embodiment 9.
- the method for fabricating semiconductor package according to an embodiment of the inventive concept dopes a mixture including the polymer material and the solder particle on the substrate in which the terminal is formed and applies heat, and thus the solder particle flows (or diffuses) toward the terminal in the heated polymer resin to adhere to the exposed surface of the terminal, i.e., the side surface and upper surface of the terminal, thereby forming the solder layer.
- the solder layer improves the adhesive strength between the terminal of the semiconductor chip and the terminal of the substrate in the subsequent flip chip bonding process.
- the pad of the substrate may protrude from the substrate, and may be configured with the pad and the bump disposed on it.
- the pitch between the semiconductor chip and the substrate can be constantly maintained by the terminal that is configured with the pad and the bump.
- the terminal includes both the pad and the bump, the risk of electrical short (which is caused by the contact of two adjacent solder layers) is removed because the bump serves as the support bar between the semiconductor chip and the substrate. Accordingly, the method for fabricating semiconductor package can be easily applied to the multiplying of pin and the narrowing of pitch.
- bonding strength can increase by the solder layer covering the surfaces of the pads that are disposed between the two substrates or between the semiconductor chip and the mounting substrate.
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Abstract
Description
- This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 of Korean Patent Application No. 10-2009-0055478, filed on Jun. 22, 2009, the entire contents of which are hereby incorporated by reference.
- The present invention disclosed herein relates to a method for fabricating semiconductor package and a semiconductor package fabricated using the same.
- As semiconductor integrated circuit applied to electronic devices is highly densified and integrated, the multiplying of pin and the narrowing of pitch progress rapidly in the electrode terminal of semiconductor chip. In mounting on the interconnection substrate of the semiconductor chip, moreover, a flip chip bonding is widely used for decreasing interconnection delay. This flip chip bonding brings the external electrode pad of the semiconductor chip in contact with the pad of a mounting substrate, and by applying heat, allows the two pads to be bonded in a reflow process. In such a flip chip bonding process, since heat is applied and compression is performed simply, the bonding strength between the electrode pad of the semiconductor chip and the pad of the mounting substrate is very low. Accordingly, the electrode pad of the semiconductor chip and the pad of the mounting substrate are easily disconnected by a physical impact.
- The present invention provides a method for fabricating semiconductor package, which is suitable for the multiplying of pin and the narrowing of pitch, and can increase bonding strength.
- The present invention also provides a semiconductor package, which is suitable for the multiplying of pin and the narrowing of pitch, and has bonding strength that has been increased.
- Embodiments of the present invention provide a method for fabricating semiconductor package including: forming a first terminal in a first substrate; providing a mixture including a polymer resin and a solder particle to cover at least one upper surface and side surface of the first terminal; and heating the first substrate at a temperature higher than a melting point of the solder particle to form a solder layer covering the upper surface and side surface of the first terminal.
- In some embodiments, the first terminal may protrude upward from an upper surface of the first substrate, and may include a metal pad and a metal bump which is disposed on the metal pad. At this point, the metal bump may have a pillar type or a stud type.
- In other embodiments, the method may further include forming a hole in the first substrate, before forming the first terminal, wherein the first terminal may cover a side wall and bottom of the hole, and the solder layer may fill the hole. The method may further include planarizing a front surface and rear surface of the first substrate.
- In still other embodiments, the mixture may be extended to cover the first terminal and another first terminal adjacent to the first terminal.
- In even other embodiments, the method may further include removing the polymer resin to expose the solder layer, after forming the solder layer. The method may further include: providing a flowable hardening resin covering a side surface of the exposed solder layer; disposing a second substrate, in which a second terminal is formed, on the first substrate to come in contact with the second terminal and the solder layer; and heating the first substrate at a temperature higher than a melting point of the solder layer to couple the first and second terminals through the solder layer, and hardening the flowable hardening resin.
- In yet other embodiments, the method may further include disposing a second substrate, in which a second terminal is formed, on the first substrate before heating the first substrate to bring the second terminal in contact with the first terminal. In this case, the mixture may further include a hardening agent, and the polymer resin may be hardened with the hardening agent by heating the first substrate.
- In further embodiments, the second substrate may include a semiconductor chip.
- In other embodiments of the present invention, a semiconductor package includes: a first substrate; a first terminal on the first substrate; and a solder layer covering a surface of the first terminal which is exposed, without contacting the first substrate.
- In some embodiments, the semiconductor package may further include: a second substrate disposed on the first substrate; and a second terminal, adjacent to the first terminal, formed in a lower surface of the second substrate, wherein the solder layer may be extended to cover a side surface of the second terminal.
- In other embodiments, the semiconductor package may further include: a dielectric layer filling a space between the first and second substrates; and a solder particle disposed in the dielectric layer, and separated from the solder layer.
- The accompanying figures are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present invention and, together with the description, serve to explain principles of the present invention. In the figures:
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FIGS. 1A through 1F are cross-sectional views illustrating a process of fabricating a semiconductor package according to an embodiment of the inventive concept; -
FIGS. 2A through 2F are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept; -
FIGS. 3A through 3F are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept; -
FIGS. 4A through 4E are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept; -
FIGS. 5A and 5B are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept; -
FIGS. 6A and 6B are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept; -
FIGS. 7A and 7B are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept; -
FIGS. 8A and 8B are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept; -
FIGS. 9A through 9D are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept; and -
FIGS. 10A through 10D are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept. - Preferred embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the figures, the dimensions of layers and regions are exaggerated for clarity of illustration. It will also be understood that when a layer (or film) is referred to as being ‘on’ another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being ‘under’ another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being ‘between’ two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout.
-
FIGS. 1A through 1F are across-sectional views illustrating a process of fabricating a semiconductor package according to an embodiment of the inventive concept. - Referring to
FIG. 1A , afirst substrate 1 in which afirst pad 2 is formed is prepared. Thefirst substrate 1, for example, may be a mounting substrate on which a semiconductor chip is mounted. Alternatively, thefirst substrate 1 may be a silicon substrate, a printed circuit board or a ceramic substrate. Thefirst pad 2 may be formed of titanium, nickel, platinum or metal such as aurum, and may be formed in a process such as electric plating. Apillar type bump 3 is formed on thefirst pad 2. Thepillar type bump 3, for example, may be formed of copper, and may be formed in a process such as electric plating. Thefirst pad 2 and thebump 3 may configure afirst terminal 50. - Referring to
FIG. 1B , amixture 7 including asolder particle 5 and apolymer resin 6 is doped on thefirst substrate 1 in which thepillar type bump 3 is formed. Themixture 7 covers the both side surfaces and upper surface of thefirst terminal 50 and fills a space between thefirst terminal 50 and another first terminal 50 adjacent to it. In themixture 7, thesolder particle 5 and thepolymer resin 6 may be mixed at a volume rate of 1:9 to 5:5. Thesolder particle 5, for example, may have a diameter of about 0.1 to 100 μm. Thesolder particle 5 may be plumbum, stannum, indium, bismuth, antimony, argentum or metal particle such as alloy of these. Thepolymer resin 6 may flow. Thepolymer resin 6 may remove an oxide layer from the surface of thesolder particle 5 when being heated. Thepolymer resin 6, for example, may be an epoxy-based resin, and may include bisphenol A and epichlorohydrin. Themixture 7 may further include a reductant. Themixture 7 may further include a deforming agent. - Referring to
FIG. 1C , themixture 7 is doped, and thefirst substrate 1 is heated. At this point, thefirst substrate 1 may be heated at a temperature higher than the melting point of thesolder particle 5. Therefore, theheated polymer resin 6 removes an oxide layer from the surface of thesolder particle 5, and thesolder particle 5 flows inside thepolymer resin 6 to move to the surface of thefirst pad 2 and thebump 3, thereby being adhered to the surface. Consequently, asolder layer 10 covering the surface of thefirst terminal 50 including thebump 3 and thefirst pad 2. That is, thesolder layer 10 is formed to cover the upper surface and both side surfaces of thepillar type bump 3 and the both side surfaces of thefirst pad 2. When themixture 7 further includes a deforming agent, the deforming agent suppresses the production of a gas in themixture 7, and thus thesolder particle 5 allows wet characteristic to be better expressed in the surface of thebump 3 and the surface of thefirst pad 2. Thepolymer resin 6 may be changed into a state before gelation, for example, aresin layer 8 of an almost liquid state by the heating process. Thesolder particle 5, which is far away from thebump 3 and thefirst pad 2, cannot reach the surface of thebump 3 and the surface of thefirst pad 2, and is left inside theresin layer 8. - Referring to
FIG. 1D , thesolder layer 10 is formed, and theresin layer 8 is removed with a solvent agent. For example, the solvent agent may be acetone, benzene, toluene or water. When removing theresin layer 8, thesolder particle 5 existing inside theresin layer 8 may be removed together. Accordingly, thesolder layer 10 and the upper surface of thefirst substrate 1 peripheral to it are exposed. - A semiconductor chip or another substrate may be mounted on the
first substrate 1 inFIG. 1D . This case will be described below with reference toFIGS. 1E and 1F . - Referring to
FIG. 1E , a flowable hardeningresin 16 is doped to cover the surface of the exposedsolder layer 10 and the upper surface of thefirst substrate 1. The flowable hardeningresin 16 may fill a space between solder layers 10 covering the surfaces of the adjacentfirst terminals 50. The flowable hardeningresin 16 may be a material similar to thepolymer resin 6, and may further include a hardening agent. The flowable hardeningresin 16 may also have a function of removing an oxide layer. Thesolder particle 5 does not exit inside flowable hardeningresin 16. The flowable hardening resin is doped, and asecond substrate 14 in which asecond pad 15 is formed is disposed on thefirst substrate 1. Thesecond substrate 14 may be another mounting substrate, or may be a semiconductor chip. Thesecond pad 15 may be called a second terminal. - Referring to
FIG. 1F , thesecond substrate 14 is disposed to come in contact with thesecond pad 15 and the upper surface of thesolder layer 10, and thefirst substrate 1 is heated at a temperature higher than the melting point of thesolder layer 10. Thus, the flowable hardeningresin 16 removes an oxide layer that may be formed in the surface of thesolder layer 10, and thesolder layer 10 flows (or diffuses) to the both side surfaces of thesecond pad 15, thereby being adhered. Thesolder layer 10, therefore, may cover thefirst pad 2, thepillar type bump 3 and the both side surfaces of thesecond pad 15. Moreover, thesolder layer 10 may be interposed between thepillar type bump 3 and thesecond pad 15. Thesolder layer 10, accordingly, bonds thepillar type bump 3 and thesecond pad 15, increasing the bonding strength between the twosubstrates resin 16 reacts with a hardening agent included in it to be hardened through a heating process, being changed into ahardened underfill resin 17. Accordingly, as illustrated inFIGS. 1E and 1F , a flip chip bonding process and an underfill process for the semiconductor chip may be performed at the same time. - Referring to a semiconductor package in
FIG. 1F , the electrical connection and physical coupling between thefirst substrate 1 and thesecond substrate 14 are achieved by thefirst pad 2, thepillar type bump 3, thesecond pad 15 and thesolder layer 10 covering their surfaces. Thepillar type bump 3 maintains and supports the pitch between thefirst substrate 1 and thesecond substrate 14. Moreover, theunderfill resin 17 fills a space between thefirst substrate 1 and thesecond substrate 14, protecting the semiconductor package against various external environment factors such as moisture and physical impacts. - The
first substrate 1 inFIG. 1D may be mounted on a mother board such as a printed circuit board in an overturned state. At this point, thefirst pad 2, thepillar type bump 3 and thesolder layer 10 covering their surfaces configure an external terminal such as a solder bump, and may electrically connect with the mother board. In this case, in thefirst substrate 1, the semiconductor chip may be mounted in the surface opposite to a surface in which thesolder layer 10 is disposed. -
FIGS. 2A through 2F are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept. - Referring to
FIGS. 2A through 2F , in another embodiment of the inventive concept, the pitch betweenfirst terminals 50 is broader than the case ofembodiment 1. In this way, when the pitch between thefirst terminals 50 is broad, amixture 7 including asolder particle 5 and apolymer resin 6 may be selectively doped on a desired position in a screen printer process, as illustrated inFIG. 2B . Subsequently, when a heating process is performed, the oxide layer of thesolder particle 5 in themixture 7 is removed, and thesolder particle 5 diffuses to the surface of thefirst terminal 50 to reveal wet characteristic, thereby forming asolder layer 10 covering the upper surface and both side surfaces of thefirst terminal 50. As shown inFIG. 2C , since distance from the edge of a region (on which themixture 7 is doped) to the surface of thefirst terminal 50 is shorter than the case ofembodiment 1, thesolder particle 5 may not almost be left inside aresin layer 8. InFIG. 2E , the providing of a flowable hardeningresin 16 may be performed in a screen printer process. In addition, detailed processes and process conditions may be the same as those ofembodiment 1. -
FIGS. 3A through 3F are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept. - Referring to
FIG. 3A , afirst substrate 1 in which afirst pad 2 is formed is prepared. Astud type bump 4 is formed on thefirst pad 2. Thestud type bump 4 may be separately fabricated in a stud type and be raised on thefirst pad 2. By performing a thermal reflow process, thestud type bump 4 may be bonded on thefirst pad 2. For example, thestud type bump 4 may be formed of aurum, copper or an alloy of these. Thefirst pad 2 and thestud type bump 4 may configure afirst terminal 51. - Referring to
FIG. 3B , amixture 7 including asolder particle 5 and apolymer resin 6 is doped on thefirst substrate 1 in which thestud type bump 4 is formed. Themixture 7 covers all the exposed surfaces of thefirst terminal 50 and fills a space between thefirst terminal 50 and another first terminal 50 adjacent to it. In themixture 7, thesolder particle 5 and thepolymer resin 6 may be mixed at a volume rate of 1:9 to 5:5. Thesolder particle 5, for example, may have a diameter of about 0.1 to 100 μm. Thesolder particle 5 may be plumbum, stannum, indium, bismuth, antimony, argentum or metal particle such as alloy of these. Thepolymer resin 6 may flow. Thepolymer resin 6 may remove an oxide layer from the surface of thesolder particle 5 when being heated. Thepolymer resin 6, for example, may be an epoxy-based resin, and may include bisphenol A and epichlorohydrin. Themixture 7 may further include a reductant. Themixture 7 may further include a deforming agent. - Referring to
FIG. 3C , themixture 7 is doped, and thefirst substrate 1 is heated. At this point, thefirst substrate 1 may be heated at a temperature higher than the melting point of thesolder particle 5. Therefore, theheated polymer resin 6 removes an oxide layer from the surface of thesolder particle 5, and thesolder particle 5 flows inside thepolymer resin 6 to move to the surface of thefirst terminal 51, thereby being adhered to the surface. Consequently, asolder layer 10 covering the surface of thefirst terminal 50 including thebump 4 and thefirst pad 2. That is, thesolder layer 10 is formed to cover the bent surface of thestud type bump 4 and the both side surfaces of thefirst pad 2. When themixture 7 further includes a deforming agent, the deforming agent suppresses the production of a gas in themixture 7, and thus thesolder particle 5 allows wet characteristic to be better expressed in the surface of thebump 4 and the surface of thefirst pad 2. Thepolymer resin 6 may be changed into a state before gelation, for example, aresin layer 8 of an almost liquid state by the heating process. Thesolder particle 5, which is far away from thebump 4 and thefirst pad 2, cannot reach the surface of thebump 3 and the surface of thefirst pad 2, and is left inside theresin layer 8. - Referring to
FIG. 3D , thesolder layer 10 is formed, and theresin layer 8 is removed with a solvent agent. For example, the solvent agent may be acetone, benzene, toluene or water. When removing theresin layer 8, thesolder particle 5 existing inside theresin layer 8 may be removed together. Accordingly, thesolder layer 10 and the upper surface of thefirst substrate 1 peripheral to it are exposed. - Referring to
FIG. 3E , a flowable hardeningresin 16 is doped to cover the surface of the exposedsolder layer 10 and the upper surface of thefirst substrate 1. The flowable hardeningresin 16 may fill a space between solder layers 10 covering the surfaces of the adjacentfirst terminals 50. The flowable hardeningresin 16 may be a material similar to thepolymer resin 6, and may further include a hardening agent. The flowable hardeningresin 16 may also have a function of removing an oxide layer. Thesolder particle 5 does not exit inside flowable hardeningresin 16. The flowable hardening resin is doped, and asecond substrate 14 in which asecond pad 15 is formed is disposed on thefirst substrate 1. Thesecond substrate 14 may be another mounting substrate, or may be a semiconductor chip. Thesecond pad 15 may be called a second terminal. - Referring to
FIG. 3F , thesecond substrate 14 is disposed to come in contact with thesecond pad 15 and the upper surface of thesolder layer 10, and thefirst substrate 1 is heated at a temperature higher than the melting point of thesolder layer 10. Thus, the flowable hardeningresin 16 removes an oxide layer that may be formed in the surface of thesolder layer 10, and thesolder layer 10 flows (or diffuses) to the both side surfaces of thesecond pad 15, thereby being adhered. Thesolder layer 10, therefore, may cover thefirst pad 2, thestud type bump 4 and the both side surfaces of thesecond pad 15. Thesolder layer 10, accordingly, bonds thestud type bump 4 and thesecond pad 15, increasing the bonding strength between the twosubstrates resin 16 reacts with a hardening agent included in it to be hardened through a heating process, being changed into ahardened underfill resin 17. Accordingly, as illustrated inFIGS. 3E and 3F , a flip chip bonding process and an underfill process for the semiconductor chip may be performed at the same time. - Referring to a semiconductor package in
FIG. 3F , the electrical connection and physical coupling between thefirst substrate 1 and thesecond substrate 14 are achieved by thefirst pad 2, thestud type bump 4, thesecond pad 15 and thesolder layer 10 covering their surfaces. Thestud type bump 4 maintains and supports the pitch between thefirst substrate 1 and thesecond substrate 14. Moreover, theunderfill resin 17 fills a space between thefirst substrate 1 and thesecond substrate 14, protecting the semiconductor package against various external environment factors such as moisture and physical impacts. - The
first substrate 1 inFIG. 3D may be mounted on a mother board such as a printed circuit board in an overturned state. At this point, thefirst pad 2, thestud type bump 4 and thesolder layer 10 covering their surfaces configure an external terminal such as a solder bump, and may electrically connect with the mother board. In this case, in thefirst substrate 1, the semiconductor chip may be mounted in the surface opposite to a surface in which thesolder layer 10 is disposed. -
FIGS. 4A through 4E are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept. - Referring to
FIGS. 4A through 4E , in another embodiment of the inventive concept, the pitch betweenfirst terminals 51 is broader than the case ofembodiment 1. In this way, when the pitch between thefirst terminals 51 is broad, amixture 7 including asolder particle 5 and apolymer resin 6 may be selectively doped on a desired position in a screen printer process, as illustrated inFIG. 4B . Subsequently, when a heating process is performed, the oxide layer of thesolder particle 5 in themixture 7 is removed, and thesolder particle 5 diffuses to the surface of thefirst terminal 51 to reveal wet characteristic, thereby forming asolder layer 10 covering the bent surface of thefirst terminal 51. As shown inFIG. 4C , since distance from the edge of a region (on which themixture 7 is doped) to the surface of thefirst terminal 51 is shorter than the case ofembodiment 3, thesolder particle 5 may not almost be left inside aresin layer 8. InFIG. 4E , the providing of a flowable hardeningresin 16 may be performed in a screen printer process. In addition, detailed processes and process conditions may be the same as those ofembodiment 3. -
FIGS. 5A and 5B are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept. - Referring to
FIG. 5A , afirst substrate 1 in which afirst pad 2 is formed is prepared. Apillar type bump 3 is formed on thefirst pad 2. Thefirst pad 2 and thepillar type bump 3 may configure afirst terminal 50. Amixture 26 including asolder particle 5 and a flowable hardeningresin 24 is doped on thefirst substrate 1 in which thepillar type bump 3 is formed. Themixture 26 covers all the both side surfaces and upper surface of thefirst terminal 50 and fills a space between thefirst terminal 50 and another first terminal 50 adjacent to it. In themixture 26, thesolder particle 5 and the flowable hardeningresin 24 may be mixed at a volume rate of 1:9 to 5:5. Thesolder particle 5, for example, may have a diameter of about 0.1 to 100 μm. Thesolder particle 5 may be plumbum, stannum, indium, bismuth, antimony, argentum or metal particle such as alloy of these. The flowable hardeningresin 24 may flow and remove an oxide layer. Moreover, the flowable hardeningresin 24 may include a hardening agent. The flowable hardeningresin 24 may further include at least one of a reductant, a catalyst and a deforming agent. Asecond substrate 14 in which asecond pad 15 is formed is disposed on thefirst substrate 1 on which themixture 26 is doped. - Referring to
FIG. 5B , thesecond substrate 14 is disposed to come in contact with thefirst terminal 50 and the upper surface of thepillar type bump 3, and thefirst substrate 1 is heated at a temperature higher than the melting point of thesolder particle 5. Thus, the flowable hardeningresin 24 removes an oxide layer that may be formed in the surface of thesolder particle 5, and thesolder particle 5 flows (or diffuses) to the both side surfaces of thefirst terminal 50 and the both side surfaces of thesecond pad 15 to be adhered, thereby forming asolder layer 10. Thesolder layer 10, therefore, may cover thefirst pad 2, thepillar type bump 3 and the both side surfaces of thesecond pad 15. Thesolder layer 10, accordingly, bonds thefirst terminal 50 and thesecond pad 15, increasing the bonding strength between the twosubstrates resin 24 reacts with a hardening agent included in it to be hardened through a heating process, being changed into ahardened underfill resin 25. Asolder particle 5 that cannot form thesolder layer 10 may be left inside thehardened underfill resin 25. However, since theleft solder particle 5 is disposed inside thehardened underfill resin 25 having dielectric properties, limitations such as electrical short between the twosubstrates - According to another embodiment of the inventive concept, a flip chip bonding process and an underfill process are performed at the same time, and the bonding strength between the two
substrates solder layer 10. Thehardened underfill resin 25 further increases the bonding strength between the twosubstrates embodiment 1, it does not all perform the processes ofFIGS. 1A through 1F , thereby being simplified. Accordingly, the cost is saved and the process time is shortened. -
FIGS. 6A and 6B are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept. - Referring to
FIGS. 6A and 6B , in another embodiment of the inventive concept, the pitch betweenfirst terminals 50 is broader than the case ofembodiment 5. In this way, when the pitch between thefirst terminals 50 is broad, amixture 7 including asolder particle 5 and a flowable hardeningresin 24 may be selectively doped on a desired position in a screen printer process, as illustrated inFIG. 6A . Asecond substrate 14 in which asecond pad 15 is formed is disposed on thefirst substrate 1, and by applying heat and compression, asolder layer 10 covering thefirst terminal 50 and the both side walls of thesecond pad 15 is formed. As shown inFIG. 6B , since distance from the edge of a region (on which themixture 26 is doped) to the surface of thefirst terminal 50 is shorter than the case ofembodiment 5, thesolder particle 5 may not almost be left inside thehardened underfill resin 25. In addition, detailed processes and process conditions may be the same as those ofembodiment 5. -
FIGS. 7A and 7B are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept. - Referring to
FIG. 7A , afirst substrate 1 in which afirst pad 2 is formed is prepared. Astud type bump 4 is formed on thefirst pad 2. For example, thestud type bump 4 may be formed of aurum, copper or an alloy of these. Thefirst pad 2 and thestud type bump 4 may configure afirst terminal 51. Amixture 26 including asolder particle 5 and a flowable hardeningresin 24 is doped on thefirst substrate 1 in which thestud type bump 4 is formed. Themixture 26 covers the bent surface of thefirst terminal 51 and fills a space between thefirst terminal 51 and another first terminal 51 adjacent to it. In themixture 26, thesolder particle 5 and the flowable hardeningresin 24 may be mixed at a volume rate of 1:9 to 5:5. Thesolder particle 5, for example, may have a diameter of about 0.1 to 100 μm. Thesolder particle 5 may be plumbum, stannum, indium, bismuth, antimony, argentum or metal particle such as alloy of these. The flowable hardeningresin 24 may flow and remove an oxide layer. Moreover, the flowable hardeningresin 24 may include a hardening agent. The flowable hardeningresin 24 may further include at least one of a reductant, a catalyst and a deforming agent. Asecond substrate 14 in which asecond pad 15 is formed is disposed on thefirst substrate 1 on which themixture 26 is doped. - Referring to
FIG. 7B , thesecond substrate 14 is disposed to come in contact with thefirst terminal 51 and the upper surface of thestud type bump 4, and thefirst substrate 1 is heated at a temperature higher than the melting point of thesolder particle 5. Thus, the flowable hardeningresin 24 removes an oxide layer that may be formed in the surface of thesolder particle 5, and thesolder particle 5 flows (or diffuses) to the bent surface of thefirst terminal 51 and the both side surfaces of thesecond pad 15 to be adhered, thereby forming asolder layer 10. Thesolder layer 10, therefore, may cover thefirst pad 2, thestud type bump 4 and the both side surfaces of thesecond pad 15. Thesolder layer 10, accordingly, bonds thefirst terminal 51 and thesecond pad 15, increasing the bonding strength between the twosubstrates resin 24 reacts with a hardening agent included in it to be hardened through a heating process, being changed into ahardened underfill resin 25. Asolder particle 5 that cannot form thesolder layer 10 may be left inside thehardened underfill resin 25. However, since theleft solder particle 5 is disposed inside thehardened underfill resin 25 having dielectric properties, limitations such as electrical short between the twosubstrates - According to another embodiment of the inventive concept, a flip chip bonding process and an underfill process are performed at the same time, and the bonding strength between the two
substrates solder layer 10. Thehardened underfill resin 25 further increases the bonding strength between the twosubstrates embodiment 3, it does not all perform the processes ofFIGS. 3A through 3F , thereby being simplified. Accordingly, the cost is saved and the process time is shortened. -
FIGS. 8A and 8B are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept. - Referring to
FIGS. 8A and 8B , in another embodiment of the inventive concept, the pitch betweenfirst terminals 51 is broader than the case ofembodiment 7. In this way, when the pitch between thefirst terminals 51 is broad, amixture 7 including asolder particle 5 and a flowable hardeningresin 24 may be selectively doped on a desired position in a screen printer process, as illustrated inFIG. 8A . Asecond substrate 14 in which asecond pad 15 is formed is disposed on thefirst substrate 1, and by applying heat and compression, asolder layer 10 covering thefirst terminal 51 and the both side walls of thesecond pad 15 is formed. As shown inFIG. 8B , since distance from the edge of a region (on which themixture 26 is doped) to the surface of thefirst terminal 51 is shorter than the case ofembodiment 7, thesolder particle 5 may not almost be left inside thehardened underfill resin 25. In addition, detailed processes and process conditions may be the same as those ofembodiment 7. -
FIGS. 9A through 9D are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept. - Referring to
FIG. 9A , a viahole 31 is formed in afirst substrate 30. Furthermore, a seed layer covering the side wall and bottom of the viahole 31 is formed. Theseed layer 27 may be formed of titanium, nickel, platinum, aurum, copper or an alloy of these. Theseed layer 27 may be formed in a Chemical Vapor Deposition (CVD) process or an Atomic Layer Deposition (ALD) process. Additionally, a planarization etching process may be further performed for forming theseed layer 27 covering the side wall and bottom of the viahole 31. Theseed layer 27 may correspond to the first terminal ofembodiment 1. - Referring to
FIG. 9B , amixture 7 including asolder particle 5 and apolymer resin 6 is doped on thefirst substrate 30 in which theseed layer 27 is formed. Themixture 7 is doped to fill the inside of the viahole 31. For this, vacuum may be given to thefirst substrate 30. The physical properties of thepolymer resin 6 and thesolder particle 5 may be the same as those ofembodiment 1. - Referring to
FIG. 9C , by heating thefirst substrate 30 at a temperature higher than the melting point of thesolder particle 5, a solder via 11 covering the exposed surface of theseed layer 27 and filling the inside of the viahole 31 is formed. The solder via 11 is not formed inside aresin layer 8, and aleft solder particle 5 may be included in theresin layer 8. - Referring to
FIG. 9D , the resin layer is removed with a solvent agent. At this point, asolder particle 5 that is left inside theresin layer 8 may also be removed together. Furthermore, by performing a planarization removal process on the front surface and rear surface of thefirst substrate 30, a terminalion of the upper portion and lower portion of thefirst substrate 30 is removed, and aseed pattern 27 a covering the inner side wall of the viahole 31 and a solder viaplug 11 a filling the viahole 31 are formed. - Subsequently, a rewiring electrically connected to the solder via
plug 11 a may be formed in the front surface and rear surface of thefirst substrate 30 including the solder viaplug 11 a. Thefirst substrate 30 may be used as a mounting substrate such as a printed circuit board or a ceramic substrate on which a semiconductor chip is mounted. Alternatively, thefirst substrate 30 may be a semiconductor chip including a through via such as a through silicon via. -
FIGS. 10A through 10D are cross-sectional views illustrating a process of fabricating a semiconductor package according to another embodiment of the inventive concept. - Referring to
FIGS. 10A through 10D , in another embodiment of the inventive concept, the pitch between viaholes 31 formed on afirst substrate 30 is broader than the case of embodiment 9. In this case, amixture 7 including asolder particle 5 and apolymer resin 6 may be doped in a screen printer process. At this point, like embodiment 9, vacuum may be given to thefirst substrate 30 in order for themixture 7 to fill the viahole 31. In addition, the order and condition of a process may be the same as those of embodiment 9. - The method for fabricating semiconductor package according to an embodiment of the inventive concept dopes a mixture including the polymer material and the solder particle on the substrate in which the terminal is formed and applies heat, and thus the solder particle flows (or diffuses) toward the terminal in the heated polymer resin to adhere to the exposed surface of the terminal, i.e., the side surface and upper surface of the terminal, thereby forming the solder layer. The solder layer improves the adhesive strength between the terminal of the semiconductor chip and the terminal of the substrate in the subsequent flip chip bonding process.
- In the method for fabricating semiconductor package according to an embodiment of the inventive concept, moreover, the pad of the substrate may protrude from the substrate, and may be configured with the pad and the bump disposed on it. The pitch between the semiconductor chip and the substrate can be constantly maintained by the terminal that is configured with the pad and the bump. Compared with a case in which the terminal includes only the pad without including the bump and there is the solder layer covering the surface of the terminal, in an embodiment of the inventive concept where the terminal includes both the pad and the bump, the risk of electrical short (which is caused by the contact of two adjacent solder layers) is removed because the bump serves as the support bar between the semiconductor chip and the substrate. Accordingly, the method for fabricating semiconductor package can be easily applied to the multiplying of pin and the narrowing of pitch.
- In the semiconductor package according to another embodiment of the inventive concept, bonding strength can increase by the solder layer covering the surfaces of the pads that are disposed between the two substrates or between the semiconductor chip and the mounting substrate.
- The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the present invention. Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.
Claims (17)
Applications Claiming Priority (2)
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KR1020090055478A KR101208028B1 (en) | 2009-06-22 | 2009-06-22 | Method of fabricating a semiconductor package and the semiconductor package |
KR10-2009-0055478 | 2009-06-22 |
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US14/066,099 Division US9237927B2 (en) | 2009-09-29 | 2013-10-29 | Flow rate monitor for fluid cooled microwave ablation probe |
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US12/565,171 Active US8030200B2 (en) | 2009-06-22 | 2009-09-23 | Method for fabricating a semiconductor package |
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US (1) | US8030200B2 (en) |
JP (2) | JP5588667B2 (en) |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110033977A1 (en) * | 2009-08-06 | 2011-02-10 | Maxim Integrated Products, Inc. | Method of forming solderable side-surface terminals of quad no-lead frame (qfn) integrated circuit packages |
US20110233767A1 (en) * | 2010-03-29 | 2011-09-29 | Panasonic Corporation | Semiconductor device and semiconductor device manufacturing method |
US20120205796A1 (en) * | 2011-02-15 | 2012-08-16 | Hynix Semiconductor Inc. | Semiconductor package and method for manufacturing the same |
WO2013177541A1 (en) * | 2012-05-25 | 2013-11-28 | Applied Materials, Inc. | Polymer hot-wire chemical vapor deposition in chip scale packaging |
US20190067240A1 (en) * | 2017-08-23 | 2019-02-28 | Boe Technology Group Co., Ltd | Flexible display panel and preparation method thereof, flexible display device |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8507325B2 (en) * | 2010-01-28 | 2013-08-13 | International Business Machines Corporation | Co-axial restraint for connectors within flip-chip packages |
KR102275705B1 (en) | 2014-07-11 | 2021-07-09 | 삼성전자주식회사 | Wafer-to-wafer bonding structure |
KR101619455B1 (en) * | 2014-11-18 | 2016-05-11 | 주식회사 프로텍 | Method for Manufacturing Package On Package |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5136365A (en) * | 1990-09-27 | 1992-08-04 | Motorola, Inc. | Anisotropic conductive adhesive and encapsulant material |
US6064120A (en) * | 1997-08-21 | 2000-05-16 | Micron Technology, Inc. | Apparatus and method for face-to-face connection of a die face to a substrate with polymer electrodes |
US6878435B2 (en) * | 2001-07-19 | 2005-04-12 | Korea Advanced Institute Of Science And Technology | High adhesion triple layered anisotropic conductive adhesive film |
US7227267B2 (en) * | 2004-10-11 | 2007-06-05 | Samsung Electro-Mechanics Co., Ltd. | Semiconductor package using flip-chip mounting technique |
US20100006625A1 (en) * | 2008-07-10 | 2010-01-14 | Electronics And Telecommunications Research Institute | Composition and methods of forming solder bump and flip chip using the same |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0521438A (en) * | 1991-07-16 | 1993-01-29 | Matsushita Electric Ind Co Ltd | Formation method of electric connection contact and manufacture of mounting board |
JPH09115955A (en) * | 1995-10-16 | 1997-05-02 | Mitsubishi Electric Corp | Semiconductor device packing substrate and its manufacturing method |
JP3346137B2 (en) * | 1995-12-01 | 2002-11-18 | 松下電器産業株式会社 | Method of forming solder bumps |
EP1448033A1 (en) | 1996-12-27 | 2004-08-18 | Matsushita Electric Industrial Co., Ltd. | Method and device for mounting electronic component on a circuit board |
JP2003023243A (en) * | 2001-07-05 | 2003-01-24 | Canon Inc | Wiring board |
JP3893100B2 (en) * | 2002-10-29 | 2007-03-14 | 新光電気工業株式会社 | Electronic component mounting method on wiring board |
JP4424020B2 (en) * | 2003-11-10 | 2010-03-03 | カシオ計算機株式会社 | Mounting structure and mounting method of semiconductor device |
JP4387265B2 (en) * | 2004-07-29 | 2009-12-16 | 株式会社タムラ製作所 | Method for manufacturing protruding electrode |
JP3955302B2 (en) | 2004-09-15 | 2007-08-08 | 松下電器産業株式会社 | Method of manufacturing flip chip mounting body |
CN101432861B (en) * | 2006-04-27 | 2011-02-09 | 松下电器产业株式会社 | Connection structure and method of producing the same |
JP5065657B2 (en) * | 2006-11-27 | 2012-11-07 | パナソニック株式会社 | Electronic device and manufacturing method thereof |
JP4859717B2 (en) * | 2007-03-14 | 2012-01-25 | 株式会社タムラ製作所 | Solder composition |
JP5245276B2 (en) * | 2007-04-11 | 2013-07-24 | 日本電気株式会社 | Electronic component mounting structure and mounting method thereof |
JP4569605B2 (en) * | 2007-07-09 | 2010-10-27 | 日本テキサス・インスツルメンツ株式会社 | Filling method of underfill of semiconductor device |
-
2009
- 2009-06-22 KR KR1020090055478A patent/KR101208028B1/en active IP Right Grant
- 2009-09-23 US US12/565,171 patent/US8030200B2/en active Active
- 2009-12-22 JP JP2009290915A patent/JP5588667B2/en not_active Expired - Fee Related
-
2014
- 2014-05-21 JP JP2014105301A patent/JP2014195107A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5136365A (en) * | 1990-09-27 | 1992-08-04 | Motorola, Inc. | Anisotropic conductive adhesive and encapsulant material |
US6064120A (en) * | 1997-08-21 | 2000-05-16 | Micron Technology, Inc. | Apparatus and method for face-to-face connection of a die face to a substrate with polymer electrodes |
US6878435B2 (en) * | 2001-07-19 | 2005-04-12 | Korea Advanced Institute Of Science And Technology | High adhesion triple layered anisotropic conductive adhesive film |
US7227267B2 (en) * | 2004-10-11 | 2007-06-05 | Samsung Electro-Mechanics Co., Ltd. | Semiconductor package using flip-chip mounting technique |
US20100006625A1 (en) * | 2008-07-10 | 2010-01-14 | Electronics And Telecommunications Research Institute | Composition and methods of forming solder bump and flip chip using the same |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110033977A1 (en) * | 2009-08-06 | 2011-02-10 | Maxim Integrated Products, Inc. | Method of forming solderable side-surface terminals of quad no-lead frame (qfn) integrated circuit packages |
US8709870B2 (en) * | 2009-08-06 | 2014-04-29 | Maxim Integrated Products, Inc. | Method of forming solderable side-surface terminals of quad no-lead frame (QFN) integrated circuit packages |
US9159586B1 (en) | 2009-08-06 | 2015-10-13 | Maxim Integrated Products, Inc. | Method of forming solderable side-surface terminals of quad no-lead frame (QFN) integrated circuit packages |
US20110233767A1 (en) * | 2010-03-29 | 2011-09-29 | Panasonic Corporation | Semiconductor device and semiconductor device manufacturing method |
US8367539B2 (en) * | 2010-03-29 | 2013-02-05 | Panasonic Corporation | Semiconductor device and semiconductor device manufacturing method |
US20120205796A1 (en) * | 2011-02-15 | 2012-08-16 | Hynix Semiconductor Inc. | Semiconductor package and method for manufacturing the same |
US8703533B2 (en) * | 2011-02-15 | 2014-04-22 | SK Hynix Inc. | Semiconductor package and method for manufacturing the same |
WO2013177541A1 (en) * | 2012-05-25 | 2013-11-28 | Applied Materials, Inc. | Polymer hot-wire chemical vapor deposition in chip scale packaging |
US20190067240A1 (en) * | 2017-08-23 | 2019-02-28 | Boe Technology Group Co., Ltd | Flexible display panel and preparation method thereof, flexible display device |
US10622330B2 (en) * | 2017-08-23 | 2020-04-14 | Boe Technology Group Co., Ltd. | Flexible display panel and preparation method thereof, flexible display device |
Also Published As
Publication number | Publication date |
---|---|
JP5588667B2 (en) | 2014-09-10 |
KR20100137183A (en) | 2010-12-30 |
KR101208028B1 (en) | 2012-12-04 |
JP2014195107A (en) | 2014-10-09 |
US8030200B2 (en) | 2011-10-04 |
JP2011003876A (en) | 2011-01-06 |
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