US20100315094A1 - Overlay key, method of forming the overlay key and method of measuring overlay accuracy using the overlay key - Google Patents
Overlay key, method of forming the overlay key and method of measuring overlay accuracy using the overlay key Download PDFInfo
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- US20100315094A1 US20100315094A1 US12/805,725 US80572510A US2010315094A1 US 20100315094 A1 US20100315094 A1 US 20100315094A1 US 80572510 A US80572510 A US 80572510A US 2010315094 A1 US2010315094 A1 US 2010315094A1
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
- H01L2223/5446—Located in scribe lines
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- Example embodiments relate to an overlay key used in a semiconductor manufacturing process. More particularly, example embodiments relate to an overlay key for measuring overlay accuracy between patterned layers stacked on a semiconductor substrate, method of forming the overlay key and method of measuring the overlay accuracy using the overlay key.
- a semiconductor device is manufactured by repeatedly forming patterned layers on a semiconductor substrate such as a silicon wafer, for example.
- the patterned layers may be formed by one or more layer formation processes including, but not limited to, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition, etc., and may be patterned by a photolithography process and/or an etching process, for example.
- CVD chemical vapor deposition
- PVD physical vapor deposition
- atomic layer deposition etc.
- the overlay accuracy between the patterned layers may be measured using an overlay key formed in the patterned layers.
- a conventional overlay key may include a lower overlay pattern formed in a lower layer and an upper overlay pattern formed on an upper layer.
- a conventional overlay key may have a box-in-box shape.
- the overlay accuracy may be determined by measuring the alignment accuracy between the lower and upper overlay patterns, and an alignment correction value between a semiconductor substrate and a photo mask (or reticle) may be determined according to the overlay accuracy in a photolithography process.
- Example embodiments provide an advanced form of an overlay key to improve measurement of overlay accuracy.
- Example embodiments provide a method of forming an advanced overlay key.
- Example embodiments also provide a method of measuring overlay accuracy using an overlay key.
- an overlay key may be used for measuring overlay accuracy between a first layer and a second layer on a substrate.
- An example embodiment of an overlay key may include a first mark formed in the first layer and having first patterns with a first pitch extending in a first direction; and a second mark formed on the second layer adjacent to the first mark and having second patterns with a second pitch substantially equal to the first pitch and extending in a substantially same direction as the first direction.
- the second mark may be disposed adjacent to the first mark in the first direction.
- the second mark may be disposed adjacent to the first mark in a second direction substantially perpendicular to the first direction.
- the first and second patterns may be arranged such that each of the first and second marks has a rectangular box shape.
- the first and second marks may be arranged such that a side portion of the first mark is adjacent to a side portion of the second mark.
- an overlay key may be used for measuring overlay accuracy between a first layer and a second layer on a substrate.
- the overlay key may include a first mark having first patterns with a first pitch extending in a first direction; a second mark having second patterns formed in the first layer with a second pitch and extending in a second direction substantially perpendicular to the first direction; a third mark having third patterns formed on the second layer adjacent to the first mark, extending substantially the same direction as the first direction, and having a third pitch substantially equal to the first pitch; and a fourth mark formed on the second layer adjacent to the second mark and having fourth patterns with a fourth pitch substantially equal to the second pitch and extending in substantially the same direction the second direction.
- the third mark may be adjacent to the first mark in the first direction and the fourth mark may be adjacent to the second mark in the first direction.
- the fourth mark may be adjacent to the second mark in the second direction.
- the third mark may be disposed adjacent to the first mark in the second direction.
- a first layer may be formed on a substrate and patterned to form a first mark having first patterns with a first pitch and extending in a first direction.
- a second layer may be formed on the patterned first layer, and a second mark may be formed on the second layer.
- the second mark may be adjacent to the first mark.
- the second mark may have second patterns extending in substantially the same direction as the first direction and having a second pitch substantially equal to the first pitch.
- the second mark may be adjacent to the first mark in the first direction.
- the second mark may be adjacent to the first mark in a second direction substantially perpendicular to the first direction.
- the first and second patterns may be arranged such that each of the first and second marks has a rectangular box shape. Also, the first and second marks may be arranged such that a side portion of the first mark is adjacent to a side portion of the second mark.
- a first layer may be formed on a substrate and patterned to form a first mark and a second mark.
- the first mark may include first patterns extending in a first direction and having a first pitch.
- the second mark may include second patterns extending in a second direction substantially perpendicular to the first direction and having a second pitch.
- a second layer may be formed on the patterned first layer.
- a third mark and a fourth mark may be formed on the second layer.
- the third mark may be adjacent to the first mark, and the fourth mark may be adjacent to the second mark.
- the third mark may include third patterns extending in a substantially same direction as the first direction and having a third pitch substantially equal to the first pitch.
- the fourth mark may include fourth patterns extending in substantially the same direction as the second direction and having a fourth pitch substantially equal to the second pitch.
- the third mark may be adjacent to the first mark in the first direction
- the fourth mark may be adjacent to the second mark in the first direction
- the fourth mark may be disposed adjacent to the second mark in the second direction.
- an overlay key may be used for measuring a first layer and a second layer on a substrate.
- the overlay key may include a first mark formed in the first layer and a second mark formed on the second layer adjacent to the first mark.
- the first mark may include first patterns extending in a first direction and having a first pitch; and the second mark may include second patterns extending in substantially the same direction as the first direction and having a second pitch substantially equal to the first pitch.
- a first image and a second image may be acquired from the first mark and the second mark, respectively.
- a test image may have a third pitch and may be overlaid onto the first and second images.
- the overlay accuracy between the first and second layers may be produced from position information of a first interference fringe formed by overlaying the test image onto the first image and a second interference fringe formed by overlaying the test image onto the second image.
- the test image may include a line-and-space pattern extending in substantially the same direction as the first direction.
- the second mark may be disposed adjacent to the first mark in the first direction, and the overlay accuracy may be produced according to a phase difference between the first and second interference fringes.
- the second mark may be adjacent to the first mark in a second direction substantially perpendicular to the first direction, and the overlay accuracy may be produced according to an angle between the first and second interference fringes.
- the test image may include a line-and-space pattern extending in a second direction that is tilted with respect to the first direction.
- FIGS. 2 and 3 are cross-sectional views illustrating the example embodiment of the overlay key shown in FIG. 1 ;
- FIG. 4 is a plan view illustrating another example embodiment of an overlay key
- FIGS. 5 and 6 are cross-sectional views illustrating the example embodiment of the overlay key shown in FIG. 4 ;
- FIGS. 7 to 9 are plan views illustrating additional example embodiments of overlay keys
- FIGS. 10 to 13 are plan views and cross-sectional views illustrating an example embodiment of a method of forming the overlay key shown in FIG. 7 ;
- FIG. 14 is a flow chart illustrating an example embodiment of a method of measuring overlay accuracy using the overlay key shown in FIG. 1 ;
- FIG. 15 is a schematic view illustrating an example test image, and example first and second images acquired from the first and second marks shown in FIG. 1 ;
- FIG. 16 is a schematic view illustrating example first and second interference fringes formed by overlaying the test image onto the first and second images shown in FIG. 15 ;
- FIG. 17 is a schematic view illustrating another example of first and second interference fringes formed by overlaying the test image onto the first and second images shown in FIG. 15 ;
- FIG. 18 is a schematic view illustrating variation of the example interference fringes according to rotation of a second mark of the overlay key shown in FIG. 1 ;
- FIG. 19 is a schematic view illustrating example first and second interference fringes formed by overlaying an example test image onto the example first and second images acquired from the first and second marks shown in FIG. 3 ;
- FIG. 20 is a schematic view illustrating another example of first and second interference fringes formed by overlaying an example test image onto the example first and second images acquired from first and second marks shown in FIG. 3 ;
- FIG. 21 is a schematic view illustrating variation of the example interference fringes according to rotation of a second mark of the example embodiment of the overlay key shown in FIG. 3 .
- first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.
- a first thin film could be termed a second thin film, and, similarly, a second thin film could be termed a first thin film without departing from the teachings of the disclosure.
- relative terms such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element's relationship to another element as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The exemplary term “lower,” can therefore, encompasses both an orientation of “lower” and “upper,” depending of the particular orientation of the figure.
- Example embodiments are described herein with reference to cross section illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as flat may have rough and/or nonlinear features. Moreover, sharp angles that are illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present invention.
- FIG. 1 is a plan view illustrating an example embodiment of an overlay key
- FIGS. 2 and 3 are cross-sectional views illustrating the overlay key shown in FIG. 1 .
- a semiconductor substrate 10 for example, a silicon wafer may have a plurality of device forming regions, which may be divided by a plurality of scribe lanes 12 .
- the scribe lanes 12 may intersect at right angles.
- a first layer 14 and a second layer 16 may be arranged on the substrate 10 .
- An example embodiment of an overlay key 100 may be used for measuring overlay accuracy between a first circuit pattern (not shown) formed in the first layer 14 and a second circuit pattern (not shown) formed in the second layer 16 .
- the overlay key 100 may include a first mark 110 formed in the first layer 14 and a second mark 120 formed on the second layer 16 .
- the overlay key may be formed on the scribe lane 12 .
- the first mark 110 may include first patterns 112 , which may be repeatedly formed in the first layer 14 and may have a first pitch P 1 .
- the first mark 110 may have a line-and-space shape extending in a first direction.
- the first pitch P 1 may be within a range of about 200 nm to about 2 ⁇ m.
- the first pitch P 1 may be about 1 ⁇ m.
- the second layer 16 may be formed on the first layer 14 .
- the second mark 120 and a photoresist pattern (not shown) may be formed on the second layer 16 .
- the photoresist pattern may be used as an etching mask in a subsequent patterning process for forming the second circuit pattern.
- the second mark 120 may be disposed adjacent to the first mark 110 and may include second patterns 122 that are repeatedly formed on the second layer 16 . Further, the second patterns 122 of the second mark 120 may have a second pitch P 2 substantially equal to the first pitch P 1 .
- the second mark 120 may have a line-and-space shape and may extend in a direction substantially the same as the first direction.
- the first patterns 112 and the second patterns 122 may be arranged such that each of the first and second marks 110 and 120 has a rectangular box shape. Further, the first and second marks 110 and 120 may be arranged such that a side portion of the first mark 110 is disposed adjacent to a side portion of the second mark 120 . As shown in the example embodiment of FIG. 1 , the first mark 110 may be disposed adjacent to the second mark 120 in the first direction.
- FIG. 4 is a plan view illustrating another example embodiment of an overlay key
- FIGS. 5 and 6 are cross-sectional views of the overlay key shown in FIG. 4 .
- a first layer 24 having a first circuit pattern may be formed on a semiconductor substrate 20 , and a second layer 26 may be formed on the first layer 24 .
- a photoresist pattern (not shown) may be formed on the second layer 26 , which may be used for patterning the second layer 26 to form a second circuit pattern (not shown).
- An overlay key 200 may be used for measuring overlay accuracy between the first and second circuit patterns.
- the overlay key 200 may include a first mark 210 formed in the first layer 24 and a second mark 220 formed on the second layer 26 .
- the first and second marks 210 and 220 may be formed on a scribe lane 22 of the substrate 20 .
- the first mark 210 may include first patterns 212 that are repeatedly formed in a first direction in the first layer 24 .
- the first patterns 212 may have a first pitch P 1 .
- the first mark 210 may have a line-and-space shape extending in a second direction substantially perpendicular to the first direction.
- the first pitch P 1 may be within a range of about 200 nm to about 2 ⁇ m.
- the first pitch P 1 may be about 1 ⁇ m.
- the second mark 220 may be disposed adjacent to the first mark 210 and may include second patterns 222 that are repeatedly formed in the first direction. Further, the second mark 220 may have a second pitch P 2 substantially equal to the first pitch P 1 . The second mark 220 may have a line-and-space shape extending in the second direction.
- the first pattern 212 and second pattern 222 may be arranged such that the first mark 210 and second mark 220 each have a rectangular box shape.
- the first mark 210 may be disposed adjacent to the second mark 220 in the first direction.
- FIG. 7 is a plan view illustrating still another example embodiment of an overlay key.
- a first layer having a first circuit pattern may be formed on a semiconductor substrate 30 , and a second layer to be patterned may be formed on the first layer.
- a photoresist pattern may be formed on the second layer, which may be used as etching mask during a patterning process of the second layer.
- An overlay key 300 may be formed on a scribe lane 32 of the substrate 30 .
- the overlay key 300 may include first and second marks 310 and 320 formed in the first layer, and third and fourth marks 330 and 340 formed on the second layer.
- the first mark 310 may include first patterns 312 extending in a first direction and having a first pitch P 1 .
- the second mark 320 may include second patterns 322 extending in a second direction substantially perpendicular to the first direction and having a second pitch P 2 .
- the first pitch P 1 may be substantially equal to the second pitch P 2 .
- the first pitch P 1 may be different from the second pitch P 2 according to alternative example embodiments.
- the third mark 330 may be formed on the second layer adjacent to the first mark 310 and may include third patterns 332 extending in substantially the same direction as the first direction. Further, the third mark 330 may have a third pitch P 3 substantially equal to the first pitch P 1 .
- the fourth mark 340 may be formed on the second layer adjacent to the second mark 320 and may include fourth patterns 342 extending in substantially the same direction as the second direction. Further, the fourth patterns 342 of the fourth mark 340 may have a fourth pitch P 4 substantially equal to the second pitch P 2 .
- the third and fourth marks 330 and 340 may be disposed adjacent to the first and second marks 310 and 320 in the first direction.
- the third mark 330 may be disposed adjacent to the first mark 310 and have third patterns 332 extending in the first direction
- the fourth mark 340 may be disposed adjacent to the second mark 320 and have fourth patterns 342 extending in the second direction.
- the third mark 330 may be disposed adjacent to the fourth mark 340 in the second direction
- the fourth mark 340 may be disposed adjacent to the second mark 320 in the first direction.
- the marks may be disposed in different configurations, and examples of the configurations and relations of the marks are shown in FIGS. 8 and 9 .
- a first mark 410 may be disposed on a first scribe lane extending in a first direction
- a second mark 420 may be disposed on a second scribe lane extending in a second direction substantially perpendicular to the first direction.
- the first mark 410 may extend in the first direction
- the second mark 420 may extend in the second direction.
- a third mark 430 may be disposed adjacent to the first mark 410 in the first direction, and a fourth mark 440 may be disposed adjacent to the second mark 420 in the second direction. Further, the third mark 430 may extend in the first direction, and the fourth mark 440 may extend in the second direction.
- a first mark 510 may be disposed on a first scribe lane extending in a first direction
- a second mark 520 may be disposed on a second scribe lane extending in a second direction substantially perpendicular to the first direction.
- the first mark 510 may extend in the second direction
- the second mark 520 may extend in the first direction.
- a third mark 530 may be disposed adjacent to the first mark 510 in the first direction, and a fourth mark 540 may be disposed adjacent to the second mark 520 in the second direction. Further, the third mark 530 may extend in the second direction, and the fourth mark 540 may extend in the first direction.
- FIGS. 10 to 13 are plan views and cross-sectional views illustrating a method of forming example embodiments of overlay keys such as the example embodiment of the overlay key shown in FIG. 7 , for example.
- a first layer 34 may be formed on a semiconductor substrate 30 .
- the first layer 34 may have a first circuit pattern (not shown) and first and second marks 310 and 320 .
- the first and second marks 310 and 320 may be used for measuring overlay accuracy.
- the first layer may include conductive material or insulating material and may be formed using one or more layer formation processes including, but not limited to, a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, etc.
- a mask pattern may be formed on the first layer 34 and then, the first circuit pattern, the first mark 310 and the second mark 320 may be formed by an anisotropic etching process using the mask pattern as an etching mask.
- the mask pattern may be a photoresist pattern.
- the mask pattern may be a nitride layer pattern formed using the photoresist pattern.
- the first and second marks 310 and 320 may be formed on a scribe lane 32 of the substrate 30 .
- the first mark 310 may extend in a first direction and may include first patterns 312 having a line-and-space shape.
- the first patterns 312 of the first mark 310 may have a first pitch P 1 .
- the second mark 320 may extend in a second direction substantially perpendicular to the first direction.
- the second mark 320 may include second patterns having a line-and-space shape and a second pitch P 2 .
- a second layer 36 may be formed on the first layer 34 . Then, a photoresist pattern (not shown) for patterning the second layer 36 , as well as third and fourth marks 330 and 340 for measuring the overlay accuracy may be formed on the second layer 36 .
- a second circuit pattern may be formed in the second layer 36 by patterning the second layer 36 .
- the first, second, third and fourth marks 310 , 320 , 330 and 340 may be used for measuring the overlay accuracy between the first and second circuit patterns before forming the second circuit pattern.
- the third and fourth marks 330 and 340 may include photoresist and may be disposed adjacent to the first and second marks 310 and 320 , respectively.
- the third mark 330 may include third patterns 332 extending in substantially the same direction as the first direction and having a third pitch P 3 substantially equal to the first pitch P 1 .
- the fourth mark 340 may include fourth patterns extending in substantially the same direction as the second direction and having a fourth pitch P 4 substantially equal to the second pitch P 2 .
- the second layer 36 may include conductive material or insulating material and may be formed by a layer formation process well known to those skilled in the art.
- the photoresist pattern, the third mark 330 and the fourth mark 340 may be formed by a photolithography process well known to those skilled in the art.
- FIG. 14 is a flow chart illustrating a method of measuring overlay accuracy using an example embodiment of an overlay key such as the overlay key shown in FIG. 1 , for example.
- FIG. 15 is a schematic view illustrating a test image, and example first and second images acquired from first and second marks 110 and 120 shown in FIG. 1 .
- FIG. 16 is a schematic view illustrating example first and second interference fringes formed by overlaying the test image onto the first and second images as shown in FIG. 15 .
- a first image 610 and a second image 620 may be acquired from the first and second marks 110 and 120 formed on the substrate 10 (S 100 ).
- the first and second images 610 and 620 may be acquired by an optical microscope, for example.
- the first mark 110 may include first patterns 112 that extend in a first direction having a line-and-space shape and a first pitch P 1 .
- the second mark 120 may include second patterns 122 extending in substantially the same direction as the first direction having a line-and-space shape and a second pitch P 2 substantially equal to the first pitch P 1 .
- a test image 630 may be overlaid onto the first and second images 610 and 620 (S 110 ).
- the test image may include a line-and-space pattern extending in substantially the same direction as the first direction and having a fifth pitch P 33 different from the first pitch P 1 .
- a ratio of the fifth pitch P 33 to the first pitch P 1 may be within a range of about 0.5 to about 1.5.
- the fifth pitch P 33 is within a range of about 0.5 ⁇ m to about 1.5 ⁇ m.
- the fifth pitch P 33 may be set within a range of about 0.8 ⁇ m to about 1.2 ⁇ m.
- a first interference fringe 640 may be formed by overlaying the test image 630 onto the first image 610 and a second interference fringe 650 may be formed by overlaying the test image 630 onto the second image 620 (S 110 ).
- the first and second interference fringes 640 and 650 may be formed according to a difference between the first pitch P 1 and fifth pitch P 33 .
- the overlay accuracy may be produced from position information of the first and second interference fringes 640 and 650 (S 120 ).
- Each of the first and second interference fringes 640 and 650 may have a regularly repeated pattern. However, the second interference fringe 650 may shift in a second direction substantially perpendicular to the first direction with respect to the first interference fringe 640 in accordance with the overlay accuracy between the first and second marks 110 and 120 . That is, the overlay accuracy may be produced from a phase difference between the first and second interference fringes 640 and 650 .
- a measurement range of the overlay accuracy using the first and second interference fringes 640 and 650 may be smaller than the first pitch P 1 .
- the overlay accuracy measurement using the phase difference between the first and second interference fringes 640 and 650 may be desirably performed after an overlay accuracy measurement using the first and second images 610 and 620 is performed according to an example embodiment.
- the overlay accuracy may be produced more precisely by first measuring misalignment between the first and second marks 110 and 120 using the first and second images 610 and 620 , and second producing misalignment between the first and second marks 110 and 120 using the first and second interference fringes 640 and 650 .
- FIG. 17 is a schematic view illustrating another example of first and second interference fringes formed by overlaying the test image onto the example first and second images shown in FIG. 15 .
- a test image 630 a is tilted at approximately 2° with respect to the extension direction (e.g., the first direction) of the first image 610 .
- the overlay accuracy in the second direction may be produced from the phase difference between first and second interference fringes 640 a and 650 a formed by overlaying the tilted test image 630 a onto the first and second images 610 and 620 according to an example embodiment.
- the tilted test image 630 a may have a fifth pitch P 33 substantially equal to the first pitch P 1 . Further, the tilt angle of the tilted test image 630 a may be suitably determined to improve a reliability of the overlay accuracy measurement.
- FIG. 18 is a schematic view illustrating variation of interference fringes according to rotation of a second mark of the example embodiment of the overlay key shown in FIG. 1 .
- the overlay accuracy may be readily produced using the first interference fringe 640 and a second interference fringe 650 b that is formed by overlaying the test image 630 onto the first image 610 and the rotated image 620 a .
- the overlay accuracy may be produced from an angle between extension directions of the first and second interference fringes 640 and 650 b.
- FIG. 19 is a schematic view illustrating first and second interference fringes formed by overlaying a test image onto first and second images acquired from example first and second marks shown in FIG. 3 .
- a first image 710 acquired from the first mark 210 shown in FIG. 3 may extend in a second direction and have a first pitch P 1 .
- a second image 720 acquired from the second mark 220 shown in FIG. 3 may extend in substantially the same direction as the second direction and may have a second pitch P 2 substantially equal to the first pitch P 1 .
- the first image 710 may be disposed adjacent to the second image 720 in a first direction substantially perpendicular to the second direction.
- a test image may extend in the second direction and may have a fifth pitch P 33 different from the first pitch P 1 .
- misalignment between the first and second images 710 and 720 may be produced from variation of a period between first and second interference fringes 740 and 750 .
- FIG. 20 is a schematic view illustrating another example embodiment of first and second interference fringes formed by overlaying a test image onto first and second images acquired from example first and second marks shown in FIG. 3 .
- a test image 730 a may be tilted by approximately 5° with respect to the extension direction (e.g., the second direction) of the first image 710 .
- the overlay accuracy in the first direction substantially perpendicular to the second direction may be produced from the phase difference between the first and second interference fringes 740 a and 750 a formed by overlaying the tilted test image 730 a onto the first and second images 710 and 720 .
- the phase difference may be varied in accordance with a distance between the first and second images 710 and 720 .
- the tilted test image 730 a may have a pitch substantially equal to that of the first or second image.
- FIG. 21 is a schematic view illustrating variation of interference fringes according to rotation of a second mark of the example embodiment of the overlay key shown in FIG. 3 .
- the overlay accuracy may be produced from first and second interference fringes 740 and 750 b formed by overlaying the test image 730 onto the first image 710 and the rotated second image 720 a.
- the overlay accuracy may be measured more precisely and easily using the interference fringes formed by overlaying the test image onto the images acquired from the marks of the overlay key.
Abstract
In an overlay key used for measuring overlay accuracy between first and second layers on a substrate, a first mark may be formed in the first layer, and a second mark may be formed on the second layer. The first mark may include first patterns having a first pitch and extending in a first direction. The second mark may include second patterns extending in substantially the same direction as the first direction and having a second pitch substantially equal to the first pitch. First and second images may be acquired from the first and second marks. The overlay accuracy may be produced from position information of first and second interference fringes formed by overlaying a test image having a third pitch onto the first and second images.
Description
- This application is a Divisional of U.S. application Ser. No. 11/527,592 filed Sep. 27, 2006, which claims priority from Korean Patent Application No. 2005-92637 filed on Oct. 1, 2005, the contents of each of which are hereby incorporated by reference in their entirety.
- 1. Field of the Invention
- Example embodiments relate to an overlay key used in a semiconductor manufacturing process. More particularly, example embodiments relate to an overlay key for measuring overlay accuracy between patterned layers stacked on a semiconductor substrate, method of forming the overlay key and method of measuring the overlay accuracy using the overlay key.
- 2. Description of the Related Art
- Generally, a semiconductor device is manufactured by repeatedly forming patterned layers on a semiconductor substrate such as a silicon wafer, for example. The patterned layers may be formed by one or more layer formation processes including, but not limited to, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition, etc., and may be patterned by a photolithography process and/or an etching process, for example.
- The overlay accuracy between the patterned layers may be measured using an overlay key formed in the patterned layers. In general, a conventional overlay key may include a lower overlay pattern formed in a lower layer and an upper overlay pattern formed on an upper layer. A conventional overlay key may have a box-in-box shape.
- The overlay accuracy may be determined by measuring the alignment accuracy between the lower and upper overlay patterns, and an alignment correction value between a semiconductor substrate and a photo mask (or reticle) may be determined according to the overlay accuracy in a photolithography process.
- As the packing density of semiconductor devices increase, the significance of measuring the overlay accuracy generally increases.
- Example embodiments provide an advanced form of an overlay key to improve measurement of overlay accuracy.
- Example embodiments provide a method of forming an advanced overlay key.
- Example embodiments also provide a method of measuring overlay accuracy using an overlay key.
- In an example embodiment, an overlay key may be used for measuring overlay accuracy between a first layer and a second layer on a substrate. An example embodiment of an overlay key may include a first mark formed in the first layer and having first patterns with a first pitch extending in a first direction; and a second mark formed on the second layer adjacent to the first mark and having second patterns with a second pitch substantially equal to the first pitch and extending in a substantially same direction as the first direction.
- In some example embodiments, the second mark may be disposed adjacent to the first mark in the first direction.
- In some example embodiments, the second mark may be disposed adjacent to the first mark in a second direction substantially perpendicular to the first direction.
- In some example embodiments, the first and second patterns may be arranged such that each of the first and second marks has a rectangular box shape. The first and second marks may be arranged such that a side portion of the first mark is adjacent to a side portion of the second mark.
- In another example embodiment, an overlay key may be used for measuring overlay accuracy between a first layer and a second layer on a substrate. In addition, the overlay key may include a first mark having first patterns with a first pitch extending in a first direction; a second mark having second patterns formed in the first layer with a second pitch and extending in a second direction substantially perpendicular to the first direction; a third mark having third patterns formed on the second layer adjacent to the first mark, extending substantially the same direction as the first direction, and having a third pitch substantially equal to the first pitch; and a fourth mark formed on the second layer adjacent to the second mark and having fourth patterns with a fourth pitch substantially equal to the second pitch and extending in substantially the same direction the second direction.
- In some example embodiments, the third mark may be adjacent to the first mark in the first direction and the fourth mark may be adjacent to the second mark in the first direction.
- In some example embodiments, the fourth mark may be adjacent to the second mark in the second direction.
- In some example embodiments, the third mark may be disposed adjacent to the first mark in the second direction.
- In still another example embodiment, a first layer may be formed on a substrate and patterned to form a first mark having first patterns with a first pitch and extending in a first direction. A second layer may be formed on the patterned first layer, and a second mark may be formed on the second layer. The second mark may be adjacent to the first mark. Also, the second mark may have second patterns extending in substantially the same direction as the first direction and having a second pitch substantially equal to the first pitch.
- In some example embodiments, the second mark may be adjacent to the first mark in the first direction.
- In some example embodiments, the second mark may be adjacent to the first mark in a second direction substantially perpendicular to the first direction.
- In some example embodiments, the first and second patterns may be arranged such that each of the first and second marks has a rectangular box shape. Also, the first and second marks may be arranged such that a side portion of the first mark is adjacent to a side portion of the second mark.
- In still another example embodiment, a first layer may be formed on a substrate and patterned to form a first mark and a second mark. The first mark may include first patterns extending in a first direction and having a first pitch. The second mark may include second patterns extending in a second direction substantially perpendicular to the first direction and having a second pitch. A second layer may be formed on the patterned first layer. A third mark and a fourth mark may be formed on the second layer. The third mark may be adjacent to the first mark, and the fourth mark may be adjacent to the second mark. The third mark may include third patterns extending in a substantially same direction as the first direction and having a third pitch substantially equal to the first pitch. The fourth mark may include fourth patterns extending in substantially the same direction as the second direction and having a fourth pitch substantially equal to the second pitch.
- In some example embodiments, the third mark may be adjacent to the first mark in the first direction, and the fourth mark may be adjacent to the second mark in the first direction.
- In some example embodiments, the fourth mark may be disposed adjacent to the second mark in the second direction.
- In some example embodiments, the third mark may be disposed adjacent to the first mark in the second direction.
- In still another example embodiment, an overlay key may be used for measuring a first layer and a second layer on a substrate. The overlay key may include a first mark formed in the first layer and a second mark formed on the second layer adjacent to the first mark. The first mark may include first patterns extending in a first direction and having a first pitch; and the second mark may include second patterns extending in substantially the same direction as the first direction and having a second pitch substantially equal to the first pitch. A first image and a second image may be acquired from the first mark and the second mark, respectively. A test image may have a third pitch and may be overlaid onto the first and second images. The overlay accuracy between the first and second layers may be produced from position information of a first interference fringe formed by overlaying the test image onto the first image and a second interference fringe formed by overlaying the test image onto the second image.
- In some example embodiments, the test image may include a line-and-space pattern extending in substantially the same direction as the first direction.
- In some example embodiments, the third pitch may be different from the first pitch and a ratio of the third pitch to the first pitch may be within a range of about 0.5 to about 1.5.
- In some example embodiments, the second mark may be disposed adjacent to the first mark in the first direction, and the overlay accuracy may be produced according to a phase difference between the first and second interference fringes.
- In some example embodiments, the second mark may be adjacent to the first mark in a second direction substantially perpendicular to the first direction, and the overlay accuracy may be produced according to an angle between the first and second interference fringes.
- In some example embodiments, the test image may include a line-and-space pattern extending in a second direction that is tilted with respect to the first direction.
- According to the example embodiments, the overlay accuracy may be measured more easily and precisely using interference fringes formed by overlaying the test image onto the images obtained from the marks of the overlay key.
- Example embodiments will become readily apparent by considering the following detailed description of example embodiments in conjunction with the accompanying drawings wherein:
-
FIG. 1 is a plan view illustrating an example embodiment of an overlay key; -
FIGS. 2 and 3 are cross-sectional views illustrating the example embodiment of the overlay key shown inFIG. 1 ; -
FIG. 4 is a plan view illustrating another example embodiment of an overlay key; -
FIGS. 5 and 6 are cross-sectional views illustrating the example embodiment of the overlay key shown inFIG. 4 ; -
FIGS. 7 to 9 are plan views illustrating additional example embodiments of overlay keys; -
FIGS. 10 to 13 are plan views and cross-sectional views illustrating an example embodiment of a method of forming the overlay key shown inFIG. 7 ; -
FIG. 14 is a flow chart illustrating an example embodiment of a method of measuring overlay accuracy using the overlay key shown inFIG. 1 ; -
FIG. 15 is a schematic view illustrating an example test image, and example first and second images acquired from the first and second marks shown inFIG. 1 ; -
FIG. 16 is a schematic view illustrating example first and second interference fringes formed by overlaying the test image onto the first and second images shown inFIG. 15 ; -
FIG. 17 is a schematic view illustrating another example of first and second interference fringes formed by overlaying the test image onto the first and second images shown inFIG. 15 ; -
FIG. 18 is a schematic view illustrating variation of the example interference fringes according to rotation of a second mark of the overlay key shown inFIG. 1 ; -
FIG. 19 is a schematic view illustrating example first and second interference fringes formed by overlaying an example test image onto the example first and second images acquired from the first and second marks shown inFIG. 3 ; -
FIG. 20 is a schematic view illustrating another example of first and second interference fringes formed by overlaying an example test image onto the example first and second images acquired from first and second marks shown inFIG. 3 ; and -
FIG. 21 is a schematic view illustrating variation of the example interference fringes according to rotation of a second mark of the example embodiment of the overlay key shown inFIG. 3 . - Example embodiments are described more fully hereinafter with reference to the accompanying drawings, in which example embodiments are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout.
- It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
- It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first thin film could be termed a second thin film, and, similarly, a second thin film could be termed a first thin film without departing from the teachings of the disclosure.
- The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps; operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
- Furthermore, relative terms, such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element's relationship to another element as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The exemplary term “lower,” can therefore, encompasses both an orientation of “lower” and “upper,” depending of the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. The exemplary terms “below” or “beneath” can, therefore, encompass both an orientation of above and below.
- Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
- Example embodiments are described herein with reference to cross section illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as flat may have rough and/or nonlinear features. Moreover, sharp angles that are illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present invention.
- Hereinafter, example embodiments are explained in detail with reference to the accompanying drawings.
-
FIG. 1 is a plan view illustrating an example embodiment of an overlay key, andFIGS. 2 and 3 are cross-sectional views illustrating the overlay key shown inFIG. 1 . - Referring to
FIGS. 1 to 3 , asemiconductor substrate 10, for example, a silicon wafer may have a plurality of device forming regions, which may be divided by a plurality ofscribe lanes 12. Thescribe lanes 12 may intersect at right angles. Afirst layer 14 and asecond layer 16 may be arranged on thesubstrate 10. An example embodiment of anoverlay key 100 may be used for measuring overlay accuracy between a first circuit pattern (not shown) formed in thefirst layer 14 and a second circuit pattern (not shown) formed in thesecond layer 16. Theoverlay key 100 may include afirst mark 110 formed in thefirst layer 14 and asecond mark 120 formed on thesecond layer 16. The overlay key may be formed on thescribe lane 12. - The
first mark 110 may includefirst patterns 112, which may be repeatedly formed in thefirst layer 14 and may have a first pitch P1. According to an example embodiment, thefirst mark 110 may have a line-and-space shape extending in a first direction. The first pitch P1 may be within a range of about 200 nm to about 2 μm. For example, the first pitch P1 may be about 1 μm. - The
second layer 16 may be formed on thefirst layer 14. Thesecond mark 120 and a photoresist pattern (not shown) may be formed on thesecond layer 16. The photoresist pattern may be used as an etching mask in a subsequent patterning process for forming the second circuit pattern. - The
second mark 120 may be disposed adjacent to thefirst mark 110 and may includesecond patterns 122 that are repeatedly formed on thesecond layer 16. Further, thesecond patterns 122 of thesecond mark 120 may have a second pitch P2 substantially equal to the first pitch P1. Thesecond mark 120 may have a line-and-space shape and may extend in a direction substantially the same as the first direction. - The
first patterns 112 and thesecond patterns 122 may be arranged such that each of the first andsecond marks second marks first mark 110 is disposed adjacent to a side portion of thesecond mark 120. As shown in the example embodiment ofFIG. 1 , thefirst mark 110 may be disposed adjacent to thesecond mark 120 in the first direction. -
FIG. 4 is a plan view illustrating another example embodiment of an overlay key, andFIGS. 5 and 6 are cross-sectional views of the overlay key shown inFIG. 4 . - Referring to
FIGS. 4 to 6 , afirst layer 24 having a first circuit pattern (not shown) may be formed on asemiconductor substrate 20, and asecond layer 26 may be formed on thefirst layer 24. A photoresist pattern (not shown) may be formed on thesecond layer 26, which may be used for patterning thesecond layer 26 to form a second circuit pattern (not shown). - An
overlay key 200 may be used for measuring overlay accuracy between the first and second circuit patterns. Theoverlay key 200 may include afirst mark 210 formed in thefirst layer 24 and a second mark 220 formed on thesecond layer 26. The first andsecond marks 210 and 220 may be formed on ascribe lane 22 of thesubstrate 20. - The
first mark 210 may includefirst patterns 212 that are repeatedly formed in a first direction in thefirst layer 24. Thefirst patterns 212 may have a first pitch P1. Thefirst mark 210 may have a line-and-space shape extending in a second direction substantially perpendicular to the first direction. The first pitch P1 may be within a range of about 200 nm to about 2 μm. For example, the first pitch P1 may be about 1 μm. - The second mark 220 may be disposed adjacent to the
first mark 210 and may includesecond patterns 222 that are repeatedly formed in the first direction. Further, the second mark 220 may have a second pitch P2 substantially equal to the first pitch P1. The second mark 220 may have a line-and-space shape extending in the second direction. - The
first pattern 212 andsecond pattern 222 may be arranged such that thefirst mark 210 and second mark 220 each have a rectangular box shape. Thefirst mark 210 may be disposed adjacent to the second mark 220 in the first direction. -
FIG. 7 is a plan view illustrating still another example embodiment of an overlay key. - Referring to
FIG. 7 , a first layer having a first circuit pattern may be formed on asemiconductor substrate 30, and a second layer to be patterned may be formed on the first layer. A photoresist pattern may be formed on the second layer, which may be used as etching mask during a patterning process of the second layer. An overlay key 300 may be formed on ascribe lane 32 of thesubstrate 30. In addition, the overlay key 300 may include first andsecond marks fourth marks - The
first mark 310 may includefirst patterns 312 extending in a first direction and having a first pitch P1. Thesecond mark 320 may includesecond patterns 322 extending in a second direction substantially perpendicular to the first direction and having a second pitch P2. The first pitch P1 may be substantially equal to the second pitch P2. However, the first pitch P1 may be different from the second pitch P2 according to alternative example embodiments. - The
third mark 330 may be formed on the second layer adjacent to thefirst mark 310 and may includethird patterns 332 extending in substantially the same direction as the first direction. Further, thethird mark 330 may have a third pitch P3 substantially equal to the first pitch P1. - The
fourth mark 340 may be formed on the second layer adjacent to thesecond mark 320 and may includefourth patterns 342 extending in substantially the same direction as the second direction. Further, thefourth patterns 342 of thefourth mark 340 may have a fourth pitch P4 substantially equal to the second pitch P2. - As shown in figures, the third and
fourth marks second marks - However, the
third mark 330 may be disposed adjacent to thefirst mark 310 and havethird patterns 332 extending in the first direction, and thefourth mark 340 may be disposed adjacent to thesecond mark 320 and havefourth patterns 342 extending in the second direction. Further, thethird mark 330 may be disposed adjacent to thefourth mark 340 in the second direction, and thefourth mark 340 may be disposed adjacent to thesecond mark 320 in the first direction. - Moreover, the marks may be disposed in different configurations, and examples of the configurations and relations of the marks are shown in
FIGS. 8 and 9 . - Referring to
FIG. 8 , afirst mark 410 may be disposed on a first scribe lane extending in a first direction, and asecond mark 420 may be disposed on a second scribe lane extending in a second direction substantially perpendicular to the first direction. Thefirst mark 410 may extend in the first direction, and thesecond mark 420 may extend in the second direction. - A
third mark 430 may be disposed adjacent to thefirst mark 410 in the first direction, and afourth mark 440 may be disposed adjacent to thesecond mark 420 in the second direction. Further, thethird mark 430 may extend in the first direction, and thefourth mark 440 may extend in the second direction. - Referring to
FIG. 9 , afirst mark 510 may be disposed on a first scribe lane extending in a first direction, and asecond mark 520 may be disposed on a second scribe lane extending in a second direction substantially perpendicular to the first direction. Thefirst mark 510 may extend in the second direction, and thesecond mark 520 may extend in the first direction. - A
third mark 530 may be disposed adjacent to thefirst mark 510 in the first direction, and afourth mark 540 may be disposed adjacent to thesecond mark 520 in the second direction. Further, thethird mark 530 may extend in the second direction, and thefourth mark 540 may extend in the first direction. -
FIGS. 10 to 13 are plan views and cross-sectional views illustrating a method of forming example embodiments of overlay keys such as the example embodiment of the overlay key shown inFIG. 7 , for example. - Referring to
FIGS. 10 and 11 , afirst layer 34 may be formed on asemiconductor substrate 30. Thefirst layer 34 may have a first circuit pattern (not shown) and first andsecond marks second marks - A mask pattern may be formed on the
first layer 34 and then, the first circuit pattern, thefirst mark 310 and thesecond mark 320 may be formed by an anisotropic etching process using the mask pattern as an etching mask. The mask pattern may be a photoresist pattern. Alternatively, the mask pattern may be a nitride layer pattern formed using the photoresist pattern. - The first and
second marks scribe lane 32 of thesubstrate 30. Thefirst mark 310 may extend in a first direction and may includefirst patterns 312 having a line-and-space shape. Thefirst patterns 312 of thefirst mark 310 may have a first pitch P1. Thesecond mark 320 may extend in a second direction substantially perpendicular to the first direction. Thesecond mark 320 may include second patterns having a line-and-space shape and a second pitch P2. - Referring to
FIGS. 12 and 13 , asecond layer 36 may be formed on thefirst layer 34. Then, a photoresist pattern (not shown) for patterning thesecond layer 36, as well as third andfourth marks second layer 36. A second circuit pattern may be formed in thesecond layer 36 by patterning thesecond layer 36. The first, second, third andfourth marks - The third and
fourth marks second marks - The
third mark 330 may includethird patterns 332 extending in substantially the same direction as the first direction and having a third pitch P3 substantially equal to the first pitch P1. Thefourth mark 340 may include fourth patterns extending in substantially the same direction as the second direction and having a fourth pitch P4 substantially equal to the second pitch P2. - The
second layer 36 may include conductive material or insulating material and may be formed by a layer formation process well known to those skilled in the art. The photoresist pattern, thethird mark 330 and thefourth mark 340 may be formed by a photolithography process well known to those skilled in the art. -
FIG. 14 is a flow chart illustrating a method of measuring overlay accuracy using an example embodiment of an overlay key such as the overlay key shown inFIG. 1 , for example.FIG. 15 is a schematic view illustrating a test image, and example first and second images acquired from first andsecond marks FIG. 1 .FIG. 16 is a schematic view illustrating example first and second interference fringes formed by overlaying the test image onto the first and second images as shown inFIG. 15 . - Referring to
FIGS. 1 and 14 to 16, afirst image 610 and asecond image 620 may be acquired from the first andsecond marks second images - The
first mark 110 may includefirst patterns 112 that extend in a first direction having a line-and-space shape and a first pitch P1. Thesecond mark 120 may includesecond patterns 122 extending in substantially the same direction as the first direction having a line-and-space shape and a second pitch P2 substantially equal to the first pitch P1. - A
test image 630 may be overlaid onto the first andsecond images 610 and 620 (S110). The test image may include a line-and-space pattern extending in substantially the same direction as the first direction and having a fifth pitch P33 different from the first pitch P1. Particularly, a ratio of the fifth pitch P33 to the first pitch P1 may be within a range of about 0.5 to about 1.5. For example, if the first pitch P1 is about 1 μm, the fifth pitch P33 is within a range of about 0.5 μm to about 1.5 μm. According to another example embodiment of the present invention, if the first pitch P1 is about 1 μm, the fifth pitch P33 may be set within a range of about 0.8 μm to about 1.2 μm. - According to an example embodiment, a
first interference fringe 640 may be formed by overlaying thetest image 630 onto thefirst image 610 and asecond interference fringe 650 may be formed by overlaying thetest image 630 onto the second image 620 (S110). The first andsecond interference fringes second interference fringes 640 and 650 (S120). - Each of the first and
second interference fringes second interference fringe 650 may shift in a second direction substantially perpendicular to the first direction with respect to thefirst interference fringe 640 in accordance with the overlay accuracy between the first andsecond marks second interference fringes - If the
second mark 120 shifts by the first pitch P1 from thefirst mark 110 in the second direction, the phase difference does not occur between the first andsecond interference fringes second interference fringes - Thus, the overlay accuracy measurement using the phase difference between the first and
second interference fringes second images second marks second images second marks second interference fringes -
FIG. 17 is a schematic view illustrating another example of first and second interference fringes formed by overlaying the test image onto the example first and second images shown inFIG. 15 . - Referring to
FIG. 17 , atest image 630 a is tilted at approximately 2° with respect to the extension direction (e.g., the first direction) of thefirst image 610. The overlay accuracy in the second direction may be produced from the phase difference between first andsecond interference fringes test image 630 a onto the first andsecond images - In an example embodiment using a tilted
test image 630 a, the tiltedtest image 630 a may have a fifth pitch P33 substantially equal to the first pitch P1. Further, the tilt angle of the tiltedtest image 630 a may be suitably determined to improve a reliability of the overlay accuracy measurement. -
FIG. 18 is a schematic view illustrating variation of interference fringes according to rotation of a second mark of the example embodiment of the overlay key shown inFIG. 1 . - As shown in
FIG. 18 , if thesecond mark 120 is rotated by approximately 1° with respect to thefirst mark 110, the overlay accuracy may be readily produced using thefirst interference fringe 640 and asecond interference fringe 650 b that is formed by overlaying thetest image 630 onto thefirst image 610 and the rotatedimage 620 a. In detail, the overlay accuracy may be produced from an angle between extension directions of the first andsecond interference fringes -
FIG. 19 is a schematic view illustrating first and second interference fringes formed by overlaying a test image onto first and second images acquired from example first and second marks shown inFIG. 3 . - Referring to
FIG. 19 , afirst image 710 acquired from thefirst mark 210 shown inFIG. 3 may extend in a second direction and have a first pitch P1. Asecond image 720 acquired from the second mark 220 shown inFIG. 3 may extend in substantially the same direction as the second direction and may have a second pitch P2 substantially equal to the first pitch P1. Thefirst image 710 may be disposed adjacent to thesecond image 720 in a first direction substantially perpendicular to the second direction. - A test image may extend in the second direction and may have a fifth pitch P33 different from the first pitch P1. In an example embodiment of overlaying the
test image 730 onto the first andsecond images second images second interference fringes -
FIG. 20 is a schematic view illustrating another example embodiment of first and second interference fringes formed by overlaying a test image onto first and second images acquired from example first and second marks shown inFIG. 3 . - Referring to
FIG. 20 , atest image 730 a may be tilted by approximately 5° with respect to the extension direction (e.g., the second direction) of thefirst image 710. The overlay accuracy in the first direction substantially perpendicular to the second direction may be produced from the phase difference between the first andsecond interference fringes test image 730 a onto the first andsecond images second images test image 730 a may have a pitch substantially equal to that of the first or second image. -
FIG. 21 is a schematic view illustrating variation of interference fringes according to rotation of a second mark of the example embodiment of the overlay key shown inFIG. 3 . - As shown in
FIG. 21 , if the second mark 220 is rotated by approximately 1° with respect to thefirst mark 210, the overlay accuracy may be produced from first andsecond interference fringes test image 730 onto thefirst image 710 and the rotatedsecond image 720 a. - Further detailed descriptions on methods of measuring overlay accuracy using the overlay keys as shown in
FIGS. 7 to 9 will be omitted because these methods are similar to those already described with reference toFIGS. 15 to 21 . - In accordance with the example embodiments, the overlay accuracy may be measured more precisely and easily using the interference fringes formed by overlaying the test image onto the images acquired from the marks of the overlay key.
- Although example embodiments have been described above, it is understood that the present invention should not be limited to these example embodiments but various changes and modifications can be made by those skilled in the art within the spirit and scope of the present invention as hereinafter claimed.
Claims (18)
1. An overlay key for measuring overlay accuracy between a first layer and a second layer on a substrate, the overlay key comprising:
a first mark including first patterns with a first pitch formed in the first layer and extending in a first direction; and
a second mark including second patterns formed on the second layer, the second mark disposed adjacent to the first mark, and the second patterns having a second pitch substantially equal to the first pitch and extending in a substantially same direction as the first direction.
2. The overlay key of claim 1 , wherein the second mark is disposed adjacent to the first mark in the first direction.
3. The overlay key of claim 1 , wherein the second mark is disposed adjacent to the first mark in a second direction substantially perpendicular to the first direction.
4. The overlay key of claim 1 , wherein the first and second patterns are arranged such that each of the first and second marks has a rectangular box shape, and the first and second marks are arranged such that a side portion of the first mark is adjacent to a side portion of the second mark.
5. The overlay key of claim 1 , further comprising:
a third mark including third patterns with a third pitch formed in the first layer and extending in a second direction substantially perpendicular to the first direction; and
a fourth mark including fourth patterns formed on the second layer, the fourth mark disposed adjacent to the third mark, and the fourth patterns having a fourth pitch substantially equal to the third pitch and extending in a substantially same direction as the second direction.
6. The overlay key of claim 5 , wherein the second mark is disposed adjacent to the first mark in the first direction.
7. The overlay key of claim 6 , wherein the fourth mark is disposed adjacent to the third mark in the first direction.
8. The overlay key of claim 6 , wherein the fourth mark is disposed adjacent to the second mark in the second direction.
9. The overlay key of claim 5 , wherein the third mark is disposed adjacent to the first mark in the second direction.
10. A method of forming an overlay key comprising:
forming a first layer on a substrate;
patterning the first layer to form a first mark including first patterns extending in a first direction and having a first pitch;
forming a second layer on the patterned first layer; and
forming a second mark on the second layer adjacent to the first mark, the second mark including second patterns extending in a substantially same direction as the first direction and having a second pitch substantially equal to the first pitch.
11. The method of claim 10 , wherein the second mark is formed adjacent to the first mark in the first direction.
12. The method of claim 10 , wherein the second mark is formed adjacent to the first mark in a second direction substantially perpendicular to the first direction.
13. The method of claim 10 , wherein the first and second patterns are arranged such that each of the first and second marks has a rectangular box shape, and the first and second marks are arranged such that a side portion of the first mark is adjacent to a side portion of the second mark.
14. The method of claim 10 , further comprising:
patterning the first layer to form a third mark, the third mark including third patterns extending in a second direction substantially perpendicular to the first direction and having a third pitch; and
forming a fourth mark adjacent to the third mark on the second layer, the fourth mark comprising fourth patterns extending in a substantially same direction as the second direction and having a fourth pitch substantially equal to the third pitch.
15. The method of claim 14 , wherein the second mark is formed adjacent to the first mark in the first direction.
16. The method of claim 15 , wherein the fourth mark is formed adjacent to the third mark in the first direction.
17. The method of claim 15 , wherein the fourth mark is formed adjacent to the second mark in the second direction.
18. The method of claim 14 , wherein the third mark is formed adjacent to the first mark in the second direction.
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Also Published As
Publication number | Publication date |
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US7804596B2 (en) | 2010-09-28 |
US20070077503A1 (en) | 2007-04-05 |
KR100715280B1 (en) | 2007-05-08 |
JP2007103928A (en) | 2007-04-19 |
CN101005061B (en) | 2011-07-27 |
KR20070037522A (en) | 2007-04-05 |
CN101005061A (en) | 2007-07-25 |
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