US20100245144A1 - Sigma-delta modulator including truncation and applications thereof - Google Patents
Sigma-delta modulator including truncation and applications thereof Download PDFInfo
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- US20100245144A1 US20100245144A1 US12/410,964 US41096409A US2010245144A1 US 20100245144 A1 US20100245144 A1 US 20100245144A1 US 41096409 A US41096409 A US 41096409A US 2010245144 A1 US2010245144 A1 US 2010245144A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/3002—Conversion to or from differential modulation
- H03M7/3004—Digital delta-sigma modulation
- H03M7/3015—Structural details of digital delta-sigma modulators
- H03M7/302—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/3002—Conversion to or from differential modulation
- H03M7/3004—Digital delta-sigma modulation
- H03M7/3015—Structural details of digital delta-sigma modulators
- H03M7/3031—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path
- H03M7/3033—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path the modulator having a higher order loop filter in the feedforward path, e.g. with distributed feedforward inputs
- H03M7/304—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path the modulator having a higher order loop filter in the feedforward path, e.g. with distributed feedforward inputs with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage
Definitions
- the invention is in the field of electronics.
- Sigma-delta modulators are commonly used to generate pulses whose summed area is representative of an input signal. The generated pulses may vary in their width or their separation. Sigma-delta modulators are found in a wide variety of electronic components including analog-to-digital (ADC) converters, digital-to-analog (DAC) converters, frequency synthesizers, switched-mode power supplies, switched amplifiers and motor controls.
- ADC analog-to-digital
- DAC digital-to-analog
- frequency synthesizers frequency synthesizers
- switched-mode power supplies switched amplifiers and motor controls.
- FIG. 1 illustrates an example of a second order sigma-delta modulator 100 .
- This module includes a Combiner 105 configured to combine an input signal A and a feedback signal F.
- the combined signals A and F are integrated by a first Integrator 110 to produce an output B.
- a Combiner 115 is used to combine the output B and the feedback signal F.
- the combined signals B and F are then integrated using a second Integrator 120 to produce an output C, which is quantized using a Quantizer 125 to produce a final output D.
- the output is provided to a Feedback Generator 130 to generate the feedback signal F.
- the feedback signal is configured to reduce noise introduced by the integration and quantization.
- Sigma-delta modulators of first order, third order or higher order are known in the prior art.
- the Combiner 115 and Integrator 120 would be omitted, while in a third order modulator an additional Combiner 115 and Integrator 120 would be included.
- An advantage of higher order is that each stage of Combiner 115 and Integrator 120 servers to further reduce noise in the frequency band of interest.
- a disadvantage of higher orders is that then number of bits required to represent the integrated signals (e.g., signals B and C) is greater at each stage. This increases the complexity and time required to perform the signal combinations at each subsequent combiner, e.g., Combiner 115 .
- Various embodiments of the invention include systems and methods of reducing the number of bits used to represent signals between stages of a sigma delta modulator. These embodiments include truncation of the output of one or more integrators. Typically, this truncation includes the removal of one or more least significant bits (LSB). Optionally, truncation is performed through a feedback process in which the one or more LSB is used to generate a feedback signal that is recombined with the signal to be truncated.
- LSB least significant bits
- the sigma delta modulator of the invention may be used in a switched power amplifier, a digital to analog converter, or the like. Some embodiments of the invention are used in place of prior art sigma-delta modulators in applications requiring high frequency digital inputs.
- Various embodiments of the invention include a sigma-delta modulator circuit comprising a first modulation stage including at least a first combiner and a first integrator, the first combiner configured to combine an input signal and a first feedback signal, the first integrator configured to integrate an output of the first combiner and to produce a first multi-bit output; a first truncation stage configured to receive the first multi-bit output and to truncate a least significant bit from the first multi-bit output; a second modulation stage including at least a second combiner and a second integrator, the second combiner configured to combine the truncated output of the first modulation stage and a second feedback signal, the second integrator being configured to integrate an output of the second combiner to produce a second multi-bit output; and a feedback generator configured to generate the first feedback signal and the second feedback signal.
- Various embodiments of the invention include a power amplifier comprising a first sigma-delta modulator stage configured to receive an input signal and to produce a multi-bit output; a second sigma-delta modulator stage configured to receive an input signal generated using the first sigma-delta modulator stage; a first truncation stage disposed between the first sigma-delta modulator stage and the second sigma-delta modulator stage, configured to receive the multi-bit output and configured to truncate at least one of the least significant bits of the multi-bit output prior to providing the truncated multi-bit output to the second sigma-delta modulator; and a feedback generator configured to provide a gain to a feedback loop between an output of the quantifier and the first sigma-delta modulator stage.
- Various embodiments of the invention include a method comprising receiving a signal; combining the received signal with a first feedback signal to produce a first combined signal; integrating the first combined signal to produce a first multi-bit output; truncating the first multi-bit output; combining the truncated first multi-bit output with a second feedback signal to produce a second combined signal; integrating the second combined signal to produce a second multi-bit output; quantizing the second multi-bit output or an output generated using the second multi-bit output to produce a quantized signal; and using the quantized signal to produce the first feedback signal and the second feedback signal.
- FIG. 1 illustrates a two stage sigma delta modulator of the prior art.
- FIG. 2 illustrates a multi-stage sigma-delta modulator, according to various embodiments of the invention.
- FIG. 3 illustrates a truncation circuit, according to various embodiments of the invention.
- FIG. 4 illustrates a second order truncation circuit, according to various embodiments of the invention.
- FIG. 5 illustrates methods, according to various embodiments of the invention.
- FIG. 6 illustrates a circuit including combiners having two inputs, according to various embodiments of the invention.
- a received input signal is combined with a feedback signal using a combiner.
- the output of the combiner is received by an integrator configured to output a multi-bit value representative of an integration of the output of the combiner.
- this multi-bit value includes 2, 3, 4 or more bits.
- One of the bits may be designated as a sign bit.
- the multi-bit output may be in a 2s-compliment format.
- the output of the integrator includes more bits than the input.
- Each stage of a multi-stage sigma-delta modulator includes a combiner and an integrator. Thus, each stage has a multi-bit output.
- the output of each stage includes a greater number of bits than the signal received by that stage.
- each subsequent stage must be configured to manipulate a greater number of bits.
- one or more of the stages of a multi-stage sigma-delta modulator further comprises a truncator configured to reduce the number of bits received from an integrator prior to providing the bits to a next stage of the multi-stage sigma-delta modulator.
- the truncator removes the least significant bit or bits (LSB) of the integrator output. The number of bits received by the next stage is, thus, less than that generated by the integrator of the previous stage.
- FIG. 2 illustrates a multi-stage Sigma-Delta Modulator 200 , according to various embodiments of the invention.
- Sigma-Delta Modulator 200 includes truncators between three sigma-delta stages. However, alternative embodiments of the invention include two, four or more sigma-delta stages. Truncators may be included between some or all of these sigma-delta stages. Each of the truncators is configured to remove one or more bits from the output of the preceding sigma-delta stage.
- Sigma-Delta Modulator 200 comprises an Input 205 configured to receive a signal, a plurality of Combiners 210 (individually labeled 210 A- 210 C), a plurality of Integrators 215 (individually labeled 215 A- 215 C), and a plurality of Truncators 220 (individually labeled 210 A- 210 B).
- Sigma-Delta Modulator 200 further comprises a Quantizer 225 configured to generate a signal at an Output 230 .
- the signal at Output 230 is used by a Feedback Generator 235 to generate one or more feedback signals (F) which are provided to Combiners 210 .
- Combiners 210 A- 210 C include an adder configured to add two or more signals.
- Combiners 210 A- 210 C are typically configured to operate at a frequency higher (e.g., 2 ⁇ or 4 ⁇ ) than the frequency of the received signal such that the signal is oversampled.
- Combiner 210 A is configured to process input signals of at least 100 MHz, 500 MHz, 1 GHz, 2 GHz, 4 GHz or 10 GHz, or less than 100 MHz.
- Combiners 210 A- 210 C are optionally configured to receive different numbers of bits.
- Combiner 210 A may be configured to receive 1 bit while Combiners 210 B and 210 C may each be configured to receive 1, 2, 4 or more bits.
- the numbers of bits receive d by Combiners 210 A and 210 C are dependant on the configuration of Truncators 220 A and 220 B.
- Combiner 210 B is optionally configured to receive the same number of bits as Combiner 210 A.
- Combiner 210 C is optionally configured to receive the same number of bits as Combiner 210 B.
- one or more of Combiners 210 A- 210 C include adders configure for maximum sampling frequency.
- the sampling frequency of an adder having two inputs is typically greater than an adder having more than two inputs, other factors remaining constant.
- an adder having more than two inputs can be replaced by adders in series each having just two inputs. For example, the transform illustrated in Table 1 below can be achieved if one of the adders is a special “adder” configured to output the inverse of the sign bit.
- Integrators 215 A- 215 C are configured to receive the outputs of Combiners 210 A- 210 C, respectively, to integrate these outputs over time, and to generate a multi-bit outputs of their own representative of the results of the integration.
- the complexity of each of integrators 215 A- 215 C is dependent, in part, on the number of bits they receive at their inputs. A greater number of bits requires more complexity but also provides a greater accuracy.
- Integrators 215 A- 215 C may include any of the integrator circuits used in sigma-delta modulators of the prior art.
- the sign of the output of the Integrators 215 A- 215 C is optionally stored in the most significant bit.
- Integrator 215 A is configured to receive at least six bits of input.
- Truncators 220 A and 220 B are configured to truncate the outputs of Integrators 215 A and 215 B. More specifically, they are configured to remove one or more least significant bits from the output of Integrators 215 A and 215 B. In various embodiments, number of bits removed is 1, 2, 3, 4 or more. The number of bits removed by Truncator 220 A is optionally different than the number of bits removed by Truncator 220 B. As is described further elsewhere herein, Truncators 220 A and 220 B optionally include a feedback loop in which the removed bits are used to reduce noise at the inputs of the truncators.
- Quantizer 225 is configured to quantize the output of Integrator 215 C. Quantizer 225 may be configured to process decimal or 2s-complement inputs. Quantizer 225 may include any of the quantizers used in sigma-delta modulators of the prior art. Quantizer 225 may be configured to output one bit or more than one bit.
- Feedback Generator 235 is configured to use the output of Quantizer 225 to generate one or more feedback signals (F) and to provide these feedback signals to Combiners 210 A- 210 C.
- the feedback signals provided to Combiners 210 A- 210 C may be different or the same.
- Feedback Generator 235 is optionally configured to provide a non-unitary gain, i.e., a gain not equal to one.
- Feedback Generator 235 is configured to provide a gain of approximately 1.6 ⁇ or 4 dB in the feedback to Combiner 210 A. This gain compensates for the removal of the least significant bits by Truncators 220 A and 220 B and thus results in a stable system. In alternative embodiments, this gain may be between one and two.
- the feedback loop gain at each stage is typically the same.
- FIG. 3 illustrates embodiments of Truncators 220 .
- Truncators 220 receive a signal from one of Integrators 215 at an Input 310 .
- the signal is received at a Combiner 210 D.
- Combiner 210 D is similar in operation to Combiners 210 A- 210 C.
- a signal including m+n bits is produced.
- the n least significant bits (LSB) are directed into a feedback loop including a Feedback Circuit 320 .
- the number of bits n is 1, 2, 3, 4 or more.
- the remaining m bits are provided as an output of Truncator 220 .
- Feedback Circuit 320 is configured to change the sign of the value represented by the n bits. This change in sign is equivalent to multiplying the value represented by the n bits by ⁇ 1. By combining the received signal with an inversion of the least significant bits in Combiner 210 , these bits are removed from the received signal.
- FIG. 4 illustrates alternative embodiments of Truncators 220 . These embodiments include a second order truncation in which a first of the least significant bits is multiplied by ⁇ 1 using a first Feedback Circuit 320 and combined with two or more of the least significant bits in a first Combiner 210 E. Combiner 210 E is also configured to receive a copy of the least significant bits that has been passed through an Amplifier 410 . In some embodiments, Amplifier 410 has a gain of approximately 2. Combiner 210 is configured to operate in a manner similar to the other Combiners 210 discussed herein. The output of Combiner 210 E is then multiplied by ⁇ 1 using a second Feedback Circuit 320 . The output of the second Feedback Circuit 320 is provided as the feedback signal to Combiner 210 D.
- FIG. 5 illustrates a method, according to various embodiments of the invention.
- a signal is received at Input 205 .
- This signal can be digital.
- Combine Signal Step 510 Combiner 210 A is used to combine the signal received in Receive Signal Step 505 with a feedback generated using Feedback Generator 235 . As discussed elsewhere herein, this combination is typically performed at a frequency that results in oversampling of the received signal. For example, in some embodiments Combiner 210 A is configured to sample the received signal at four times the Nyquist frequency.
- Integrator 215 A is used to integrate the output of Combiner 210 A and produce a multi-bit output.
- the output of Integrator 215 A typically includes a greater number of bits than the input of Integrator 215 A.
- the integration performed by Integrator 215 A (and 215 B and 215 C) is recursive in that the signal received at the input is dependent on the integrated output through the feedback loop.
- Truncate Step 520 one or more least significant bits are removed from the multi-bit output of Integrator 215 A using Truncator 220 A.
- This process optionally includes using the one or more least significant bits in a feedback loop to a combiner within Truncator 220 A. This feedback loop reduces noise associated with the truncation process.
- a Combine Signal Step 525 the output of Truncator 220 A is combined with a feedback signal using Combiner 210 .
- Combine Signal Step 525 is performed in a manner similar to Combine Signal Step 210 .
- Integrate Step 530 the output of Combiner 210 B is integrated using Integrator 215 B to produce a multi-bit output. Integrate Step 530 is performed in a manner similar to Integrate Step 515 .
- the output of Integrator 215 B may include fewer, the same, or more bits than the output of Integrator 215 A.
- Truncate Step 535 one or more least significant bits are removed from the multi-bit output of Integrator 215 B using Truncator 220 B.
- This process optionally includes using the one or more least significant bits in a feedback loop to a combiner within Truncator 220 B.
- a greater number of bits are removed in Truncate Step 535 relative to Truncate Step 520 . For example, two bits may be removed in Truncate Step 520 while four bits are removed in Truncate Step 535 .
- Combine Signal Step 540 the output of Truncator 220 B is combined with a feedback signal using Combiner 210 C. Combine Signal Step 540 is performed in a manner similar to that of Combine Step 525 .
- Integrate Step 545 the output of Combiner 210 C is integrated using Integrator 215 C. Integrate Step 545 is performed in a manner similar to Integrate Step 530 . Steps 535 , 540 and 545 are optional in systems comprising fewer sigma-delta stages than are illustrated in FIG. 2 . E.g., embodiments not including Combiner 210 B, Integrator 215 B and Truncator 220 B. In these embodiments the output of Truncator 220 A is received by Combiner 210 . Likewise, addition occurrences of Step 535 , 540 and 545 may be performed in systems including additional sigma-delta stages.
- a Quantize Step 550 the output of Integrator 215 C is quantized using Quantizer 225 .
- the output of Quantizer is optionally one bit.
- a Feedback Step 555 the output of Quantizer 225 is used to generate the feedback signal(s) using Feedback Generator 235 . These feedback signals are provided to Combiner 210 A, Combiner 210 B and Combiner 210 C.
- Feedback Step 555 includes providing a gain to the feedback signal. Examples of gain values that may be provided are discussed elsewhere herein.
- the feedback produced in Feedback Step 555 is configured to reduce noise introduced by the integration and/or combination steps.
- FIG. 6 illustrates a circuit including Combiners 210 D, 210 B and 210 F each having only two adder (signal) inputs, according to various embodiments of the invention.
- this circuit is a subset of the circuit illustrated in FIG. 2 .
- the Combiner 210 F in combination with an Inverter 610 includes a special adder configured for achieving the transfer function illustrated in Table 1.
- an input including nm bits is received from Integrator 215 B. This input is separated into n and m bits.
- the least significant bits (n) are directed to a two input embodiment of Combiner 210 D in Truncator 220 B.
- the carry bit of this combiner servers as the output of Truncator 220 B.
- the m most significant bits are provided to the two input special adder.
- the output of the special adder and the carry bit are combined in Combiner 210 C. Similar circuits may be used elsewhere in embodiments of the invention. Typically, the value of n is one.
- the disclosed sigma-delta modulator may be included in a power amplifier.
- the signal provided at Output 230 is provided to an antenna and Quantizer 225 is configured to match the impedance of this antenna.
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Abstract
Description
- This application claims priority to and benefit of U.S. Provisional Patent Application No. 61/163,182 entitled “Improved Delta Sigma Modulators for High Speed Applications” and filed Mar. 25, 2009. This provisional patent application is hereby included herein by reference.
- 1. Field of the Invention
- The invention is in the field of electronics.
- 2. Related Art
- Sigma-delta modulators are commonly used to generate pulses whose summed area is representative of an input signal. The generated pulses may vary in their width or their separation. Sigma-delta modulators are found in a wide variety of electronic components including analog-to-digital (ADC) converters, digital-to-analog (DAC) converters, frequency synthesizers, switched-mode power supplies, switched amplifiers and motor controls.
-
FIG. 1 illustrates an example of a second order sigma-delta modulator 100. This module includes aCombiner 105 configured to combine an input signal A and a feedback signal F. The combined signals A and F are integrated by afirst Integrator 110 to produce an output B. A Combiner 115 is used to combine the output B and the feedback signal F. The combined signals B and F are then integrated using asecond Integrator 120 to produce an output C, which is quantized using aQuantizer 125 to produce a final output D. The output is provided to aFeedback Generator 130 to generate the feedback signal F. The feedback signal is configured to reduce noise introduced by the integration and quantization. - Sigma-delta modulators of first order, third order or higher order are known in the prior art. In a first order sigma-delta modulator the Combiner 115 and Integrator 120 would be omitted, while in a third order modulator an
additional Combiner 115 and Integrator 120 would be included. An advantage of higher order is that each stage of Combiner 115 and Integrator 120 servers to further reduce noise in the frequency band of interest. A disadvantage of higher orders is that then number of bits required to represent the integrated signals (e.g., signals B and C) is greater at each stage. This increases the complexity and time required to perform the signal combinations at each subsequent combiner, e.g., Combiner 115. - Various embodiments of the invention include systems and methods of reducing the number of bits used to represent signals between stages of a sigma delta modulator. These embodiments include truncation of the output of one or more integrators. Typically, this truncation includes the removal of one or more least significant bits (LSB). Optionally, truncation is performed through a feedback process in which the one or more LSB is used to generate a feedback signal that is recombined with the signal to be truncated.
- The sigma delta modulator of the invention may be used in a switched power amplifier, a digital to analog converter, or the like. Some embodiments of the invention are used in place of prior art sigma-delta modulators in applications requiring high frequency digital inputs.
- Various embodiments of the invention include a sigma-delta modulator circuit comprising a first modulation stage including at least a first combiner and a first integrator, the first combiner configured to combine an input signal and a first feedback signal, the first integrator configured to integrate an output of the first combiner and to produce a first multi-bit output; a first truncation stage configured to receive the first multi-bit output and to truncate a least significant bit from the first multi-bit output; a second modulation stage including at least a second combiner and a second integrator, the second combiner configured to combine the truncated output of the first modulation stage and a second feedback signal, the second integrator being configured to integrate an output of the second combiner to produce a second multi-bit output; and a feedback generator configured to generate the first feedback signal and the second feedback signal.
- Various embodiments of the invention include a power amplifier comprising a first sigma-delta modulator stage configured to receive an input signal and to produce a multi-bit output; a second sigma-delta modulator stage configured to receive an input signal generated using the first sigma-delta modulator stage; a first truncation stage disposed between the first sigma-delta modulator stage and the second sigma-delta modulator stage, configured to receive the multi-bit output and configured to truncate at least one of the least significant bits of the multi-bit output prior to providing the truncated multi-bit output to the second sigma-delta modulator; and a feedback generator configured to provide a gain to a feedback loop between an output of the quantifier and the first sigma-delta modulator stage.
- Various embodiments of the invention include a method comprising receiving a signal; combining the received signal with a first feedback signal to produce a first combined signal; integrating the first combined signal to produce a first multi-bit output; truncating the first multi-bit output; combining the truncated first multi-bit output with a second feedback signal to produce a second combined signal; integrating the second combined signal to produce a second multi-bit output; quantizing the second multi-bit output or an output generated using the second multi-bit output to produce a quantized signal; and using the quantized signal to produce the first feedback signal and the second feedback signal.
-
FIG. 1 illustrates a two stage sigma delta modulator of the prior art. -
FIG. 2 illustrates a multi-stage sigma-delta modulator, according to various embodiments of the invention. -
FIG. 3 illustrates a truncation circuit, according to various embodiments of the invention. -
FIG. 4 illustrates a second order truncation circuit, according to various embodiments of the invention. -
FIG. 5 illustrates methods, according to various embodiments of the invention. -
FIG. 6 illustrates a circuit including combiners having two inputs, according to various embodiments of the invention. - In sigma delta modulator a received input signal is combined with a feedback signal using a combiner. The output of the combiner is received by an integrator configured to output a multi-bit value representative of an integration of the output of the combiner. In various embodiments, this multi-bit value includes 2, 3, 4 or more bits. One of the bits may be designated as a sign bit. The multi-bit output may be in a 2s-compliment format. The output of the integrator includes more bits than the input.
- Each stage of a multi-stage sigma-delta modulator includes a combiner and an integrator. Thus, each stage has a multi-bit output. In prior art sigma-delta modulators the output of each stage includes a greater number of bits than the signal received by that stage. As a result, each subsequent stage must be configured to manipulate a greater number of bits. In contrast, in various embodiments of the invention one or more of the stages of a multi-stage sigma-delta modulator further comprises a truncator configured to reduce the number of bits received from an integrator prior to providing the bits to a next stage of the multi-stage sigma-delta modulator. Typically, the truncator removes the least significant bit or bits (LSB) of the integrator output. The number of bits received by the next stage is, thus, less than that generated by the integrator of the previous stage.
-
FIG. 2 illustrates a multi-stage Sigma-Delta Modulator 200, according to various embodiments of the invention. Sigma-Delta Modulator 200 includes truncators between three sigma-delta stages. However, alternative embodiments of the invention include two, four or more sigma-delta stages. Truncators may be included between some or all of these sigma-delta stages. Each of the truncators is configured to remove one or more bits from the output of the preceding sigma-delta stage. - More specifically, Sigma-Delta Modulator 200 comprises an
Input 205 configured to receive a signal, a plurality of Combiners 210 (individually labeled 210A-210C), a plurality of Integrators 215 (individually labeled 215A-215C), and a plurality of Truncators 220 (individually labeled 210A-210B). Sigma-Delta Modulator 200 further comprises a Quantizer 225 configured to generate a signal at anOutput 230. The signal atOutput 230 is used by aFeedback Generator 235 to generate one or more feedback signals (F) which are provided to Combiners 210. - In some embodiments, Combiners 210A-210C include an adder configured to add two or more signals. In applications wherein a high frequency signal is received Combiners 210A-210C are typically configured to operate at a frequency higher (e.g., 2× or 4×) than the frequency of the received signal such that the signal is oversampled. In various embodiments, Combiner 210A is configured to process input signals of at least 100 MHz, 500 MHz, 1 GHz, 2 GHz, 4 GHz or 10 GHz, or less than 100 MHz.
- Different members of Combiners 210A-210C are optionally configured to receive different numbers of bits. For example, in various embodiments, Combiner 210A may be configured to receive 1 bit while Combiners 210B and 210C may each be configured to receive 1, 2, 4 or more bits. As is discussed elsewhere herein, the numbers of bits receive d by
Combiners Combiner 210B is optionally configured to receive the same number of bits asCombiner 210A. Likewise,Combiner 210C is optionally configured to receive the same number of bits asCombiner 210B. - In some embodiments, one or more of
Combiners 210A-210C include adders configure for maximum sampling frequency. For example, the sampling frequency of an adder having two inputs is typically greater than an adder having more than two inputs, other factors remaining constant. In addition, an adder having more than two inputs can be replaced by adders in series each having just two inputs. For example, the transform illustrated in Table 1 below can be achieved if one of the adders is a special “adder” configured to output the inverse of the sign bit. -
TABLE 1 X0 −> Y0 X1 −> Y1 X2 −> Y2 X3 −> Y3 Sign bit −> (inversion) −> Y4 Feedback bit −> New Sign bit
The special adder is used on that part of the output of theTruncators 220, discussed further elsewhere herein, that includes the most significant bits (other than a carry bit). The carry bit of theTruncators 220 is then combined with the output of the special adder using another two input adder. An example, of this configuration is provided elsewhere herein, for example in relation toFIG. 6 . -
Integrators 215A-215C are configured to receive the outputs ofCombiners 210A-210C, respectively, to integrate these outputs over time, and to generate a multi-bit outputs of their own representative of the results of the integration. The complexity of each ofintegrators 215A-215C is dependent, in part, on the number of bits they receive at their inputs. A greater number of bits requires more complexity but also provides a greater accuracy.Integrators 215A-215C may include any of the integrator circuits used in sigma-delta modulators of the prior art. The sign of the output of theIntegrators 215A-215C is optionally stored in the most significant bit. In some embodiments,Integrator 215A is configured to receive at least six bits of input. -
Truncators Integrators Integrators Truncator 220A is optionally different than the number of bits removed byTruncator 220B. As is described further elsewhere herein,Truncators -
Quantizer 225 is configured to quantize the output ofIntegrator 215C.Quantizer 225 may be configured to process decimal or 2s-complement inputs.Quantizer 225 may include any of the quantizers used in sigma-delta modulators of the prior art.Quantizer 225 may be configured to output one bit or more than one bit. -
Feedback Generator 235 is configured to use the output ofQuantizer 225 to generate one or more feedback signals (F) and to provide these feedback signals toCombiners 210A-210C. The feedback signals provided toCombiners 210A-210C may be different or the same.Feedback Generator 235 is optionally configured to provide a non-unitary gain, i.e., a gain not equal to one. For example, in someembodiments Feedback Generator 235 is configured to provide a gain of approximately 1.6× or 4 dB in the feedback toCombiner 210A. This gain compensates for the removal of the least significant bits byTruncators -
FIG. 3 illustrates embodiments ofTruncators 220.Truncators 220 receive a signal from one of Integrators 215 at anInput 310. The signal is received at aCombiner 210D.Combiner 210D is similar in operation toCombiners 210A-210C. At anOutput 315 of Combiner 210 a signal including m+n bits is produced. Of these bits the n least significant bits (LSB) are directed into a feedback loop including aFeedback Circuit 320. In various embodiments, the number of bits n is 1, 2, 3, 4 or more. The remaining m bits are provided as an output ofTruncator 220.Feedback Circuit 320 is configured to change the sign of the value represented by the n bits. This change in sign is equivalent to multiplying the value represented by the n bits by −1. By combining the received signal with an inversion of the least significant bits in Combiner 210, these bits are removed from the received signal. -
FIG. 4 illustrates alternative embodiments ofTruncators 220. These embodiments include a second order truncation in which a first of the least significant bits is multiplied by −1 using afirst Feedback Circuit 320 and combined with two or more of the least significant bits in afirst Combiner 210E.Combiner 210E is also configured to receive a copy of the least significant bits that has been passed through anAmplifier 410. In some embodiments,Amplifier 410 has a gain of approximately 2. Combiner 210 is configured to operate in a manner similar to the other Combiners 210 discussed herein. The output ofCombiner 210E is then multiplied by −1 using asecond Feedback Circuit 320. The output of thesecond Feedback Circuit 320 is provided as the feedback signal toCombiner 210D. -
FIG. 5 illustrates a method, according to various embodiments of the invention. In a ReceiveSignal Step 505, a signal is received atInput 205. This signal can be digital.Combine Signal Step 510,Combiner 210A is used to combine the signal received in ReceiveSignal Step 505 with a feedback generated usingFeedback Generator 235. As discussed elsewhere herein, this combination is typically performed at a frequency that results in oversampling of the received signal. For example, in someembodiments Combiner 210A is configured to sample the received signal at four times the Nyquist frequency. - In an Integrate
Step 515,Integrator 215A is used to integrate the output ofCombiner 210A and produce a multi-bit output. The output ofIntegrator 215A typically includes a greater number of bits than the input ofIntegrator 215A. The integration performed byIntegrator 215A (and 215B and 215C) is recursive in that the signal received at the input is dependent on the integrated output through the feedback loop. - In a
Truncate Step 520, one or more least significant bits are removed from the multi-bit output ofIntegrator 215 A using Truncator 220A. This process optionally includes using the one or more least significant bits in a feedback loop to a combiner withinTruncator 220A. This feedback loop reduces noise associated with the truncation process. - In a
Combine Signal Step 525, the output ofTruncator 220A is combined with a feedback signal using Combiner 210.Combine Signal Step 525 is performed in a manner similar to Combine Signal Step 210. - In an Integrate
Step 530, the output ofCombiner 210B is integrated usingIntegrator 215B to produce a multi-bit output. IntegrateStep 530 is performed in a manner similar to IntegrateStep 515. The output ofIntegrator 215B may include fewer, the same, or more bits than the output ofIntegrator 215A. - In a
Truncate Step 535, one or more least significant bits are removed from the multi-bit output ofIntegrator 215 B using Truncator 220B. This process optionally includes using the one or more least significant bits in a feedback loop to a combiner withinTruncator 220B. In some embodiments, a greater number of bits are removed inTruncate Step 535 relative toTruncate Step 520. For example, two bits may be removed inTruncate Step 520 while four bits are removed inTruncate Step 535. - In a
Combine Signal Step 540, the output ofTruncator 220B is combined with a feedbacksignal using Combiner 210C.Combine Signal Step 540 is performed in a manner similar to that ofCombine Step 525. - In an Integrate
Step 545, the output ofCombiner 210C is integrated usingIntegrator 215C. IntegrateStep 545 is performed in a manner similar to IntegrateStep 530.Steps FIG. 2 . E.g., embodiments not includingCombiner 210B,Integrator 215B andTruncator 220B. In these embodiments the output ofTruncator 220A is received by Combiner 210. Likewise, addition occurrences ofStep - In a
Quantize Step 550, the output ofIntegrator 215C is quantized usingQuantizer 225. The output of Quantizer is optionally one bit. In aFeedback Step 555, the output ofQuantizer 225 is used to generate the feedback signal(s) usingFeedback Generator 235. These feedback signals are provided toCombiner 210A,Combiner 210B andCombiner 210C. In some embodiments,Feedback Step 555 includes providing a gain to the feedback signal. Examples of gain values that may be provided are discussed elsewhere herein. The feedback produced inFeedback Step 555 is configured to reduce noise introduced by the integration and/or combination steps. -
FIG. 6 illustrates acircuit including Combiners FIG. 2 . TheCombiner 210F in combination with anInverter 610 includes a special adder configured for achieving the transfer function illustrated in Table 1. In this circuit, an input including nm bits is received fromIntegrator 215B. This input is separated into n and m bits. The least significant bits (n) are directed to a two input embodiment ofCombiner 210D inTruncator 220B. The carry bit of this combiner servers as the output ofTruncator 220B. The m most significant bits are provided to the two input special adder. The output of the special adder and the carry bit are combined inCombiner 210C. Similar circuits may be used elsewhere in embodiments of the invention. Typically, the value of n is one. - Several embodiments are specifically illustrated and/or described herein. However, it will be appreciated that modifications and variations are covered by the above teachings and within the scope of the appended claims without departing from the spirit and intended scope thereof. For example, the disclosed sigma-delta modulator may be included in a power amplifier. In some embodiment the signal provided at
Output 230 is provided to an antenna andQuantizer 225 is configured to match the impedance of this antenna. - The embodiments discussed herein are illustrative of the present invention. As these embodiments of the present invention are described with reference to illustrations, various modifications or adaptations of the methods and or specific structures described may become apparent to those skilled in the art. All such modifications, adaptations, or variations that rely upon the teachings of the present invention, and through which these teachings have advanced the art, are considered to be within the spirit and scope of the present invention. Hence, these descriptions and drawings should not be considered in a limiting sense, as it is understood that the present invention is in no way limited to only the embodiments illustrated.
Claims (26)
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US12/873,073 US7969341B2 (en) | 2009-03-25 | 2010-08-31 | Sigma-delta modulator including truncation and applications thereof |
JP2013168045A JP5496399B2 (en) | 2009-03-25 | 2013-08-13 | Sigma delta modulator with shortening and its application |
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US20080224735A1 (en) * | 2007-03-13 | 2008-09-18 | Viet Linh Do | Frequency Synthesis Rational Division |
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US8762436B1 (en) | 2007-03-13 | 2014-06-24 | Applied Micro Circuits Corporation | Frequency synthesis with low resolution rational division |
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Also Published As
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JP5496399B2 (en) | 2014-05-21 |
US20100321222A1 (en) | 2010-12-23 |
EP2412098A4 (en) | 2013-01-23 |
JP2012521727A (en) | 2012-09-13 |
CN102365824A (en) | 2012-02-29 |
JP5345242B2 (en) | 2013-11-20 |
TW201130232A (en) | 2011-09-01 |
WO2010111128A1 (en) | 2010-09-30 |
JP2014033449A (en) | 2014-02-20 |
US7808415B1 (en) | 2010-10-05 |
EP2412098A1 (en) | 2012-02-01 |
CN102365824B (en) | 2015-07-29 |
KR101635818B1 (en) | 2016-07-04 |
KR20120001782A (en) | 2012-01-04 |
US7969341B2 (en) | 2011-06-28 |
TWI359572B (en) | 2012-03-01 |
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