US20100230755A1

US20100230755A1 - Process for producing an mos transistor and corresponding integrated circuit

Info

Publication number: US20100230755A1
Application number: US12/787,193
Authority: US
Inventors: Philippe Coronel; Claire Gallon; Claire Fenouillet-Beranger
Original assignee: Commissariat a lEnergie Atomique CEA; STMicroelectronics Crolles 2 SAS
Current assignee: STMicroelectronics Crolles 2 SAS; Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date: 2005-07-18
Filing date: 2010-05-25
Publication date: 2010-09-16
Also published as: EP1746643B1; US20070037324A1; FR2888665A1; FR2888665B1; US7749858B2; EP1746643A1

Abstract

A silicon substrate (SOI) is placed on a buried oxide layer (BOX). An MOS transistor is produced in an active zone of the substrate which is defined by an isolating region. A gate region and source and drain regions, which between them define a channel, are produced so that the gate region extends above the channel. The isolating region is produced by localized formation of a zone of material that can be selectively etched with respect to silicon. That material is selectively etched, and a dielectric material is deposited in the etched feature. The etching is carried out after the gate region has been produced. An upper surface of the substrate and an upper surface of the isolating region are flush with each other so as to define a planar surface on which the transistor gate region is formed.

Description

PRIORITY CLAIM

The present application is a divisional application from United States Application for Ser. No. 11/487,706 filed Jul. 17, 2006, which claims priority from French Application for Patent No. 05 07598 filed Jul. 18, 2005, the disclosures of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Technical Field of the Invention
The present invention relates to integrated circuits and more particularly to MOS-type transistors.
2. Description of Related Art
The fabrication of transistors produced in MOS technology is faced with several problems, among which to be noted are short-channel effects.
Such is in particular the case in transistors produced on a bulk silicon substrate.
It will be recalled here that a short-channel, that is to say one having a distance (or length) that is very short between the source and the drain of the transistor, leads to a reduction in the threshold voltage of the transistor. This may in the extreme limit lead to a transistor being obtained that is very difficult to control.
Transistors produced in SOI (Silicon On Insulator) technology, in particular in fully-depleted SOI technology, apart from the advantages associated with the formation of a more compact architecture than in a bulk silicon substrate, make it possible to reduce the short-channel effects.
Using this technique, the substrate is made of silicon and is formed on top of a buried oxide (BOX) layer.
Now, in an SOI structure, the thickness of both the silicon film and the buried oxide layer is relatively small. This is because the buried oxide layer is generally between 1450 and 4000 Å. Such is also the case of the SOI film, the thickness of which is generally around 200 Å.
It has been found that the small thickness of the buried oxide layer reduces the electrostatic coupling between the drain region and the source region. This limits the phenomenon of short-channel effects.
During the etching operations carried out when producing the isolation region that defines the active zone, in which the transistor is defined, the buried oxide layer is liable to be etched. This results in an excessive consumption of insulation material for producing the STI (Shallow Trench Isolation) region.
In addition, it has also been found that, when using this technique, the SOI film protrudes on top of the buried oxide layer, so that the gate region is also formed laterally on either side of the SOI region, thereby tending to create parasitic transistors on the SOI sidewalls coated with the gate material.
There is accordingly a need in the art to alleviate the drawbacks of the techniques for fabricating MOS transistors produced in SOI technology.

SUMMARY OF THE INVENTION

In accordance with an embodiment of the invention, a process for producing an MOS transistor on an SOI silicon substrate placed on a buried oxide layer, said transistor being produced in an active substrate zone defined by an isolating region, comprises: defining the isolating region; and producing a gate region and source and drain regions, which between them define a channel so that the gate region extends above the channel.
The isolating region is produced by localized formation of a zone of material that can be selectively etched with respect to silicon, by selectively etching said material and depositing a dielectric material in the etched features.
Furthermore, the etching is carried out after the gate region has been produced.
Thus, by producing the gate by deposition of a gate material on the dielectric or high-permittivity material, it being possible for the latter to be selectively etched with respect to silicon, the silicon can therefore be actively etched after the gate. The silicon etching step, implemented using conventional processes, which is usually carried out at the start of the process and has a tendency to etch the buried oxide layer, is omitted. Furthermore, the gate may be formed on a perfectly planar surface, thereby preventing the formation of parasitic transistors on the SOI sidewalls.
In one way of implementing the process according to the invention, a germanium ion implantation is carried out in the future isolating region, the substrate is annealed so as locally to convert the substrate into a silicon-germanium alloy, a layer of gate material is deposited on the substrate, with interposition of a gate oxide layer, etching of the gate is carried out, then etching is carried out in the silicon-germanium alloy zone, so as to remove said alloy, and said dielectric material is deposited in the etched substrate zone.
Preferably, spacers for the gate are formed before the substrate is etched.
For example, the dielectric deposited is a dielectric of the same type as that of the spacers.
In one example of how the process is implemented, etching is either an isotropic plasma etching step or an isotropic wet etching step.
Etching may be carried out so as to etch the silicon-germanium alloy down to the underlying oxide layer.
According to another embodiment of the invention, an integrated circuit comprises an MOS transistor having a gate region formed on top of an SOI silicon substrate deposited on a buried oxide layer between mutually opposed zones of an isolating region defining an active zone in which the transistor is formed.
According to a general feature of this circuit, the upper surface of the isolating region is flush with the upper portion of the SOI substrate so that the gate region lies on a planar surface.
According to an embodiment, a method comprises: defining an isolating region in a silicon substrate placed on a buried oxide layer, the isolating region being a zone of material surrounding an active region of the silicon substrate, the material capable of being selectively etched with respect to silicon; forming a gate region over at least a portion of the active region; removing the material by etching to create an isolating region cavity after the gate region is formed; and filling the isolating region cavity with an insulating material.
In an embodiment, an integrated circuit comprises: a buried oxide layer and a silicon on insulator substrate formed on top of the buried oxide layer. The silicon on insulator substrate has an upper surface and including a source region, a drain region and a channel region. An isolation region is formed on top of the buried oxide layer defining an active region of the silicon on insulator substrate which contains the source region, drain region and channel region. The isolation region has an upper surface which is flush with the upper surface of the silicon on insulator substrate. A transistor gate structure is formed over the channel region on a planar surface defined by the flush upper surfaces of the silicon on insulator substrate and isolation region

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the method and apparatus of the present invention may be acquired by reference to the following Detailed Description when taken in conjunction with the accompanying Drawings wherein:

FIG. 1 is a sectional view of a semiconductor device in the course of being produced, showing the formation of the active zone by means of a process according to the prior art;

FIG. 2 is another sectional view of a semiconductor device after a cleaning step, before formation of the gate region by means of a process according to the prior art;

FIG. 3 is a sectional view of a semiconductor device during a first phase of forming an isolation region by means of a process according to the invention;

FIG. 4 is a top view of a semiconductor device in the course of being produced by means of a process according to the invention, after conversion of the isolation region into a silicon-germanium alloy and formation of the gate region;

FIG. 5 is a sectional view in another direction of the device of FIG. 4, showing the formation of the spacers;

FIG. 6 is a sectional view of the device of FIGS. 3 to 5, after the etching operation; and

FIG. 7 shows the device of FIG. 6 after the filling of the cavity formed after etching.

DETAILED DESCRIPTION OF THE DRAWINGS

FIGS. 1 and 2 show two consecutive phases in the production of a semiconductor device by means of a process according to the prior art.
As shown in these figures, the process comprises producing MOS transistors on a silicon substrate of the SOI type placed on a buried oxide layer (BOX).
According to this type of technology, the buried oxide layer has a thickness of around 1500 Å.
The process step shown in FIG. 1 corresponds to an active photolithography phase prior to deposition of gate material on the SOI substrate.
At this stage, the SOI substrate is covered with a layer of photoresist 10 with interposition of a hard mask 12 and layer 13 of nitride Si₃N₄.
Referring to FIG. 2, before the gate material is deposited it is necessary to carry out a cleaning phase. As shown in FIG. 2, this cleaning phase results in a not insignificant etching of the buried oxide layer BOX down to a thickness that may reach 100 or even 150 Å.
As will be understood, it is not possible with this technique to produce transistors on a substrate deposited on a buried oxide layer having a thickness of around 200 Å so as to limit electrical coupling and create field lines between the drain and the source of the transistor through the BOX layer and to avoid standard integration of the isolation region STI.
Furthermore, as FIG. 2 reveals, the gate material is deposited using this technique on a non-planar surface, which, as mentioned above, results in the appearance of lateral parasitic transistors.
A process for producing MOS transistors according to the invention that helps to alleviate these drawbacks will be described with reference to FIGS. 3 to 7.
The process described in these figures comprises producing MOS transistors on a semiconductor SOI substrate placed on a buried oxide layer BOX.
As will be described in detail further on, this process makes it possible to produce transistors on an oxide layer with a thickness of around 200 Å placed on top of a buried oxide layer also having a thickness of around 200 Å, or even 100 Å.
Referring firstly to FIG. 3, the first phase of the process comprises carrying out a conventional active photolithography step during which a photolithography mask M is deposited in that point of a zone of the substrate which is intended to constitute the active zone in which a transistor will be formed. Such a mask M is formed by depositing a resist appropriate for the intended use, using a technique known per se.
Referring also to FIG. 4, after the mask has been deposited, a germanium ion implantation is carried out in a zone of the substrate located in the isolating region R that defines the active zone.
The resist is removed and the substrate is annealed in order to form, locally, a silicon-germanium alloy in the isolation region R.
Referring also to FIG. 5, the gate G is then formed.
This gate formation phase is carried out in a conventional manner and will therefore not be described in detail below.
However, it should be noted that it essentially comprises depositing a gate oxide layer 14 on the SOI substrate and then in depositing a layer of gate material, for example polycrystalline silicon, on the gate oxide layer. A photolithography step followed by an etching step are then carried out, so as to leave behind only a deposit of a gate oxide covered with gate material in the gate region for the transistor to be produced.
Next, spacer material is deposited and then etched, so as to produce the spacers E.
During the following step, that is to say after formation of the gate provided with these spacers E, the silicon-germanium alloy is selectively removed and then, later, a silicidation phase is carried out. Various techniques may be used for the selective removal of this silicon-germanium alloy. For example, it is thus possible to use isotropic plasma or wet etching, it also being possible for chemical etching to be employed for this purpose.
It should be noted that the germanium ion implantation into the region R of the substrate intended to constitute the isolating region was carried out so as subsequently to form a localized zone of a silicon-germanium alloy, which may be selectively etched with respect to the silicon of the SOI substrate. As a variant, it is also possible to carry out a localized implantation of any other material that can be selectively etched with respect to silicon. However, the use of a silicon-germanium alloy is advantageous in so far as the SiGe alloy zone can then be easily formed relatively rapidly by conventional techniques.
After this etching phase, the device is in the step shown in FIG. 6, in which a cavity C has been created in the silicon-germanium.
During the next step, a dielectric is deposited in order to fill the cavities created after the etching step.
A dielectric is then deposited, as shown with reference to FIG. 7. For example, this dielectric may be of the same type as that used for forming the spacers E, so that the spacers may also be formed during this step. For example, the dielectric filling the cavity C consists of silicon nitride. Various techniques may be used to carry out this step. Thus, for example, it is possible to deposit dielectric using a chemical vapor deposition (CVD) or low pressure chemical vapor deposition (LPCVD) technique. The integrated circuit visible in FIG. 7, in which the cavities are filled with nitride (SiN), is then obtained.
As may be seen in this figure, the upper face of the isolation region R is flush with the upper face of the SOI substrate.
Finally, as is conventional in SOI, the source and drain regions then have to be formed by conventional photolithography, ion implantation and silicidation techniques, and then the whole assembly has to be covered with a PMD (Pre-Metal Dielectric) layer.
Thanks to the process that has just been described, it was thus possible to produce a gate region on an SOI substrate deposited on a relatively thin buried oxide layer BOX, that is to say with a thickness of around 200 Å, in so far as no process step results in the oxide layer BOX being etched. Furthermore, the gate lies on a perfectly planar surface, thus preventing the creation of lateral parasitic transistors.
In addition, the process according to the invention makes it possible to obtain the following advantages:
thanks to the invention, it is unnecessary to provide a step of forming an STI module in order to produce the isolation region;
the actual isolation region may be formed after formation of the gate;
the process, and in particular the deposition of dielectric, may be carried out at low temperature, and adaptable to various technologies;
the process makes it possible to strain the transistor channel by deposition, for example, of tensile or compressive silicon nitride SiN in the isolation region; and
the benefit of having SiGe makes it possible, inter alia, to have a single-crystal material for growth of the gate oxide and to reduce the problems of oxide reliability compared for example with a material of the Si₃N₄type.
Although preferred embodiments of the method and apparatus of the present invention have been illustrated in the accompanying Drawings and described in the foregoing Detailed Description, it will be understood that the invention is not limited to the embodiments disclosed, but is capable of numerous rearrangements, modifications and substitutions without departing from the spirit of the invention as set forth and defined by the following claims.

Claims

1. An integrated circuit, comprising:

an MOS transistor having a gate region formed on top of a silicon on insulator (SOI) substrate deposited on top of a buried oxide layer between mutually opposed zones of an isolating region defining an active zone in which the transistor is formed,

wherein an upper surface of the isolating region is flush with an upper surface of the silicon on insulator substrate so that the gate region lies across the silicon on insulator substrate and the isolating region on a planar surface.

2. The circuit according to claim 1, wherein the isolating region is made of a material of the same type as that of the spacers for the gate.

3. The circuit according to claim 2, wherein the material of the isolating region and spacers for the gate is a silicon nitride.

4. The circuit according to claim 3, wherein the silicon nitride in the isolating region is compressive silicon nitride, the MOS transistor having a strained channel.

5. The circuit according to claim 3, wherein the silicon nitride in the isolating region is tensile silicon nitride, the MOS transistor having a strained channel.

6. The circuit according to claim 1, wherein the gate region is defined by a gate oxide lying on the planar surface and a conductive gate material lying on the gate oxide.

7. The circuit according to claim 6, wherein the gate oxide is made of a grown single crystal material.

8. The circuit according to claim 1, wherein the buried oxide layer has a thickness of about 200 Angstroms.

9. The circuit according to claim 1, wherein the buried oxide layer has a thickness less than about 200 Angstroms.

10. The circuit according to claim 1, wherein the buried oxide layer has a thickness of about 100 Angstroms.

11. An integrated circuit, comprising:

a buried oxide layer;

a silicon on insulator substrate formed on top of the buried oxide layer, the silicon on insulator substrate having an upper surface and including a source region, a drain region and a channel region;

an isolation region formed on top of the buried oxide layer defining an active region of the silicon on insulator substrate which contains the source region, drain region and channel region, the isolation region having an upper surface which is flush with the upper surface of the silicon on insulator substrate; and

a transistor gate structure formed over the channel region on a planar surface defined by the flush upper surfaces of the silicon on insulator substrate and isolation region.

12. The circuit according to claim 11, further comprising side wall spacers on opposite sides of the transistor gate structure, the sidewall spacers being made of a material which is a same material as a material used to form the isolation region.

13. The circuit according to claim 11, wherein the transistor gate structure is defined by a gate oxide lying on the planar surface and a conductive gate material lying on the gate oxide.

14. The circuit according to claim 13, wherein the gate oxide is made of a grown single crystal material.

15. The circuit according to claim 11, wherein a material used to form the isolation region is a compressive material which causes the channel region to be a strained channel region.

16. The circuit according to claim 11, wherein a material used to form the isolation region is a tensile material which causes the channel region to be a strained channel region.

17. The circuit according to claim 11, wherein the buried oxide layer has a thickness of about 200 Angstroms.

18. The circuit according to claim 11, wherein the buried oxide layer has a thickness less than about 200 Angstroms.

19. The circuit according to claim 11, wherein the buried oxide layer has a thickness of about 100 Angstroms.