US20100224942A1 - Semiconductor device and method of fabricating the same - Google Patents
Semiconductor device and method of fabricating the same Download PDFInfo
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- US20100224942A1 US20100224942A1 US12/660,943 US66094310A US2010224942A1 US 20100224942 A1 US20100224942 A1 US 20100224942A1 US 66094310 A US66094310 A US 66094310A US 2010224942 A1 US2010224942 A1 US 2010224942A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title abstract description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 61
- 125000006850 spacer group Chemical group 0.000 claims abstract description 61
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 57
- 238000002955 isolation Methods 0.000 claims abstract description 44
- 239000012535 impurity Substances 0.000 claims description 38
- 239000000758 substrate Substances 0.000 claims description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 18
- 238000005468 ion implantation Methods 0.000 abstract description 9
- 239000010410 layer Substances 0.000 description 127
- 230000015654 memory Effects 0.000 description 24
- 238000002513 implantation Methods 0.000 description 21
- 238000004891 communication Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910021339 platinum silicide Inorganic materials 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
- H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Definitions
- the inventive concept relates to a semiconductor device and a method of fabricating the same.
- a gate sidewall spacer is used as an ion implantation mask in a transistor to form source/drain regions. Furthermore, the gate sidewall spacer plays important roles in insulating a silicide layer and a gate layer, which will be formed by a subsequent salicide process, from each other such that they are not connected to each other. Due to the silicide layer and the gate layer, however, there are problems that the integration degree of semiconductor devices deteriorates and the contact area becomes smaller, resulting in increasing the contact resistance.
- the present inventive concept provides a semiconductor device and a method of fabricating the same that can increase an operation speed of devices.
- the present inventive concept also provides a semiconductor device and a method of fabricating the same that can prevent current from leaking into a semiconductor substrate.
- Embodiments of the inventive concept provide a semiconductor device including: a device isolation layer located on a semiconductor substrate to define an active region; a gate pattern crossing over the active region and the device isolation layer; a sidewall spacer pattern covering a sidewall of the gate pattern on the active pattern; and a gate silicide layer covering at least a part of both sidewalls of the gate pattern on the device isolation layer.
- the sidewall spacer pattern may expose all of both sidewalls of the gate pattern on the device isolation layer, and the gate silicide layer may cover both of the exposed sidewalls of the gate pattern.
- the sidewall spacer pattern may cover a lower portion of both sidewalls of the gate pattern on the device isolation layer, and a width of the sidewall spacer pattern located on the device isolation layer may be smaller than half of that of the sidewall spacer pattern located on the active region.
- the semiconductor device may further include: a conductive line located on the device isolation layer adjacent to the active region, the conductive line being adjacent to the gate pattern; a conductive line silicide layer covering at least both sidewalls of the conductive line; an active silicide layer formed on the active region and coming in contact with a sidewall of the device isolation layer; and a shared contact coming in contact with the active silicide layer and the conductive line silicide layer at the same time.
- the gate pattern and the conductive line may include a polysilicon layer doped with impurities or undoped with impurities.
- Embodiments of the inventive concept also provide a method of fabricating a semiconductor device, the method including: forming a device isolation layer defining an active region on a semiconductor substrate; forming a gate pattern crossing over the active region and the device isolation layer; forming a sidewall spacer covering entirely a sidewall of the gate pattern; and forming a sidewall spacer pattern by removing remaining portions of the sidewall spacer except for portions which are used as an ion implantation mask to form source/drain regions.
- the removing of a portion of the sidewall spacer includes leaving a remaining portion of the sidewall spacer used as an ion implantation mask to form source/drain regions.
- the removing of a portion of the sidewall spacer includes: forming a mask layer covering the sidewall spacer located on the sidewall of the gate pattern on the active region but exposing the sidewall spacer on the device isolation layer; and removing at least a part of the sidewall spacer exposed by the mask layer.
- the forming of the sidewall spacer pattern may include: forming a mask layer covering the sidewall spacer located on the sidewall of the gate pattern on the active region but exposing the sidewall spacer on the device isolation layer; and removing at least a part of the sidewall spacer exposed by the mask layer.
- the method may further include: forming a conductive line adjacent to the gate pattern, the conductive line crossing over the device isolation layer; and forming a conductive line spacer covering entirely a sidewall of the conductive layer. In this configuration, at least a part of the conductive line spacer on the device isolation layer may be removed in the removing of at least a part of the sidewall spacer.
- the part of the conductive line spacer may be formed to come in contact with an active region located between the gate pattern and the conductive line.
- the method may further include: forming an impurity implantation region in the active region by using an ion implantation process; forming a conductive silicide layer covering at least a part of both sidewalls of the conductive line and an active silicide layer on the active region; and forming a shared contact coming in contact with the active silicide layer and the conductive line silicide layer at the same time.
- the conductive line and the gate pattern may include a polysilicon layer doped with impurities or undoped with impurities.
- FIG. 1A is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept.
- FIG. 1B is a sectional view taken along the lines I-I, II-II, and of FIG. 1A .
- FIG. 2A is a perspective view illustrating a transistor in a periphery circuit region illustrated in FIG. 1A .
- FIG. 2B is a perspective view illustrating a silicide layer illustrated in FIG. 2A .
- FIGS. 3A , 4 A, 5 A, 6 A, 7 A, and 8 A are plan views illustrating a process of manufacturing the semiconductor device illustrated in FIG. 1A .
- FIGS. 3B , 4 B, 5 B, 6 B, 7 B, and 8 B are sectional views taken along the lines I-I, II-II, and III-III of FIGS. 3A , 4 A, 5 A, 6 A, 7 A, and 8 A, respectively.
- FIG. 7C is a sectional view taken along the lines I-I, II-II, and III-III of FIG. 7A .
- FIG. 9A is a plan view illustrating a semiconductor device according to another embodiment of the inventive concept.
- FIG. 9B is a sectional view taken along the lines I-I, II-II, and III-III of FIG. 9A .
- FIG. 9C is a perspective view illustrating a part of a transistor in a periphery circuit region illustrated in FIG. 9A .
- FIG. 10 is a block diagram schematically illustrating an electronic device including the semiconductor memory device according to the embodiment of the inventive concept.
- FIG. 11 is a block diagram illustrating a memory system including the semiconductor memory device according to the embodiment of the inventive concept.
- any layers such as a conductive layer, a semiconductor layer, or an insulating layer are referred to as being “on” another material layer or substrate, it may be directly on the other material layer or substrate, or intervening elements or layers may be present.
- first, second, etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Accordingly, a first layer used in one embodiment of the inventive concept may be used to as a second layer in another embodiment of the inventive concept.
- FIG. 1A is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept.
- FIG. 1B is a sectional view taken along the lines I-I, II-II, and of FIG. 1A .
- a region “a” shows a sectional view taken along the line I-I of FIG. 1A
- a region “b” shows a sectional view taken along the line II-II of FIG. 1A
- a region “c” shows a sectional view taken along the of FIG. 1A .
- a device isolation layer 3 defining active regions 5 is disposed on a semiconductor substrate 1 including a cell memory region and a periphery circuit region.
- One exemplary transistor is illustrated in the periphery circuit region.
- An exemplary unit memory cell of a full CMOS-type SRAM is illustrated in the cell memory region.
- On the semiconductor substrate 1 of the cell memory region specifically, four parallel bar-shaped active regions 5 are formed in one direction, and long bar-shaped cell gate patterns 111 to 114 cross over the active regions 5 in a direction perpendicular to the one direction.
- the cell gate patterns 111 to 114 include a first cell gate pattern 111 , a second cell gate pattern 112 , a third cell gate pattern 113 , and a fourth cell gate pattern 114 .
- a gate insulating layer 9 is interposed between the semiconductor substrate 1 and each of the cell gate patterns 111 to 114 .
- a low-concentration impurity implantation region 13 a and a high-concentration impurity implantation region 19 a are formed in the semiconductor substrate 1 of the active regions adjacent to the cell gate patterns 111 to 114 .
- the impurity implantation regions 13 a and 19 a and the cell gate patterns 111 to 114 form six transistors Q 1 to Q 6 .
- the transistors Q 1 to Q 6 include two access transistors Q 1 and Q 2 , two drive transistors Q 3 and Q 4 , and two load transistors Q 5 and Q 6 , which form two flip-flop circuits, respectively.
- the periphery circuit region is provided with a periphery circuit transistor which includes a periphery gate pattern 115 , which crosses over the active region 5 , and a low-concentration impurity implantation region 13 c and a high-concentration impurity implantation region 19 c formed in the semiconductor substrate 1 of the active region 5 adjacent to the periphery gate pattern 115 .
- the gate patterns 111 to 115 may include a polysilicon layer that is doped with impurities or undoped with impurities.
- sidewall spacer patterns 150 are formed on the sidewalls of the gate patterns 111 to 115 crossing over the active regions 5 or on the sidewalls of the gate patterns 111 to 115 overlapping with the active regions 5 . That is, the sidewall spacer patterns 150 are formed on the sidewalls of the gate patterns 111 to 115 forming the transistors. In the gate patterns 111 to 115 , the surfaces which are not covered with the sidewall spacer patterns 150 are all covered with gate silicide layers 211 to 215 , respectively. Moreover, an active silicide layer 210 is formed on the semiconductor substrate 1 of the active region 5 which are not covered with the sidewall spacer pattern 150 , which is illustrated in detail in FIGS. 2A and 2B .
- FIG. 2A is a perspective view illustrating the transistor in the periphery circuit region of FIG. 1A .
- FIG. 2B is a perspective view illustrating the periphery gate silicide layer 215 illustrated in FIG. 2A .
- the device isolation layer 3 is formed on the semiconductor substrate 1 of the periphery circuit region to define the active regions 5 .
- the periphery gate pattern 115 crosses over the active region 5 and is located on the device isolation layer 3 .
- the sidewall spacer patterns 150 are formed on only the sidewalls of the periphery gate pattern 115 , and the periphery gate silicide layer 215 covers all of the sidewalls and the upper surface of the circuit gate pattern 115 corresponding to the exposed remaining portions which are not covered with the sidewall spacer pattern 150 .
- the shape of the periphery gate silicide layer 215 of FIG. 2B is similar to a lid covering the periphery gate pattern 115 . Therefore, since the area where the periphery circuit gate pattern 115 is covered with the silicide layer 215 having a relatively low resistance is maximized, it is possible to reduce the resistance of a gate electrode.
- the cell gate silicide layers 211 to 214 include a first cell gate silicide layer 211 , a second cell gate silicide layer 212 , a third cell gate silicide layer 213 , and a fourth cell gate silicide 214 .
- Contact plugs 251 and 252 are disposed on the active silicide layer 210 and the third and fourth cell gate silicide layers 213 and 214 to apply a voltage.
- the active silicide layer 210 and the first and second cell gate silicide layers 211 and 212 come in contact with a shared contact 250 .
- the active silicide layer 210 is adjacent to the load transistors Q 5 and Q 6 among the transistors Q 1 to Q 6 and is located between the first cell gate pattern 111 and the second cell gate pattern 112 .
- First and second cell gate silicide layers 211 and 212 cover the end potions of the first and second cell gate patterns 111 and 112 located on the device isolation layer 3 adjacent to the active silicide layer 210 .
- the active silicide layer 210 disposed below the shared contact 250 comes in contact with the sidewall of the device isolation layer 3 , it can prevent current from leaking to the semiconductor substrate 1 . With reference to the sectional view of the region “a” of FIG. 1B , since an area of the active silicide layer 210 and the second cell gate silicide 212 coming in contact with the shared contact 250 is large, a contact resistance can be reduced.
- FIGS. 3A , 4 A, 5 A, 6 A, 7 A, and 8 A are plan views illustrating the process of fabricating the semiconductor device illustrated in FIG. 1A .
- FIGS. 3B , 4 B, 5 B, 6 B, 7 B, and 8 B are sectional views taken along the lines I-I, II-II, and of FIGS. 3A , 4 A, 5 A, 6 A, 7 A, and 8 A, respectively.
- FIG. 7C is a sectional view taken along the lines I-I, II-II, and of FIG. 7A .
- the device isolation layer 3 is formed on the semiconductor substrate 1 to define the active regions 5 .
- the device isolation layer 3 is formed by, for example, STI (Shallow Trench Isolation).
- the well region may be formed by implanting impurities into the semiconductor substrate 1 .
- the semiconductor substrate 1 of the active regions 5 is subjected to a thermal oxidation process to form the gate insulating layer 9 .
- a gate layer is formed on the entire surface of the semiconductor substrate 1 .
- the gate patterns 111 to 115 are formed by patterning the gate layer.
- a capping layer may further be formed on the gate layer. When the gate layer is patterned, the capping layer may be patterned together to form capping layer patterns on the gate patterns 111 to 115 , respectively.
- the gate patterns 111 to 115 may include a polysilicon layer doped with impurities or undoped with impurities. Alternatively, the gate patterns 111 to 115 may be formed so as to include a metal containing layer.
- low-concentration impurities are implanted into the semiconductor substrate 1 of the active regions 5 on both sides of the gate patterns 111 to 115 to form the low-concentration impurity implantation regions 13 a, 13 b, and 13 c.
- the low-concentration impurity implantation regions 13 a, 13 b, and 13 c may include a first low-concentration impurity implantation region 13 a, a second low-concentration impurity implantation region 13 b, and a third low-concentration impurity implantation region 13 c.
- the first low-concentration impurity implantation region 13 a may be doped with P-type impurities.
- the second low-concentration impurity implantation region 13 b may be doped with N-type impurities.
- a spacer layer is stacked on the entire surface of the semiconductor substrate 1 .
- the spacer layer is anisotropically etched to form sidewall spacers 15 covering all of the sidewalls of the gate patterns 111 to 115 .
- the spacer layer may be at least one selected from a group including a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Since the sidewall spacer 15 covers all of the sidewalls of the gate patterns 111 to 115 , the sidewall spacer 15 is formed not only on the active regions 5 but also on the device isolation layer 3 .
- a mask 17 is formed to expose the remaining portions of the sidewall spacer 15 except for portions which are used as the ion implantation mask to form source/drain regions.
- the mask 17 is formed so as to cover the sidewall spacer 15 located on the sidewalls of the gate patterns 111 to 115 overlapping with the active patterns 5 .
- the mask 17 may be, for example, a photoresist pattern.
- the exposed sidewall spacer 15 which is not covered with the mask 17 is removed using the mask 17 as an etching mask.
- an anisotropic dry etching process may be executed.
- the sidewall spacer pattern 150 is formed, which covers the sidewalls of the gate patterns 111 to 115 overlapping with the active patterns 5 .
- the high-concentration impurity implantation regions 19 a, 19 b, and 19 c are formed by implanting high-concentration impurities into the sidewall spacer pattern 150 using as an ion implantation mask.
- the high-concentration impurity implantation regions 19 a, 19 b, and 19 c include a first high-concentration impurity implantation region 19 a, a second high-concentration impurity implantation region 19 b, and a third high-concentration impurity implantation region 19 c.
- the first high-concentration impurity implantation region 19 a may be doped with P-type impurities.
- the second high-concentration impurity implantation region 19 b may be doped with N-type impurities. Referring to the sectional view of a region “c” of FIG. 7C , the first high-concentration impurity implantation region 19 a is formed so as to come in contact with the device isolation layer 3 .
- a metal layer is stacked on the entire surface of the structure and subjected to heat treatment to form the silicide layers 210 to 215 .
- the gate silicide layers 211 to 215 are formed on sidewalls and upper surfaces of the gate patterns 111 to 115 on the exposed device isolation layer 3 which are not covered with the sidewall spacer pattern 150 , respectively.
- the active silicide layer 210 is formed on the semiconductor substrate 1 of the active patterns 5 .
- the metal layer is formed of titanium, cobalt, nickel, or platinum.
- the silicide layers 210 to 215 are formed, for example, of titanium, cobalt, nickel, or platinum silicide. Unsilicided metal layer is removed. Referring to the sectional view of a region “a” of FIG. 8B , the active silicide layer 210 is formed so as to come in contact with the sidewall of the device isolation layer 3 adjacent to the second cell gate pattern 112 .
- a process of removing the capping layer pattern may additionally be provided before a salicide process of forming the silicide layers 210 to 215 .
- an interlayer insulating layer 23 is formed on the entire surface of the structure.
- the contact plugs 250 to 252 are formed by penetrating the interlayer insulating layer 23 to be in contact with the active silicide layer 210 or the gate silicide layers 211 to 215 .
- the contact plugs 250 to 252 when contact holes (not illustrated) for exposing the silicide layers 210 to 215 are formed by patterning the interlayer insulating layer 23 , the silicide layers 210 to 215 serve as an etch stop layer. Accordingly, the surface of the semiconductor substrate 1 may be less damaged.
- remaining sidewall spacers 150 r may be formed by not removing entirely the exposed sidewall spacers 15 using the mask 17 in the process of removing the exposed sidewall spacers 15 .
- FIGS. 9A , 9 B, and 9 C illustrate the semiconductor device including such remaining spacers 150 r, respectively.
- FIG. 9A is a plan view illustrating the semiconductor device according to another embodiment of the inventive concept.
- FIG. 9B is a sectional view taken along the lines I-I, II-II, and III-III of FIG. 9A .
- FIG. 9C is a perspective view illustrating a part of the transistor in the periphery circuit region illustrated in FIG. 9A .
- the remaining sidewall spacers 150 r remain in the sidewalls of the gate patterns 111 to 115 on the device isolation layer 3 . It is desirable that the width W 1 of the remaining sidewall spacer 150 r be smaller than half of the width W 2 of the sidewall spacer pattern 150 .
- the remaining sidewall spacers 150 r are formed so as to expose a part (that is, upper portion) of the gate patterns 111 to 115 on the device isolation layer 3 .
- gate silicide layers 221 to 225 are formed in a part and the upper surface of the both sides of the gate patterns 111 to 115 exposed to the device isolation layer 3 , and active silicide layers 220 are formed in the active regions 5 .
- the active silicide layer 220 located between the first cell gate pattern 111 and the second cell gate pattern 112 may come in contact with the device isolation layer 3 by the remaining sidewall spacer 150 r covering a part of the sidewalls of the second cell gate pattern 112 on the device isolation layer 3 .
- the other configuration and the manufacturing process are the same as the above-described configuration and process.
- CMOS type SDAM has been described as an example of the cell memory according to the embodiment of the inventive concept.
- configuration of the inventive concept is applicable to a variety of semiconductor devices such as other DRAMs and NAND or NOR flash memories.
- FIG. 10 is a block diagram schematically illustrating an electronic device including the semiconductor memory device according to an embodiment of the inventive concept.
- FIG. 11 is a block diagram illustrating a memory system including the semiconductor memory device according to an embodiment of the inventive concept.
- the electronic device 300 may be used in wireless communication apparatuses such as a PDA, a laptop computer, a portable computer, a web tablet, a wireless telephone, a cellular phone, and a digital music player, or all elements capable of transmitting and/or receiving information in a wireless environment.
- wireless communication apparatuses such as a PDA, a laptop computer, a portable computer, a web tablet, a wireless telephone, a cellular phone, and a digital music player, or all elements capable of transmitting and/or receiving information in a wireless environment.
- the electronic device 300 includes a controller 310 , an input/output device 320 such as a keypad, a keyboard, or a display, a memory 330 , and a wireless interface 340 which are connected to each other through a bus 350 .
- the controller 310 may include one or more microprocessors, digital signal processors, or microcontrollers or include an equivalent thereof.
- the memory 330 may be used to store commands executed by the controller 310 , for example. Moreover, the memory 330 may be used to store data of a user.
- the memory 330 includes the semiconductor memory device according to embodiments of the inventive concept.
- the electronic device 300 may use the wireless interface 340 in order to transmit data to a wireless communication network carrying out communication by use of RF signals or to receive data from a network.
- the wireless interface 340 may include an antenna or a wireless transceiver.
- the electronic device 300 may be used in communication interface protocols of a third generation communication system such as CDMA, GSM, NADC, E-TDMA, WCDAM, and CDMA2000.
- a third generation communication system such as CDMA, GSM, NADC, E-TDMA, WCDAM, and CDMA2000.
- FIG. 11 a memory system including the semiconductor memory device according to an embodiment of the inventive concept will be described.
- a memory system 400 includes a memory 410 storing mass data and a memory controller 420 .
- the memory controller 420 controls the memory 410 to read or write stored data from or to the memory 410 in response to a request for reading/writing the data from a host 430 .
- the memory controller 420 may create an address mapping table used to map addresses supplied from the host 430 (a mobile device or a computer system) to physical addresses of the memory 410 .
- the memory 410 may include the semiconductor memory device according to the embodiment of the inventive concept.
- the silicide layer is formed on at least a part of both sidewalls of a gate pattern on a device isolation layer, thereby reducing resistance of the gate pattern. This makes an operation speed of the device rapid.
- the active silicide layer formed on the active region comes in contact with the sidewall of the device isolation layer, the shared contact does not come in contact with the semiconductor substrate, thereby preventing current from leaking to the semiconductor substrate.
- the sidewall spacer is not provided on the sidewall of the conduct line located on the device isolation layer and coming in contact with the shared contact, the area of the shared contact is larger, thereby reducing the contact resistance.
- the sidewall spacer pattern is formed on at least a part of both sidewalls of the gate pattern in a subsequent salicide process by entirely or partially removing remaining portions of the sidewall spacer except for portions which are used as an ion implantation mask to form source/drain regions. This can reduce resistance of the gate pattern, thereby fabricating a semiconductor device with a rapid operation speed.
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Abstract
Provided are a semiconductor device and a method of fabricating the same. According to the semiconductor device, a silicide layer is formed on at least a part of both sidewalls of a gate pattern on a device isolation layer, thereby reducing resistance of the gate pattern. This makes an operation speed of the device rapid. According to the method of the semiconductor device, a sidewall spacer pattern is formed on at least a part of both sidewalls of the gate pattern in following salicide process by entirely or partially removing remaining portions of the sidewall spacer except for portions which are used as an ion implantation mask to form source/drain regions. This can reduce resistance of the gate pattern, thereby fabricating a semiconductor device with a rapid operation speed.
Description
- This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 of Korean Patent Application 10-2009-0019943, filed in the Korean Intellectual Property Office on Mar. 9, 2009, the entire contents of which are hereby incorporated by reference.
- The inventive concept relates to a semiconductor device and a method of fabricating the same.
- Generally, a gate sidewall spacer is used as an ion implantation mask in a transistor to form source/drain regions. Furthermore, the gate sidewall spacer plays important roles in insulating a silicide layer and a gate layer, which will be formed by a subsequent salicide process, from each other such that they are not connected to each other. Due to the silicide layer and the gate layer, however, there are problems that the integration degree of semiconductor devices deteriorates and the contact area becomes smaller, resulting in increasing the contact resistance.
- The present inventive concept provides a semiconductor device and a method of fabricating the same that can increase an operation speed of devices.
- The present inventive concept also provides a semiconductor device and a method of fabricating the same that can prevent current from leaking into a semiconductor substrate.
- Embodiments of the inventive concept provide a semiconductor device including: a device isolation layer located on a semiconductor substrate to define an active region; a gate pattern crossing over the active region and the device isolation layer; a sidewall spacer pattern covering a sidewall of the gate pattern on the active pattern; and a gate silicide layer covering at least a part of both sidewalls of the gate pattern on the device isolation layer.
- In some embodiments, the sidewall spacer pattern may expose all of both sidewalls of the gate pattern on the device isolation layer, and the gate silicide layer may cover both of the exposed sidewalls of the gate pattern.
- In some embodiments, the sidewall spacer pattern may cover a lower portion of both sidewalls of the gate pattern on the device isolation layer, and a width of the sidewall spacer pattern located on the device isolation layer may be smaller than half of that of the sidewall spacer pattern located on the active region.
- In some embodiments, the semiconductor device may further include: a conductive line located on the device isolation layer adjacent to the active region, the conductive line being adjacent to the gate pattern; a conductive line silicide layer covering at least both sidewalls of the conductive line; an active silicide layer formed on the active region and coming in contact with a sidewall of the device isolation layer; and a shared contact coming in contact with the active silicide layer and the conductive line silicide layer at the same time.
- In some embodiments, the gate pattern and the conductive line may include a polysilicon layer doped with impurities or undoped with impurities.
- Embodiments of the inventive concept also provide a method of fabricating a semiconductor device, the method including: forming a device isolation layer defining an active region on a semiconductor substrate; forming a gate pattern crossing over the active region and the device isolation layer; forming a sidewall spacer covering entirely a sidewall of the gate pattern; and forming a sidewall spacer pattern by removing remaining portions of the sidewall spacer except for portions which are used as an ion implantation mask to form source/drain regions.
- In some embodiments, the removing of a portion of the sidewall spacer includes leaving a remaining portion of the sidewall spacer used as an ion implantation mask to form source/drain regions.
- In some embodiments, the removing of a portion of the sidewall spacer includes: forming a mask layer covering the sidewall spacer located on the sidewall of the gate pattern on the active region but exposing the sidewall spacer on the device isolation layer; and removing at least a part of the sidewall spacer exposed by the mask layer.
- In some embodiments, the forming of the sidewall spacer pattern may include: forming a mask layer covering the sidewall spacer located on the sidewall of the gate pattern on the active region but exposing the sidewall spacer on the device isolation layer; and removing at least a part of the sidewall spacer exposed by the mask layer.
- In some embodiments, the method may further include: forming a conductive line adjacent to the gate pattern, the conductive line crossing over the device isolation layer; and forming a conductive line spacer covering entirely a sidewall of the conductive layer. In this configuration, at least a part of the conductive line spacer on the device isolation layer may be removed in the removing of at least a part of the sidewall spacer.
- In some embodiments, the part of the conductive line spacer may be formed to come in contact with an active region located between the gate pattern and the conductive line. In this configuration, the method may further include: forming an impurity implantation region in the active region by using an ion implantation process; forming a conductive silicide layer covering at least a part of both sidewalls of the conductive line and an active silicide layer on the active region; and forming a shared contact coming in contact with the active silicide layer and the conductive line silicide layer at the same time.
- In some embodiments, the conductive line and the gate pattern may include a polysilicon layer doped with impurities or undoped with impurities.
- The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the inventive concept and, together with the description, serve to describe principles of the inventive concept.
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FIG. 1A is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept. -
FIG. 1B is a sectional view taken along the lines I-I, II-II, and ofFIG. 1A . -
FIG. 2A is a perspective view illustrating a transistor in a periphery circuit region illustrated inFIG. 1A . -
FIG. 2B is a perspective view illustrating a silicide layer illustrated inFIG. 2A . -
FIGS. 3A , 4A, 5A, 6A, 7A, and 8A are plan views illustrating a process of manufacturing the semiconductor device illustrated inFIG. 1A . -
FIGS. 3B , 4B, 5B, 6B, 7B, and 8B are sectional views taken along the lines I-I, II-II, and III-III ofFIGS. 3A , 4A, 5A, 6A, 7A, and 8A, respectively. -
FIG. 7C is a sectional view taken along the lines I-I, II-II, and III-III ofFIG. 7A . -
FIG. 9A is a plan view illustrating a semiconductor device according to another embodiment of the inventive concept. -
FIG. 9B is a sectional view taken along the lines I-I, II-II, and III-III ofFIG. 9A . -
FIG. 9C is a perspective view illustrating a part of a transistor in a periphery circuit region illustrated inFIG. 9A . -
FIG. 10 is a block diagram schematically illustrating an electronic device including the semiconductor memory device according to the embodiment of the inventive concept. -
FIG. 11 is a block diagram illustrating a memory system including the semiconductor memory device according to the embodiment of the inventive concept. - Preferred embodiments of the inventive concept will be described below in more detail with reference to the accompanying drawings. Advantages and features of the inventive concept may be understood more readily by reference to the following detailed description of preferred embodiments and the accompanying drawings. The exemplary embodiments of the inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this description will be thorough and complete and will fully convey the scope of the inventive concept to those skilled in the art, and the embodiments of the inventive concept will only be defined by the appended claims. Like reference numerals refer to like elements throughout the specification.
- It will be understood that when any layers such as a conductive layer, a semiconductor layer, or an insulating layer are referred to as being “on” another material layer or substrate, it may be directly on the other material layer or substrate, or intervening elements or layers may be present. Moreover, it will be understood that, although the terms first, second, etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Accordingly, a first layer used in one embodiment of the inventive concept may be used to as a second layer in another embodiment of the inventive concept.
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FIG. 1A is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept.FIG. 1B is a sectional view taken along the lines I-I, II-II, and ofFIG. 1A . InFIG. 1B , a region “a” shows a sectional view taken along the line I-I ofFIG. 1A , a region “b” shows a sectional view taken along the line II-II ofFIG. 1A , and a region “c” shows a sectional view taken along the ofFIG. 1A . - With reference to
FIGS. 1A and 1B , adevice isolation layer 3 definingactive regions 5 is disposed on asemiconductor substrate 1 including a cell memory region and a periphery circuit region. One exemplary transistor is illustrated in the periphery circuit region. An exemplary unit memory cell of a full CMOS-type SRAM is illustrated in the cell memory region. On thesemiconductor substrate 1 of the cell memory region, specifically, four parallel bar-shapedactive regions 5 are formed in one direction, and long bar-shapedcell gate patterns 111 to 114 cross over theactive regions 5 in a direction perpendicular to the one direction. In the cell memory region, thecell gate patterns 111 to 114 include a firstcell gate pattern 111, a secondcell gate pattern 112, a thirdcell gate pattern 113, and a fourthcell gate pattern 114. Agate insulating layer 9 is interposed between thesemiconductor substrate 1 and each of thecell gate patterns 111 to 114. A low-concentrationimpurity implantation region 13 a and a high-concentrationimpurity implantation region 19 a are formed in thesemiconductor substrate 1 of the active regions adjacent to thecell gate patterns 111 to 114. Theimpurity implantation regions cell gate patterns 111 to 114 form six transistors Q1 to Q6. The transistors Q1 to Q6 include two access transistors Q1 and Q2, two drive transistors Q3 and Q4, and two load transistors Q5 and Q6, which form two flip-flop circuits, respectively. - The periphery circuit region is provided with a periphery circuit transistor which includes a
periphery gate pattern 115, which crosses over theactive region 5, and a low-concentrationimpurity implantation region 13 c and a high-concentrationimpurity implantation region 19 c formed in thesemiconductor substrate 1 of theactive region 5 adjacent to theperiphery gate pattern 115. Thegate patterns 111 to 115 may include a polysilicon layer that is doped with impurities or undoped with impurities. - In the semiconductor device of
FIGS. 1A and 1B ,sidewall spacer patterns 150 are formed on the sidewalls of thegate patterns 111 to 115 crossing over theactive regions 5 or on the sidewalls of thegate patterns 111 to 115 overlapping with theactive regions 5. That is, thesidewall spacer patterns 150 are formed on the sidewalls of thegate patterns 111 to 115 forming the transistors. In thegate patterns 111 to 115, the surfaces which are not covered with thesidewall spacer patterns 150 are all covered with gate silicide layers 211 to 215, respectively. Moreover, anactive silicide layer 210 is formed on thesemiconductor substrate 1 of theactive region 5 which are not covered with thesidewall spacer pattern 150, which is illustrated in detail inFIGS. 2A and 2B . -
FIG. 2A is a perspective view illustrating the transistor in the periphery circuit region ofFIG. 1A .FIG. 2B is a perspective view illustrating the peripherygate silicide layer 215 illustrated inFIG. 2A . Referring toFIGS. 2A and 2B , thedevice isolation layer 3 is formed on thesemiconductor substrate 1 of the periphery circuit region to define theactive regions 5. Theperiphery gate pattern 115 crosses over theactive region 5 and is located on thedevice isolation layer 3. In theactive region 5, thesidewall spacer patterns 150 are formed on only the sidewalls of theperiphery gate pattern 115, and the peripherygate silicide layer 215 covers all of the sidewalls and the upper surface of thecircuit gate pattern 115 corresponding to the exposed remaining portions which are not covered with thesidewall spacer pattern 150. The shape of the peripherygate silicide layer 215 ofFIG. 2B is similar to a lid covering theperiphery gate pattern 115. Therefore, since the area where the peripherycircuit gate pattern 115 is covered with thesilicide layer 215 having a relatively low resistance is maximized, it is possible to reduce the resistance of a gate electrode. - Referring again to
FIGS. 1A and 1B , with respect to thecell gate patterns 111 to 114 of the cell memory region, all of the remaining portions other than the sidewalls overlapping with theactive regions 5 are also covered with the cell gate silicide layers 211 to 214, like theperiphery gate pattern 115. The cell gate silicide layers 211 to 214 include a first cellgate silicide layer 211, a second cellgate silicide layer 212, a third cellgate silicide layer 213, and a fourthcell gate silicide 214. Contact plugs 251 and 252 are disposed on theactive silicide layer 210 and the third and fourth cell gate silicide layers 213 and 214 to apply a voltage. Theactive silicide layer 210 and the first and second cell gate silicide layers 211 and 212 come in contact with a sharedcontact 250. Theactive silicide layer 210 is adjacent to the load transistors Q5 and Q6 among the transistors Q1 to Q6 and is located between the firstcell gate pattern 111 and the secondcell gate pattern 112. First and second cell gate silicide layers 211 and 212 cover the end potions of the first and secondcell gate patterns device isolation layer 3 adjacent to theactive silicide layer 210. Theactive silicide layer 210 disposed below the sharedcontact 250 comes in contact with the sidewall of thedevice isolation layer 3, it can prevent current from leaking to thesemiconductor substrate 1. With reference to the sectional view of the region “a” ofFIG. 1B , since an area of theactive silicide layer 210 and the secondcell gate silicide 212 coming in contact with the sharedcontact 250 is large, a contact resistance can be reduced. - Next, a process of fabricating the semiconductor device illustrated in
FIGS. 1A and 1B will be described.FIGS. 3A , 4A, 5A, 6A, 7A, and 8A are plan views illustrating the process of fabricating the semiconductor device illustrated inFIG. 1A .FIGS. 3B , 4B, 5B, 6B, 7B, and 8B are sectional views taken along the lines I-I, II-II, and ofFIGS. 3A , 4A, 5A, 6A, 7A, and 8A, respectively.FIG. 7C is a sectional view taken along the lines I-I, II-II, and ofFIG. 7A . - Referring to
FIGS. 3A and 3B , thedevice isolation layer 3 is formed on thesemiconductor substrate 1 to define theactive regions 5. Thedevice isolation layer 3 is formed by, for example, STI (Shallow Trench Isolation). Before and/or after thedevice isolation layer 3 is formed, the well region may be formed by implanting impurities into thesemiconductor substrate 1. - Referring to
FIGS. 4A and 4B , thesemiconductor substrate 1 of theactive regions 5 is subjected to a thermal oxidation process to form thegate insulating layer 9. A gate layer is formed on the entire surface of thesemiconductor substrate 1. Thegate patterns 111 to 115 are formed by patterning the gate layer. Although not illustrated in drawings, a capping layer may further be formed on the gate layer. When the gate layer is patterned, the capping layer may be patterned together to form capping layer patterns on thegate patterns 111 to 115, respectively. Thegate patterns 111 to 115 may include a polysilicon layer doped with impurities or undoped with impurities. Alternatively, thegate patterns 111 to 115 may be formed so as to include a metal containing layer. By using thegate patterns 111 to 115 as an ion implantation mask, low-concentration impurities are implanted into thesemiconductor substrate 1 of theactive regions 5 on both sides of thegate patterns 111 to 115 to form the low-concentrationimpurity implantation regions impurity implantation regions impurity implantation region 13 a, a second low-concentrationimpurity implantation region 13 b, and a third low-concentrationimpurity implantation region 13 c. The first low-concentrationimpurity implantation region 13 a may be doped with P-type impurities. The second low-concentrationimpurity implantation region 13 b may be doped with N-type impurities. - Referring to
FIGS. 5A and 5B , a spacer layer is stacked on the entire surface of thesemiconductor substrate 1. The spacer layer is anisotropically etched to formsidewall spacers 15 covering all of the sidewalls of thegate patterns 111 to 115. The spacer layer may be at least one selected from a group including a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Since thesidewall spacer 15 covers all of the sidewalls of thegate patterns 111 to 115, thesidewall spacer 15 is formed not only on theactive regions 5 but also on thedevice isolation layer 3. - Referring to
FIGS. 6A and 6B , amask 17 is formed to expose the remaining portions of thesidewall spacer 15 except for portions which are used as the ion implantation mask to form source/drain regions. Themask 17 is formed so as to cover thesidewall spacer 15 located on the sidewalls of thegate patterns 111 to 115 overlapping with theactive patterns 5. Themask 17 may be, for example, a photoresist pattern. - Referring to
FIGS. 7A and 7B , the exposedsidewall spacer 15 which is not covered with themask 17 is removed using themask 17 as an etching mask. At this time, for example, an anisotropic dry etching process may be executed. In this way, thesidewall spacer pattern 150 is formed, which covers the sidewalls of thegate patterns 111 to 115 overlapping with theactive patterns 5. - Referring to
FIGS. 7A and 7C , the high-concentrationimpurity implantation regions sidewall spacer pattern 150 using as an ion implantation mask. The high-concentrationimpurity implantation regions impurity implantation region 19 a, a second high-concentrationimpurity implantation region 19 b, and a third high-concentrationimpurity implantation region 19 c. The first high-concentrationimpurity implantation region 19 a may be doped with P-type impurities. The second high-concentrationimpurity implantation region 19 b may be doped with N-type impurities. Referring to the sectional view of a region “c” ofFIG. 7C , the first high-concentrationimpurity implantation region 19 a is formed so as to come in contact with thedevice isolation layer 3. - Referring to
FIGS. 8A and 8B , a metal layer is stacked on the entire surface of the structure and subjected to heat treatment to form the silicide layers 210 to 215. In this way, the gate silicide layers 211 to 215 are formed on sidewalls and upper surfaces of thegate patterns 111 to 115 on the exposeddevice isolation layer 3 which are not covered with thesidewall spacer pattern 150, respectively. Theactive silicide layer 210 is formed on thesemiconductor substrate 1 of theactive patterns 5. The metal layer is formed of titanium, cobalt, nickel, or platinum. The silicide layers 210 to 215 are formed, for example, of titanium, cobalt, nickel, or platinum silicide. Unsilicided metal layer is removed. Referring to the sectional view of a region “a” ofFIG. 8B , theactive silicide layer 210 is formed so as to come in contact with the sidewall of thedevice isolation layer 3 adjacent to the secondcell gate pattern 112. - When the capping layer pattern is formed on upper surfaces of the
gate patterns 111 to 115, a process of removing the capping layer pattern may additionally be provided before a salicide process of forming the silicide layers 210 to 215. - Subsequently, referring again to
FIGS. 1A and 1B , aninterlayer insulating layer 23 is formed on the entire surface of the structure. The contact plugs 250 to 252 are formed by penetrating theinterlayer insulating layer 23 to be in contact with theactive silicide layer 210 or the gate silicide layers 211 to 215. In order to form the contact plugs 250 to 252, when contact holes (not illustrated) for exposing the silicide layers 210 to 215 are formed by patterning theinterlayer insulating layer 23, the silicide layers 210 to 215 serve as an etch stop layer. Accordingly, the surface of thesemiconductor substrate 1 may be less damaged. - According to a modified exemplary embodiment of the inventive concept, in
FIGS. 6A and 6B , remainingsidewall spacers 150 r may be formed by not removing entirely the exposedsidewall spacers 15 using themask 17 in the process of removing the exposedsidewall spacers 15.FIGS. 9A , 9B, and 9C illustrate the semiconductor device including such remainingspacers 150 r, respectively.FIG. 9A is a plan view illustrating the semiconductor device according to another embodiment of the inventive concept.FIG. 9B is a sectional view taken along the lines I-I, II-II, and III-III ofFIG. 9A .FIG. 9C is a perspective view illustrating a part of the transistor in the periphery circuit region illustrated inFIG. 9A . - Referring to the semiconductor device of
FIGS. 9A , 9B, and 9C, the remainingsidewall spacers 150 r remain in the sidewalls of thegate patterns 111 to 115 on thedevice isolation layer 3. It is desirable that the width W1 of the remainingsidewall spacer 150 r be smaller than half of the width W2 of thesidewall spacer pattern 150. The remainingsidewall spacers 150 r are formed so as to expose a part (that is, upper portion) of thegate patterns 111 to 115 on thedevice isolation layer 3. Then, in a subsequent salicide process, gate silicide layers 221 to 225 are formed in a part and the upper surface of the both sides of thegate patterns 111 to 115 exposed to thedevice isolation layer 3, andactive silicide layers 220 are formed in theactive regions 5. Theactive silicide layer 220 located between the firstcell gate pattern 111 and the secondcell gate pattern 112 may come in contact with thedevice isolation layer 3 by the remainingsidewall spacer 150 r covering a part of the sidewalls of the secondcell gate pattern 112 on thedevice isolation layer 3. The other configuration and the manufacturing process are the same as the above-described configuration and process. - The full CMOS type SDAM has been described as an example of the cell memory according to the embodiment of the inventive concept. However, it should be apparent to those skilled in the art that the configuration of the inventive concept is applicable to a variety of semiconductor devices such as other DRAMs and NAND or NOR flash memories.
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FIG. 10 is a block diagram schematically illustrating an electronic device including the semiconductor memory device according to an embodiment of the inventive concept.FIG. 11 is a block diagram illustrating a memory system including the semiconductor memory device according to an embodiment of the inventive concept. - Referring to
FIG. 10 , anelectronic device 300 including the semiconductor memory device according to an embodiment of the inventive concept will be described. Theelectronic device 300 may be used in wireless communication apparatuses such as a PDA, a laptop computer, a portable computer, a web tablet, a wireless telephone, a cellular phone, and a digital music player, or all elements capable of transmitting and/or receiving information in a wireless environment. - The
electronic device 300 includes acontroller 310, an input/output device 320 such as a keypad, a keyboard, or a display, amemory 330, and awireless interface 340 which are connected to each other through abus 350. Thecontroller 310 may include one or more microprocessors, digital signal processors, or microcontrollers or include an equivalent thereof. Thememory 330 may be used to store commands executed by thecontroller 310, for example. Moreover, thememory 330 may be used to store data of a user. Thememory 330 includes the semiconductor memory device according to embodiments of the inventive concept. - The
electronic device 300 may use thewireless interface 340 in order to transmit data to a wireless communication network carrying out communication by use of RF signals or to receive data from a network. For example, thewireless interface 340 may include an antenna or a wireless transceiver. - The
electronic device 300 according to the embodiments of the inventive concept may be used in communication interface protocols of a third generation communication system such as CDMA, GSM, NADC, E-TDMA, WCDAM, and CDMA2000. - Referring to
FIG. 11 , a memory system including the semiconductor memory device according to an embodiment of the inventive concept will be described. - A
memory system 400 includes amemory 410 storing mass data and amemory controller 420. Thememory controller 420 controls thememory 410 to read or write stored data from or to thememory 410 in response to a request for reading/writing the data from ahost 430. Thememory controller 420 may create an address mapping table used to map addresses supplied from the host 430 (a mobile device or a computer system) to physical addresses of thememory 410. Thememory 410 may include the semiconductor memory device according to the embodiment of the inventive concept. - In the semiconductor device according to one embodiment of the inventive concept, the silicide layer is formed on at least a part of both sidewalls of a gate pattern on a device isolation layer, thereby reducing resistance of the gate pattern. This makes an operation speed of the device rapid.
- In the semiconductor device according to another embodiment of the inventive concept, since the active silicide layer formed on the active region comes in contact with the sidewall of the device isolation layer, the shared contact does not come in contact with the semiconductor substrate, thereby preventing current from leaking to the semiconductor substrate.
- In the semiconductor device according to another embodiment of the inventive concept, since the sidewall spacer is not provided on the sidewall of the conduct line located on the device isolation layer and coming in contact with the shared contact, the area of the shared contact is larger, thereby reducing the contact resistance.
- In the semiconductor device according to another embodiment of the inventive concept, the sidewall spacer pattern is formed on at least a part of both sidewalls of the gate pattern in a subsequent salicide process by entirely or partially removing remaining portions of the sidewall spacer except for portions which are used as an ion implantation mask to form source/drain regions. This can reduce resistance of the gate pattern, thereby fabricating a semiconductor device with a rapid operation speed.
- The above-described subject matter is to be considered illustrative and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the inventive concept. Thus, to the maximum extent allowed by law, the scope of the inventive concept is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.
Claims (6)
1. A semiconductor device comprising:
a device isolation layer located on a semiconductor substrate to define an active region;
a gate pattern crossing over the active region and the device isolation layer;
a sidewall spacer pattern covering a sidewall of the gate pattern on the active pattern; and
a gate silicide layer covering at least a part of both sidewalls of the gate pattern on the device isolation layer.
2. The semiconductor device of claim 1 , wherein the sidewall spacer pattern exposes all of both sidewalls of the gate pattern on the device isolation layer, and the gate silicide layer covers both of the exposed sidewalls of the gate pattern.
3. The semiconductor device of claim 1 , wherein the sidewall spacer pattern covers a lower portion of both sidewalls of the gate pattern on the device isolation layer, and a width of the sidewall spacer pattern located on the device isolation layer is smaller than half of that of the sidewall spacer pattern located on the active region.
4. The semiconductor device of claim 1 , further comprising:
a conductive line located on the device isolation layer adjacent to the active region, the conductive line being adjacent to the gate pattern;
a conductive line silicide layer covering at least both sidewalls of the conductive line;
an active silicide layer formed on the active region and contacting with a sidewall of the device isolation layer; and
a shared contact contacting with both the active silicide layer and the conductive line silicide layer.
5. The semiconductor device of claim 1 , wherein the gate pattern and the conductive line comprise a polysilicon layer doped with impurities or undoped with impurities.
6-11. (canceled)
Priority Applications (2)
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US14/013,853 US8916941B2 (en) | 2009-03-09 | 2013-08-29 | Semiconductor device having silicide on gate sidewalls in isolation regions |
US14/535,851 US9281377B2 (en) | 2009-03-09 | 2014-11-07 | Semiconductor device having silicide on gate sidewalls in isolation regions |
Applications Claiming Priority (2)
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KR10-2009-0019943 | 2009-03-09 | ||
KR1020090019943A KR20100101446A (en) | 2009-03-09 | 2009-03-09 | Semiconductor device and method of forming the same |
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US14/013,853 Continuation US8916941B2 (en) | 2009-03-09 | 2013-08-29 | Semiconductor device having silicide on gate sidewalls in isolation regions |
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US20100224942A1 true US20100224942A1 (en) | 2010-09-09 |
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US12/660,943 Abandoned US20100224942A1 (en) | 2009-03-09 | 2010-03-08 | Semiconductor device and method of fabricating the same |
US14/013,853 Active - Reinstated US8916941B2 (en) | 2009-03-09 | 2013-08-29 | Semiconductor device having silicide on gate sidewalls in isolation regions |
US14/535,851 Active US9281377B2 (en) | 2009-03-09 | 2014-11-07 | Semiconductor device having silicide on gate sidewalls in isolation regions |
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US14/535,851 Active US9281377B2 (en) | 2009-03-09 | 2014-11-07 | Semiconductor device having silicide on gate sidewalls in isolation regions |
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100200929A1 (en) * | 2009-02-09 | 2010-08-12 | Dong Suk Shin | Semiconductor integrated circuit device |
CN103378065A (en) * | 2012-04-27 | 2013-10-30 | 佳能株式会社 | Semiconductor device and method for fabricating the same |
US8916941B2 (en) | 2009-03-09 | 2014-12-23 | Samsung Electronics Co., Ltd. | Semiconductor device having silicide on gate sidewalls in isolation regions |
US20160276164A1 (en) * | 2015-03-16 | 2016-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for Forming Patterns with Sharp Jogs |
US9761436B2 (en) | 2014-06-30 | 2017-09-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming patterns using multiple lithography processes |
US20230163083A1 (en) * | 2017-07-21 | 2023-05-25 | Stmicroelectronics (Rousset) Sas | Integrated circuit containing a decoy structure |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9978755B2 (en) * | 2014-05-15 | 2018-05-22 | Taiwan Semiconductor Manufacturing Company Limited | Methods and devices for intra-connection structures |
KR20180052171A (en) * | 2016-11-09 | 2018-05-18 | 삼성전자주식회사 | Design method of semiconductor integrated circuit layout and method for forming semiconductor device using the same |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050272256A1 (en) * | 2003-08-25 | 2005-12-08 | Yu-Piao Wang | Semiconductor device and fabricating method thereof |
US20070023832A1 (en) * | 2005-08-01 | 2007-02-01 | Nec Electronics Corporation | Semiconductor device and method of fabricating the same |
US20080203493A1 (en) * | 2007-02-22 | 2008-08-28 | Fujitsu Limited | Semiconductor memory device and fabrication process thereof |
US20080311718A1 (en) * | 2007-06-15 | 2008-12-18 | Renesas Technology Corp. | Manufacturing method of semiconductor device |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR960030440A (en) | 1995-01-12 | 1996-08-17 | 모리시다 요이치 | Semiconductor device and manufacturing method thereof |
JP2005033098A (en) * | 2003-03-05 | 2005-02-03 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
US7279746B2 (en) * | 2003-06-30 | 2007-10-09 | International Business Machines Corporation | High performance CMOS device structures and method of manufacture |
US6939770B1 (en) * | 2003-07-11 | 2005-09-06 | Advanced Micro Devices, Inc. | Method of fabricating semiconductor device having triple LDD structure and lower gate resistance formed with a single implant process |
US7122849B2 (en) * | 2003-11-14 | 2006-10-17 | International Business Machines Corporation | Stressed semiconductor device structures having granular semiconductor material |
KR100576360B1 (en) * | 2003-12-08 | 2006-05-03 | 삼성전자주식회사 | Method of fabricating a semiconductor device including a T-shaped gate and an L-shaped spacer |
JP2007027348A (en) | 2005-07-15 | 2007-02-01 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
US7339230B2 (en) * | 2006-01-09 | 2008-03-04 | International Business Machines Corporation | Structure and method for making high density mosfet circuits with different height contact lines |
US7622339B2 (en) * | 2006-01-26 | 2009-11-24 | Freescale Semiconductor, Inc. | EPI T-gate structure for CoSi2 extendibility |
US7563700B2 (en) * | 2006-02-22 | 2009-07-21 | Freescale Semiconductor, Inc. | Method for improving self-aligned silicide extendibility with spacer recess using an aggregated spacer recess etch (ASRE) integration |
KR20100101446A (en) | 2009-03-09 | 2010-09-17 | 삼성전자주식회사 | Semiconductor device and method of forming the same |
-
2009
- 2009-03-09 KR KR1020090019943A patent/KR20100101446A/en not_active Application Discontinuation
-
2010
- 2010-03-08 US US12/660,943 patent/US20100224942A1/en not_active Abandoned
-
2013
- 2013-08-29 US US14/013,853 patent/US8916941B2/en active Active - Reinstated
-
2014
- 2014-11-07 US US14/535,851 patent/US9281377B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050272256A1 (en) * | 2003-08-25 | 2005-12-08 | Yu-Piao Wang | Semiconductor device and fabricating method thereof |
US20070023832A1 (en) * | 2005-08-01 | 2007-02-01 | Nec Electronics Corporation | Semiconductor device and method of fabricating the same |
US7633126B2 (en) * | 2005-08-01 | 2009-12-15 | Nec Electronics Corporation | Semiconductor device having a shared contact and method of fabricating the same |
US20080203493A1 (en) * | 2007-02-22 | 2008-08-28 | Fujitsu Limited | Semiconductor memory device and fabrication process thereof |
US20080311718A1 (en) * | 2007-06-15 | 2008-12-18 | Renesas Technology Corp. | Manufacturing method of semiconductor device |
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8207594B2 (en) * | 2009-02-09 | 2012-06-26 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit device |
US20100200929A1 (en) * | 2009-02-09 | 2010-08-12 | Dong Suk Shin | Semiconductor integrated circuit device |
US8916941B2 (en) | 2009-03-09 | 2014-12-23 | Samsung Electronics Co., Ltd. | Semiconductor device having silicide on gate sidewalls in isolation regions |
US9281377B2 (en) | 2009-03-09 | 2016-03-08 | Samsung Electronics Co., Ltd. | Semiconductor device having silicide on gate sidewalls in isolation regions |
KR101592231B1 (en) | 2012-04-27 | 2016-02-05 | 캐논 가부시끼가이샤 | Semiconductor device and method for fabricating the same |
US9136403B2 (en) * | 2012-04-27 | 2015-09-15 | Canon Kabushiki Kaisha | Semiconductor device with wirings of differing young's modulus and method for fabricating the same |
US20130285189A1 (en) * | 2012-04-27 | 2013-10-31 | Canon Kabushiki Kaisha | Semiconductor device and method for fabricating the same |
CN103378065A (en) * | 2012-04-27 | 2013-10-30 | 佳能株式会社 | Semiconductor device and method for fabricating the same |
US9761436B2 (en) | 2014-06-30 | 2017-09-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming patterns using multiple lithography processes |
US10276363B2 (en) | 2014-06-30 | 2019-04-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming patterns using multiple lithography processes |
US10770303B2 (en) | 2014-06-30 | 2020-09-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming patterns using multiple lithography processes |
US20160276164A1 (en) * | 2015-03-16 | 2016-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for Forming Patterns with Sharp Jogs |
US9711369B2 (en) * | 2015-03-16 | 2017-07-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming patterns with sharp jogs |
US20230163083A1 (en) * | 2017-07-21 | 2023-05-25 | Stmicroelectronics (Rousset) Sas | Integrated circuit containing a decoy structure |
US12051656B2 (en) * | 2017-07-21 | 2024-07-30 | Stmicroelectronics (Rousset) Sas | Integrated circuit containing a decoy structure |
Also Published As
Publication number | Publication date |
---|---|
KR20100101446A (en) | 2010-09-17 |
US20130341732A1 (en) | 2013-12-26 |
US9281377B2 (en) | 2016-03-08 |
US20150061039A1 (en) | 2015-03-05 |
US8916941B2 (en) | 2014-12-23 |
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