US20100097253A1 - Low power linear interpolation digital-to-analog conversion - Google Patents
Low power linear interpolation digital-to-analog conversion Download PDFInfo
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- 230000001052 transient effect Effects 0.000 claims abstract description 13
- 238000001914 filtration Methods 0.000 claims abstract description 8
- 238000004891 communication Methods 0.000 claims description 21
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- 230000003111 delayed effect Effects 0.000 claims description 12
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/20—Modulator circuits; Transmitter circuits
- H04L27/2032—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner
- H04L27/2053—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases
- H04L27/206—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases using a pair of orthogonal carriers, e.g. quadrature carriers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/661—Improving the reconstruction of the analogue output signal beyond the resolution of the digital input signal, e.g. by interpolation, by curve-fitting, by smoothing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/78—Simultaneous conversion using ladder network
- H03M1/785—Simultaneous conversion using ladder network using resistors, i.e. R-2R ladders
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/80—Simultaneous conversion using weighted impedances
- H03M1/808—Simultaneous conversion using weighted impedances using resistors
Definitions
- the present invention generally relates to resistor network digital-to-analog conversion methods and apparatus, and particularly relates to low power digital-to-analog conversion using linear interpolation therein.
- Digital-to-analog converters convert digital words into analog values, such as analog voltage values or analog current values.
- the digital word consists of n bits
- the corresponding analog value may be generated by applying progressive power of two weightings to each of the n bits.
- Conventional resistor network digital-to-analog converters use a network of resistor stages to apply the progressive weightings to each bit.
- Known resistor network digital-to-analog converters include, for example, binary weighted digital-to-analog converters and R/2R ladder digital-to-analog converters. These conventional resistor network digital-to-analog converters sample each bit at a reconstruction clock frequency, f s , and apply those sampled bit values to progressively weighted resistor stages. Each of these stages, however, introduces reconstruction error into the analog output signal in the form of both static error and transient error (e.g. noise spikes).
- Methods and apparatus taught herein advantageously move reconstruction errors of a resistor network digital to analog converter (DAC) to frequencies outside the range of interest while consuming less power than would be required to obtain similar frequency shifting through an increase in the reconstruction clock. Instead of increasing the reconstruction clock frequency, the methods and apparatus taught herein subdivide each sampling clock cycle of the DAC into a number of phases.
- DAC resistor network digital to analog converter
- the input bit value is sampled at each phase.
- Each of those sampled values is then applied to a respective resistor branch, and the parallel set of resistor branches forms the parallel equivalent of the desired input resistor weight for that bit input. Doing so effectively applies the bit value in weighted form to the resistor network in a step-wise, linear interpolation process that eliminates or reduces both the static and transient effects in the analog output signal associated with applying the bit value.
- a resistor network DAC includes a set of bit input circuits, an analog signal output circuit, and a clocking circuit.
- the set of bit input circuits is configured to receive input bit values of an n-bit digital word.
- Each bit input circuit has an input sampling circuit configured to sample an input bit value according to clock signals of the clocking circuit and a driver circuit to apply the sampled value to an associated input resistor having a desired input resistor weight.
- the clocking circuit comprises a multi-phase clock generator configured to subdivide each sampling clock cycle of the DAC into a number of phases.
- the sampling circuit comprises a number of parallel sampling circuits configured to each sample the input bit value at a different one of those equally spaced phases.
- the driver circuit within that bit input comprises a corresponding number of parallel driver circuits each configured to apply the corresponding sampled value to a respective resistor branch. Because the parallel combination of all respective resistor branches forms the equivalent of the desired input resistor weight for that bit input circuit, the desired contribution of that input bit value is spread over the entire sampling clock period.
- the analog signal output circuit is configured to generate the analog (output) signal as the resistor-weighted sum of all input bit values.
- one or more method and apparatus embodiments presented herein apply each sampled value to its respective resistor branch via a slew-rate controlled driver, to smooth the analog signal transient edges at the output nodes of the resistor network. That is, the bit inputs that are configured as multi-phase bit inputs use slew-rate controlled drivers for the sampled values, to further smooth output signal transient edges.
- Such slew-rate controlled drivers may comprise a current-mirror circuit tied to a slew-rate limiting current source.
- the slew-rate controlled drivers may each comprise a delay circuit configured to generate a number of instances of the sampled value, each instance being the sampled value delayed by an increasing number of delay units, and a parallel driver set circuit, each driver within the set having its input driven by a different one of those instances.
- the resistor network DAC comprises part of a communication transmitter and is configured to convert a baseband communication signal into an analog signal.
- the resistor network DAC may be further configured to provide the analog signal to a current-mode low-pass filter circuit, for filtering in advance of current mode modulation.
- FIG. 1 is a block diagram illustrating one embodiment of a resistor network digital-to-analog converter of the present invention.
- FIG. 2 is a logic flow diagram illustrating one embodiment of a resistor network digital-to-analog converter of the present invention.
- FIGS. 3A and 3B are schematic diagrams of example embodiments of the bit input circuits for the resistor network digital-to-analog converter of FIG. 1 .
- FIG. 4 is a waveform diagram comparing a conventional reconstructed analog waveform without linear-interpolation error reduction to a reconstructed analog waveform with linear-interpolation error reduction as provided by the resistor network digital to analog converter of FIG. 1 .
- FIG. 5 is a schematic diagram of one embodiment of slew-rate controlled drivers, each comprising a current-mirror circuit tied to a slew-rate limiting current source.
- FIG. 6 is a waveform diagram similar to that shown in FIG. 4 , but where the reconstructed analog waveform with linear-interpolation error reduction is further improved through the use of the slew-rate controlled drivers of FIG. 5 .
- FIG. 7 is a block diagram of another embodiment of slew-rate controlled drivers, each comprising a delay circuit and a parallel driver set circuit.
- FIG. 8 is a schematic diagram for one embodiment of the delay circuits and parallel driver set circuits for the slew-rate controlled drivers of FIG. 7 .
- FIG. 9 is a schematic diagram of another embodiment of the delay circuits and parallel driver circuits for the slew-rate controlled drivers of FIG. 7 .
- FIG. 10 is a waveform diagram depicting the generation of delayed instances of a sampled bit input value according to the delay circuit of FIG. 7 and the combination of those delayed instances according to the parallel driver set circuit of FIG. 7 .
- FIG. 11 is a waveform diagram for the reconstruction curves for various tuning of the delay units in the slew-rate controlled drivers of FIG. 7 .
- FIG. 12 is a block diagram illustrating one embodiment of the resistor network digital to analog converter of FIG. 1 as applied to a communication transmitter.
- FIG. 1 illustrates one embodiment of a resistor network digital-to-analog converter (DAC) 10 , which receives an n-bit digital word and generates an analog signal representation thereof.
- the resistor network DAC 10 includes a set of bit inputs circuits 20 , 30 , a clocking circuit 40 , and an analog signal output circuit 50 .
- the set of bit inputs circuits 20 , 30 is configured to receive input bit values (Bit 0 , Bit 1 . . . Bit n-1 ) of an n-bit digital word.
- Each bit input circuit 20 , 30 has an input sampling circuit 22 , 32 configured to successively sample the input bit values with a fixed delay and a driver circuit 24 , 34 configured to apply the sampled value(s) 26 , 36 to an associated input resistor 28 , 38 having a desired input resistor weight R A , R B .
- the desired input resistor weights R A , R B may be, for example, proportional to the desired contribution of the corresponding input bit value to the analog signal during a given sampling clock period.
- the contributions of all bit input circuits 20 , 30 , as resistor-weighted input bit values, are combined via bridge resistors Rs and termination resistor R T . These contributions are then input into the analog signal output circuit 50 .
- the analog signal output circuit 50 is configured to generate an analog signal as the sum of the resistor-weighted input bit values of each bit input circuit 20 , 30 .
- each input sampling circuit 22 , 32 receives one or more clock signals (Ck i , CK) provided by the clocking circuit 40 .
- the clocking circuit 40 comprises a multi-phase clock generator 42 configured to subdivide each sampling clock cycle of the resistor network DAC 10 into m phases (Ck 0 , Ck 1 . . . Ck m-1 ) at reconstruction clock frequency f s .
- the phase difference or delay, P m between two successive phases is P s /m, where P s equals the clock period of the reconstruction clock f s .
- the bit input circuit(s) 30 are multi-phase bit input circuits that are clocked by some or all of the m clock signals, CK, each at a different phase.
- the sampling circuit 32 comprises m parallel sampling circuits 33 configured to each sample the corresponding input bit value at a different one of the m phases (Ck 0 , Ck 1 . . . Ck m-1 ).
- the sampling circuit 32 therefore, generates m sampled values 36 , each of which represents the corresponding input bit value sampled at a different equally spaced phase or time interval.
- Each of these m sampled values 36 serves as an input into a different one of m parallel driver circuits 35 within the driver circuit 34 .
- the parallel driver circuits 35 are configured to each apply a sampled value 36 to a respective resistor branch 39 within the associated input resistor 38 .
- each sampled value 36 represents the corresponding input bit value during a successive time interval
- such operation has the effect of cumulatively applying during successive time intervals the corresponding input bit value to the respective resistor branches 39 .
- the parallel combination of these respective resistor branches 39 forms the equivalent of the desired input resistor weight R B of the associated input resistor 38 .
- the corresponding input bit value is applied to a portion of the desired input resistor weight R B during successive time intervals and the desired contribution of the input bit value is spread linearly over the entire sampling clock period.
- Such linear interpolation effectively increases the frequency of amplitude transitions in the analog output signal so as to shift the reconstruction error due to the at least one bit input circuit 30 into a frequency outside the range of interest, specifically m*f s .
- shifting the reconstruction error to frequency m*f s in this manner consumes less power than oversampling at that same frequency.
- the resistor network DAC 10 may be implemented with such linear interpolation as described above for any number of its bit inputs, e.g., any mix of single-phase bit input circuits 20 and multi-phase bit input circuits 30 can be used.
- bit input circuits 30 can be used for all n bit inputs.
- the least significant bit inputs contribute little to the reconstruction errors within the analog signal output.
- using bit input circuits 30 for the least significant bits may be unnecessary for those applications which tolerate at least minimal reconstruction errors.
- the desired input resistor weights R A , R B , as well as the bridge resistors Rs and the termination resistor R T may depend on the type of resistor network DAC 10 being implemented.
- the resistor network DAC 10 comprises an R/2R ladder DAC
- the termination resistor Rt connected at the bridge node of the least significant bit is infinitive large in the case of binary weighted resistor implementation.
- the resistor network DAC 10 comprises an R/ 2 R ladder DAC or a binary weighted resistor DAC, however, the resistor network DAC 10 implements a method of converting a digital signal into an analog signal, an example of which is given in FIG. 2 .
- the illustrated conversion “begins” with the resistor network DAC 10 receiving input bit values of an n-bit digital word on the set of bit input circuits 20 , 30 (Block 100 ).
- the multiphase clock generator 42 subdivides each sampling clock cycle of the clocking circuit 40 into m phases (Block 110 ), and the sampling circuit 32 of each bit input circuit 30 samples the respective input bit value at each of the m phases (Block 120 ).
- a parallel driver circuit 35 applies the sampled value 36 to a respective resistor branch 39 in a parallel set of resistor branches 39 that form the parallel equivalent of the desired input resistor weight R B for that at least one bit input circuit 30 (Block 130 ). That is, each sampled value is applied at a respective one of the clock phases, which effectively results in the overall contribution of the input bit value being accumulated incrementally over the reconstruction frequency clock period.
- the overall conversion operation includes the analog signal output circuit 50 generating the analog signal by summing the resistor weighted sampled values for all bit input circuits 20 , 30 (Block 140 ).
- the analog signal output circuit 50 may comprise, for example, a summer circuit consisting of either an operational amplifier using feedback for a unity gain, or just a resistor for providing a voltage output in the case that output current equals zero.
- the output of the bit input circuits 20 , 30 may be used directly as the analog signal.
- the analog signal output circuit 50 may simply connect these outputs together without the use of an operational amplifier or any resistance.
- summer circuits may also be used to add the resistor weighted sampled values.
- multiphase clock generator 42 used to subdivide each sampling clock cycle of clocking circuit 40 into m phases.
- a delay locked loop (DLL), or a phase locked loop (PLL), for example, can be employed to create these m phases at reconstruction clock frequency f s .
- a clock at frequency of m*f s may be used and the m phases at frequency f s generated using divide-by-m.
- FIGS. 3A and 3B Example implementations of the bit input circuits 20 , 30 are illustrated in FIGS. 3A and 3B . It should be understood that these detailed examples are non-limiting illustrations of physical and/or functional circuit arrangements offering advantageous operation in certain applications.
- FIG. 3A illustrates one example of an implementation of a least significant bit input circuit 20 .
- a single delay flip-flop, DFF is used as the sampling circuit 22 .
- the DFF latches the input bit value (Bit 1 ) into memory on the trig (rising/falling) edge of Ck i and holds that sampled value 26 for the entire sampling clocking cycle. Therefore, upon the rising edge of Ck i and for the remainder of the sampling clock cycle, a buffer, BUFF, within the driver circuit 24 applies that sampled value 26 to the associated input resistor 28 .
- the associated input resistor 28 comprises a single resistor representing the entire desired input resistor weight R A for the bit input circuit 20 .
- the buffer, BUFF applies the entire desired contribution of the input bit value (Bit 1 ) at the beginning of and throughout the sampling clock period.
- FIG. 3B illustrates how the bit input circuit 30 linearly spreads the desired contribution of the input bit value over the sampling clock period.
- the bit input circuit 30 receives m clock signals CK offset in phase into the m parallel sampling circuits 33 , each of which comprise one of m delay flip-flops (DFF 0 , DFF 1 . . . DFF m-1 ).
- DFF 0 , DFF 1 . . . DFF m-1 Each of the m DFFs latches the input bit value (Bit n-1 ) into its respective memory on the trig edge of its respective clock signal and holds that sampled value 36 until clocked again.
- sampled values 36 are applied to a respective resistor branch 39 via one of the m parallel driver circuits 35 , which comprises m buffers (BUFF 0 , BUFF 1 . . . BUFF m-1 ).
- the m resistor branches 39 likewise comprise m resistors, each with a resistance of m*R B so that the parallel equivalent of the m resistors equals the desired input resistor weight R B .
- the input bit value (Bit n-1 ) is applied to each of the m resistors, representing a portion of the desired input resistor weight R B , during successive time intervals.
- FIG. 4 The advantages of the resulting analog signal generated by such a resistor network DAC 10 having bit input circuits 30 are illustrated in FIG. 4 .
- Plotted within FIG. 4 is an original analog signal x 1 , the reconstructed analog signal x 2 generated by a conventional resistor network DAC with reconstruction frequency f s , and the reconstructed analog signal x 3 generated by the above-described resistor network DAC 10 also at f s .
- a conventional resistor network DAC outputs a reconstructed analog signal x 2 with large steps at the beginning of each clock cycle, resulting in relatively large reconstruction errors within the frequency band of interest.
- the reconstructed analog signal x 3 depicts the output of the above-described resistor network DAC 10 .
- the incremental, multi-phase application of one or more of the most significant input bit values reduces the reconstruction error at any given time instant, and, furthermore, maps such errors into a higher frequency, m*f s .
- the parallel driver circuits 35 may comprise parallel slew-rate controlled driver circuits 35 . These parallel slew-rate controlled driver circuits 35 are further configured to each smooth transient edges in the generated analog output signal.
- FIG. 5 illustrates one example of such an embodiment having parallel slew-rate controlled driver circuits 35 .
- the bit input circuit 30 shown in FIG. 5 essentially imitates that previously described in FIG. 3B , with the exception that the parallel driver circuits 35 each comprise an inverter circuit (INV 0 , INV 1 . . . INV m-1 ) coupled to a current-mirror circuit, CM, tied to a slew-rate limiting current source, IC.
- INV 0 inverter circuit
- CM current-mirror circuit
- the current-mirror circuit CM is connected to each of transistors Tps 0 , Tps 1 . . . Tps m-1 and Tns 0 , Tns 1 . . . Tns m-1 so as to mirror the slew-rate limiting current IC through each of the inverting buffers (INV 0 , INV 1 . . . INV m-1 ) comprised of transistors (Tp 0 , Tn 0 ), (Tp 1 , Tn 1 ) . . . (Tp m-1 , Tn m-1 ).
- the slew-rate limiting current source, IC limits the rate at which a sampled value 36 may be applied by each inverting buffer (INV 0 , INV 1 . . . INV m-1 ) to a resistor branch 39 .
- the sampled value 36 as output from DFF 0 changes from low to high, such change occurs at a given slew rate.
- the high voltage at the output of the inverting buffer INV 0 discharges the capacitance on the output node through transistor Tn 0 as well as transistor Tns 0 .
- the capacitance includes all parasitic capacitances in output nodes, like device parasitic capacitance and routing parasitic capacitance.
- the slew-rate at which that output is pulled down toward ground is limited by the value of IC which is mirrored in Tns 0 .
- the output of the inverting buffer INV 0 will change from high to low at an independent slew rate which is controlled by the magnitude of the current source IC.
- the magnitude of the slew-rate limiting current source IC may be tuned accordingly in order to reduce transients in the analog signal output by analog signal output circuit 50 .
- FIG. 6 illustrates the additional advantages of such a resistor network DAC 10 having the above-described parallel slew-rate controlled driver circuits 35 .
- the plot of FIG. 6 essentially imitates that previously described in FIG. 4 , except for the addition of the reconstructed analog signal, x 4 , generated by a resistor network DAC 10 having parallel slew-rate controlled driver circuits 35 .
- This resistor network DAC 10 outputs a reconstructed analog signal x 4 similar to that of x 3 , but with a slower slew rate. Such results in even smaller reconstruction errors while still mapping these errors into a higher frequency.
- FIG. 7 illustrates an alternative resistor network DAC 10 comprising parallel slew-rate controlled driver circuits 35 .
- the bit input circuit 30 shown in FIG. 7 essentially imitates that previously described in FIG. 3B , with the exception that the parallel driver circuits 35 each comprise a delay circuit and a parallel driver set circuit.
- the delay circuit within each parallel driver circuit 35 is configured to generate k instances (d 0 , d 1 . . . d k-1 ) of the sampled value 36 , each instance being the sampled value 36 delayed by an increasing number of delay units.
- the parallel driver set circuit within each parallel driver circuit 35 itself comprises a parallel set of drivers, each such driver having its input driven by a different one of the instances (d 0 , d 1 . . . d k-1 ).
- FIGS. 8 and 9 illustrate two such implementations.
- the delay circuit comprises a series of k cascaded resistive-capacitive segments, each of which imposes an additional small delay unit on the sampled value 36 proportional to its RC constant. Imposing these small delay units via cascaded resistive-capacitive segments is more effective than accomplishing the same with a PLL or DLL using very high speed delay cells. Furthermore, because the delay is small, the distortion introduced by the delay can be ignored. Thus, one of k instances is taken between each of the k resistive-capacitive segments, each instance, therefore, being the sampled value 36 delayed by an increasing number of delay units. Each of the k instances is input into one of k drivers which comprise the parallel driver set circuit. The combination of all delayed sampled values is then applied to the respective resistor branch 39 having resistance m*R B .
- each of the k resistors likewise has a resistance of k*m*R B so as to form the parallel equivalent of the respective resistor branch 39 having resistance m*R B .
- each of the 8 instances (d 0 , d 1 . . . d 7 ) comprises the sampled value 36 delayed by an increasing number of delay units.
- the first instance, d 0 is the sampled value 36 delayed by one delay unit
- the second instance, d 1 is the sampled value 36 delayed by two delay units, and so on.
- the respective resistor branch 39 is driven with the summation of all 8 instances. As can been seen from FIG. 10 , such summation has a slower slew rate than any of the instances of the sampled value 36 .
- the magnitude of the delay unit P k may be tuned accordingly in order to smooth transient edges in the analog signal generated by analog signal output circuit 50 .
- the delay units are formed with a series of k cascaded resistive-capacitive segments, as in FIGS. 8 and 9 , the RC constant of those resistive-capacitive segments may be chosen to produce such a tuned delay unit P k .
- FIG. 11 shows a number of reconstruction curves where the magnitude of the delay unit P k has been tuned to different values.
- Tuning the delay unit P k to 0.5 also results in a reconstruction curve y 1 whose timing leads that of the reconstruction clock cycle of frequency fs (clock cycle 1 in FIG. 11 ).
- FIG. 12 illustrates one example of such a communication transceiver 70 .
- the communication transceiver 70 comprises a communication transmitter 71 , a duplexer 72 , an antenna 73 , a communication receiver 74 , and a baseband processor 75 .
- radio frequency signals are received from the antenna 73 via the duplexer 72 which provides filter functions and isolates the received signals 76 and the transmitted signals 77 .
- the received signals 76 are input into the communication receiver 74 , which comprises a low noise amplifier (LNA) 78 , an IQ demodulator 79 , and a low pass filter (LPF) 80 , variable gain amplifier (VGA) 81 , and an analog-to-digital converter (ADC) 82 for each of the I and Q channels.
- LNA low noise amplifier
- VGA variable gain amplifier
- ADC analog-to-digital converter
- the baseband processor 75 creates baseband communication signals 83 , e.g., streams of digital n-bit words at a baseband clock rate or frequency, and feeds each of these signals 83 to the communication transmitter 71 .
- the communication transmitter 71 comprises a resistor network DAC 10 and a low pass filter (LPF) 85 for each of the I and Q channels, an IQ modulator 86 , a variable gain amplifier (VGA) 87 , and a power amplifier (PA) 88 .
- LPF low pass filter
- Each of the resistor network DACs 10 within the communication transmitter 71 receives one of the baseband communication signals 83 .
- the resistor network DACs 10 are configured to convert baseband communication signals 83 into analog signals 84 .
- the resistor network DACs 10 use linear interpolation to move the reconstruction errors of the analog signals 84 to a higher frequency while consuming less power than would be used for equivalent oversampling of the baseband communication signals 83 .
- the design requirements of any LPF 85 used to filter out these errors may be relaxed. Such relaxation permits, but does not require, the use of a LPF 85 whose filter transfer function is not sharp in the transition band.
- LPF 85 includes a current-mode LPF.
- Current mode modulation improves the linearity of the IQ modulator 86 , and thus, use of a CMLPF as the LPF 85 is preferred.
- the resistor network DACs 10 therefore enable high linearity and low noise modulation while consuming less power than the comparable conventional resistor network DACs.
- the resistor network DACs 10 are advantageously used to provide the analog signal 84 to a current-mode low-pass filter circuit 85 , for filtering in advance of current mode modulation.
- the baseband signals are thereafter up-converted to radio frequency signals in the IQ modulator 86 by multiplying with quadrature transmission clocks. These modulated radio frequency signals are then amplified by the VGA 87 and the PA 88 before being transmitted by the antenna 73 via the duplexer 72 .
Abstract
Description
- The present invention generally relates to resistor network digital-to-analog conversion methods and apparatus, and particularly relates to low power digital-to-analog conversion using linear interpolation therein.
- Digital-to-analog converters convert digital words into analog values, such as analog voltage values or analog current values. When the digital word consists of n bits, the corresponding analog value may be generated by applying progressive power of two weightings to each of the n bits.
- Conventional resistor network digital-to-analog converters use a network of resistor stages to apply the progressive weightings to each bit. Known resistor network digital-to-analog converters include, for example, binary weighted digital-to-analog converters and R/2R ladder digital-to-analog converters. These conventional resistor network digital-to-analog converters sample each bit at a reconstruction clock frequency, fs, and apply those sampled bit values to progressively weighted resistor stages. Each of these stages, however, introduces reconstruction error into the analog output signal in the form of both static error and transient error (e.g. noise spikes).
- Increasing fs has the advantage of moving these reconstruction errors introduced by the resistor network to a higher frequency, thereby relaxing the design requirements for filtering out those reconstruction errors. This increase, however, results in the digital-to-analog converter consuming more power. The higher power consumption may be unacceptable in low power applications, such as mobile communication devices.
- Methods and apparatus taught herein advantageously move reconstruction errors of a resistor network digital to analog converter (DAC) to frequencies outside the range of interest while consuming less power than would be required to obtain similar frequency shifting through an increase in the reconstruction clock. Instead of increasing the reconstruction clock frequency, the methods and apparatus taught herein subdivide each sampling clock cycle of the DAC into a number of phases.
- For at least one bit input of the DAC that is associated with a desired input resistor weight, the input bit value is sampled at each phase. Each of those sampled values is then applied to a respective resistor branch, and the parallel set of resistor branches forms the parallel equivalent of the desired input resistor weight for that bit input. Doing so effectively applies the bit value in weighted form to the resistor network in a step-wise, linear interpolation process that eliminates or reduces both the static and transient effects in the analog output signal associated with applying the bit value.
- In one or more embodiments, a resistor network DAC includes a set of bit input circuits, an analog signal output circuit, and a clocking circuit. The set of bit input circuits is configured to receive input bit values of an n-bit digital word. Each bit input circuit has an input sampling circuit configured to sample an input bit value according to clock signals of the clocking circuit and a driver circuit to apply the sampled value to an associated input resistor having a desired input resistor weight. The clocking circuit comprises a multi-phase clock generator configured to subdivide each sampling clock cycle of the DAC into a number of phases. For at least one bit input, the sampling circuit comprises a number of parallel sampling circuits configured to each sample the input bit value at a different one of those equally spaced phases. Likewise, the driver circuit within that bit input comprises a corresponding number of parallel driver circuits each configured to apply the corresponding sampled value to a respective resistor branch. Because the parallel combination of all respective resistor branches forms the equivalent of the desired input resistor weight for that bit input circuit, the desired contribution of that input bit value is spread over the entire sampling clock period. The analog signal output circuit is configured to generate the analog (output) signal as the resistor-weighted sum of all input bit values.
- Additionally or alternatively, one or more method and apparatus embodiments presented herein apply each sampled value to its respective resistor branch via a slew-rate controlled driver, to smooth the analog signal transient edges at the output nodes of the resistor network. That is, the bit inputs that are configured as multi-phase bit inputs use slew-rate controlled drivers for the sampled values, to further smooth output signal transient edges. Such slew-rate controlled drivers may comprise a current-mirror circuit tied to a slew-rate limiting current source. Alternatively, the slew-rate controlled drivers may each comprise a delay circuit configured to generate a number of instances of the sampled value, each instance being the sampled value delayed by an increasing number of delay units, and a parallel driver set circuit, each driver within the set having its input driven by a different one of those instances.
- In another embodiment taught herein, the resistor network DAC comprises part of a communication transmitter and is configured to convert a baseband communication signal into an analog signal. The resistor network DAC may be further configured to provide the analog signal to a current-mode low-pass filter circuit, for filtering in advance of current mode modulation.
- Of course, the present invention is not limited to the above features and advantages. Indeed, those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.
-
FIG. 1 is a block diagram illustrating one embodiment of a resistor network digital-to-analog converter of the present invention. -
FIG. 2 is a logic flow diagram illustrating one embodiment of a resistor network digital-to-analog converter of the present invention. -
FIGS. 3A and 3B are schematic diagrams of example embodiments of the bit input circuits for the resistor network digital-to-analog converter ofFIG. 1 . -
FIG. 4 is a waveform diagram comparing a conventional reconstructed analog waveform without linear-interpolation error reduction to a reconstructed analog waveform with linear-interpolation error reduction as provided by the resistor network digital to analog converter ofFIG. 1 . -
FIG. 5 is a schematic diagram of one embodiment of slew-rate controlled drivers, each comprising a current-mirror circuit tied to a slew-rate limiting current source. -
FIG. 6 is a waveform diagram similar to that shown inFIG. 4 , but where the reconstructed analog waveform with linear-interpolation error reduction is further improved through the use of the slew-rate controlled drivers ofFIG. 5 . -
FIG. 7 is a block diagram of another embodiment of slew-rate controlled drivers, each comprising a delay circuit and a parallel driver set circuit. -
FIG. 8 is a schematic diagram for one embodiment of the delay circuits and parallel driver set circuits for the slew-rate controlled drivers ofFIG. 7 . -
FIG. 9 is a schematic diagram of another embodiment of the delay circuits and parallel driver circuits for the slew-rate controlled drivers ofFIG. 7 . -
FIG. 10 is a waveform diagram depicting the generation of delayed instances of a sampled bit input value according to the delay circuit ofFIG. 7 and the combination of those delayed instances according to the parallel driver set circuit ofFIG. 7 . -
FIG. 11 is a waveform diagram for the reconstruction curves for various tuning of the delay units in the slew-rate controlled drivers ofFIG. 7 . -
FIG. 12 is a block diagram illustrating one embodiment of the resistor network digital to analog converter ofFIG. 1 as applied to a communication transmitter. -
FIG. 1 illustrates one embodiment of a resistor network digital-to-analog converter (DAC) 10, which receives an n-bit digital word and generates an analog signal representation thereof. Theresistor network DAC 10 includes a set ofbit inputs circuits clocking circuit 40, and an analogsignal output circuit 50. - The set of
bit inputs circuits bit input circuit input sampling circuit driver circuit input resistor - The contributions of all
bit input circuits signal output circuit 50. The analogsignal output circuit 50 is configured to generate an analog signal as the sum of the resistor-weighted input bit values of eachbit input circuit - In order to sample those input bit values, each
input sampling circuit clocking circuit 40. Theclocking circuit 40 comprises amulti-phase clock generator 42 configured to subdivide each sampling clock cycle of theresistor network DAC 10 into m phases (Ck0, Ck1 . . . Ckm-1) at reconstruction clock frequency fs. The phase difference or delay, Pm, between two successive phases is Ps/m, where Ps equals the clock period of the reconstruction clock fs. - The bit input circuit(s) 20 are single-phase circuits clocked, e.g., by one of the m clock signals Cki (i=0,1 . . . m-1), or by another clock signal at the reconstruction clock frequency fs. In contrast, the bit input circuit(s) 30 are multi-phase bit input circuits that are clocked by some or all of the m clock signals, CK, each at a different phase. For each
bit input circuit 30, thesampling circuit 32 comprises mparallel sampling circuits 33 configured to each sample the corresponding input bit value at a different one of the m phases (Ck0, Ck1 . . . Ckm-1). Thesampling circuit 32, therefore, generates m sampled values 36, each of which represents the corresponding input bit value sampled at a different equally spaced phase or time interval. Each of these m sampledvalues 36 serves as an input into a different one of mparallel driver circuits 35 within thedriver circuit 34. Theparallel driver circuits 35 are configured to each apply a sampledvalue 36 to arespective resistor branch 39 within the associatedinput resistor 38. - Because each sampled
value 36 represents the corresponding input bit value during a successive time interval, such operation has the effect of cumulatively applying during successive time intervals the corresponding input bit value to therespective resistor branches 39. The parallel combination of theserespective resistor branches 39 forms the equivalent of the desired input resistor weight RB of the associatedinput resistor 38. Thus, the corresponding input bit value is applied to a portion of the desired input resistor weight RB during successive time intervals and the desired contribution of the input bit value is spread linearly over the entire sampling clock period. Such linear interpolation effectively increases the frequency of amplitude transitions in the analog output signal so as to shift the reconstruction error due to the at least onebit input circuit 30 into a frequency outside the range of interest, specifically m*fs. Advantageously, shifting the reconstruction error to frequency m*fs in this manner consumes less power than oversampling at that same frequency. - Those skilled in the art will appreciate that the
resistor network DAC 10 may be implemented with such linear interpolation as described above for any number of its bit inputs, e.g., any mix of single-phasebit input circuits 20 and multi-phasebit input circuits 30 can be used. For example, bitinput circuits 30 can be used for all n bit inputs. In practice, though, the least significant bit inputs contribute little to the reconstruction errors within the analog signal output. Thus, usingbit input circuits 30 for the least significant bits may be unnecessary for those applications which tolerate at least minimal reconstruction errors. - For the least significant bit
input circuits 20 which may receive only a single clock signal Cki, i=0,1, . . . , m-1, thesampling circuit 22 only samples its corresponding input bit value at one of the m phases, Cki, thereby generating the sampledvalue 26. Whilesampling circuit 22 may use any of these m phases to sample the input bit value, use of i=m/2 can reduce the small time introduced error. Regardless of the phase at which the sampledvalue 26 is generated, though, thedriver circuit 24 within eachbit input circuit 20 is configured to apply that sampledvalue 26 to the associatedinput resistor 28 having the desired input resistor weight RA. Thus, the corresponding input bit value is applied to the desired input resistor weight RA all at once and the desired contribution of the input bit value occurs entirely at the beginning of the sampling clock period. - Regardless of the application, however, it should be noted that the desired input resistor weights RA, RB, as well as the bridge resistors Rs and the termination resistor RT, may depend on the type of
resistor network DAC 10 being implemented. For example, where theresistor network DAC 10 comprises an R/2R ladder DAC the bridge resistors Rs may couple adjacentbit input circuits resistor network DAC 10 comprises a binary weighted resistor DAC, the input resistor binary weight RA of least significant bits is desired to be 2i times greater than the input resistor binary weight RB corresponding to the bit i, where i=1,2, . . . , n-1, and the bridge resistors Rs may not contribute any series resistance, i.e, Rs=0. The termination resistor Rt connected at the bridge node of the least significant bit is infinitive large in the case of binary weighted resistor implementation. - Whether the
resistor network DAC 10 comprises an R/2R ladder DAC or a binary weighted resistor DAC, however, theresistor network DAC 10 implements a method of converting a digital signal into an analog signal, an example of which is given inFIG. 2 . The illustrated conversion “begins” with theresistor network DAC 10 receiving input bit values of an n-bit digital word on the set ofbit input circuits 20, 30 (Block 100). Themultiphase clock generator 42 subdivides each sampling clock cycle of theclocking circuit 40 into m phases (Block 110), and thesampling circuit 32 of eachbit input circuit 30 samples the respective input bit value at each of the m phases (Block 120). For each of those sampledvalues 36, aparallel driver circuit 35 applies the sampledvalue 36 to arespective resistor branch 39 in a parallel set ofresistor branches 39 that form the parallel equivalent of the desired input resistor weight RB for that at least one bit input circuit 30 (Block 130). That is, each sampled value is applied at a respective one of the clock phases, which effectively results in the overall contribution of the input bit value being accumulated incrementally over the reconstruction frequency clock period. The overall conversion operation includes the analogsignal output circuit 50 generating the analog signal by summing the resistor weighted sampled values for all bitinput circuits 20, 30 (Block 140). - In order for the analog
signal output circuit 50 to sum the resistor weighted sampled values in such a manner, the analogsignal output circuit 50 may comprise, for example, a summer circuit consisting of either an operational amplifier using feedback for a unity gain, or just a resistor for providing a voltage output in the case that output current equals zero. Alternatively, the output of thebit input circuits signal output circuit 50 may simply connect these outputs together without the use of an operational amplifier or any resistance. Those skilled in the art will appreciate, however, that other summer circuits may also be used to add the resistor weighted sampled values. - Those skilled in the art will also appreciate various implementations of the
multiphase clock generator 42 used to subdivide each sampling clock cycle of clockingcircuit 40 into m phases. A delay locked loop (DLL), or a phase locked loop (PLL), for example, can be employed to create these m phases at reconstruction clock frequency fs. Alternatively, a clock at frequency of m*fs may be used and the m phases at frequency fs generated using divide-by-m. - Example implementations of the
bit input circuits FIGS. 3A and 3B . It should be understood that these detailed examples are non-limiting illustrations of physical and/or functional circuit arrangements offering advantageous operation in certain applications. -
FIG. 3A illustrates one example of an implementation of a least significant bitinput circuit 20. As thebit input circuit 20 receives only a single clocking signal Cki from theclocking circuit 40, a single delay flip-flop, DFF, is used as thesampling circuit 22. The DFF latches the input bit value (Bit 1) into memory on the trig (rising/falling) edge of Cki and holds that sampledvalue 26 for the entire sampling clocking cycle. Therefore, upon the rising edge of Cki and for the remainder of the sampling clock cycle, a buffer, BUFF, within thedriver circuit 24 applies that sampledvalue 26 to the associatedinput resistor 28. The associatedinput resistor 28 comprises a single resistor representing the entire desired input resistor weight RA for thebit input circuit 20. Thus, as mentioned previously, the buffer, BUFF, applies the entire desired contribution of the input bit value (Bit 1) at the beginning of and throughout the sampling clock period. - In the example implementation of a multi-phase
bit input circuit 30, which is advantageously used for one or more of the most significant input bits, on the other hand,FIG. 3B illustrates how thebit input circuit 30 linearly spreads the desired contribution of the input bit value over the sampling clock period. Thebit input circuit 30 receives m clock signals CK offset in phase into the mparallel sampling circuits 33, each of which comprise one of m delay flip-flops (DFF0, DFF1 . . . DFFm-1). Each of the m DFFs latches the input bit value (Bitn-1) into its respective memory on the trig edge of its respective clock signal and holds that sampledvalue 36 until clocked again. These sampled values 36 are applied to arespective resistor branch 39 via one of the mparallel driver circuits 35, which comprises m buffers (BUFF0, BUFF1 . . . BUFFm-1). Them resistor branches 39 likewise comprise m resistors, each with a resistance of m*RB so that the parallel equivalent of the m resistors equals the desired input resistor weight RB. Thus, the input bit value (Bitn-1) is applied to each of the m resistors, representing a portion of the desired input resistor weight RB, during successive time intervals. - The advantages of the resulting analog signal generated by such a
resistor network DAC 10 having bit inputcircuits 30 are illustrated inFIG. 4 . Plotted withinFIG. 4 is an original analog signal x1, the reconstructed analog signal x2 generated by a conventional resistor network DAC with reconstruction frequency fs, and the reconstructed analog signal x3 generated by the above-describedresistor network DAC 10 also at fs. A conventional resistor network DAC outputs a reconstructed analog signal x2 with large steps at the beginning of each clock cycle, resulting in relatively large reconstruction errors within the frequency band of interest. - In contrast, the reconstructed analog signal x3 depicts the output of the above-described
resistor network DAC 10. One sees that the incremental, multi-phase application of one or more of the most significant input bit values reduces the reconstruction error at any given time instant, and, furthermore, maps such errors into a higher frequency, m*fs. - Yet in order to further reduce the reconstruction errors introduced into the reconstructed analog signal, the
parallel driver circuits 35 may comprise parallel slew-rate controlleddriver circuits 35. These parallel slew-rate controlleddriver circuits 35 are further configured to each smooth transient edges in the generated analog output signal. -
FIG. 5 illustrates one example of such an embodiment having parallel slew-rate controlleddriver circuits 35. Thebit input circuit 30 shown inFIG. 5 essentially imitates that previously described inFIG. 3B , with the exception that theparallel driver circuits 35 each comprise an inverter circuit (INV0, INV1 . . . INVm-1) coupled to a current-mirror circuit, CM, tied to a slew-rate limiting current source, IC. - As shown in
FIG. 5 , the current-mirror circuit CM is connected to each of transistors Tps0, Tps1 . . . Tpsm-1 and Tns0, Tns1 . . . Tnsm-1 so as to mirror the slew-rate limiting current IC through each of the inverting buffers (INV0, INV1 . . . INVm-1) comprised of transistors (Tp0, Tn0), (Tp1, Tn1) . . . (Tpm-1, Tnm-1). In operation, then, the slew-rate limiting current source, IC, limits the rate at which a sampledvalue 36 may be applied by each inverting buffer (INV0, INV1 . . . INVm-1) to aresistor branch 39. - For example, when the sampled
value 36 as output from DFF0 changes from low to high, such change occurs at a given slew rate. Upon such a change, the high voltage at the output of the inverting buffer INV0 discharges the capacitance on the output node through transistor Tn0 as well as transistor Tns0. The capacitance includes all parasitic capacitances in output nodes, like device parasitic capacitance and routing parasitic capacitance. The slew-rate at which that output is pulled down toward ground, however, is limited by the value of IC which is mirrored in Tns0. Thus, the output of the inverting buffer INV0 will change from high to low at an independent slew rate which is controlled by the magnitude of the current source IC. Those skilled in the art, then, will appreciate that the magnitude of the slew-rate limiting current source IC may be tuned accordingly in order to reduce transients in the analog signal output by analogsignal output circuit 50. - Even absent such tuning, however,
FIG. 6 illustrates the additional advantages of such aresistor network DAC 10 having the above-described parallel slew-rate controlleddriver circuits 35. The plot ofFIG. 6 essentially imitates that previously described inFIG. 4 , except for the addition of the reconstructed analog signal, x4, generated by aresistor network DAC 10 having parallel slew-rate controlleddriver circuits 35. Thisresistor network DAC 10 outputs a reconstructed analog signal x4 similar to that of x3, but with a slower slew rate. Such results in even smaller reconstruction errors while still mapping these errors into a higher frequency. - Furthermore, these same advantages may be obtained from the alternative embodiment of
FIG. 7 which illustrates an alternativeresistor network DAC 10 comprising parallel slew-rate controlleddriver circuits 35. Again, thebit input circuit 30 shown inFIG. 7 essentially imitates that previously described inFIG. 3B , with the exception that theparallel driver circuits 35 each comprise a delay circuit and a parallel driver set circuit. - In
FIG. 7 , the delay circuit within eachparallel driver circuit 35 is configured to generate k instances (d0, d1 . . . dk-1) of the sampledvalue 36, each instance being the sampledvalue 36 delayed by an increasing number of delay units. A delay unit may have a delay, for example, of Pk=Ps/(mk)=Pm/k. The parallel driver set circuit within eachparallel driver circuit 35 itself comprises a parallel set of drivers, each such driver having its input driven by a different one of the instances (d0, d1 . . . dk-1). - Those skilled in the art will appreciate that the above-described delay circuit and parallel driver set circuit may be implemented in a variety of ways.
FIGS. 8 and 9 , however, illustrate two such implementations. - In
FIG. 8 , the delay circuit comprises a series of k cascaded resistive-capacitive segments, each of which imposes an additional small delay unit on the sampledvalue 36 proportional to its RC constant. Imposing these small delay units via cascaded resistive-capacitive segments is more effective than accomplishing the same with a PLL or DLL using very high speed delay cells. Furthermore, because the delay is small, the distortion introduced by the delay can be ignored. Thus, one of k instances is taken between each of the k resistive-capacitive segments, each instance, therefore, being the sampledvalue 36 delayed by an increasing number of delay units. Each of the k instances is input into one of k drivers which comprise the parallel driver set circuit. The combination of all delayed sampled values is then applied to therespective resistor branch 39 having resistance m*RB. - Alternatively, in
FIG. 9 , all delayed sampled values are first applied to a parallel set of k resistors before being combined. Each of the k resistors likewise has a resistance of k*m*RB so as to form the parallel equivalent of therespective resistor branch 39 having resistance m*RB. - When k=8 in either of these implementations, the result of imposing the sampled
value 36 to a delay circuit and a parallel driver set circuit can be seen inFIG. 10 for two clock cycles. Each of the 8 instances (d0, d1 . . . d7) comprises the sampledvalue 36 delayed by an increasing number of delay units. For example, the first instance, d0, is the sampledvalue 36 delayed by one delay unit, the second instance, d1, is the sampledvalue 36 delayed by two delay units, and so on. When each of these instances serves as the input into one of the drivers within the parallel set of drivers, therespective resistor branch 39 is driven with the summation of all 8 instances. As can been seen fromFIG. 10 , such summation has a slower slew rate than any of the instances of the sampledvalue 36. - Those skilled in the art will appreciate that the magnitude of the delay unit Pk may be tuned accordingly in order to smooth transient edges in the analog signal generated by analog
signal output circuit 50. Where the delay units are formed with a series of k cascaded resistive-capacitive segments, as inFIGS. 8 and 9 , the RC constant of those resistive-capacitive segments may be chosen to produce such a tuned delay unit Pk. - To illustrate the effects of such tuning,
FIG. 11 shows a number of reconstruction curves where the magnitude of the delay unit Pk has been tuned to different values. With a normalized delay unit Pk=0.5, the resulting reconstruction curve y1 experiences non-linearity with steps occurring within each clock cycle of frequency m*fs(here m=4). Tuning the delay unit Pk to 0.5 also results in a reconstruction curve y1 whose timing leads that of the reconstruction clock cycle of frequency fs (clock cycle 1 inFIG. 11 ). Optimal timing and linearity, however, may be acquired with a normalized delay unit Pk=1.0 as can be seen in the resulting reconstruction curve y2. No such steps occur within the clock cycle and the timing of the curve y2 matches that of the reconstruction clock cycle. Increasing the normalized delay unit Pk to 1.5, however, results in a reconstruction curve y3 whose timing lags that of the reconstruction clock cycle.FIG. 11 demonstrates, then, that the reconstruction curve resulting from a normalized delay unit within a small margin of 1.0 (e.g. 0.8 to 1.2) is acceptable for most applications. - One application of the above-described low power
resistor network DAC 10 includes wireless mobile communications, where power consumption considerations play a large role in the design of communication transceivers.FIG. 12 illustrates one example of such acommunication transceiver 70. Thecommunication transceiver 70 comprises acommunication transmitter 71, aduplexer 72, anantenna 73, acommunication receiver 74, and abaseband processor 75. - In
FIG. 12 , radio frequency signals are received from theantenna 73 via theduplexer 72 which provides filter functions and isolates the received signals 76 and the transmitted signals 77. The received signals 76 are input into thecommunication receiver 74, which comprises a low noise amplifier (LNA) 78, anIQ demodulator 79, and a low pass filter (LPF) 80, variable gain amplifier (VGA) 81, and an analog-to-digital converter (ADC) 82 for each of the I and Q channels. Once received by thecommunication receiver 74, the received signals 76 are amplified by the low noise amplifier (LNA) 78, and are directly down-converted into baseband signals by theIQ demodulator 79. Each of the baseband I and Q channels are passed through aLPF 80,VGA 81, and anADC 82 before being input into thebaseband processor 75. - On the transmission side, the
baseband processor 75 creates baseband communication signals 83, e.g., streams of digital n-bit words at a baseband clock rate or frequency, and feeds each of thesesignals 83 to thecommunication transmitter 71. Thecommunication transmitter 71 comprises aresistor network DAC 10 and a low pass filter (LPF) 85 for each of the I and Q channels, anIQ modulator 86, a variable gain amplifier (VGA) 87, and a power amplifier (PA) 88. - Each of the
resistor network DACs 10 within thecommunication transmitter 71 receives one of the baseband communication signals 83. As described above, theresistor network DACs 10 are configured to convert baseband communication signals 83 into analog signals 84. Unlike conventional resistor network DACs, however, theresistor network DACs 10 use linear interpolation to move the reconstruction errors of the analog signals 84 to a higher frequency while consuming less power than would be used for equivalent oversampling of the baseband communication signals 83. With the reconstruction errors of the analog signals 84 at a higher frequency, the design requirements of anyLPF 85 used to filter out these errors may be relaxed. Such relaxation permits, but does not require, the use of aLPF 85 whose filter transfer function is not sharp in the transition band. - One non-limiting example of such a
LPF 85, the use of which is permitted by theresistor network DACs 10, includes a current-mode LPF. The co-pending and commonly owned U.S. patent application identified by application Ser. No. 12/210,483, filed on 15 Sep. 2008 and entitled “Method and Apparatus for Tunable Current-Mode Filtering,” discloses useful examples of current-mode filter circuits, some set in communication transmitter contexts. - While at least some CMLPF circuits have relatively poor attenuation in their transition bands, they advantageously provide current output with low noise, and therefore, permit use of current-mode modulation in the
IQ Modulator 86. Current mode modulation improves the linearity of theIQ modulator 86, and thus, use of a CMLPF as theLPF 85 is preferred. Theresistor network DACs 10 therefore enable high linearity and low noise modulation while consuming less power than the comparable conventional resistor network DACs. As such, theresistor network DACs 10 are advantageously used to provide theanalog signal 84 to a current-mode low-pass filter circuit 85, for filtering in advance of current mode modulation. - Regardless of the type of
LPF 85, however, the baseband signals are thereafter up-converted to radio frequency signals in theIQ modulator 86 by multiplying with quadrature transmission clocks. These modulated radio frequency signals are then amplified by theVGA 87 and thePA 88 before being transmitted by theantenna 73 via theduplexer 72. - However, it should be understood that the foregoing description and the accompanying drawings represent non-limiting examples of the methods and individual apparatuses taught herein. As such, the present invention is not limited by the foregoing description and accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.
Claims (24)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/254,441 US7714759B1 (en) | 2008-10-20 | 2008-10-20 | Low power linear interpolation digital-to-analog conversion |
PCT/EP2009/062939 WO2010046228A1 (en) | 2008-10-20 | 2009-10-06 | Low power linear interpolation digital-to-analog conversion |
ES09783766T ES2391810T3 (en) | 2008-10-20 | 2009-10-06 | Digital to analog conversion with low power linear interpolation |
EP09783766A EP2342827B1 (en) | 2008-10-20 | 2009-10-06 | Low power linear interpolation digital-to-analog conversion |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/254,441 US7714759B1 (en) | 2008-10-20 | 2008-10-20 | Low power linear interpolation digital-to-analog conversion |
Publications (2)
Publication Number | Publication Date |
---|---|
US20100097253A1 true US20100097253A1 (en) | 2010-04-22 |
US7714759B1 US7714759B1 (en) | 2010-05-11 |
Family
ID=41572594
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/254,441 Expired - Fee Related US7714759B1 (en) | 2008-10-20 | 2008-10-20 | Low power linear interpolation digital-to-analog conversion |
Country Status (4)
Country | Link |
---|---|
US (1) | US7714759B1 (en) |
EP (1) | EP2342827B1 (en) |
ES (1) | ES2391810T3 (en) |
WO (1) | WO2010046228A1 (en) |
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US10224950B2 (en) | 2015-05-29 | 2019-03-05 | Reinet S.A.R.L. | Digital to analogue conversion |
US10128863B2 (en) * | 2017-03-20 | 2018-11-13 | Silanna Asia Pte Ltd | Resistor-based configuration system |
WO2020205094A1 (en) * | 2019-03-29 | 2020-10-08 | Intel Corporation | Digital-to-analog converter, transmitter and mobile device |
US11750209B2 (en) | 2019-03-29 | 2023-09-05 | Intel Corporation | Digital-to-analog converter, transmitter and mobile device |
WO2021133373A1 (en) * | 2019-12-23 | 2021-07-01 | Intel Corporation | Digital-to-analog converter, digital-to-analog conversion system, electronic system, base station and mobile device |
Also Published As
Publication number | Publication date |
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WO2010046228A1 (en) | 2010-04-29 |
EP2342827A1 (en) | 2011-07-13 |
EP2342827B1 (en) | 2012-07-18 |
US7714759B1 (en) | 2010-05-11 |
ES2391810T3 (en) | 2012-11-30 |
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