US20100001288A1 - Low Etch Pit Density (EPD) Semi-Insulating GaAs Wafers - Google Patents
Low Etch Pit Density (EPD) Semi-Insulating GaAs Wafers Download PDFInfo
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- US20100001288A1 US20100001288A1 US12/506,209 US50620909A US2010001288A1 US 20100001288 A1 US20100001288 A1 US 20100001288A1 US 50620909 A US50620909 A US 50620909A US 2010001288 A1 US2010001288 A1 US 2010001288A1
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- 229910001218 Gallium arsenide Inorganic materials 0.000 title claims abstract description 34
- 235000012431 wafers Nutrition 0.000 title abstract description 39
- 238000000034 method Methods 0.000 claims abstract description 54
- 239000013078 crystal Substances 0.000 claims abstract description 28
- 238000000137 annealing Methods 0.000 claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 29
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 10
- 229910052733 gallium Inorganic materials 0.000 claims description 10
- 230000007547 defect Effects 0.000 claims description 9
- 239000000155 melt Substances 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 239000002245 particle Substances 0.000 claims description 5
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 238000001816 cooling Methods 0.000 claims description 3
- 238000002425 crystallisation Methods 0.000 claims description 3
- 230000008025 crystallization Effects 0.000 claims description 3
- 229910005540 GaP Inorganic materials 0.000 claims 2
- 239000003708 ampul Substances 0.000 description 10
- 239000002019 doping agent Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 239000002994 raw material Substances 0.000 description 3
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010494 dissociation reaction Methods 0.000 description 1
- 230000005593 dissociations Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B11/00—Single-crystal growth by normal freezing or freezing under temperature gradient, e.g. Bridgman-Stockbarger method
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
- C30B29/42—Gallium arsenide
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
- C30B33/02—Heat treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3228—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of AIIIBV compounds, e.g. to make them semi-insulating
Definitions
- a method for manufacturing low etch pit density (EPD) GaAs wafers that can be used to manufacture Heterostructure Bipolar Transistors (HBT) and pseudo-morphic High Electron Mobility (pHEMT) devices is provided.
- EPD etch pit density
- HBT Heterostructure Bipolar Transistors
- pHEMT pseudo-morphic High Electron Mobility
- GaAs Gallium Arsenide
- EPD etch pit density
- Wafer annealing is well known.
- ingot annealing is known as described in “Improved Uniformity of LEC Undoped Gallium Arsenide Produced by High Temperature Annealing” by Rumsby et al., GaAs IC Symposium, pp. 34-37 (1983).
- VGF vertical gradient freeze
- FIG. 1 illustrates a method for fabricating GaAs wafers using a vertical growth furnace process
- FIG. 2 illustrates an EPD map for an exemplary wafer.
- the method is particularly applicable to manufacturing a GaAs substrate and it is in this context that the method will be described. It will be appreciated, however, that the method has greater utility since it can be used, for example, to manufacture other types of substrates, such as indium phosphide (InP), gallium phosphide (GaP) and other related III-V compound semiconductors.
- substrates such as indium phosphide (InP), gallium phosphide (GaP) and other related III-V compound semiconductors.
- FIG. 1 illustrates a method for fabricating GaAs wafers using a vertical growth furnace process 100 .
- the process results in low light point defect, low etch pit density GaAs substrates.
- This process may also be used to fabricate indium phosphide (InP), gallium phosphide (GaP) or other related III-V compound semiconductors.
- the fabrication method is a combination of a very low EPD crystal growth process (described below in more detail) and a wafer annealing process (described in more detail below) to achieve the very low EPD and very low light point defects (LPD) wafers.
- the growth of very low EPD, semi-insulating GaAs wafers by the VGF process results in high device yield in highly integrated GaAs circuits.
- the wafer annealing process yields very low LPD and a controlled level of Oxygen in the wafers.
- the low LPD wafers are desired by all semiconductor epitaxial growers since higher LPDs result in lower device yields from the substrates with the higher LPDs due to failure of devices made with the higher LPD substrate.
- raw Arsenide (As) and Gallium (Ga) are obtained ( 102 ) and testing may be performed on the raw materials ( 103 ). Once the raw materials are tested, a known poly synthesis process ( 104 ) is used to produce polycrystalline GaAs which may then be tested ( 105 ). Once the polycrystalline GaAs is generated, vertical gradient freeze (VGF) crystal growth occurs ( 106 ) as described in more detail in U.S. Pat. No. 6,896,729 to Liu et al. which is incorporated herein by reference.
- VVF vertical gradient freeze
- VGF fabrication according to the present innovations encompass crystal growth technology, apparatus, and processes whereby large single crystal ingots are grown with a very high level of structural uniformity and low defect density.
- controlled growth of GaAs is achieved by placing a dopant material in an ampoule outside a growth crucible, not in contact with the molten charge. Since the dopant materials are separated from the melt or the internal wall of the crucible, the process is favorable for achieving a high single crystal growth yield.
- Exemplary VGF processes for achieving controlled incorporation of carbon in the growth of semi-insulating GaAs material may include: (1) loading charges of GaAs raw materials into the crucible, (2) placing carbon doping sources within, generally at a low end of, the ampoule, (3) loading the crucible with the GaAs charges into the ampoule, (4) evacuating/sealing under vacuum the ampoule containing the dopant, the crucible, the GaAs charges, and B2O3 material, and (5) heating/melting the charge and then controlling the liquid-solid interface, wherein control of the amount of the dopant and/or the temperature are used to grow semi-insulating GaAs ingots with high uniformity and low defects.
- the VGF grown crystals may be tested ( 107 ).
- an etch pin density of less than 900/cm 2 In testing, the process has achieved an EPD as low as 600/cm 2 for 3′′ diameter GaAs wafers.
- There are conventional processes that can produce low EPD GaAs substrates as low as 900/cm 2 however none of the conventional processes can produce GaAs or other similar wafers at less than 900/cm 2 .
- typical processes may achieve an EPD of 900/cm 2 , but cannot achieve the lower EPD levels provided by the VGF process.
- the parameters may include the shape of the melt/crystal interface which is controlled to be concave or convex to the melt front at ⁇ 2 mm, crystallization velocity from 2-16 mm/hour, the temperature gradient at the melt/crystal interface between 0.1 to 2 degrees C. and/or a total temperature gradient of between 1 to 4 degrees C.
- a well known ingot shaping process ( 108 ) is conducted and the shaped ingot may also be tested ( 109 ).
- the ingot is sliced into wafers ( 110 ) and the wafers may be optionally tested ( 111 ).
- the above processes may also be used to product InGaP wafers. As a result of this process, low EPD GaAs/InGaP wafers are produced.
- a wafer annealing process ( 112 ) is performed wherein the annealed wafers may be tested ( 113 ).
- a one-stage annealing process is used. During that process the wafers are loaded vertically into a horizontal quartz boat and inserted in a horizontal quartz ampoule along with the required Arsenic lumps. These Arsenic lumps are carefully weighed to provide the needed vapor pressure at the annealing temperature to avoid any Arsenic dissociation from the substrates. The ampoule is then pumped down to a high vacuum level ( ⁇ 5E-3 Torr) and sealed.
- the ampoule and its contents are then inserted into a horizontal 3-zone furnace and the heating of the ampoule and its contents to the desired set (platform) temperature is initiated.
- the platform temperature 900 C to 1050 C
- the heating is decreased and the ampoule is allowed to cool down to room temperature within a set time (6 to 24 hrs).
- the oxygen level in the GaAs wafers is controlled by adjusting the vacuum level in the ampoule
- the annealing process conditions were optimized for heating rate, platform temperature and cooling rate to achieve very low LPD levels ( ⁇ 1/cm2).
- the wafer has light point defects as low as ⁇ 1/cm2 with particle size >0.3 ⁇ m.
- the wafer may have as low as ⁇ 120 particles/wafer, particle size >0.3 ⁇ m for 6′′ wafers.
- a known wafer polishing process ( 114 ) is performed that polishes the low EPD wafers and the polished wafers may be optionally tested ( 115 ). Once the wafers are polished, the wafers are cleaned ( 116 ) and optionally tested ( 117 ) and then packaged for shipping to customers ( 118 ).
- the EPD measurements are performed in accordance with SEMI M36-0699 and ASTM Test Method F1404-92.
- An example of the EPD level as measured at 37 points (each point having an area of 0.024 cm2) is shown in FIG. 2 .
- This example shows an average EPD of 695/cm2. Note that the EPD is not evenly distributed across the wafer and for this sample, the maximum EPD is 1167/cm2. All the numbers shown in FIG. 2 are actual counts of the number of EPDs—to obtain the EPD value, these numbers should be divided by the unit area (namely, 0.024 cm 2 ) to obtain the number per cm 2 .
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- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Inorganic Chemistry (AREA)
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Abstract
A method for manufacturing wafers using a low EPD crystal growth process and a wafer annealing process is provided that results in GaAs/InGaP wafers that provide higher device yields from the wafer.
Description
- This is a continuation of application Ser. No. 11/801,712, filed May 9, 2007, published as US2008/0280427A1, now U.S. Pat. No. 7,566,641, which are incorporated herein by reference in entirety.
- 1. Field
- A method for manufacturing low etch pit density (EPD) GaAs wafers that can be used to manufacture Heterostructure Bipolar Transistors (HBT) and pseudo-morphic High Electron Mobility (pHEMT) devices is provided.
- 2. Description of Related Information
- It is well known in the Gallium Arsenide (GaAs) industry that a etch pit density (EPD) level of a substrate is very important in minority carrier device reliability and in the yield of devices from the substrate. However, in GaAs electronic devices, such as hetero-structure bipolar transistors (HBTs) and pseudomorphic high electron mobility transistors (pHEMTs), substrate EPD is not known to be a determining factor in device yield.
- Wafer annealing is well known. In addition, ingot annealing is known as described in “Improved Uniformity of LEC Undoped Gallium Arsenide Produced by High Temperature Annealing” by Rumsby et al., GaAs IC Symposium, pp. 34-37 (1983).
- Techniques for growing semiconductor crystals using a vertical gradient freeze (VGF) and carbon doping are known, such as those disclosed in U.S. Pat. No. 6,896,729 to Liu et al. It is desirable to provide a method for manufacturing low etch pit density (EPD) InGaP and GaAs wafers using annealing and VGF and it is to this end that the present invention is directed.
- The accompanying drawings, which constitute a part of this specification, illustrate various implementations and aspects of the present invention and, together with the description, explain principles consistent with the innovations herein. In the drawings:
-
FIG. 1 illustrates a method for fabricating GaAs wafers using a vertical growth furnace process; and -
FIG. 2 illustrates an EPD map for an exemplary wafer. - The method is particularly applicable to manufacturing a GaAs substrate and it is in this context that the method will be described. It will be appreciated, however, that the method has greater utility since it can be used, for example, to manufacture other types of substrates, such as indium phosphide (InP), gallium phosphide (GaP) and other related III-V compound semiconductors.
-
FIG. 1 illustrates a method for fabricating GaAs wafers using a vertical growth furnace process 100. The process results in low light point defect, low etch pit density GaAs substrates. This process may also be used to fabricate indium phosphide (InP), gallium phosphide (GaP) or other related III-V compound semiconductors. The fabrication method is a combination of a very low EPD crystal growth process (described below in more detail) and a wafer annealing process (described in more detail below) to achieve the very low EPD and very low light point defects (LPD) wafers. The growth of very low EPD, semi-insulating GaAs wafers by the VGF process results in high device yield in highly integrated GaAs circuits. The wafer annealing process yields very low LPD and a controlled level of Oxygen in the wafers. The low LPD wafers are desired by all semiconductor epitaxial growers since higher LPDs result in lower device yields from the substrates with the higher LPDs due to failure of devices made with the higher LPD substrate. - Returning to
FIG. 1 , raw Arsenide (As) and Gallium (Ga) are obtained (102) and testing may be performed on the raw materials (103). Once the raw materials are tested, a known poly synthesis process (104) is used to produce polycrystalline GaAs which may then be tested (105). Once the polycrystalline GaAs is generated, vertical gradient freeze (VGF) crystal growth occurs (106) as described in more detail in U.S. Pat. No. 6,896,729 to Liu et al. which is incorporated herein by reference. Consistent with Liu et al., VGF fabrication according to the present innovations encompass crystal growth technology, apparatus, and processes whereby large single crystal ingots are grown with a very high level of structural uniformity and low defect density. According to one exemplary implementation, controlled growth of GaAs is achieved by placing a dopant material in an ampoule outside a growth crucible, not in contact with the molten charge. Since the dopant materials are separated from the melt or the internal wall of the crucible, the process is favorable for achieving a high single crystal growth yield. Exemplary VGF processes for achieving controlled incorporation of carbon in the growth of semi-insulating GaAs material, here, may include: (1) loading charges of GaAs raw materials into the crucible, (2) placing carbon doping sources within, generally at a low end of, the ampoule, (3) loading the crucible with the GaAs charges into the ampoule, (4) evacuating/sealing under vacuum the ampoule containing the dopant, the crucible, the GaAs charges, and B2O3 material, and (5) heating/melting the charge and then controlling the liquid-solid interface, wherein control of the amount of the dopant and/or the temperature are used to grow semi-insulating GaAs ingots with high uniformity and low defects. - Referring again to
FIG. 1 , the VGF grown crystals may be tested (107). During the VGF crystal growth, an etch pin density of less than 900/cm2. In testing, the process has achieved an EPD as low as 600/cm2 for 3″ diameter GaAs wafers. There are conventional processes that can produce low EPD GaAs substrates as low as 900/cm2, however none of the conventional processes can produce GaAs or other similar wafers at less than 900/cm2. Thus, typical processes may achieve an EPD of 900/cm2, but cannot achieve the lower EPD levels provided by the VGF process. - To achieve the low EPD, several VGF parameters are carefully controlled . The parameters may include the shape of the melt/crystal interface which is controlled to be concave or convex to the melt front at ±2 mm, crystallization velocity from 2-16 mm/hour, the temperature gradient at the melt/crystal interface between 0.1 to 2 degrees C. and/or a total temperature gradient of between 1 to 4 degrees C.
- Once the VGF crystals are grown (and optionally tested), a well known ingot shaping process (108) is conducted and the shaped ingot may also be tested (109). Once the ingot is shaped, the ingot is sliced into wafers (110) and the wafers may be optionally tested (111). The above processes may also be used to product InGaP wafers. As a result of this process, low EPD GaAs/InGaP wafers are produced.
- Once the low EPD wafers have been sliced from the ingot, a wafer annealing process (112) is performed wherein the annealed wafers may be tested (113). Instead of the typical three-stage annealing process, a one-stage annealing process is used. During that process the wafers are loaded vertically into a horizontal quartz boat and inserted in a horizontal quartz ampoule along with the required Arsenic lumps. These Arsenic lumps are carefully weighed to provide the needed vapor pressure at the annealing temperature to avoid any Arsenic dissociation from the substrates. The ampoule is then pumped down to a high vacuum level (<5E-3 Torr) and sealed. The ampoule and its contents are then inserted into a horizontal 3-zone furnace and the heating of the ampoule and its contents to the desired set (platform) temperature is initiated. When the platform temperature (900 C to 1050 C) is reached it is held constant for several hours (10 to 48 hours). Subsequently, the heating is decreased and the ampoule is allowed to cool down to room temperature within a set time (6 to 24 hrs). During the one-stage annealing process, the oxygen level in the GaAs wafers is controlled by adjusting the vacuum level in the ampoule The annealing process conditions were optimized for heating rate, platform temperature and cooling rate to achieve very low LPD levels (<1/cm2). As a result of the annealing process, the wafer has light point defects as low as <<1/cm2 with particle size >0.3 μm. In addition, the wafer may have as low as <120 particles/wafer, particle size >0.3 μm for 6″ wafers.
- Once the low EPD wafers are annealed and optionally tested, a known wafer polishing process (114) is performed that polishes the low EPD wafers and the polished wafers may be optionally tested (115). Once the wafers are polished, the wafers are cleaned (116) and optionally tested (117) and then packaged for shipping to customers (118).
- The EPD measurements are performed in accordance with SEMI M36-0699 and ASTM Test Method F1404-92. An example of the EPD level as measured at 37 points (each point having an area of 0.024 cm2) is shown in
FIG. 2 . This example shows an average EPD of 695/cm2. Note that the EPD is not evenly distributed across the wafer and for this sample, the maximum EPD is 1167/cm2. All the numbers shown inFIG. 2 are actual counts of the number of EPDs—to obtain the EPD value, these numbers should be divided by the unit area (namely, 0.024 cm2) to obtain the number per cm2. - While the foregoing has been with reference to a particular embodiment of the invention, it will be appreciated by those skilled in the art that changes in this embodiment may be made without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims.
Claims (16)
1. A method for manufacture a gallium based material with a low etch pit density (EPD), the method comprising:
forming polycrystalline gallium based compounds; and
performing vertical gradient freeze crystal growth using the polycrystalline gallium based compounds wherein the gallium based crystal has an etch pit density of less than 900 per square centimeter.
2. The method of claim 1 , wherein the crystal has an etch pit density of about 600 per square centimeter.
3. The method of claim 2 further comprising forming a gallium arsenide substrate from the gallium based crystal.
4. The method of claim 2 further comprising forming a indium phosphide, gallium phosphide or other III-IV substrates from the gallium based crystal.
5. The method of claim 1 , wherein performing vertical gradient freeze crystal growth further comprises controlling a shape of the melt/crystal interface during the vertical gradient freeze crystal growth wherein the shape is concave or convex to a melt front.
6. The method of claim 1 , wherein performing vertical gradient freeze crystal growth further comprises controlling a crystallization velocity during the vertical gradient freeze crystal growth wherein the crystallization velocity is between 2 and 16 mm/hour.
7. The method of claim 1 , wherein performing vertical gradient freeze crystal growth further comprises controlling a temperature gradient at a melt/crystal interface during the vertical gradient freeze crystal growth wherein the temperature gradient at the melt/crystal interface is between 0.1 to 2 degrees Celsius.
8. The method of claim 1 , wherein performing vertical gradient freeze crystal growth further comprises controlling a total temperature gradient during the vertical gradient freeze crystal growth wherein the total temperature gradient is between 1 and 5 degrees Celsius.
9. A method for manufacture a substrate with low light defects, the method comprising:
forming a gallium arsenide based substrate;
annealing the gallium arsenide based substrate using a single step annealing;
controlling the oxygen into a surface of the gallium based substrate during the annealing process; and
removing a portion of the surface of the gallium based substrate to form a gallium arsenide based substrate having a predetermined oxygen content level and a light point defect of less than 1 per square centimeter per gallium arsenide based substrate with a particle size of greater than 0.3 micrometers.
10. The method of claim 9 , wherein annealing the gallium arsenide based substrate further comprises controlling a heating rate during the annealing wherein the heating rate is 900 to 1050 degrees Celsius over 10 to 48 hours.
11. The method of claim 9 , wherein annealing the gallium arsenide based substrate further comprises controlling a platform temperature during the annealing wherein the platform temperature is 900 to 1050 degrees Celsius.
12. The method of claim 9 , wherein annealing the gallium arsenide based substrate further comprises controlling a cooling rate during the annealing wherein the cooling rate is to room temperature in 6 to 24 hours.
13. A gallium based substrate, comprising:
a substrate having an etch pit density of less than 900 per square centimeter using a vertical gradient freeze process; and
the substrate having less than 120 light point defects and a light point defect particle size of less than 0.3 micrometers.
14. The substrate of claim 13 , wherein the substrate is gallium arsenide (GaAs).
15. The substrate of claim 13 , wherein the substrate is indium phosphide, gallium phosphide or other III-V compounds.
16-30. (canceled)
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Application Number | Priority Date | Filing Date | Title |
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US12/506,209 US20100001288A1 (en) | 2007-05-09 | 2009-07-20 | Low Etch Pit Density (EPD) Semi-Insulating GaAs Wafers |
US13/207,291 US8361225B2 (en) | 2007-05-09 | 2011-08-10 | Low etch pit density (EPD) semi-insulating III-V wafers |
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US11/801,712 US7566641B2 (en) | 2007-05-09 | 2007-05-09 | Low etch pit density (EPD) semi-insulating GaAs wafers |
US12/506,209 US20100001288A1 (en) | 2007-05-09 | 2009-07-20 | Low Etch Pit Density (EPD) Semi-Insulating GaAs Wafers |
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US11/801,712 Continuation US7566641B2 (en) | 2007-05-09 | 2007-05-09 | Low etch pit density (EPD) semi-insulating GaAs wafers |
US13/207,291 Continuation US8361225B2 (en) | 2007-05-09 | 2011-08-10 | Low etch pit density (EPD) semi-insulating III-V wafers |
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US12/991,911 Abandoned US20110089538A1 (en) | 2007-05-09 | 2008-05-09 | Low etch pit density (epd) semi-insulating iii-v wafers |
US12/506,209 Abandoned US20100001288A1 (en) | 2007-05-09 | 2009-07-20 | Low Etch Pit Density (EPD) Semi-Insulating GaAs Wafers |
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US11/801,712 Active 2027-09-19 US7566641B2 (en) | 2007-05-09 | 2007-05-09 | Low etch pit density (EPD) semi-insulating GaAs wafers |
US12/991,911 Abandoned US20110089538A1 (en) | 2007-05-09 | 2008-05-09 | Low etch pit density (epd) semi-insulating iii-v wafers |
Country Status (4)
Country | Link |
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US (3) | US7566641B2 (en) |
JP (2) | JP2010526755A (en) |
CN (2) | CN101307501B (en) |
WO (1) | WO2008140763A1 (en) |
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WO2013023194A1 (en) * | 2011-08-10 | 2013-02-14 | Axt, Inc. | Low etch pit density (epd) semi-insulating iii-v wafer |
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US11608569B2 (en) * | 2020-02-28 | 2023-03-21 | Axt, Inc. | Low etch pit density, low slip line density, and low strain indium phosphide |
CN112420511A (en) * | 2020-11-23 | 2021-02-26 | 陕西科技大学 | Annealing treatment method of GaAs substrate |
WO2024062991A1 (en) * | 2022-09-21 | 2024-03-28 | Dowaエレクトロニクス株式会社 | Method for producing gaas ingot, and gaas ingot |
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Also Published As
Publication number | Publication date |
---|---|
JP2010526755A (en) | 2010-08-05 |
US20110089538A1 (en) | 2011-04-21 |
WO2008140763A1 (en) | 2008-11-20 |
US7566641B2 (en) | 2009-07-28 |
JP2015006988A (en) | 2015-01-15 |
JP6008144B2 (en) | 2016-10-19 |
US20080280427A1 (en) | 2008-11-13 |
CN101688323A (en) | 2010-03-31 |
CN101307501B (en) | 2012-12-26 |
CN101307501A (en) | 2008-11-19 |
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