US20090293266A1 - Linked Chip Attach And Underfill - Google Patents

Linked Chip Attach And Underfill Download PDF

Info

Publication number
US20090293266A1
US20090293266A1 US12/539,690 US53969009A US2009293266A1 US 20090293266 A1 US20090293266 A1 US 20090293266A1 US 53969009 A US53969009 A US 53969009A US 2009293266 A1 US2009293266 A1 US 2009293266A1
Authority
US
United States
Prior art keywords
underfill
assembly
integrated circuit
particular embodiment
curing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/539,690
Inventor
Edward A. Zarbock
Ming Lei
Sabina Houle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to US12/539,690 priority Critical patent/US20090293266A1/en
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HOULE, SABINA, LEI, MING, ZARBOCK, EDWARD A.
Publication of US20090293266A1 publication Critical patent/US20090293266A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/53—Means to assemble or disassemble
    • Y10T29/5313—Means to assemble electrical device
    • Y10T29/53174—Means to fasten electrical component to wiring board, base, or substrate
    • Y10T29/53178—Chip component

Definitions

  • Integrated circuit (IC) dice tend to be fragile and are typically packaged for protection from physical damage and for heat dissipation.
  • ICs may comprise one or more passive and/or active elements, one or more layers of metal interconnects and one or more layers of dielectric material.
  • the dielectric layer formed between metal interconnects may be referred to as “inner layer dielectric” (ILD).
  • ILD inner layer dielectric
  • An IC die and package are typically electrically interconnected via a first level interconnect (FLI) such as, for instance, by wirebonding or soldering.
  • FLI first level interconnect
  • package assembly may include die placement at room temperature, solder reflow in the range of 220 degrees Celsius (° C.), cooling again to room temperature, deflux performed in the range of 90° C., prebake performed in the range of 160° C., underfill dispense performed in the range of 110° C., cooling again to room temperature and then underfill cure performed in the range of 160° C.
  • Thermomechanical stresses during packaging may exceed the effective strength of ILD and solder joints which may result in ILD and solder joint cracking. Such defects may cause IC failures. Further, due to a constant drive to reduce die size and improve performance, FLI solder bump pitches and diameters are decreasing. To improve electrical performance, manufacturers are increasingly using low dielectric constant (low k) materials in ICs which tend to be weaker than previously used ILD materials. Both trends may further reduce solder joint and underlying ILD strength increasing the damaging effects of CTE mismatch during packaging.
  • FIG. 1 is a block diagram depicting a particular embodiment of a process for attaching an IC to a package substrate.
  • FIG. 2 is a block diagram depicting a particular embodiment of a system for attaching an IC to a package substrate.
  • FIG. 3 is a thermal profile of a conventional process to attach an IC to a substrate.
  • FIG. 4 is a thermal profile of a particular embodiment of process to attach an IC to a substrate.
  • integrated circuit is used and is intended to refer to a discrete set of electronic components and interconnections patterned in and/or on a semiconductor die.
  • die is used throughout the disclosure and is intended to refer to an integrated circuit.
  • interconnect is used throughout the following disclosure and is intended to refer to a physical and/or electrical connection between connected items.
  • flip chip is used throughout the following disclosure and is intended to refer to an integrated circuit, designed for a face-up or face-down direct interconnection with an underlying electrical component.
  • package is used throughout the disclosure and is intended to refer to materials and components for encapsulating and interconnecting a die to a printed circuit board.
  • solder and “solder material” are used throughout the following disclosure and are intended to refer to materials such as pure metal or metal alloy used to bond other metals together.
  • reflow is used throughout the following disclosure and is intended to refer to a process of heating and melting thermal interface and/or solder material to facilitate physical, thermal and/or electrical interconnection between parts to be coupled via a thermal interface and/or solder material.
  • FIG. 1 is a block diagram depicting a particular embodiment of a process 100 for attaching an IC 101 to a package substrate 103 via an FLI 107 .
  • Process 100 refers to a controlled collapse chip connection (C4) packaging technique, however, it will be recognized by one of ordinary skill in the art that process 100 may be adapted to other packaging techniques interconnecting one or more ICs and/or substrates, such as, for instance in a multi-chip stack up and/or other package board assemblies.
  • C4 controlled collapse chip connection
  • process 100 may begin at block 102 wherein solder may be applied to bond pads (not shown) on the first surface of substrate 103 .
  • solder may be applied to bond pads of IC 101 as well and claimed subject matter is not limited in this regard.
  • the solder may be applied using any number of suitable techniques such as, for instance, printing, vapor deposition and/or electroplating and claimed subject matter is not limited in this regard.
  • substrate 103 may be heated to beyond the solder's melting point to reflow the solder and to facilitate wetting of the bond pads to form solder bumps 111 .
  • a flux material such as, for instance, no-clean flux 105 may be applied over a first surface of substrate 103 substantially encapsulating solder bumps 111 .
  • No-clean flux 105 may comprise any of a variety of commercially available or custom no-clean fluxes, such as, for instance, “No-Clean Flip Chip Flux ICA-1127-47” available from Indium Corporation, Utica, N.Y., United States “Kester 245 No-Clean Flux” available from Kester Company, Itasca, Ill., United States and/or “No-Clean Flux NS-316” available from Nihon Superior Company, Suita City, Osaka, Japan and claimed subject matter is not limited in this regard.
  • no-clean flux 105 may eliminate at least one thermal cycle from process 100 .
  • no-clean flux 105 may have a boiling point below the melting point of solder bumps 111 enabling no-clean flux 105 to be substantially volatilized during die attach reflow. Accordingly, no-clean flux 105 may leave little or no residue on assembly 120 after reflow thus eliminating the need for a later de-flux stage. In a particular embodiment, because no-clean flux 105 may leave behind substantially no residue, a de-flux stage may be removed from process 100 .
  • De-flux In conventional package assembly, if a flux material leaves behind residue, the residue may be removed during a de-flux stage.
  • De-flux generally requires assembly 120 to be cooled from a reflow temperature of about 220° C. to about room temperature. During de-flux pressurized deionized water at about 90° C. is sprayed between IC 101 and substrate 103 to remove flux residue. Then IC 101 is cooled again to about room temperature. Additionally, a de-flux stage may leave excess moisture that should be removed before underfill. After de-flux, assembly 120 is typically prebaked at about 160° C. to remove excess moisture left behind by de-flux processing. Thus, use of no-clean flux 105 in process 100 may enable eliminating two thermal cycles from process 100 by eliminating a thermal cycle associated with de-flux itself and eliminating thermal cycling of a prebake stage involved with by a de-flux stage.
  • no-clean flux 105 may be held at a flux activation temperature for an extended duration.
  • assembly 120 may be held at about 140° C. for about 100 seconds.
  • Long FAT processing may enable flux carriers to volatilize in a controlled manner substantially reducing IC/substrate misalignment.
  • this is merely an example of a method of holding no-clean flux for an extended duration at the activation temperature and claimed subject matter is not so limited.
  • other flux activation temperatures and holding times may be appropriate.
  • process 100 may proceed to block 104 wherein IC 101 may be attached to a substrate 103 via compression, adhesion and/or thermocompression or any number of other suitable techniques known to those of skill in the art.
  • metal bumps 109 and solder bumps 111 may be aligned and heat and/or pressure may be applied to IC/substrate assembly 120 to hold the IC 101 and substrate 103 together prior to reflow.
  • a flux material such as, for instance, no-clean flux 105 may facilitate adhesion between IC 101 and substrate 103 .
  • process 100 may proceed to block 112 where IC 101 and substrate 103 may be electrically connected via solder reflow.
  • solder bumps 111 may be heated to their melting point and joined to metal bumps 109 by soldering.
  • heat may be applied to solder bumps 111 by a variety of methods such as, for instance, by a heated gas flow, electrical pulse heating and/or direct heat applied via an internal or external heating element and claimed subject matter is not limited in this regard.
  • solder bumps 111 may melt at temperatures in the range of 220° C. However, this is merely an example of a solder reflow method and reflow temperature and claimed subject matter is not so limited.
  • process 100 may proceed to block 114 where assembly 120 may be cooled to about 120° C. and optionally prebaked at a temperature in the range of about 160° C.
  • assembly 120 may be kept at a temperature above about 120° C. after reflow, during an optional prebake stage and before transfer to an underfill station.
  • maintaining the temperature at or above 120° C. may reduce the temperature fluctuation at this stage of process 100 from having a temperature change ( ⁇ ) of about 200° C. to about ⁇ 100° C. and may thermally link a reflow stage with an underfill stage of process 100 . Preventing large temperature fluctuations between reflow and underfill may substantially reduce damage to assembly 120 induced, for instance, by CTE mismatch between IC 101 and substrate 103 .
  • assemblies 120 may be maintained at temperatures at or above 120° C. until a downstream line interruption is cleared and the assembly line is running again. Maintaining the temperature of assemblies 120 at or above 120° C. may prevent line interruptions from destroying assemblies 120 by preventing assemblies 120 from cooling significantly before an underfill stage of process 100 . Such cooling (for instance, to room temperature) may cause severe solder joint 121 and ILD 122 damage, especially, if it occurs before a protective underfill material has been applied.
  • process 100 may proceed to block 116 where underfill 124 may be applied to assembly 120 between IC 101 and substrate 103 to protect and stabilize FLI 107 of assembly 120 .
  • underfill 124 may comprise a variety of materials, such as, for instance, an epoxy polymer, with or without filler such as ceramic material and/or silica and claimed subject matter is not limited in this regard.
  • underfill 124 may be applied by a variety of filling techniques, such as, for instance, capillary underfill, needle injection and/or corner dot underfill and claimed subject matter is not limited in this regard.
  • process 100 may proceed to block 118 where underfill 124 may be partially cured.
  • underfill 124 may be cured to a gelling phase, such that underfill 124 may protect the solder joint 121 and underlying ILD 122 prior to returning to room temperature.
  • partial curing may take place at a temperature of about 170° C. until underfill gelling occurs.
  • process 100 may proceed to block 130 where assembly 120 may be cooled to room temperature.
  • such cooling may occur passively, for instance while assembly 120 is being unloaded off a process 100 assembly line and/or stored prior to a subsequent process 100 stage.
  • this is merely an example of a method of cooling assembly 120 and claimed subject matter is not limited in this regard.
  • assembly 120 may be actively cooled while waiting on-line to move to a subsequent process 100 stage.
  • process 100 may proceed to block 132 where underfill 124 may be completely cured.
  • underfill 124 may be cured to at a temperature in the range of 170° C. Full curing of underfill 124 may enable protection of protect solder joint 121 and underlying ILD 122 of FLI 107 .
  • this is merely an example of a method of curing underfill 124 and claimed subject matter is not so limited.
  • a system comprising operational equipment adapted to carry out process 100 is disclosed in FIG. 2 .
  • FIG. 2 is a block diagram illustrating a particular embodiment of a system 200 for producing assembly 120 via process 100 .
  • system 200 may comprise various pieces of operational equipment capable of performing various stages of process 100 .
  • assembly 120 produced by system 200 is also shown.
  • system 200 may comprise a single production line, batch equipment or may be a combination of online and batch equipment and claimed subject matter is not limited in this regard.
  • assembly 120 proceeds from one piece of operational equipment to the next via conveyorized connection 203 .
  • assembly 120 may move from one stage of process 100 to the next by a variety of methods, such as, by being manually moved and claimed subject matter is not limited in this regard.
  • system 200 may begin after solder bumps 111 have been formed on substrate 103 .
  • chip-attach module (CAM) 202 may be capable of applying flux material, such as, for instance, no-clean flux 105 (shown in FIG. 1 ) to a first surface of substrate 103 by a variety of methods, such as, by brushing, screen-printing, dipping and/or spraying and claimed subject matter is not limited in this regard.
  • CAM 202 may be adapted to pick and place IC 101 over substrate 103 to enable alignment of metal bumps 109 with solder bumps 111 of substrate 103 .
  • Such alignment may be maintained by a variety of methods such as self-alignment and/or thermocompression and may be facilitated by the presence of flux on substrate 103 .
  • no-clean flux for instance, may aid adhesion of IC 101 to substrate 103 .
  • assembly 120 may proceed to reflow module 204 where IC 101 may be electrically connected to substrate 103 by soldering.
  • assembly 120 may proceed from CAM 202 to reflow module 204 via conveyorized connection 203 .
  • CAM 202 may be thermally and/or mechanically linked to reflow module 204 via conveyorized connection 203 .
  • Such a conveyorized connection may comprise a variety of configurations including belts and/or rollers and may or may not be covered and claimed subject matter is not limited in this regard.
  • reflow module 204 may be adapted to apply heat to assembly 120 to melt solder bumps 111 by a variety of methods. Such methods may include, for instance, passing assembly 120 though a reflow oven such as a pulsed heat, convection and/or vapor phase oven and claimed subject matter is not limited in this regard.
  • a reflow oven such as a pulsed heat, convection and/or vapor phase oven and claimed subject matter is not limited in this regard.
  • assembly 120 may proceed to heated buffer 206 via conveyorized connection 203 .
  • heated buffer 206 may be thermally and/or mechanically linked upstream to reflow module 204 via conveyorized connection 203 and thermally and/or mechanically linked downstream to prebake oven 208 and/or underfill dispenser 210 via conveyorized connection 203 .
  • reflow module 204 may continuously process assemblies 120 which may be passed through heated buffer 206 .
  • system 200 may be subject to delays due to a variety of causes such as, downstream back-up at underfill dispenser 210 , material replenish downtime and/or lot change over. If delays develop on an assembly 120 production line, heated buffer 206 may buffer assemblies 120 to store and maintain assembly 120 temperature.
  • heated buffer 206 may be adapted to load a substantial portion or the entire capacity of reflow module 204 into one or more support elements 207 .
  • Such support elements may be adapted to support a substrate, substrate panel, and/or tray of substrates.
  • support elements 207 may be a magazine racks.
  • support elements 207 may be random access first in first out (FIFO) and/or last in first out (LIFO) storage racks and claimed subject matter is not limited in this regard.
  • heated buffer 206 may maintain assemblies 120 at or above a constant temperature for an indefinite period of time.
  • heated buffer 206 may be adapted to begin dispensing assemblies 120 from support elements 207 when a back-up on assembly 120 production line is cleared.
  • heated buffer 206 may reduce the risk of damage to ILD 121 and solder joints 122 by preventing unintended thermal cycling.
  • the storage capacity of heated buffer 206 may enable system 200 to continue functioning even when there are downstream interruptions or delays and may reduce the risk of damage to assemblies 120 due to CTE mismatch during such delays.
  • assembly 120 may proceed to an optional prebake stage in prebake oven 208 via conveyorized connection 203 .
  • a prebake oven may drive excess moisture or residue off of assembly 120 .
  • a prebake stage may be eliminated.
  • assembly 120 may proceed directly to underfill dispenser 210 from heated buffer 206 via conveyorized connection 203 .
  • underfill dispenser 210 may be adapted to apply an underfill material to assembly 120 between IC 101 and substrate 103 .
  • underfill 124 may be applied by a variety of filling techniques, such as, for instance, capillary underfill, needle injection and/or corner dot underfill and claimed subject matter is not limited in this regard.
  • assembly 120 may proceed to partial underfill cure oven 212 adapted to partially cure underfill 124 via conveyorized connection 203 .
  • partial curing may result in hardening of underfill 124 such that it is capable of providing protection to ILD 121 and solder joints 122 as assembly 120 returns to room temperature.
  • a partial cure may cure underfill to just beyond a gelling phase before a complete cure is achieved.
  • partial curing oven 212 may operate at temperatures in the range of 170° C. However, this is merely an example of a temperature at which a partial underfill cure oven may operate and claimed subject matter is not so limited.
  • assembly 120 may be cooled to room temperature and assembly 120 may be transported to full underfill cure oven 214 adapted to fully cure underfill 124 .
  • assembly 120 may be transported via conveyorized connection 203 .
  • underfill cure oven 214 may be off-line and assembly 120 may be transported to underfill cure oven 214 manually.
  • full underfill cure oven 214 may operate at a temperature in the range of 170° C. However, this is merely an example of a temperature at which a full underfill curing oven may operate and claimed subject matter is not limited in this regard.
  • FIG. 3 a thermal profile of a conventional packaging process is shown and FIG. 4 depicts a thermal profile of a packaging process according to process 100 for comparison.
  • FIG. 3 depicts a thermal profile 300 of an IC/substrate assembly as it is assembled in a conventional process including a deflux stage and not including a heated buffer stage.
  • an IC/substrate assembly may undergo a temperature fluctuation on the order of about 200° C.
  • an IC/substrate assembly may undergo another temperature fluctuation on the order of about 135° C.
  • an IC/substrate assembly may undergo yet another temperature fluctuation on the order of about 60° C.
  • FIG. 4 depicts a thermal profile 400 of a particular embodiment of an IC/substrate packaging process as described with reference to FIG. 1 comprising a heated buffer stage and not including a deflux step.
  • thermal profile 300 at line segment 401 - 402 before a heated buffering stage there is no deflux step and therefore the temperature fluctuation is about 100° C. rather than 200° C.
  • package assemblies may be kept at or above a constant temperature of about 120° C. as they transfer from a heated buffer, to a prebake and then underfill stage from line segment 402 to line segment 404 .
  • pre-underfill dispense temperature fluctuations may be substantially reduced minimizing damage to ILDs and solder joints caused by CTE mismatch.
  • IC/substrate assemblies were packaged and examined for defects such as solder cracking and inner layer dielectric delamination using C-mode scanning acoustic microscropy (C-SAM).
  • C-SAM C-mode scanning acoustic microscropy
  • the experimental assemblies all comprised low-k inner layer dielectric material.
  • Two packaging technologies were tested: packaging according to process 100 and packaging according to conventional methods. Assemblies were packaged with or without integrated heat spreaders (IHS) attached. Examination for defects was conducted before and after temperature shock thermal cycling from about 0° C. to about 160° C. on the order of about 50 cycles. Experimental data reported in Table 1 below shows that defects were detected in over 50.0% of assemblies packaged according to conventional methods using low-k dielectric ILDs while no defects were detected in assemblies packaged according to process 100 .
  • IHS integrated heat spreaders

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

An integrated circuit packaging method, system and apparatus for maintaining a predetermined temperature between reflow and underfill dispense are disclosed.

Description

    BACKGROUND
  • Integrated circuit (IC) dice tend to be fragile and are typically packaged for protection from physical damage and for heat dissipation. ICs may comprise one or more passive and/or active elements, one or more layers of metal interconnects and one or more layers of dielectric material. The dielectric layer formed between metal interconnects may be referred to as “inner layer dielectric” (ILD). An IC die and package are typically electrically interconnected via a first level interconnect (FLI) such as, for instance, by wirebonding or soldering.
  • During package assembly an IC die and package may be exposed to repeated thermal cycles which may induce thermomechanical stress on the ILD and solder joints. For instance, package assembly may include die placement at room temperature, solder reflow in the range of 220 degrees Celsius (° C.), cooling again to room temperature, deflux performed in the range of 90° C., prebake performed in the range of 160° C., underfill dispense performed in the range of 110° C., cooling again to room temperature and then underfill cure performed in the range of 160° C.
  • Other factors in the packaging process may cause additional temperature fluctuations. For instance, various stages of the assembly process take place in different pieces of assembly equipment. While being transferred on the line or off the line from one assembly apparatus to another, an IC/package assembly may cool significantly. Also, there may be downtime on the line caused by underfill bottlenecking, assist or material replenishment or lot changeover. In the event of downtime on the line, an IC/package assembly may cool while waiting for the line to return to function. Multiple thermal cycles with temperature fluctuations ranging to about 200° C. may have deleterious effects on ILD and solder joints due in part to coefficient of thermal expansion (CTE) mismatch between the IC and the package substrate.
  • Thermomechanical stresses during packaging may exceed the effective strength of ILD and solder joints which may result in ILD and solder joint cracking. Such defects may cause IC failures. Further, due to a constant drive to reduce die size and improve performance, FLI solder bump pitches and diameters are decreasing. To improve electrical performance, manufacturers are increasingly using low dielectric constant (low k) materials in ICs which tend to be weaker than previously used ILD materials. Both trends may further reduce solder joint and underlying ILD strength increasing the damaging effects of CTE mismatch during packaging.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a block diagram depicting a particular embodiment of a process for attaching an IC to a package substrate.
  • FIG. 2 is a block diagram depicting a particular embodiment of a system for attaching an IC to a package substrate.
  • FIG. 3 is a thermal profile of a conventional process to attach an IC to a substrate.
  • FIG. 4 is a thermal profile of a particular embodiment of process to attach an IC to a substrate.
    •  DETAILED DESCRIPTION
  • In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of claimed subject matter. However, it will be understood by those skilled in the art that claimed subject matter may be practiced without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to obscure claimed subject matter.
  • Throughout the following disclosure the term “integrated circuit” is used and is intended to refer to a discrete set of electronic components and interconnections patterned in and/or on a semiconductor die. The term “die” is used throughout the disclosure and is intended to refer to an integrated circuit. The term “interconnect” is used throughout the following disclosure and is intended to refer to a physical and/or electrical connection between connected items. The term “flip chip” is used throughout the following disclosure and is intended to refer to an integrated circuit, designed for a face-up or face-down direct interconnection with an underlying electrical component. The term “package” is used throughout the disclosure and is intended to refer to materials and components for encapsulating and interconnecting a die to a printed circuit board. The terms “solder” and “solder material” are used throughout the following disclosure and are intended to refer to materials such as pure metal or metal alloy used to bond other metals together. The term “reflow” is used throughout the following disclosure and is intended to refer to a process of heating and melting thermal interface and/or solder material to facilitate physical, thermal and/or electrical interconnection between parts to be coupled via a thermal interface and/or solder material.
  • The following detailed description discloses example embodiments of arrangements to package a single IC and substrate using an controlled collapse chip connection (C4), however, the following disclosure contemplates use with other types of integrated circuit mounting and package technologies, such as multiple integrated circuit stack-ups and/or with other types of mounting and packaging technologies. In addition, embodiments of the invention are applicable to a variety of package and substrate materials including organic, ceramic, and flex packages.
  • FIG. 1 is a block diagram depicting a particular embodiment of a process 100 for attaching an IC 101 to a package substrate 103 via an FLI 107. Each block is accompanied by a cross-sectional illustration of an IC/package assembly 120. Process 100 refers to a controlled collapse chip connection (C4) packaging technique, however, it will be recognized by one of ordinary skill in the art that process 100 may be adapted to other packaging techniques interconnecting one or more ICs and/or substrates, such as, for instance in a multi-chip stack up and/or other package board assemblies.
  • In a particular embodiment, process 100 may begin at block 102 wherein solder may be applied to bond pads (not shown) on the first surface of substrate 103. According to another particular embodiment, solder may be applied to bond pads of IC 101 as well and claimed subject matter is not limited in this regard. The solder may be applied using any number of suitable techniques such as, for instance, printing, vapor deposition and/or electroplating and claimed subject matter is not limited in this regard. After the solder is applied, substrate 103 may be heated to beyond the solder's melting point to reflow the solder and to facilitate wetting of the bond pads to form solder bumps 111.
  • In a particular embodiment, a flux material, such as, for instance, no-clean flux 105 may be applied over a first surface of substrate 103 substantially encapsulating solder bumps 111. No-clean flux 105 may comprise any of a variety of commercially available or custom no-clean fluxes, such as, for instance, “No-Clean Flip Chip Flux ICA-1127-47” available from Indium Corporation, Utica, N.Y., United States “Kester 245 No-Clean Flux” available from Kester Company, Itasca, Ill., United States and/or “No-Clean Flux NS-316” available from Nihon Superior Company, Suita City, Osaka, Japan and claimed subject matter is not limited in this regard. According to a particular embodiment, use of no-clean flux 105 may eliminate at least one thermal cycle from process 100. In a particular embodiment, no-clean flux 105 may have a boiling point below the melting point of solder bumps 111 enabling no-clean flux 105 to be substantially volatilized during die attach reflow. Accordingly, no-clean flux 105 may leave little or no residue on assembly 120 after reflow thus eliminating the need for a later de-flux stage. In a particular embodiment, because no-clean flux 105 may leave behind substantially no residue, a de-flux stage may be removed from process 100.
  • In conventional package assembly, if a flux material leaves behind residue, the residue may be removed during a de-flux stage. De-flux generally requires assembly 120 to be cooled from a reflow temperature of about 220° C. to about room temperature. During de-flux pressurized deionized water at about 90° C. is sprayed between IC 101 and substrate 103 to remove flux residue. Then IC 101 is cooled again to about room temperature. Additionally, a de-flux stage may leave excess moisture that should be removed before underfill. After de-flux, assembly 120 is typically prebaked at about 160° C. to remove excess moisture left behind by de-flux processing. Thus, use of no-clean flux 105 in process 100 may enable eliminating two thermal cycles from process 100 by eliminating a thermal cycle associated with de-flux itself and eliminating thermal cycling of a prebake stage involved with by a de-flux stage.
  • According to a particular embodiment, no-clean flux 105 may be held at a flux activation temperature for an extended duration. For instance, assembly 120 may be held at about 140° C. for about 100 seconds. Such an extended duration at an activation temperature may be referred to as “Long FAT”. In a particular embodiment, Long FAT processing may enable flux carriers to volatilize in a controlled manner substantially reducing IC/substrate misalignment. However, this is merely an example of a method of holding no-clean flux for an extended duration at the activation temperature and claimed subject matter is not so limited. For instance, in another particular embodiment, other flux activation temperatures and holding times may be appropriate.
  • In a particular embodiment, process 100 may proceed to block 104 wherein IC 101 may be attached to a substrate 103 via compression, adhesion and/or thermocompression or any number of other suitable techniques known to those of skill in the art. In a particular embodiment, metal bumps 109 and solder bumps 111 may be aligned and heat and/or pressure may be applied to IC/substrate assembly 120 to hold the IC 101 and substrate 103 together prior to reflow. In a particular embodiment, a flux material such as, for instance, no-clean flux 105 may facilitate adhesion between IC 101 and substrate 103.
  • In a particular embodiment, process 100 may proceed to block 112 where IC 101 and substrate 103 may be electrically connected via solder reflow. In a particular embodiment, during reflow, solder bumps 111 may be heated to their melting point and joined to metal bumps 109 by soldering. According to a particular embodiment, heat may be applied to solder bumps 111 by a variety of methods such as, for instance, by a heated gas flow, electrical pulse heating and/or direct heat applied via an internal or external heating element and claimed subject matter is not limited in this regard. According to a particular embodiment, solder bumps 111 may melt at temperatures in the range of 220° C. However, this is merely an example of a solder reflow method and reflow temperature and claimed subject matter is not so limited.
  • In a particular embodiment, process 100 may proceed to block 114 where assembly 120 may be cooled to about 120° C. and optionally prebaked at a temperature in the range of about 160° C. As previously noted, the use of no-clean flux 105 during reflow enables elimination of a deflux stage of process 100. Accordingly, without the temperature fluctuation of a deflux step, assembly 120 may be kept at a temperature above about 120° C. after reflow, during an optional prebake stage and before transfer to an underfill station. In contrast to conventional methods, maintaining the temperature at or above 120° C. may reduce the temperature fluctuation at this stage of process 100 from having a temperature change (Δ) of about 200° C. to about Δ100° C. and may thermally link a reflow stage with an underfill stage of process 100. Preventing large temperature fluctuations between reflow and underfill may substantially reduce damage to assembly 120 induced, for instance, by CTE mismatch between IC 101 and substrate 103.
  • In a particular embodiment, if an process 100 occurs on an assembly line (not shown) and the line experiences interruptions, assemblies 120 may be maintained at temperatures at or above 120° C. until a downstream line interruption is cleared and the assembly line is running again. Maintaining the temperature of assemblies 120 at or above 120° C. may prevent line interruptions from destroying assemblies 120 by preventing assemblies 120 from cooling significantly before an underfill stage of process 100. Such cooling (for instance, to room temperature) may cause severe solder joint 121 and ILD 122 damage, especially, if it occurs before a protective underfill material has been applied.
  • In a particular embodiment, process 100 may proceed to block 116 where underfill 124 may be applied to assembly 120 between IC 101 and substrate 103 to protect and stabilize FLI 107 of assembly 120. According to a particular embodiment, underfill 124 may comprise a variety of materials, such as, for instance, an epoxy polymer, with or without filler such as ceramic material and/or silica and claimed subject matter is not limited in this regard. According to a particular embodiment, underfill 124 may be applied by a variety of filling techniques, such as, for instance, capillary underfill, needle injection and/or corner dot underfill and claimed subject matter is not limited in this regard.
  • In a particular embodiment, process 100 may proceed to block 118 where underfill 124 may be partially cured. According to a particular embodiment, underfill 124 may be cured to a gelling phase, such that underfill 124 may protect the solder joint 121 and underlying ILD 122 prior to returning to room temperature. According to a particular embodiment, partial curing may take place at a temperature of about 170° C. until underfill gelling occurs.
  • In a particular embodiment, process 100 may proceed to block 130 where assembly 120 may be cooled to room temperature. In a particular embodiment, such cooling may occur passively, for instance while assembly 120 is being unloaded off a process 100 assembly line and/or stored prior to a subsequent process 100 stage. However, this is merely an example of a method of cooling assembly 120 and claimed subject matter is not limited in this regard. For instance, assembly 120 may be actively cooled while waiting on-line to move to a subsequent process 100 stage.
  • In a particular embodiment, process 100 may proceed to block 132 where underfill 124 may be completely cured. According to a particular embodiment, underfill 124 may be cured to at a temperature in the range of 170° C. Full curing of underfill 124 may enable protection of protect solder joint 121 and underlying ILD 122 of FLI 107. However, this is merely an example of a method of curing underfill 124 and claimed subject matter is not so limited. A system comprising operational equipment adapted to carry out process 100 is disclosed in FIG. 2.
  • FIG. 2 is a block diagram illustrating a particular embodiment of a system 200 for producing assembly 120 via process 100. In a particular embodiment, system 200 may comprise various pieces of operational equipment capable of performing various stages of process 100. Also shown is assembly 120 produced by system 200. In a particular embodiment, system 200 may comprise a single production line, batch equipment or may be a combination of online and batch equipment and claimed subject matter is not limited in this regard.
  • In the following example embodiment, assembly 120 proceeds from one piece of operational equipment to the next via conveyorized connection 203. However, in other embodiments of system 200, assembly 120 may move from one stage of process 100 to the next by a variety of methods, such as, by being manually moved and claimed subject matter is not limited in this regard.
  • In a particular embodiment, system 200 may begin after solder bumps 111 have been formed on substrate 103. According to a particular embodiment, chip-attach module (CAM) 202 may be capable of applying flux material, such as, for instance, no-clean flux 105 (shown in FIG. 1) to a first surface of substrate 103 by a variety of methods, such as, by brushing, screen-printing, dipping and/or spraying and claimed subject matter is not limited in this regard. According to a particular embodiment, CAM 202 may be adapted to pick and place IC 101 over substrate 103 to enable alignment of metal bumps 109 with solder bumps 111 of substrate 103. Such alignment may be maintained by a variety of methods such as self-alignment and/or thermocompression and may be facilitated by the presence of flux on substrate 103. In a particular embodiment, no-clean flux, for instance, may aid adhesion of IC 101 to substrate 103.
  • In a particular embodiment, assembly 120 may proceed to reflow module 204 where IC 101 may be electrically connected to substrate 103 by soldering. In a particular embodiment, assembly 120 may proceed from CAM 202 to reflow module 204 via conveyorized connection 203. Additionally, CAM 202 may be thermally and/or mechanically linked to reflow module 204 via conveyorized connection 203. Such a conveyorized connection may comprise a variety of configurations including belts and/or rollers and may or may not be covered and claimed subject matter is not limited in this regard.
  • According to a particular embodiment, reflow module 204 may be adapted to apply heat to assembly 120 to melt solder bumps 111 by a variety of methods. Such methods may include, for instance, passing assembly 120 though a reflow oven such as a pulsed heat, convection and/or vapor phase oven and claimed subject matter is not limited in this regard.
  • In a particular embodiment, assembly 120 may proceed to heated buffer 206 via conveyorized connection 203. In a particular embodiment, heated buffer 206 may be thermally and/or mechanically linked upstream to reflow module 204 via conveyorized connection 203 and thermally and/or mechanically linked downstream to prebake oven 208 and/or underfill dispenser 210 via conveyorized connection 203.
  • According to a particular embodiment, heated buffer 206 may be adapted to maintain assembly 120 at or above a constant temperature of, for instance but not limited to >/=120° C. as assembly 120 proceeds from a reflow stage of process 100 to an underfill stage. In high volume manufacturing as many as 5000 assembly 120 units may be produced per hour. In a particular embodiment, reflow module 204 may continuously process assemblies 120 which may be passed through heated buffer 206. However, system 200 may be subject to delays due to a variety of causes such as, downstream back-up at underfill dispenser 210, material replenish downtime and/or lot change over. If delays develop on an assembly 120 production line, heated buffer 206 may buffer assemblies 120 to store and maintain assembly 120 temperature.
  • According to a particular embodiment, heated buffer 206 may be adapted to load a substantial portion or the entire capacity of reflow module 204 into one or more support elements 207. Such support elements may be adapted to support a substrate, substrate panel, and/or tray of substrates. In a particular embodiment, support elements 207 may be a magazine racks. In a particular embodiment, support elements 207 may be random access first in first out (FIFO) and/or last in first out (LIFO) storage racks and claimed subject matter is not limited in this regard. As noted previously, heated buffer 206 may maintain assemblies 120 at or above a constant temperature for an indefinite period of time. In a particular embodiment, heated buffer 206 may be adapted to begin dispensing assemblies 120 from support elements 207 when a back-up on assembly 120 production line is cleared. Thus, heated buffer 206 may reduce the risk of damage to ILD 121 and solder joints 122 by preventing unintended thermal cycling. Additionally, the storage capacity of heated buffer 206 may enable system 200 to continue functioning even when there are downstream interruptions or delays and may reduce the risk of damage to assemblies 120 due to CTE mismatch during such delays.
  • In a particular embodiment, assembly 120 may proceed to an optional prebake stage in prebake oven 208 via conveyorized connection 203. In a particular embodiment a prebake oven may drive excess moisture or residue off of assembly 120. However, in another particular embodiment a prebake stage may be eliminated. In such an embodiment, assembly 120 may proceed directly to underfill dispenser 210 from heated buffer 206 via conveyorized connection 203.
  • In a particular embodiment, underfill dispenser 210 may be adapted to apply an underfill material to assembly 120 between IC 101 and substrate 103. According to a particular embodiment, underfill 124 may be applied by a variety of filling techniques, such as, for instance, capillary underfill, needle injection and/or corner dot underfill and claimed subject matter is not limited in this regard.
  • In a particular embodiment, assembly 120 may proceed to partial underfill cure oven 212 adapted to partially cure underfill 124 via conveyorized connection 203. Such partial curing may result in hardening of underfill 124 such that it is capable of providing protection to ILD 121 and solder joints 122 as assembly 120 returns to room temperature. In a particular embodiment, a partial cure may cure underfill to just beyond a gelling phase before a complete cure is achieved. According to a particular embodiment, partial curing oven 212 may operate at temperatures in the range of 170° C. However, this is merely an example of a temperature at which a partial underfill cure oven may operate and claimed subject matter is not so limited.
  • In a particular embodiment, assembly 120 may be cooled to room temperature and assembly 120 may be transported to full underfill cure oven 214 adapted to fully cure underfill 124. In a particular embodiment, assembly 120 may be transported via conveyorized connection 203. In another particular embodiment, underfill cure oven 214 may be off-line and assembly 120 may be transported to underfill cure oven 214 manually. According to a particular embodiment, full underfill cure oven 214 may operate at a temperature in the range of 170° C. However, this is merely an example of a temperature at which a full underfill curing oven may operate and claimed subject matter is not limited in this regard. In FIG. 3 a thermal profile of a conventional packaging process is shown and FIG. 4 depicts a thermal profile of a packaging process according to process 100 for comparison.
  • FIG. 3 depicts a thermal profile 300 of an IC/substrate assembly as it is assembled in a conventional process including a deflux stage and not including a heated buffer stage. At line segment 302 between reflow and deflux, an IC/substrate assembly may undergo a temperature fluctuation on the order of about 200° C. At line segment 304 between deflux and prebake an IC/substrate assembly may undergo another temperature fluctuation on the order of about 135° C. At line segment 306 between prebake and underfill dispense an IC/substrate assembly may undergo yet another temperature fluctuation on the order of about 60° C. These frequent and large temperature fluctuation especially before underfill, may cause physical damage to fragile ILDs and solder joints due to CTE mismatch.
  • FIG. 4 depicts a thermal profile 400 of a particular embodiment of an IC/substrate packaging process as described with reference to FIG. 1 comprising a heated buffer stage and not including a deflux step. In contrast to thermal profile 300, at line segment 401-402 before a heated buffering stage there is no deflux step and therefore the temperature fluctuation is about 100° C. rather than 200° C. Thereafter package assemblies may be kept at or above a constant temperature of about 120° C. as they transfer from a heated buffer, to a prebake and then underfill stage from line segment 402 to line segment 404. Thus pre-underfill dispense temperature fluctuations may be substantially reduced minimizing damage to ILDs and solder joints caused by CTE mismatch.
    • Example 1
  • IC/substrate assemblies were packaged and examined for defects such as solder cracking and inner layer dielectric delamination using C-mode scanning acoustic microscropy (C-SAM). The experimental assemblies all comprised low-k inner layer dielectric material. Two packaging technologies were tested: packaging according to process 100 and packaging according to conventional methods. Assemblies were packaged with or without integrated heat spreaders (IHS) attached. Examination for defects was conducted before and after temperature shock thermal cycling from about 0° C. to about 160° C. on the order of about 50 cycles. Experimental data reported in Table 1 below shows that defects were detected in over 50.0% of assemblies packaged according to conventional methods using low-k dielectric ILDs while no defects were detected in assemblies packaged according to process 100.
  • TABLE 1
    Packaging Technology Defects pre-shock Defects post-shock
    Process 100 - w/o IHS 0.0% (n = 24) 0.0% (n = 10)
    Process 100 - w/IHS 0.0% (n = 36) 0.0% (n = 12)
    Conventional - w/o IHS 66.67% (n = 6) 66.67% (n = 3)
    Conventional - w/IHS X 58.34% (n = 12)
  • While certain features of claimed subject matter have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such embodiments and changes as fall within the spirit of claimed subject matter.

Claims (12)

1-9. (canceled)
10. A system comprising:
a chip attach module adapted to place an integrated circuit onto a package substrate;
a reflow module coupled to the chip attach module adapted melt solder for attaching the integrated circuit to the package substrate;
a heated buffer coupled to the reflow module adapted to maintain the temperature of the integrated circuit and package assembly at or above a predetermined temperature prior to dispensing an underfill between the package substrate and the integrated circuit;
an underfill dispenser coupled to the heated buffer adapted to dispense an underfill material between the package substrate and the integrated circuit; and
a first curing oven coupled to the underfill dispenser adapted to cure the underfill material in the integrated circuit and package assembly to a first level of curing and further adapted to cure the underfill material to a second level of curing wherein the second level of curing is greater than the first level of curing.
11. The system of claim 10 further comprising a prebaking oven coupled to the heated buffer adapted to prebake the assembly prior to being transported to the underfill dispenser.
12. The system of claim 10 further comprising a conveyorized connection adapted to couple the reflow module to the heated buffer thermally or mechanically or combinations thereof.
13. The system of claim 10 further comprising a conveyorized connection adapted to couple the heated buffer to the underfill dispenser thermally or mechanically or combinations thereof.
14. The system of claim 10 wherein the predetermined temperature is approximately 120° C.
15. The system of claim 10 further comprising a second curing oven adapted to cure the underfill material to a second level of curing.
16. An apparatus comprising:
a heated buffer adapted to couple a reflow module with an underfill dispenser on an integrated circuit packaging assembly line, wherein the heated buffer comprises one or more support elements adapted to support one or more integrated circuit package assemblies at a predetermined temperature.
17. The apparatus of claim 16 wherein the one or more support elements comprise one or more magazine racks.
18. The apparatus of claim 17 wherein the one or more magazine racks are are first in first out random access magazine racks.
19. The apparatus of claim 17 wherein the one or more magazine racks are last in first out random access racks.
20. The apparatus of claim 16 wherein the predetermined temperature is approximately 120° C.
US12/539,690 2008-03-31 2009-08-12 Linked Chip Attach And Underfill Abandoned US20090293266A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/539,690 US20090293266A1 (en) 2008-03-31 2009-08-12 Linked Chip Attach And Underfill

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/059,047 US7588968B1 (en) 2008-03-31 2008-03-31 Linked chip attach and underfill
US12/539,690 US20090293266A1 (en) 2008-03-31 2009-08-12 Linked Chip Attach And Underfill

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US12/059,047 Division US7588968B1 (en) 2008-03-31 2008-03-31 Linked chip attach and underfill

Publications (1)

Publication Number Publication Date
US20090293266A1 true US20090293266A1 (en) 2009-12-03

Family

ID=41058778

Family Applications (2)

Application Number Title Priority Date Filing Date
US12/059,047 Expired - Fee Related US7588968B1 (en) 2008-03-31 2008-03-31 Linked chip attach and underfill
US12/539,690 Abandoned US20090293266A1 (en) 2008-03-31 2009-08-12 Linked Chip Attach And Underfill

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US12/059,047 Expired - Fee Related US7588968B1 (en) 2008-03-31 2008-03-31 Linked chip attach and underfill

Country Status (1)

Country Link
US (2) US7588968B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8008122B1 (en) * 2010-09-21 2011-08-30 International Business Machines Corporation Pressurized underfill cure

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7588968B1 (en) * 2008-03-31 2009-09-15 Intel Corporation Linked chip attach and underfill
US9275879B1 (en) 2014-08-11 2016-03-01 International Business Machines Corporation Multi-chip module with rework capability
US10160066B2 (en) * 2016-11-01 2018-12-25 GM Global Technology Operations LLC Methods and systems for reinforced adhesive bonding using solder elements and flux
JP6950737B2 (en) * 2017-04-17 2021-10-13 東京エレクトロン株式会社 Insulating film film forming method, insulating film film forming equipment and substrate processing system
US11545444B2 (en) 2020-12-31 2023-01-03 International Business Machines Corporation Mitigating cooldown peeling stress during chip package assembly
US11824037B2 (en) * 2020-12-31 2023-11-21 International Business Machines Corporation Assembly of a chip to a substrate

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2997096A (en) * 1957-05-16 1961-08-22 Owens Corning Fiberglass Corp Multiple stage methods and apparatus for curing the binder of fibrous glass masses
US6902954B2 (en) * 2003-03-31 2005-06-07 Intel Corporation Temperature sustaining flip chip assembly process
US20050124090A1 (en) * 2003-12-05 2005-06-09 Odegard Charles A. Manufacturing system and apparatus for balanced product flow with application to low-stress underfilling of flip-chip electronic devices
US7262079B2 (en) * 2005-02-10 2007-08-28 Altera Corporation Consolidated flip chip BGA assembly process and apparatus
US7408264B2 (en) * 2002-05-13 2008-08-05 International Business Machines Corporation SMT passive device noflow underfill methodology and structure
US20090045507A1 (en) * 2003-11-10 2009-02-19 Stats Chippac Ltd. Flip chip interconnection
US7588968B1 (en) * 2008-03-31 2009-09-15 Intel Corporation Linked chip attach and underfill

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2997096A (en) * 1957-05-16 1961-08-22 Owens Corning Fiberglass Corp Multiple stage methods and apparatus for curing the binder of fibrous glass masses
US7408264B2 (en) * 2002-05-13 2008-08-05 International Business Machines Corporation SMT passive device noflow underfill methodology and structure
US6902954B2 (en) * 2003-03-31 2005-06-07 Intel Corporation Temperature sustaining flip chip assembly process
US7391119B2 (en) * 2003-03-31 2008-06-24 Intel Corporation Temperature sustaining flip chip assembly process
US20090045507A1 (en) * 2003-11-10 2009-02-19 Stats Chippac Ltd. Flip chip interconnection
US20050124090A1 (en) * 2003-12-05 2005-06-09 Odegard Charles A. Manufacturing system and apparatus for balanced product flow with application to low-stress underfilling of flip-chip electronic devices
US7262079B2 (en) * 2005-02-10 2007-08-28 Altera Corporation Consolidated flip chip BGA assembly process and apparatus
US7588968B1 (en) * 2008-03-31 2009-09-15 Intel Corporation Linked chip attach and underfill
US20090246917A1 (en) * 2008-03-31 2009-10-01 Zarbock Edward A Linked chip attach and underfill

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8008122B1 (en) * 2010-09-21 2011-08-30 International Business Machines Corporation Pressurized underfill cure

Also Published As

Publication number Publication date
US7588968B1 (en) 2009-09-15
US20090246917A1 (en) 2009-10-01

Similar Documents

Publication Publication Date Title
US7588968B1 (en) Linked chip attach and underfill
US6949404B1 (en) Flip chip package with warpage control
US10350713B2 (en) No clean flux composition and methods for use thereof
US6610559B2 (en) Integrated void-free process for assembling a solder bumped chip
US6696644B1 (en) Polymer-embedded solder bumps for reliable plastic package attachment
US7534715B2 (en) Methods including fluxless chip attach processes
US20040152238A1 (en) Flip chip interconnection using no-clean flux
KR100351996B1 (en) Method for manufacturing semiconductor devices
US20050040525A1 (en) Package module for an IC device and method of forming the same
US7629203B2 (en) Thermal interface material for combined reflow
US7919356B2 (en) Method and structure to reduce cracking in flip chip underfill
US6259155B1 (en) Polymer enhanced column grid array
US20240063171A1 (en) Assembly of a chip to a substrate
US6979600B2 (en) Apparatus and methods for an underfilled integrated circuit package
US10568245B2 (en) Electronic-component mounting apparatus
CN112271170A (en) Packaging substrate, flip chip packaging structure and manufacturing method thereof
US6956165B1 (en) Underfill for maximum flip chip package reliability
US20100314433A1 (en) Method for Manufacturing Tight Pitch, Flip Chip Integrated Circuit Packages
US20130256870A1 (en) Packaging device and method of making the same
US20120318850A1 (en) Chip bonding apparatus
US20030202332A1 (en) Second level packaging interconnection method with improved thermal and reliability performance
Wang et al. Coreless substrate for high performance flip chip packaging
KR100884192B1 (en) Manufacturing method of semiconductor package
US20060063305A1 (en) Process of fabricating flip-chip packages
US9455234B2 (en) Fixture to constrain laminate and method of assembly

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION